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clk: qcom: Enumerate remaining msm8998 resets
The current list of defined resets is incomplete compared to what the hardware implements. Enumerate the remaining resets according to the hardware documentation. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Jeffrey Hugo
Stephen Boyd
parent
11832328c5
commit
c0cb7c7e71
@ -2772,6 +2772,93 @@ static const struct qcom_reset_map gcc_msm8998_resets[] = {
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[GCC_TSIF_BCR] = { 0x36000 },
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[GCC_UFS_BCR] = { 0x75000 },
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[GCC_USB_30_BCR] = { 0xf000 },
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[GCC_SYSTEM_NOC_BCR] = { 0x4000 },
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[GCC_CONFIG_NOC_BCR] = { 0x5000 },
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[GCC_AHB2PHY_EAST_BCR] = { 0x7000 },
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[GCC_IMEM_BCR] = { 0x8000 },
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[GCC_PIMEM_BCR] = { 0xa000 },
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[GCC_MMSS_BCR] = { 0xb000 },
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[GCC_QDSS_BCR] = { 0xc000 },
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[GCC_WCSS_BCR] = { 0x11000 },
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[GCC_BLSP1_BCR] = { 0x17000 },
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[GCC_BLSP1_UART1_BCR] = { 0x1a000 },
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[GCC_BLSP1_UART2_BCR] = { 0x1c000 },
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[GCC_BLSP1_UART3_BCR] = { 0x1e000 },
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[GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },
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[GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },
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[GCC_BLSP2_BCR] = { 0x25000 },
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[GCC_BLSP2_UART1_BCR] = { 0x27000 },
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[GCC_BLSP2_UART2_BCR] = { 0x29000 },
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[GCC_BLSP2_UART3_BCR] = { 0x2b000 },
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[GCC_SRAM_SENSOR_BCR] = { 0x2d000 },
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[GCC_PRNG_BCR] = { 0x34000 },
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[GCC_TSIF_0_RESET] = { 0x36024 },
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[GCC_TSIF_1_RESET] = { 0x36028 },
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[GCC_TCSR_BCR] = { 0x37000 },
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[GCC_BOOT_ROM_BCR] = { 0x38000 },
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[GCC_MSG_RAM_BCR] = { 0x39000 },
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[GCC_TLMM_BCR] = { 0x3a000 },
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[GCC_MPM_BCR] = { 0x3b000 },
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[GCC_SEC_CTRL_BCR] = { 0x3d000 },
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[GCC_SPMI_BCR] = { 0x3f000 },
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[GCC_SPDM_BCR] = { 0x40000 },
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[GCC_CE1_BCR] = { 0x41000 },
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[GCC_BIMC_BCR] = { 0x44000 },
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[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
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[GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },
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[GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },
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[GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },
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[GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
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[GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },
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[GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },
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[GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
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[GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
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[GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
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[GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
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[GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
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[GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
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[GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
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[GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
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[GCC_APB2JTAG_BCR] = { 0x4c000 },
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[GCC_RBCPR_CX_BCR] = { 0x4e000 },
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[GCC_RBCPR_MX_BCR] = { 0x4f000 },
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[GCC_USB3_PHY_BCR] = { 0x50020 },
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[GCC_USB3PHY_PHY_BCR] = { 0x50024 },
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[GCC_USB3_DP_PHY_BCR] = { 0x50028 },
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[GCC_SSC_BCR] = { 0x63000 },
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[GCC_SSC_RESET] = { 0x63020 },
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[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
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[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
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[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
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[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
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[GCC_PCIE_PHY_BCR] = { 0x6f000 },
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[GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },
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[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },
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[GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
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[GCC_GPU_BCR] = { 0x71000 },
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[GCC_SPSS_BCR] = { 0x72000 },
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[GCC_OBT_ODT_BCR] = { 0x73000 },
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[GCC_VS_BCR] = { 0x7a000 },
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[GCC_MSS_VS_RESET] = { 0x7a100 },
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[GCC_GPU_VS_RESET] = { 0x7a104 },
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[GCC_APC0_VS_RESET] = { 0x7a108 },
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[GCC_APC1_VS_RESET] = { 0x7a10c },
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[GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
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[GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
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[GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },
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[GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },
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[GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },
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[GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },
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[GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },
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[GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },
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[GCC_AGGRE1_NOC_BCR] = { 0x82000 },
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[GCC_AGGRE2_NOC_BCR] = { 0x83000 },
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[GCC_DCC_BCR] = { 0x84000 },
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[GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },
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[GCC_IPA_BCR] = { 0x89000 },
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[GCC_GLM_BCR] = { 0x8b000 },
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[GCC_SKL_BCR] = { 0x8c000 },
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[GCC_MSMPU_BCR] = { 0x8d000 },
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};
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static const struct regmap_config gcc_msm8998_regmap_config = {
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@ -204,5 +204,92 @@
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#define GCC_TSIF_BCR 16
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#define GCC_UFS_BCR 17
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#define GCC_USB_30_BCR 18
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#define GCC_SYSTEM_NOC_BCR 19
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#define GCC_CONFIG_NOC_BCR 20
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#define GCC_AHB2PHY_EAST_BCR 21
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#define GCC_IMEM_BCR 22
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#define GCC_PIMEM_BCR 23
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#define GCC_MMSS_BCR 24
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#define GCC_QDSS_BCR 25
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#define GCC_WCSS_BCR 26
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#define GCC_BLSP1_BCR 27
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#define GCC_BLSP1_UART1_BCR 28
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#define GCC_BLSP1_UART2_BCR 29
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#define GCC_BLSP1_UART3_BCR 30
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#define GCC_CM_PHY_REFGEN1_BCR 31
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#define GCC_CM_PHY_REFGEN2_BCR 32
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#define GCC_BLSP2_BCR 33
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#define GCC_BLSP2_UART1_BCR 34
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#define GCC_BLSP2_UART2_BCR 35
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#define GCC_BLSP2_UART3_BCR 36
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#define GCC_SRAM_SENSOR_BCR 37
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#define GCC_PRNG_BCR 38
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#define GCC_TSIF_0_RESET 39
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#define GCC_TSIF_1_RESET 40
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#define GCC_TCSR_BCR 41
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#define GCC_BOOT_ROM_BCR 42
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#define GCC_MSG_RAM_BCR 43
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#define GCC_TLMM_BCR 44
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#define GCC_MPM_BCR 45
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#define GCC_SEC_CTRL_BCR 46
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#define GCC_SPMI_BCR 47
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#define GCC_SPDM_BCR 48
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#define GCC_CE1_BCR 49
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#define GCC_BIMC_BCR 50
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#define GCC_SNOC_BUS_TIMEOUT0_BCR 51
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#define GCC_SNOC_BUS_TIMEOUT1_BCR 52
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#define GCC_SNOC_BUS_TIMEOUT3_BCR 53
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#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 54
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#define GCC_PNOC_BUS_TIMEOUT0_BCR 55
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#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR 56
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#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR 57
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#define GCC_CNOC_BUS_TIMEOUT0_BCR 58
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#define GCC_CNOC_BUS_TIMEOUT1_BCR 59
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#define GCC_CNOC_BUS_TIMEOUT2_BCR 60
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#define GCC_CNOC_BUS_TIMEOUT3_BCR 61
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#define GCC_CNOC_BUS_TIMEOUT4_BCR 62
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#define GCC_CNOC_BUS_TIMEOUT5_BCR 63
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#define GCC_CNOC_BUS_TIMEOUT6_BCR 64
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#define GCC_CNOC_BUS_TIMEOUT7_BCR 65
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#define GCC_APB2JTAG_BCR 66
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#define GCC_RBCPR_CX_BCR 67
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#define GCC_RBCPR_MX_BCR 68
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#define GCC_USB3_PHY_BCR 69
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#define GCC_USB3PHY_PHY_BCR 70
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#define GCC_USB3_DP_PHY_BCR 71
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#define GCC_SSC_BCR 72
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#define GCC_SSC_RESET 73
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 74
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#define GCC_PCIE_0_LINK_DOWN_BCR 75
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#define GCC_PCIE_0_PHY_BCR 76
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#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 77
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#define GCC_PCIE_PHY_BCR 78
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#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 79
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#define GCC_PCIE_PHY_CFG_AHB_BCR 80
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#define GCC_PCIE_PHY_COM_BCR 81
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#define GCC_GPU_BCR 82
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#define GCC_SPSS_BCR 83
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#define GCC_OBT_ODT_BCR 84
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#define GCC_VS_BCR 85
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#define GCC_MSS_VS_RESET 86
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#define GCC_GPU_VS_RESET 87
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#define GCC_APC0_VS_RESET 88
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#define GCC_APC1_VS_RESET 89
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#define GCC_CNOC_BUS_TIMEOUT8_BCR 90
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#define GCC_CNOC_BUS_TIMEOUT9_BCR 91
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#define GCC_CNOC_BUS_TIMEOUT10_BCR 92
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#define GCC_CNOC_BUS_TIMEOUT11_BCR 93
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#define GCC_CNOC_BUS_TIMEOUT12_BCR 94
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#define GCC_CNOC_BUS_TIMEOUT13_BCR 95
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#define GCC_CNOC_BUS_TIMEOUT14_BCR 96
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#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 97
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#define GCC_AGGRE1_NOC_BCR 98
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#define GCC_AGGRE2_NOC_BCR 99
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#define GCC_DCC_BCR 100
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#define GCC_QREFS_VBG_CAL_BCR 101
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#define GCC_IPA_BCR 102
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#define GCC_GLM_BCR 103
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#define GCC_SKL_BCR 104
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#define GCC_MSMPU_BCR 105
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#endif
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