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[ARM] MX35: Add register definitions for the i.MX35
This patch moves the stuff common to i.MX31 and i.MX35 to mx3x.h and the specifics to mx31.h/mx35.h. We can build a kernel which runs on i.MX31 and i.MX35, so always include mx31.h and mx35.h Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
7e8549bcee
commit
c0a5f85523
@ -23,7 +23,9 @@
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#include <asm/sizes.h>
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#ifdef CONFIG_ARCH_MX3
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# include <mach/mx31.h>
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#include <mach/mx3x.h>
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#include <mach/mx31.h>
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#include <mach/mx35.h>
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#endif
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#ifdef CONFIG_ARCH_MX2
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@ -1,360 +1,45 @@
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/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MXC_MX31_H__
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#define __ASM_ARCH_MXC_MX31_H__
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#ifndef __ASM_ARCH_MXC_HARDWARE_H__
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#error "Do not include directly."
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#endif
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/*
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* MX31 memory map:
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*
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* Virt Phys Size What
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* ---------------------------------------------------------------------------
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* F8000000 1FFC0000 16K IRAM
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* F9000000 30000000 256M L2CC
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* FC000000 43F00000 1M AIPS 1
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* FC100000 50000000 1M SPBA
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* FC200000 53F00000 1M AIPS 2
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* FC500000 60000000 128M ROMPATCH
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* FC400000 68000000 128M AVIC
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* 70000000 256M IPU (MAX M2)
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* 80000000 256M CSD0 SDRAM/DDR
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* 90000000 256M CSD1 SDRAM/DDR
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* A0000000 128M CS0 Flash
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* A8000000 128M CS1 Flash
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* B0000000 32M CS2
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* B2000000 32M CS3
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* F4000000 B4000000 32M CS4
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* B6000000 32M CS5
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* FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
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* C0000000 64M PCMCIA/CF
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*/
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#define CS0_BASE_ADDR 0xA0000000
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#define CS1_BASE_ADDR 0xA8000000
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#define CS2_BASE_ADDR 0xB0000000
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#define CS3_BASE_ADDR 0xB2000000
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#define CS4_BASE_ADDR 0xB4000000
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#define CS4_BASE_ADDR_VIRT 0xF4000000
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#define CS4_SIZE SZ_32M
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#define CS5_BASE_ADDR 0xB6000000
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#define PCMCIA_MEM_BASE_ADDR 0xBC000000
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/*
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* IRAM
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*/
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#define IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
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#define IRAM_BASE_ADDR_VIRT 0xF8000000
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#define IRAM_SIZE SZ_16K
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#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
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#define MX31_IRAM_SIZE SZ_16K
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/*
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* L2CC
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*/
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#define L2CC_BASE_ADDR 0x30000000
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#define L2CC_BASE_ADDR_VIRT 0xF9000000
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#define L2CC_SIZE SZ_1M
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/*
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* AIPS 1
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*/
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#define AIPS1_BASE_ADDR 0x43F00000
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#define AIPS1_BASE_ADDR_VIRT 0xFC000000
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#define AIPS1_SIZE SZ_1M
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#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
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#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
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#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
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#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
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#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
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#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
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#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
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#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
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#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
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#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
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#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
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#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
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#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
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#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
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#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
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#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
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#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
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#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
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#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
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#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
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#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
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#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
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/*
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* SPBA global module enabled #0
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*/
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#define SPBA0_BASE_ADDR 0x50000000
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#define SPBA0_BASE_ADDR_VIRT 0xFC100000
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#define SPBA0_SIZE SZ_1M
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#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
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#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
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#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
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#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
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#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
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#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
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#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
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#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
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#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
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#define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
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#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
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/*
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* AIPS 2
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*/
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#define AIPS2_BASE_ADDR 0x53F00000
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#define AIPS2_BASE_ADDR_VIRT 0xFC200000
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#define AIPS2_SIZE SZ_1M
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#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
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#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
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#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
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#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
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#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
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#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
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#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
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#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
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#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
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#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
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#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
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#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
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#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
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#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
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#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
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#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
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#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
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#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
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#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
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#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
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#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
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/*
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* ROMP and AVIC
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*/
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#define ROMP_BASE_ADDR 0x60000000
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#define ROMP_BASE_ADDR_VIRT 0xFC500000
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#define ROMP_SIZE SZ_1M
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#define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
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#define AVIC_BASE_ADDR 0x68000000
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#define AVIC_BASE_ADDR_VIRT 0xFC400000
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#define AVIC_SIZE SZ_1M
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/*
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* NAND, SDRAM, WEIM, M3IF, EMI controllers
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*/
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#define X_MEMC_BASE_ADDR 0xB8000000
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#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
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#define X_MEMC_SIZE SZ_64K
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#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
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#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
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#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
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#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
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#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
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#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
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/*
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* Memory regions and CS
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*/
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#define IPU_MEM_BASE_ADDR 0x70000000
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#define CSD0_BASE_ADDR 0x80000000
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#define CSD1_BASE_ADDR 0x90000000
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#define CS0_BASE_ADDR 0xA0000000
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#define CS1_BASE_ADDR 0xA8000000
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#define CS2_BASE_ADDR 0xB0000000
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#define CS3_BASE_ADDR 0xB2000000
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#define CS4_BASE_ADDR 0xB4000000
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#define CS4_BASE_ADDR_VIRT 0xF4000000
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#define CS4_SIZE SZ_32M
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#define CS5_BASE_ADDR 0xB6000000
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#define PCMCIA_MEM_BASE_ADDR 0xBC000000
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/*!
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* This macro defines the physical to virtual address mapping for all the
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* peripheral modules. It is used by passing in the physical address as x
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* and returning the virtual address. If the physical address is not mapped,
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* it returns 0xDEADBEEF
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*/
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#define IO_ADDRESS(x) \
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(void __iomem *) \
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(((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
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((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
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((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
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((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
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((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
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((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
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((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
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((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
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((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
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0xDEADBEEF)
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/*
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* define the address mapping macros: in physical address order
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*/
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#define IRAM_IO_ADDRESS(x) \
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(((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
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#define L2CC_IO_ADDRESS(x) \
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(((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
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#define AIPS1_IO_ADDRESS(x) \
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(((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
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#define SPBA0_IO_ADDRESS(x) \
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(((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
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#define AIPS2_IO_ADDRESS(x) \
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(((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
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#define ROMP_IO_ADDRESS(x) \
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(((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
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#define AVIC_IO_ADDRESS(x) \
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(((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
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#define CS4_IO_ADDRESS(x) \
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(((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
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#define X_MEMC_IO_ADDRESS(x) \
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(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
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#define PCMCIA_IO_ADDRESS(x) \
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(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
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/*
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* Interrupt numbers
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*/
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#define MXC_INT_PEN_ADS7843 0
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#define MXC_INT_RESV1 1
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#define MXC_INT_CS8900A 2
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#define MXC_INT_I2C3 3
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#define MXC_INT_I2C2 4
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#define MXC_INT_MPEG4_ENCODER 5
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#define MXC_INT_RTIC 6
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#define MXC_INT_FIRI 7
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#define MXC_INT_MMC_SDHC2 8
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#define MX31_INT_MMC_SDHC2 8
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#define MXC_INT_MMC_SDHC1 9
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#define MXC_INT_I2C 10
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#define MXC_INT_SSI2 11
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#define MXC_INT_SSI1 12
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#define MXC_INT_CSPI2 13
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#define MXC_INT_CSPI1 14
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#define MXC_INT_ATA 15
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#define MX31_INT_SSI2 11
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#define MX31_INT_SSI1 12
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#define MXC_INT_MBX 16
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#define MXC_INT_CSPI3 17
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#define MXC_INT_UART3 18
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#define MXC_INT_IIM 19
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#define MXC_INT_SIM2 20
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#define MXC_INT_SIM1 21
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#define MXC_INT_RNGA 22
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#define MXC_INT_EVTMON 23
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#define MXC_INT_KPP 24
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#define MXC_INT_RTC 25
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#define MXC_INT_PWM 26
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#define MXC_INT_EPIT2 27
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#define MXC_INT_EPIT1 28
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#define MXC_INT_GPT 29
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#define MXC_INT_RESV30 30
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#define MXC_INT_RESV31 31
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#define MXC_INT_UART2 32
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#define MXC_INT_NANDFC 33
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#define MXC_INT_SDMA 34
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#define MXC_INT_CCM_DVFS 31
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#define MXC_INT_USB1 35
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#define MXC_INT_USB2 36
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#define MXC_INT_USB3 37
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#define MXC_INT_USB4 38
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#define MXC_INT_MSHC1 39
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#define MXC_INT_MSHC2 40
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#define MXC_INT_IPU_ERR 41
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#define MXC_INT_IPU_SYN 42
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#define MXC_INT_RESV43 43
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#define MXC_INT_RESV44 44
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#define MXC_INT_UART1 45
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#define MXC_INT_UART4 46
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#define MXC_INT_UART5 47
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#define MXC_INT_ECT 48
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#define MXC_INT_SCC_SCM 49
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#define MXC_INT_SCC_SMN 50
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#define MXC_INT_GPIO2 51
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#define MXC_INT_GPIO1 52
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#define MXC_INT_CCM 53
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#define MXC_INT_PCMCIA 54
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#define MXC_INT_WDOG 55
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#define MXC_INT_GPIO3 56
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#define MXC_INT_RESV57 57
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#define MXC_INT_EXT_POWER 58
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#define MXC_INT_EXT_TEMPER 59
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#define MXC_INT_EXT_SENSOR60 60
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#define MXC_INT_EXT_SENSOR61 61
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#define MXC_INT_EXT_WDOG 62
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#define MXC_INT_EXT_TV 63
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#define PROD_SIGNATURE 0x1 /* For MX31 */
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/* silicon revisions specific to i.MX31 */
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#define CHIP_REV_1_0 0x10
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#define CHIP_REV_1_1 0x11
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#define CHIP_REV_1_2 0x12
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#define CHIP_REV_1_3 0x13
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#define CHIP_REV_2_0 0x20
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#define CHIP_REV_2_1 0x21
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#define CHIP_REV_2_2 0x22
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#define CHIP_REV_2_3 0x23
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#define CHIP_REV_3_0 0x30
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#define CHIP_REV_3_1 0x31
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#define CHIP_REV_3_2 0x32
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#define SYSTEM_REV_MIN CHIP_REV_1_0
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#define SYSTEM_REV_NUM 3
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/* gpio and gpio based interrupt handling */
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#define GPIO_DR 0x00
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#define GPIO_GDIR 0x04
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#define GPIO_PSR 0x08
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#define GPIO_ICR1 0x0C
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#define GPIO_ICR2 0x10
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#define GPIO_IMR 0x14
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#define GPIO_ISR 0x18
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#define GPIO_INT_LOW_LEV 0x0
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#define GPIO_INT_HIGH_LEV 0x1
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#define GPIO_INT_RISE_EDGE 0x2
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#define GPIO_INT_FALL_EDGE 0x3
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#define GPIO_INT_NONE 0x4
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/* Mandatory defines used globally */
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/* this CPU supports up to 96 GPIOs */
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#define ARCH_NR_GPIOS 96
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#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
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/* this is a i.MX31 CPU */
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#define cpu_is_mx31() (1)
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extern unsigned int system_rev;
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static inline int mx31_revision(void)
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{
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return system_rev;
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}
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#endif
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#endif /* __ASM_ARCH_MXC_MX31_H__ */
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29
arch/arm/plat-mxc/include/mach/mx35.h
Normal file
29
arch/arm/plat-mxc/include/mach/mx35.h
Normal file
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* IRAM
|
||||
*/
|
||||
#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
|
||||
#define MX35_IRAM_SIZE SZ_128K
|
||||
|
||||
#define MXC_FEC_BASE_ADDR 0x50038000
|
||||
#define MX35_NFC_BASE_ADDR 0xBB000000
|
||||
|
||||
/*
|
||||
* Interrupt numbers
|
||||
*/
|
||||
#define MXC_INT_OWIRE 2
|
||||
#define MX35_INT_MMC_SDHC1 7
|
||||
#define MXC_INT_MMC_SDHC2 8
|
||||
#define MXC_INT_MMC_SDHC3 9
|
||||
#define MX35_INT_SSI1 11
|
||||
#define MX35_INT_SSI2 12
|
||||
#define MXC_INT_GPU2D 16
|
||||
#define MXC_INT_ASRC 17
|
||||
#define MXC_INT_USBHS 35
|
||||
#define MXC_INT_USBOTG 37
|
||||
#define MXC_INT_ESAI 40
|
||||
#define MXC_INT_CAN1 43
|
||||
#define MXC_INT_CAN2 44
|
||||
#define MXC_INT_MLB 46
|
||||
#define MXC_INT_SPDIF 47
|
||||
#define MXC_INT_FEC 57
|
||||
|
||||
290
arch/arm/plat-mxc/include/mach/mx3x.h
Normal file
290
arch/arm/plat-mxc/include/mach/mx3x.h
Normal file
@ -0,0 +1,290 @@
|
||||
/*
|
||||
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MXC_MX31_H__
|
||||
#define __ASM_ARCH_MXC_MX31_H__
|
||||
|
||||
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
|
||||
#error "Do not include directly."
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MX31 memory map:
|
||||
*
|
||||
* Virt Phys Size What
|
||||
* ---------------------------------------------------------------------------
|
||||
* FC000000 43F00000 1M AIPS 1
|
||||
* FC100000 50000000 1M SPBA
|
||||
* FC200000 53F00000 1M AIPS 2
|
||||
* FC500000 60000000 128M ROMPATCH
|
||||
* FC400000 68000000 128M AVIC
|
||||
* 70000000 256M IPU (MAX M2)
|
||||
* 80000000 256M CSD0 SDRAM/DDR
|
||||
* 90000000 256M CSD1 SDRAM/DDR
|
||||
* A0000000 128M CS0 Flash
|
||||
* A8000000 128M CS1 Flash
|
||||
* B0000000 32M CS2
|
||||
* B2000000 32M CS3
|
||||
* F4000000 B4000000 32M CS4
|
||||
* B6000000 32M CS5
|
||||
* FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
|
||||
* C0000000 64M PCMCIA/CF
|
||||
*/
|
||||
|
||||
#define CS0_BASE_ADDR 0xA0000000
|
||||
#define CS1_BASE_ADDR 0xA8000000
|
||||
#define CS2_BASE_ADDR 0xB0000000
|
||||
#define CS3_BASE_ADDR 0xB2000000
|
||||
|
||||
#define CS4_BASE_ADDR 0xB4000000
|
||||
#define CS4_BASE_ADDR_VIRT 0xF4000000
|
||||
#define CS4_SIZE SZ_32M
|
||||
|
||||
#define CS5_BASE_ADDR 0xB6000000
|
||||
#define PCMCIA_MEM_BASE_ADDR 0xBC000000
|
||||
|
||||
/*
|
||||
* L2CC
|
||||
*/
|
||||
#define L2CC_BASE_ADDR 0x30000000
|
||||
#define L2CC_SIZE SZ_1M
|
||||
|
||||
/*
|
||||
* AIPS 1
|
||||
*/
|
||||
#define AIPS1_BASE_ADDR 0x43F00000
|
||||
#define AIPS1_BASE_ADDR_VIRT 0xFC000000
|
||||
#define AIPS1_SIZE SZ_1M
|
||||
|
||||
#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
|
||||
#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
|
||||
#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
|
||||
#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
|
||||
#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
|
||||
#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
|
||||
#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
|
||||
#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
|
||||
#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
|
||||
#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
|
||||
#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
|
||||
#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
|
||||
#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
|
||||
#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
|
||||
#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
|
||||
#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
|
||||
#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
|
||||
#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
|
||||
|
||||
/*
|
||||
* SPBA global module enabled #0
|
||||
*/
|
||||
#define SPBA0_BASE_ADDR 0x50000000
|
||||
#define SPBA0_BASE_ADDR_VIRT 0xFC100000
|
||||
#define SPBA0_SIZE SZ_1M
|
||||
|
||||
#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
|
||||
#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
|
||||
#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
|
||||
#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
|
||||
#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
|
||||
#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
|
||||
|
||||
/*
|
||||
* AIPS 2
|
||||
*/
|
||||
#define AIPS2_BASE_ADDR 0x53F00000
|
||||
#define AIPS2_BASE_ADDR_VIRT 0xFC200000
|
||||
#define AIPS2_SIZE SZ_1M
|
||||
#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
|
||||
#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
|
||||
#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
|
||||
#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
|
||||
#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
|
||||
#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
|
||||
#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
|
||||
#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
|
||||
#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
|
||||
#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
|
||||
#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
|
||||
#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
|
||||
#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
|
||||
#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
|
||||
#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
|
||||
#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
|
||||
|
||||
/*
|
||||
* ROMP and AVIC
|
||||
*/
|
||||
#define ROMP_BASE_ADDR 0x60000000
|
||||
#define ROMP_BASE_ADDR_VIRT 0xFC500000
|
||||
#define ROMP_SIZE SZ_1M
|
||||
|
||||
#define AVIC_BASE_ADDR 0x68000000
|
||||
#define AVIC_BASE_ADDR_VIRT 0xFC400000
|
||||
#define AVIC_SIZE SZ_1M
|
||||
|
||||
/*
|
||||
* NAND, SDRAM, WEIM, M3IF, EMI controllers
|
||||
*/
|
||||
#define X_MEMC_BASE_ADDR 0xB8000000
|
||||
#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
|
||||
#define X_MEMC_SIZE SZ_64K
|
||||
|
||||
#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
|
||||
#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
|
||||
#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
|
||||
#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
|
||||
#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
|
||||
|
||||
/*
|
||||
* Memory regions and CS
|
||||
*/
|
||||
#define IPU_MEM_BASE_ADDR 0x70000000
|
||||
#define CSD0_BASE_ADDR 0x80000000
|
||||
#define CSD1_BASE_ADDR 0x90000000
|
||||
|
||||
/*!
|
||||
* This macro defines the physical to virtual address mapping for all the
|
||||
* peripheral modules. It is used by passing in the physical address as x
|
||||
* and returning the virtual address. If the physical address is not mapped,
|
||||
* it returns 0xDEADBEEF
|
||||
*/
|
||||
#define IO_ADDRESS(x) \
|
||||
(void __iomem *) \
|
||||
(((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
|
||||
((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
|
||||
((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
|
||||
((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
|
||||
((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
|
||||
((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
|
||||
((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
|
||||
0xDEADBEEF)
|
||||
|
||||
/*
|
||||
* define the address mapping macros: in physical address order
|
||||
*/
|
||||
#define L2CC_IO_ADDRESS(x) \
|
||||
(((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
|
||||
|
||||
#define AIPS1_IO_ADDRESS(x) \
|
||||
(((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
|
||||
|
||||
#define SPBA0_IO_ADDRESS(x) \
|
||||
(((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
|
||||
|
||||
#define AIPS2_IO_ADDRESS(x) \
|
||||
(((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
|
||||
|
||||
#define ROMP_IO_ADDRESS(x) \
|
||||
(((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
|
||||
|
||||
#define AVIC_IO_ADDRESS(x) \
|
||||
(((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
|
||||
|
||||
#define CS4_IO_ADDRESS(x) \
|
||||
(((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
|
||||
|
||||
#define X_MEMC_IO_ADDRESS(x) \
|
||||
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
|
||||
|
||||
#define PCMCIA_IO_ADDRESS(x) \
|
||||
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
|
||||
|
||||
/*
|
||||
* Interrupt numbers
|
||||
*/
|
||||
#define MXC_INT_I2C3 3
|
||||
#define MXC_INT_I2C2 4
|
||||
#define MXC_INT_RTIC 6
|
||||
#define MXC_INT_I2C 10
|
||||
#define MXC_INT_CSPI2 13
|
||||
#define MXC_INT_CSPI1 14
|
||||
#define MXC_INT_ATA 15
|
||||
#define MXC_INT_UART3 18
|
||||
#define MXC_INT_IIM 19
|
||||
#define MXC_INT_RNGA 22
|
||||
#define MXC_INT_EVTMON 23
|
||||
#define MXC_INT_KPP 24
|
||||
#define MXC_INT_RTC 25
|
||||
#define MXC_INT_PWM 26
|
||||
#define MXC_INT_EPIT2 27
|
||||
#define MXC_INT_EPIT1 28
|
||||
#define MXC_INT_GPT 29
|
||||
#define MXC_INT_POWER_FAIL 30
|
||||
#define MXC_INT_UART2 32
|
||||
#define MXC_INT_NANDFC 33
|
||||
#define MXC_INT_SDMA 34
|
||||
#define MXC_INT_MSHC1 39
|
||||
#define MXC_INT_IPU_ERR 41
|
||||
#define MXC_INT_IPU_SYN 42
|
||||
#define MXC_INT_UART1 45
|
||||
#define MXC_INT_ECT 48
|
||||
#define MXC_INT_SCC_SCM 49
|
||||
#define MXC_INT_SCC_SMN 50
|
||||
#define MXC_INT_GPIO2 51
|
||||
#define MXC_INT_GPIO1 52
|
||||
#define MXC_INT_WDOG 55
|
||||
#define MXC_INT_GPIO3 56
|
||||
#define MXC_INT_EXT_POWER 58
|
||||
#define MXC_INT_EXT_TEMPER 59
|
||||
#define MXC_INT_EXT_SENSOR60 60
|
||||
#define MXC_INT_EXT_SENSOR61 61
|
||||
#define MXC_INT_EXT_WDOG 62
|
||||
#define MXC_INT_EXT_TV 63
|
||||
|
||||
#define PROD_SIGNATURE 0x1 /* For MX31 */
|
||||
|
||||
/* silicon revisions specific to i.MX31 */
|
||||
#define CHIP_REV_1_0 0x10
|
||||
#define CHIP_REV_1_1 0x11
|
||||
#define CHIP_REV_1_2 0x12
|
||||
#define CHIP_REV_1_3 0x13
|
||||
#define CHIP_REV_2_0 0x20
|
||||
#define CHIP_REV_2_1 0x21
|
||||
#define CHIP_REV_2_2 0x22
|
||||
#define CHIP_REV_2_3 0x23
|
||||
#define CHIP_REV_3_0 0x30
|
||||
#define CHIP_REV_3_1 0x31
|
||||
#define CHIP_REV_3_2 0x32
|
||||
|
||||
#define SYSTEM_REV_MIN CHIP_REV_1_0
|
||||
#define SYSTEM_REV_NUM 3
|
||||
|
||||
/* gpio and gpio based interrupt handling */
|
||||
#define GPIO_DR 0x00
|
||||
#define GPIO_GDIR 0x04
|
||||
#define GPIO_PSR 0x08
|
||||
#define GPIO_ICR1 0x0C
|
||||
#define GPIO_ICR2 0x10
|
||||
#define GPIO_IMR 0x14
|
||||
#define GPIO_ISR 0x18
|
||||
#define GPIO_INT_LOW_LEV 0x0
|
||||
#define GPIO_INT_HIGH_LEV 0x1
|
||||
#define GPIO_INT_RISE_EDGE 0x2
|
||||
#define GPIO_INT_FALL_EDGE 0x3
|
||||
#define GPIO_INT_NONE 0x4
|
||||
|
||||
/* Mandatory defines used globally */
|
||||
|
||||
/* this CPU supports up to 96 GPIOs */
|
||||
#define ARCH_NR_GPIOS 96
|
||||
|
||||
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
|
||||
|
||||
extern unsigned int system_rev;
|
||||
|
||||
static inline int mx31_revision(void)
|
||||
{
|
||||
return system_rev;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_MXC_MX31_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user