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KVM: PPC: Book3S: Add GET/SET_ONE_REG interface for VRSAVE
The VRSAVE register value for a vcpu is accessible through the GET/SET_SREGS interface for Book E processors, but not for Book 3S processors. In order to make this accessible for Book 3S processors, this adds a new register identifier for GET/SET_ONE_REG, and adds the code to implement it. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -1834,6 +1834,7 @@ registers, find a list below:
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PPC | KVM_REG_PPC_TCSCR | 64
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PPC | KVM_REG_PPC_PID | 64
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PPC | KVM_REG_PPC_ACOP | 64
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PPC | KVM_REG_PPC_VRSAVE | 32
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PPC | KVM_REG_PPC_TM_GPR0 | 64
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...
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PPC | KVM_REG_PPC_TM_GPR31 | 64
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@ -532,6 +532,8 @@ struct kvm_get_htab_header {
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#define KVM_REG_PPC_PID (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2)
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#define KVM_REG_PPC_ACOP (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)
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#define KVM_REG_PPC_VRSAVE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)
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/* Transactional Memory checkpointed state:
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* This is all GPRs, all VSX regs and a subset of SPRs
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*/
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@ -528,6 +528,9 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
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}
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val = get_reg_val(reg->id, vcpu->arch.vscr.u[3]);
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break;
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case KVM_REG_PPC_VRSAVE:
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val = get_reg_val(reg->id, vcpu->arch.vrsave);
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break;
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#endif /* CONFIG_ALTIVEC */
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case KVM_REG_PPC_DEBUG_INST: {
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u32 opcode = INS_TW;
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@ -605,6 +608,13 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
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}
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vcpu->arch.vscr.u[3] = set_reg_val(reg->id, val);
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break;
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case KVM_REG_PPC_VRSAVE:
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if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
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r = -ENXIO;
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break;
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}
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vcpu->arch.vrsave = set_reg_val(reg->id, val);
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break;
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#endif /* CONFIG_ALTIVEC */
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#ifdef CONFIG_KVM_XICS
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case KVM_REG_PPC_ICP_STATE:
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