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https://github.com/edk2-porting/linux-next.git
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drm/nv50-/disp: audit and version SOR_DP_PWR method
The full object interfaces are about to be exposed to userspace, so we need to check for any security-related issues and version the structs to make it easier to handle any changes we may need in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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a3761fa248
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@ -928,6 +928,30 @@ nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd,
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return ret;
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}
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break;
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case NV50_DISP_MTHD_V1_SOR_DP_PWR: {
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struct nvkm_output_dp *outpdp = (void *)outp;
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union {
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struct nv50_disp_sor_dp_pwr_v0 v0;
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} *args = data;
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nv_ioctl(object, "disp sor dp pwr size %d\n", size);
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if (nvif_unpack(args->v0, 0, 0, false)) {
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nv_ioctl(object, "disp sor dp pwr vers %d state %d\n",
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args->v0.version, args->v0.state);
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if (args->v0.state == 0) {
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nvkm_notify_put(&outpdp->irq);
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((struct nvkm_output_dp_impl *)nv_oclass(outp))
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->lnk_pwr(outpdp, 0);
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atomic_set(&outpdp->lt.done, 0);
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return 0;
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} else
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if (args->v0.state != 0) {
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nvkm_output_dp_train(&outpdp->base, 0, true);
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return 0;
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}
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} else
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return ret;
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}
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break;
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default:
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break;
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}
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@ -77,7 +77,6 @@ int nv84_hdmi_ctrl(NV50_DISP_MTHD_V1);
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int nva3_hdmi_ctrl(NV50_DISP_MTHD_V1);
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int nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1);
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int nv50_sor_mthd(struct nouveau_object *, u32, void *, u32);
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int nv50_sor_power(NV50_DISP_MTHD_V1);
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int nv94_sor_dp_train_init(struct nv50_disp_priv *, int, int, int, u16, u16,
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@ -74,7 +74,6 @@ nv94_disp_sclass[] = {
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static struct nouveau_omthds
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nv94_disp_base_omthds[] = {
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{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
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{ SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd },
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@ -46,7 +46,6 @@ nva3_disp_sclass[] = {
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static struct nouveau_omthds
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nva3_disp_base_omthds[] = {
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{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
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{ SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd },
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@ -712,7 +712,6 @@ nvd0_disp_base_ofuncs = {
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struct nouveau_omthds
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nvd0_disp_base_omthds[] = {
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{ HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nvd0_disp_base_scanoutpos },
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{ SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd },
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@ -57,54 +57,3 @@ nv50_sor_power(NV50_DISP_MTHD_V1)
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nv_wait(priv, 0x61c030 + soff, 0x10000000, 0x00000000);
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return 0;
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}
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int
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nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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const u8 type = (mthd & NV50_DISP_SOR_MTHD_TYPE) >> 12;
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const u8 head = (mthd & NV50_DISP_SOR_MTHD_HEAD) >> 3;
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const u8 link = (mthd & NV50_DISP_SOR_MTHD_LINK) >> 2;
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const u8 or = (mthd & NV50_DISP_SOR_MTHD_OR);
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const u16 mask = (0x0100 << head) | (0x0040 << link) | (0x0001 << or);
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struct nvkm_output *outp = NULL, *temp;
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u32 data;
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int ret = -EINVAL;
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if (size < sizeof(u32))
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return -EINVAL;
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data = *(u32 *)args;
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list_for_each_entry(temp, &priv->base.outp, head) {
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if ((temp->info.hasht & 0xff) == type &&
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(temp->info.hashm & mask) == mask) {
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outp = temp;
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break;
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}
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}
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switch (mthd & ~0x3f) {
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case NV94_DISP_SOR_DP_PWR:
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if (outp) {
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struct nvkm_output_dp *outpdp = (void *)outp;
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switch (data) {
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case NV94_DISP_SOR_DP_PWR_STATE_OFF:
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nvkm_notify_put(&outpdp->irq);
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((struct nvkm_output_dp_impl *)nv_oclass(outp))
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->lnk_pwr(outpdp, 0);
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atomic_set(&outpdp->lt.done, 0);
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break;
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case NV94_DISP_SOR_DP_PWR_STATE_ON:
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nvkm_output_dp_train(&outpdp->base, 0, true);
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break;
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default:
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return -EINVAL;
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}
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}
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break;
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default:
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BUG_ON(1);
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}
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return ret;
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}
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@ -53,17 +53,6 @@ struct nv04_display_scanoutpos {
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#define NV50_DISP_SCANOUTPOS 0x00000000
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#define NV50_DISP_SOR_MTHD 0x00010000
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#define NV50_DISP_SOR_MTHD_TYPE 0x0000f000
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#define NV50_DISP_SOR_MTHD_HEAD 0x00000018
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#define NV50_DISP_SOR_MTHD_LINK 0x00000004
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#define NV50_DISP_SOR_MTHD_OR 0x00000003
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#define NV94_DISP_SOR_DP_PWR 0x00016000
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#define NV94_DISP_SOR_DP_PWR_STATE 0x00000001
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#define NV94_DISP_SOR_DP_PWR_STATE_OFF 0x00000000
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#define NV94_DISP_SOR_DP_PWR_STATE_ON 0x00000001
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#define NV50_DISP_PIOR_MTHD 0x00030000
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#define NV50_DISP_PIOR_MTHD_TYPE 0x0000f000
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#define NV50_DISP_PIOR_MTHD_OR 0x00000003
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@ -1785,9 +1785,18 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
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.base.hashm = nv_encoder->dcb->hashm,
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.pwr.state = mode == DRM_MODE_DPMS_ON,
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};
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struct {
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struct nv50_disp_mthd_v1 base;
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struct nv50_disp_sor_dp_pwr_v0 pwr;
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} link = {
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.base.version = 1,
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.base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
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.base.hasht = nv_encoder->dcb->hasht,
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.base.hashm = nv_encoder->dcb->hashm,
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.pwr.state = mode == DRM_MODE_DPMS_ON,
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};
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struct drm_device *dev = encoder->dev;
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struct drm_encoder *partner;
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u32 mthd, data;
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nv_encoder->last_dpms = mode;
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@ -1805,16 +1814,10 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
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}
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}
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mthd = (ffs(nv_encoder->dcb->heads) - 1) << 3;
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mthd |= (ffs(nv_encoder->dcb->sorconf.link) - 1) << 2;
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mthd |= nv_encoder->or;
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if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
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args.pwr.state = 1;
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nvif_mthd(disp->disp, 0, &args, sizeof(args));
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data = (mode == DRM_MODE_DPMS_ON);
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mthd |= NV94_DISP_SOR_DP_PWR;
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nvif_exec(disp->disp, mthd, &data, sizeof(data));
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nvif_mthd(disp->disp, 0, &link, sizeof(link));
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} else {
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nvif_mthd(disp->disp, 0, &args, sizeof(args));
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}
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@ -367,4 +367,10 @@ struct nv50_disp_sor_lvds_script_v0 {
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__u8 pad04[4];
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};
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struct nv50_disp_sor_dp_pwr_v0 {
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__u8 version;
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__u8 state;
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__u8 pad02[6];
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};
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#endif
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