mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-20 03:04:01 +08:00
powerpc/5200: Add support for the Media5200 board from Freescale
This patch adds board support for the Media5200 platform. Changes are: - add the media5200 device tree - add the media5200 platform support code and cascaded interrupt controller - add media5200 to the build targets. Note: this patch also includes a minor tweak to the lite5200(b) target images list to add the .dtb files to the image list. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Grant Likely
parent
5496eab243
commit
bfee95bb83
@ -235,7 +235,9 @@ image-$(CONFIG_PPC_ADDER875) += cuImage.adder875-uboot \
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dtbImage.adder875-redboot
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# Board ports in arch/powerpc/platform/52xx/Kconfig
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image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 cuImage.lite5200b
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image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 lite5200.dtb
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image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200b lite5200b.dtb
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image-$(CONFIG_PPC_MEDIA5200) += cuImage.media5200 media5200.dtb
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# Board ports in arch/powerpc/platform/82xx/Kconfig
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image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads
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318
arch/powerpc/boot/dts/media5200.dts
Normal file
318
arch/powerpc/boot/dts/media5200.dts
Normal file
@ -0,0 +1,318 @@
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/*
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* Freescale Media5200 board Device Tree Source
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*
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* Copyright 2009 Secret Lab Technologies Ltd.
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* Grant Likely <grant.likely@secretlab.ca>
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* Steven Cavanagh <scavanagh@secretlab.ca>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "fsl,media5200";
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compatible = "fsl,media5200";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&mpc5200_pic>;
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aliases {
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console = &console;
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ethernet0 = ð0;
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};
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chosen {
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linux,stdout-path = &console;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,5200@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <0x4000>; // L1, 16K
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i-cache-size = <0x4000>; // L1, 16K
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timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
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bus-frequency = <132000000>; // 132 MHz
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clock-frequency = <396000000>; // 396 MHz
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x08000000>; // 128MB RAM
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};
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soc@f0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc5200b-immr";
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ranges = <0 0xf0000000 0x0000c000>;
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reg = <0xf0000000 0x00000100>;
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bus-frequency = <132000000>;// 132 MHz
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system-frequency = <0>; // from bootloader
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cdm@200 {
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compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
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reg = <0x200 0x38>;
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};
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mpc5200_pic: interrupt-controller@500 {
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// 5200 interrupts are encoded into two levels;
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interrupt-controller;
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#interrupt-cells = <3>;
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compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
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reg = <0x500 0x80>;
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};
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timer@600 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x600 0x10>;
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interrupts = <1 9 0>;
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fsl,has-wdt;
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};
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timer@610 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x610 0x10>;
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interrupts = <1 10 0>;
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};
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timer@620 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x620 0x10>;
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interrupts = <1 11 0>;
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};
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timer@630 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x630 0x10>;
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interrupts = <1 12 0>;
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};
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timer@640 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x640 0x10>;
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interrupts = <1 13 0>;
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};
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timer@650 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x650 0x10>;
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interrupts = <1 14 0>;
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};
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timer@660 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x660 0x10>;
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interrupts = <1 15 0>;
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};
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timer@670 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x670 0x10>;
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interrupts = <1 16 0>;
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};
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rtc@800 { // Real time clock
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compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
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reg = <0x800 0x100>;
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interrupts = <1 5 0 1 6 0>;
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};
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can@900 {
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compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
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interrupts = <2 17 0>;
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reg = <0x900 0x80>;
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};
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can@980 {
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compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
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interrupts = <2 18 0>;
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reg = <0x980 0x80>;
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};
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gpio_simple: gpio@b00 {
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compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
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reg = <0xb00 0x40>;
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interrupts = <1 7 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio_wkup: gpio@c00 {
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compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
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reg = <0xc00 0x40>;
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interrupts = <1 8 0 0 3 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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spi@f00 {
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compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
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reg = <0xf00 0x20>;
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interrupts = <2 13 0 2 14 0>;
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};
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usb@1000 {
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compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
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reg = <0x1000 0x100>;
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interrupts = <2 6 0>;
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};
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dma-controller@1200 {
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compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
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reg = <0x1200 0x80>;
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interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
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3 4 0 3 5 0 3 6 0 3 7 0
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3 8 0 3 9 0 3 10 0 3 11 0
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3 12 0 3 13 0 3 14 0 3 15 0>;
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};
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xlb@1f00 {
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compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
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reg = <0x1f00 0x100>;
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};
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// PSC6 in uart mode
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console: serial@2c00 { // PSC6
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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cell-index = <5>;
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port-number = <0>; // Logical port assignment
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reg = <0x2c00 0x100>;
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interrupts = <2 4 0>;
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};
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eth0: ethernet@3000 {
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compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
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reg = <0x3000 0x400>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <2 5 0>;
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phy-handle = <&phy0>;
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};
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mdio@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
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reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
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interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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ata@3a00 {
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compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
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reg = <0x3a00 0x100>;
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interrupts = <2 7 0>;
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};
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i2c@3d00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
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reg = <0x3d00 0x40>;
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interrupts = <2 15 0>;
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fsl5200-clocking;
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};
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i2c@3d40 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
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reg = <0x3d40 0x40>;
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interrupts = <2 16 0>;
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fsl5200-clocking;
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};
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sram@8000 {
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compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
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reg = <0x8000 0x4000>;
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};
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};
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pci@f0000d00 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
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reg = <0xf0000d00 0x100>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
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0xc000 0 0 2 &media5200_fpga 0 3
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0xc000 0 0 3 &media5200_fpga 0 4
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0xc000 0 0 4 &media5200_fpga 0 5
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0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
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0xc800 0 0 2 &media5200_fpga 0 4
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0xc800 0 0 3 &media5200_fpga 0 5
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0xc800 0 0 4 &media5200_fpga 0 2
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0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
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0xd000 0 0 2 &media5200_fpga 0 5
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0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
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>;
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clock-frequency = <0>; // From boot loader
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interrupts = <2 8 0 2 9 0 2 10 0>;
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interrupt-parent = <&mpc5200_pic>;
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bus-range = <0 0>;
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ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
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0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
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0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
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};
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localbus {
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compatible = "fsl,mpc5200b-lpb","simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = < 0 0 0xfc000000 0x02000000
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1 0 0xfe000000 0x02000000
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2 0 0xf0010000 0x00010000
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3 0 0xf0020000 0x00010000 >;
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flash@0,0 {
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compatible = "amd,am29lv28ml", "cfi-flash";
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reg = <0 0x0 0x2000000>; // 32 MB
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bank-width = <4>; // Width in bytes of the flash bank
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device-width = <2>; // Two devices on each bank
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};
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flash@1,0 {
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compatible = "amd,am29lv28ml", "cfi-flash";
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reg = <1 0 0x2000000>; // 32 MB
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bank-width = <4>; // Width in bytes of the flash bank
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device-width = <2>; // Two devices on each bank
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};
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media5200_fpga: fpga@2,0 {
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compatible = "fsl,media5200-fpga";
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interrupt-controller;
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#interrupt-cells = <2>; // 0:bank 1:id; no type field
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reg = <2 0 0x10000>;
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interrupt-parent = <&mpc5200_pic>;
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interrupts = <0 0 3 // IRQ bank 0
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1 1 3>; // IRQ bank 1
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};
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uart@3,0 {
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compatible = "ti,tl16c752bpt";
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reg = <3 0 0x10000>;
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interrupt-parent = <&media5200_fpga>;
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interrupts = <0 0 0 1>; // 2 irqs
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};
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};
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};
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@ -35,6 +35,11 @@ config PPC_LITE5200
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depends on PPC_MPC52xx
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select DEFAULT_UIMAGE
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config PPC_MEDIA5200
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bool "Freescale Media5200 Eval Board"
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depends on PPC_MPC52xx
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select DEFAULT_UIMAGE
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config PPC_MPC5200_BUGFIX
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bool "MPC5200 (L25R) bugfix support"
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depends on PPC_MPC52xx
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@ -7,6 +7,7 @@ obj-$(CONFIG_PCI) += mpc52xx_pci.o
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obj-$(CONFIG_PPC_MPC5200_SIMPLE) += mpc5200_simple.o
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obj-$(CONFIG_PPC_EFIKA) += efika.o
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obj-$(CONFIG_PPC_LITE5200) += lite5200.o
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obj-$(CONFIG_PPC_MEDIA5200) += media5200.o
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obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o
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ifeq ($(CONFIG_PPC_LITE5200),y)
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273
arch/powerpc/platforms/52xx/media5200.c
Normal file
273
arch/powerpc/platforms/52xx/media5200.c
Normal file
@ -0,0 +1,273 @@
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/*
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* Support for 'media5200-platform' compatible boards.
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*
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* Copyright (C) 2008 Secret Lab Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Description:
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* This code implements support for the Freescape Media5200 platform
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* (built around the MPC5200 SoC).
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*
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* Notable characteristic of the Media5200 is the presence of an FPGA
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* that has all external IRQ lines routed through it. This file implements
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* a cascaded interrupt controller driver which attaches itself to the
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* Virtual IRQ subsystem after the primary mpc5200 interrupt controller
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* is initialized.
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*
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*/
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#undef DEBUG
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/time.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/mpc52xx.h>
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static struct of_device_id mpc5200_gpio_ids[] __initdata = {
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{ .compatible = "fsl,mpc5200-gpio", },
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{ .compatible = "mpc5200-gpio", },
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{}
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};
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/* FPGA register set */
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#define MEDIA5200_IRQ_ENABLE (0x40c)
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#define MEDIA5200_IRQ_STATUS (0x410)
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#define MEDIA5200_NUM_IRQS (6)
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#define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
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struct media5200_irq {
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void __iomem *regs;
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spinlock_t lock;
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struct irq_host *irqhost;
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};
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struct media5200_irq media5200_irq;
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static void media5200_irq_unmask(unsigned int virq)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&media5200_irq.lock, flags);
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val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
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val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq);
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out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
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spin_unlock_irqrestore(&media5200_irq.lock, flags);
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}
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static void media5200_irq_mask(unsigned int virq)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&media5200_irq.lock, flags);
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val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
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val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq));
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out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
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spin_unlock_irqrestore(&media5200_irq.lock, flags);
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}
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static struct irq_chip media5200_irq_chip = {
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.typename = "Media5200 FPGA",
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.unmask = media5200_irq_unmask,
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.mask = media5200_irq_mask,
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.mask_ack = media5200_irq_mask,
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};
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void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
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{
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int sub_virq, val;
|
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u32 status, enable;
|
||||
|
||||
/* Mask off the cascaded IRQ */
|
||||
spin_lock(&desc->lock);
|
||||
desc->chip->mask(virq);
|
||||
spin_unlock(&desc->lock);
|
||||
|
||||
/* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs
|
||||
* are pending. 'ffs()' is 1 based */
|
||||
status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
|
||||
enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
|
||||
val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
|
||||
if (val) {
|
||||
sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
|
||||
/* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
|
||||
* __func__, virq, status, enable, val - 1, sub_virq);
|
||||
*/
|
||||
generic_handle_irq(sub_virq);
|
||||
}
|
||||
|
||||
/* Processing done; can reenable the cascade now */
|
||||
spin_lock(&desc->lock);
|
||||
desc->chip->ack(virq);
|
||||
if (!(desc->status & IRQ_DISABLED))
|
||||
desc->chip->unmask(virq);
|
||||
spin_unlock(&desc->lock);
|
||||
}
|
||||
|
||||
static int media5200_irq_map(struct irq_host *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
struct irq_desc *desc = get_irq_desc(virq);
|
||||
|
||||
pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
|
||||
set_irq_chip_data(virq, &media5200_irq);
|
||||
set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
|
||||
set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
|
||||
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
|
||||
desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct,
|
||||
u32 *intspec, unsigned int intsize,
|
||||
irq_hw_number_t *out_hwirq,
|
||||
unsigned int *out_flags)
|
||||
{
|
||||
if (intsize != 2)
|
||||
return -1;
|
||||
|
||||
pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
|
||||
*out_hwirq = intspec[1];
|
||||
*out_flags = IRQ_TYPE_NONE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_host_ops media5200_irq_ops = {
|
||||
.map = media5200_irq_map,
|
||||
.xlate = media5200_irq_xlate,
|
||||
};
|
||||
|
||||
/*
|
||||
* Setup Media5200 IRQ mapping
|
||||
*/
|
||||
static void __init media5200_init_irq(void)
|
||||
{
|
||||
struct device_node *fpga_np;
|
||||
int cascade_virq;
|
||||
|
||||
/* First setup the regular MPC5200 interrupt controller */
|
||||
mpc52xx_init_irq();
|
||||
|
||||
/* Now find the FPGA IRQ */
|
||||
fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
|
||||
if (!fpga_np)
|
||||
goto out;
|
||||
pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name);
|
||||
|
||||
media5200_irq.regs = of_iomap(fpga_np, 0);
|
||||
if (!media5200_irq.regs)
|
||||
goto out;
|
||||
pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
|
||||
|
||||
cascade_virq = irq_of_parse_and_map(fpga_np, 0);
|
||||
if (!cascade_virq)
|
||||
goto out;
|
||||
pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
|
||||
|
||||
/* Disable all FPGA IRQs */
|
||||
out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
|
||||
|
||||
spin_lock_init(&media5200_irq.lock);
|
||||
|
||||
media5200_irq.irqhost = irq_alloc_host(fpga_np, IRQ_HOST_MAP_LINEAR,
|
||||
MEDIA5200_NUM_IRQS,
|
||||
&media5200_irq_ops, -1);
|
||||
if (!media5200_irq.irqhost)
|
||||
goto out;
|
||||
pr_debug("%s: allocated irqhost\n", __func__);
|
||||
|
||||
media5200_irq.irqhost->host_data = &media5200_irq;
|
||||
|
||||
set_irq_data(cascade_virq, &media5200_irq);
|
||||
set_irq_chained_handler(cascade_virq, media5200_irq_cascade);
|
||||
|
||||
return;
|
||||
|
||||
out:
|
||||
pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup the architecture
|
||||
*/
|
||||
static void __init media5200_setup_arch(void)
|
||||
{
|
||||
|
||||
struct device_node *np;
|
||||
struct mpc52xx_gpio __iomem *gpio;
|
||||
u32 port_config;
|
||||
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress("media5200_setup_arch()", 0);
|
||||
|
||||
/* Map important registers from the internal memory map */
|
||||
mpc52xx_map_common_devices();
|
||||
|
||||
/* Some mpc5200 & mpc5200b related configuration */
|
||||
mpc5200_setup_xlb_arbiter();
|
||||
|
||||
mpc52xx_setup_pci();
|
||||
|
||||
np = of_find_matching_node(NULL, mpc5200_gpio_ids);
|
||||
gpio = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
if (!gpio) {
|
||||
printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set port config */
|
||||
port_config = in_be32(&gpio->port_config);
|
||||
|
||||
port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */
|
||||
port_config |= 0x01000000;
|
||||
|
||||
out_be32(&gpio->port_config, port_config);
|
||||
|
||||
/* Unmap zone */
|
||||
iounmap(gpio);
|
||||
|
||||
}
|
||||
|
||||
/* list of the supported boards */
|
||||
static char *board[] __initdata = {
|
||||
"fsl,media5200",
|
||||
NULL
|
||||
};
|
||||
|
||||
/*
|
||||
* Called very early, MMU is off, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init media5200_probe(void)
|
||||
{
|
||||
unsigned long node = of_get_flat_dt_root();
|
||||
int i = 0;
|
||||
|
||||
while (board[i]) {
|
||||
if (of_flat_dt_is_compatible(node, board[i]))
|
||||
break;
|
||||
i++;
|
||||
}
|
||||
|
||||
return (board[i] != NULL);
|
||||
}
|
||||
|
||||
define_machine(media5200_platform) {
|
||||
.name = "media5200-platform",
|
||||
.probe = media5200_probe,
|
||||
.setup_arch = media5200_setup_arch,
|
||||
.init = mpc52xx_declare_of_platform_devices,
|
||||
.init_IRQ = media5200_init_irq,
|
||||
.get_irq = mpc52xx_get_irq,
|
||||
.restart = mpc52xx_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user