mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-19 10:44:14 +08:00
Merge branch 'topic/owl' into for-linus
This commit is contained in:
Vinod Koul
commit
bfda902087
@ -21,6 +21,7 @@
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include <linux/slab.h>
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#include "virt-dma.h"
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@ -161,10 +162,12 @@ struct owl_dma_lli {
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* struct owl_dma_txd - Wrapper for struct dma_async_tx_descriptor
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* @vd: virtual DMA descriptor
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* @lli_list: link list of lli nodes
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* @cyclic: flag to indicate cyclic transfers
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*/
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struct owl_dma_txd {
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struct virt_dma_desc vd;
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struct list_head lli_list;
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bool cyclic;
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};
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/**
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@ -186,11 +189,15 @@ struct owl_dma_pchan {
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* @vc: wrappped virtual channel
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* @pchan: the physical channel utilized by this channel
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* @txd: active transaction on this channel
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* @cfg: slave configuration for this channel
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* @drq: physical DMA request ID for this channel
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*/
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struct owl_dma_vchan {
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struct virt_dma_chan vc;
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struct owl_dma_pchan *pchan;
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struct owl_dma_txd *txd;
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struct dma_slave_config cfg;
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u8 drq;
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};
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/**
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@ -200,6 +207,7 @@ struct owl_dma_vchan {
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* @clk: clock for the DMA controller
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* @lock: a lock to use when change DMA controller global register
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* @lli_pool: a pool for the LLI descriptors
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* @irq: interrupt ID for the DMA controller
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* @nr_pchans: the number of physical channels
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* @pchans: array of data for the physical channels
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* @nr_vchans: the number of physical channels
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@ -336,9 +344,11 @@ static struct owl_dma_lli *owl_dma_alloc_lli(struct owl_dma *od)
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static struct owl_dma_lli *owl_dma_add_lli(struct owl_dma_txd *txd,
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struct owl_dma_lli *prev,
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struct owl_dma_lli *next)
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struct owl_dma_lli *next,
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bool is_cyclic)
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{
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list_add_tail(&next->node, &txd->lli_list);
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if (!is_cyclic)
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list_add_tail(&next->node, &txd->lli_list);
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if (prev) {
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prev->hw.next_lli = next->phys;
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@ -351,7 +361,9 @@ static struct owl_dma_lli *owl_dma_add_lli(struct owl_dma_txd *txd,
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static inline int owl_dma_cfg_lli(struct owl_dma_vchan *vchan,
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struct owl_dma_lli *lli,
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dma_addr_t src, dma_addr_t dst,
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u32 len, enum dma_transfer_direction dir)
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u32 len, enum dma_transfer_direction dir,
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struct dma_slave_config *sconfig,
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bool is_cyclic)
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{
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struct owl_dma_lli_hw *hw = &lli->hw;
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u32 mode;
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@ -364,6 +376,32 @@ static inline int owl_dma_cfg_lli(struct owl_dma_vchan *vchan,
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OWL_DMA_MODE_DT_DCU | OWL_DMA_MODE_SAM_INC |
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OWL_DMA_MODE_DAM_INC;
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break;
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case DMA_MEM_TO_DEV:
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mode |= OWL_DMA_MODE_TS(vchan->drq)
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| OWL_DMA_MODE_ST_DCU | OWL_DMA_MODE_DT_DEV
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| OWL_DMA_MODE_SAM_INC | OWL_DMA_MODE_DAM_CONST;
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/*
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* Hardware only supports 32bit and 8bit buswidth. Since the
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* default is 32bit, select 8bit only when requested.
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*/
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if (sconfig->dst_addr_width == DMA_SLAVE_BUSWIDTH_1_BYTE)
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mode |= OWL_DMA_MODE_NDDBW_8BIT;
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break;
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case DMA_DEV_TO_MEM:
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mode |= OWL_DMA_MODE_TS(vchan->drq)
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| OWL_DMA_MODE_ST_DEV | OWL_DMA_MODE_DT_DCU
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| OWL_DMA_MODE_SAM_CONST | OWL_DMA_MODE_DAM_INC;
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/*
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* Hardware only supports 32bit and 8bit buswidth. Since the
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* default is 32bit, select 8bit only when requested.
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*/
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if (sconfig->src_addr_width == DMA_SLAVE_BUSWIDTH_1_BYTE)
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mode |= OWL_DMA_MODE_NDDBW_8BIT;
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break;
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default:
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return -EINVAL;
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@ -381,7 +419,10 @@ static inline int owl_dma_cfg_lli(struct owl_dma_vchan *vchan,
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OWL_DMA_LLC_SAV_LOAD_NEXT |
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OWL_DMA_LLC_DAV_LOAD_NEXT);
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hw->ctrlb = llc_hw_ctrlb(OWL_DMA_INTCTL_SUPER_BLOCK);
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if (is_cyclic)
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hw->ctrlb = llc_hw_ctrlb(OWL_DMA_INTCTL_BLOCK);
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else
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hw->ctrlb = llc_hw_ctrlb(OWL_DMA_INTCTL_SUPER_BLOCK);
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return 0;
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}
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@ -443,6 +484,16 @@ static void owl_dma_terminate_pchan(struct owl_dma *od,
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spin_unlock_irqrestore(&od->lock, flags);
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}
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static void owl_dma_pause_pchan(struct owl_dma_pchan *pchan)
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{
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pchan_writel(pchan, 1, OWL_DMAX_PAUSE);
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}
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static void owl_dma_resume_pchan(struct owl_dma_pchan *pchan)
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{
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pchan_writel(pchan, 0, OWL_DMAX_PAUSE);
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}
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static int owl_dma_start_next_txd(struct owl_dma_vchan *vchan)
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{
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struct owl_dma *od = to_owl_dma(vchan->vc.chan.device);
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@ -464,7 +515,10 @@ static int owl_dma_start_next_txd(struct owl_dma_vchan *vchan)
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lli = list_first_entry(&txd->lli_list,
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struct owl_dma_lli, node);
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int_ctl = OWL_DMA_INTCTL_SUPER_BLOCK;
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if (txd->cyclic)
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int_ctl = OWL_DMA_INTCTL_BLOCK;
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else
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int_ctl = OWL_DMA_INTCTL_SUPER_BLOCK;
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pchan_writel(pchan, OWL_DMAX_MODE, OWL_DMA_MODE_LME);
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pchan_writel(pchan, OWL_DMAX_LINKLIST_CTL,
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@ -627,6 +681,54 @@ static int owl_dma_terminate_all(struct dma_chan *chan)
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return 0;
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}
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static int owl_dma_config(struct dma_chan *chan,
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struct dma_slave_config *config)
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{
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struct owl_dma_vchan *vchan = to_owl_vchan(chan);
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/* Reject definitely invalid configurations */
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if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
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config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
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return -EINVAL;
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memcpy(&vchan->cfg, config, sizeof(struct dma_slave_config));
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return 0;
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}
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static int owl_dma_pause(struct dma_chan *chan)
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{
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struct owl_dma_vchan *vchan = to_owl_vchan(chan);
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unsigned long flags;
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spin_lock_irqsave(&vchan->vc.lock, flags);
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owl_dma_pause_pchan(vchan->pchan);
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spin_unlock_irqrestore(&vchan->vc.lock, flags);
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return 0;
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}
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static int owl_dma_resume(struct dma_chan *chan)
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{
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struct owl_dma_vchan *vchan = to_owl_vchan(chan);
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unsigned long flags;
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if (!vchan->pchan && !vchan->txd)
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return 0;
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dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc);
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spin_lock_irqsave(&vchan->vc.lock, flags);
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owl_dma_resume_pchan(vchan->pchan);
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spin_unlock_irqrestore(&vchan->vc.lock, flags);
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return 0;
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}
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static u32 owl_dma_getbytes_chan(struct owl_dma_vchan *vchan)
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{
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struct owl_dma_pchan *pchan;
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@ -754,13 +856,14 @@ static struct dma_async_tx_descriptor
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bytes = min_t(size_t, (len - offset), OWL_DMA_FRAME_MAX_LENGTH);
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ret = owl_dma_cfg_lli(vchan, lli, src + offset, dst + offset,
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bytes, DMA_MEM_TO_MEM);
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bytes, DMA_MEM_TO_MEM,
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&vchan->cfg, txd->cyclic);
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if (ret) {
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dev_warn(chan2dev(chan), "failed to config lli\n");
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goto err_txd_free;
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}
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prev = owl_dma_add_lli(txd, prev, lli);
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prev = owl_dma_add_lli(txd, prev, lli, false);
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}
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return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
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@ -770,6 +873,133 @@ err_txd_free:
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return NULL;
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}
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static struct dma_async_tx_descriptor
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*owl_dma_prep_slave_sg(struct dma_chan *chan,
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struct scatterlist *sgl,
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unsigned int sg_len,
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enum dma_transfer_direction dir,
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unsigned long flags, void *context)
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{
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struct owl_dma *od = to_owl_dma(chan->device);
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struct owl_dma_vchan *vchan = to_owl_vchan(chan);
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struct dma_slave_config *sconfig = &vchan->cfg;
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struct owl_dma_txd *txd;
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struct owl_dma_lli *lli, *prev = NULL;
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struct scatterlist *sg;
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dma_addr_t addr, src = 0, dst = 0;
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size_t len;
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int ret, i;
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txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
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if (!txd)
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return NULL;
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INIT_LIST_HEAD(&txd->lli_list);
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for_each_sg(sgl, sg, sg_len, i) {
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addr = sg_dma_address(sg);
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len = sg_dma_len(sg);
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if (len > OWL_DMA_FRAME_MAX_LENGTH) {
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dev_err(od->dma.dev,
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"frame length exceeds max supported length");
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goto err_txd_free;
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}
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lli = owl_dma_alloc_lli(od);
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if (!lli) {
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dev_err(chan2dev(chan), "failed to allocate lli");
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goto err_txd_free;
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}
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if (dir == DMA_MEM_TO_DEV) {
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src = addr;
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dst = sconfig->dst_addr;
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} else {
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src = sconfig->src_addr;
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dst = addr;
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}
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ret = owl_dma_cfg_lli(vchan, lli, src, dst, len, dir, sconfig,
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txd->cyclic);
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if (ret) {
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dev_warn(chan2dev(chan), "failed to config lli");
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goto err_txd_free;
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}
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prev = owl_dma_add_lli(txd, prev, lli, false);
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}
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return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
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err_txd_free:
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owl_dma_free_txd(od, txd);
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return NULL;
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}
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static struct dma_async_tx_descriptor
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*owl_prep_dma_cyclic(struct dma_chan *chan,
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dma_addr_t buf_addr, size_t buf_len,
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size_t period_len,
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enum dma_transfer_direction dir,
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unsigned long flags)
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{
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struct owl_dma *od = to_owl_dma(chan->device);
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struct owl_dma_vchan *vchan = to_owl_vchan(chan);
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struct dma_slave_config *sconfig = &vchan->cfg;
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struct owl_dma_txd *txd;
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struct owl_dma_lli *lli, *prev = NULL, *first = NULL;
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dma_addr_t src = 0, dst = 0;
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unsigned int periods = buf_len / period_len;
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int ret, i;
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txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
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if (!txd)
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return NULL;
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INIT_LIST_HEAD(&txd->lli_list);
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txd->cyclic = true;
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for (i = 0; i < periods; i++) {
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lli = owl_dma_alloc_lli(od);
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if (!lli) {
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dev_warn(chan2dev(chan), "failed to allocate lli");
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goto err_txd_free;
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}
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if (dir == DMA_MEM_TO_DEV) {
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src = buf_addr + (period_len * i);
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dst = sconfig->dst_addr;
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} else if (dir == DMA_DEV_TO_MEM) {
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src = sconfig->src_addr;
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dst = buf_addr + (period_len * i);
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}
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ret = owl_dma_cfg_lli(vchan, lli, src, dst, period_len,
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dir, sconfig, txd->cyclic);
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if (ret) {
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dev_warn(chan2dev(chan), "failed to config lli");
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goto err_txd_free;
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}
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if (!first)
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first = lli;
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prev = owl_dma_add_lli(txd, prev, lli, false);
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}
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/* close the cyclic list */
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owl_dma_add_lli(txd, prev, first, true);
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return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
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err_txd_free:
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owl_dma_free_txd(od, txd);
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return NULL;
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}
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static void owl_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct owl_dma_vchan *vchan = to_owl_vchan(chan);
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@ -790,6 +1020,27 @@ static inline void owl_dma_free(struct owl_dma *od)
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}
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}
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static struct dma_chan *owl_dma_of_xlate(struct of_phandle_args *dma_spec,
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struct of_dma *ofdma)
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{
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struct owl_dma *od = ofdma->of_dma_data;
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struct owl_dma_vchan *vchan;
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struct dma_chan *chan;
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u8 drq = dma_spec->args[0];
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if (drq > od->nr_vchans)
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return NULL;
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chan = dma_get_any_slave_channel(&od->dma);
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if (!chan)
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return NULL;
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vchan = to_owl_vchan(chan);
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vchan->drq = drq;
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return chan;
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}
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static int owl_dma_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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@ -833,12 +1084,19 @@ static int owl_dma_probe(struct platform_device *pdev)
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spin_lock_init(&od->lock);
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dma_cap_set(DMA_MEMCPY, od->dma.cap_mask);
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dma_cap_set(DMA_SLAVE, od->dma.cap_mask);
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dma_cap_set(DMA_CYCLIC, od->dma.cap_mask);
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od->dma.dev = &pdev->dev;
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od->dma.device_free_chan_resources = owl_dma_free_chan_resources;
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od->dma.device_tx_status = owl_dma_tx_status;
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od->dma.device_issue_pending = owl_dma_issue_pending;
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od->dma.device_prep_dma_memcpy = owl_dma_prep_memcpy;
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od->dma.device_prep_slave_sg = owl_dma_prep_slave_sg;
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od->dma.device_prep_dma_cyclic = owl_prep_dma_cyclic;
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od->dma.device_config = owl_dma_config;
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od->dma.device_pause = owl_dma_pause;
|
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od->dma.device_resume = owl_dma_resume;
|
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od->dma.device_terminate_all = owl_dma_terminate_all;
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od->dma.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
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od->dma.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
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@ -910,8 +1168,18 @@ static int owl_dma_probe(struct platform_device *pdev)
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goto err_pool_free;
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}
|
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|
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/* Device-tree DMA controller registration */
|
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ret = of_dma_controller_register(pdev->dev.of_node,
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owl_dma_of_xlate, od);
|
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if (ret) {
|
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dev_err(&pdev->dev, "of_dma_controller_register failed\n");
|
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goto err_dma_unregister;
|
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}
|
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|
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return 0;
|
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|
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err_dma_unregister:
|
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dma_async_device_unregister(&od->dma);
|
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err_pool_free:
|
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clk_disable_unprepare(od->clk);
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dma_pool_destroy(od->lli_pool);
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@ -923,6 +1191,7 @@ static int owl_dma_remove(struct platform_device *pdev)
|
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{
|
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struct owl_dma *od = platform_get_drvdata(pdev);
|
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|
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of_dma_controller_free(pdev->dev.of_node);
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dma_async_device_unregister(&od->dma);
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/* Mask all interrupts for this execution environment */
|
||||
|
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