mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-22 20:23:57 +08:00
drm/amdgpu/VCN2.0: add DPG mode start and stop (v2)
This is for using SRAM directly v2: rebase (Alex) Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leo Liu
Alex Deucher
parent
19c663fc77
commit
bf4865b587
@ -66,6 +66,11 @@
|
||||
|
||||
#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
|
||||
|
||||
#define mmUVD_RBC_XX_IB_REG_CHECK 0x026b
|
||||
#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1
|
||||
#define mmUVD_REG_XX_MASK 0x026c
|
||||
#define mmUVD_REG_XX_MASK_BASE_IDX 1
|
||||
|
||||
static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
|
||||
static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
|
||||
static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
|
||||
@ -257,7 +262,8 @@ static int vcn_v2_0_hw_init(void *handle)
|
||||
|
||||
done:
|
||||
if (!r)
|
||||
DRM_INFO("VCN decode and encode initialized successfully.\n");
|
||||
DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
|
||||
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
|
||||
|
||||
return r;
|
||||
}
|
||||
@ -275,8 +281,9 @@ static int vcn_v2_0_hw_fini(void *handle)
|
||||
struct amdgpu_ring *ring = &adev->vcn.ring_dec;
|
||||
int i;
|
||||
|
||||
if (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
|
||||
RREG32_SOC15(VCN, 0, mmUVD_STATUS))
|
||||
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
|
||||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
|
||||
RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
|
||||
vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
|
||||
|
||||
ring->sched.ready = false;
|
||||
@ -389,6 +396,77 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
|
||||
WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
|
||||
}
|
||||
|
||||
static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
|
||||
{
|
||||
uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
|
||||
uint32_t offset;
|
||||
|
||||
/* cache window 0: fw */
|
||||
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
|
||||
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
|
||||
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
|
||||
offset = 0;
|
||||
} else {
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
|
||||
lower_32_bits(adev->vcn.gpu_addr), 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
|
||||
upper_32_bits(adev->vcn.gpu_addr), 0, indirect);
|
||||
offset = size;
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
|
||||
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
|
||||
}
|
||||
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
|
||||
|
||||
/* cache window 1: stack */
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
|
||||
lower_32_bits(adev->vcn.gpu_addr + offset), 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
|
||||
upper_32_bits(adev->vcn.gpu_addr + offset), 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
|
||||
|
||||
/* cache window 2: context */
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
|
||||
lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
|
||||
upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
|
||||
|
||||
/* non-cache window */
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
|
||||
|
||||
/* VCN global tiling registers */
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
|
||||
}
|
||||
|
||||
/**
|
||||
* vcn_v2_0_disable_clock_gating - disable VCN clock gating
|
||||
*
|
||||
@ -499,6 +577,54 @@ static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
|
||||
WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
|
||||
}
|
||||
|
||||
static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
|
||||
uint8_t sram_sel, uint8_t indirect)
|
||||
{
|
||||
uint32_t reg_data = 0;
|
||||
|
||||
/* enable sw clock gating control */
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
|
||||
reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
|
||||
else
|
||||
reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
|
||||
reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
|
||||
reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
|
||||
reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
|
||||
UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
|
||||
UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
|
||||
UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
|
||||
UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
|
||||
UVD_CGC_CTRL__SYS_MODE_MASK |
|
||||
UVD_CGC_CTRL__UDEC_MODE_MASK |
|
||||
UVD_CGC_CTRL__MPEG2_MODE_MASK |
|
||||
UVD_CGC_CTRL__REGS_MODE_MASK |
|
||||
UVD_CGC_CTRL__RBC_MODE_MASK |
|
||||
UVD_CGC_CTRL__LMI_MC_MODE_MASK |
|
||||
UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
|
||||
UVD_CGC_CTRL__IDCT_MODE_MASK |
|
||||
UVD_CGC_CTRL__MPRD_MODE_MASK |
|
||||
UVD_CGC_CTRL__MPC_MODE_MASK |
|
||||
UVD_CGC_CTRL__LBSI_MODE_MASK |
|
||||
UVD_CGC_CTRL__LRBBM_MODE_MASK |
|
||||
UVD_CGC_CTRL__WCB_MODE_MASK |
|
||||
UVD_CGC_CTRL__VCPU_MODE_MASK |
|
||||
UVD_CGC_CTRL__SCPU_MODE_MASK);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
|
||||
|
||||
/* turn off clock gating */
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
|
||||
|
||||
/* turn on SUVD clock gating */
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
|
||||
|
||||
/* turn on sw mode in UVD_SUVD_CGC_CTRL */
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
|
||||
}
|
||||
|
||||
/**
|
||||
* jpeg_v2_0_start - start JPEG block
|
||||
*
|
||||
@ -768,6 +894,124 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
|
||||
}
|
||||
}
|
||||
|
||||
static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
|
||||
{
|
||||
struct amdgpu_ring *ring = &adev->vcn.ring_dec;
|
||||
uint32_t rb_bufsz, tmp;
|
||||
|
||||
vcn_v2_0_enable_static_power_gating(adev);
|
||||
|
||||
/* enable dynamic power gating mode */
|
||||
tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
|
||||
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
|
||||
tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
|
||||
WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
|
||||
|
||||
/* enable clock gating */
|
||||
vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
|
||||
|
||||
/* enable VCPU clock */
|
||||
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
|
||||
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
|
||||
tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
|
||||
|
||||
/* disable master interupt */
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
|
||||
|
||||
/* setup mmUVD_LMI_CTRL */
|
||||
tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
|
||||
UVD_LMI_CTRL__REQ_MODE_MASK |
|
||||
UVD_LMI_CTRL__CRC_RESET_MASK |
|
||||
UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
|
||||
UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
|
||||
UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
|
||||
(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
|
||||
0x00100000L);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
|
||||
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_MPC_CNTL),
|
||||
0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
|
||||
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_MPC_SET_MUXA0),
|
||||
((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
|
||||
(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
|
||||
(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
|
||||
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
|
||||
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_MPC_SET_MUXB0),
|
||||
((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
|
||||
(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
|
||||
(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
|
||||
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
|
||||
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_MPC_SET_MUX),
|
||||
((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
|
||||
(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
|
||||
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
|
||||
|
||||
vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
|
||||
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
|
||||
|
||||
/* release VCPU reset to boot */
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
|
||||
|
||||
/* enable LMI MC and UMC channels */
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_LMI_CTRL2),
|
||||
0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
|
||||
|
||||
/* enable master interrupt */
|
||||
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
|
||||
UVD, 0, mmUVD_MASTINT_EN),
|
||||
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
|
||||
|
||||
/* force RBC into idle state */
|
||||
rb_bufsz = order_base_2(ring->ring_size);
|
||||
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
|
||||
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
|
||||
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
|
||||
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
|
||||
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
|
||||
|
||||
/* set the write pointer delay */
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
|
||||
|
||||
/* set the wb address */
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
|
||||
(upper_32_bits(ring->gpu_addr) >> 2));
|
||||
|
||||
/* programm the RB_BASE for ring buffer */
|
||||
WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
|
||||
lower_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
|
||||
upper_32_bits(ring->gpu_addr));
|
||||
|
||||
/* Initialize the ring buffer's read and write pointers */
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
|
||||
|
||||
WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
|
||||
|
||||
ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
|
||||
lower_32_bits(ring->wptr));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vcn_v2_0_start(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_ring *ring = &adev->vcn.ring_dec;
|
||||
@ -778,6 +1022,13 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
|
||||
if (adev->pm.dpm_enabled)
|
||||
amdgpu_dpm_enable_uvd(adev, true);
|
||||
|
||||
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
|
||||
r = vcn_v2_0_start_dpg_mode(adev, 0);
|
||||
if (r)
|
||||
return r;
|
||||
goto jpeg;
|
||||
}
|
||||
|
||||
vcn_v2_0_disable_static_power_gating(adev);
|
||||
|
||||
/* set uvd status busy */
|
||||
@ -928,11 +1179,44 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
|
||||
|
||||
jpeg:
|
||||
r = jpeg_v2_0_start(adev);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
|
||||
{
|
||||
int ret_code = 0;
|
||||
uint32_t tmp;
|
||||
|
||||
/* Wait for power status to be 1 */
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
|
||||
/* wait for read ptr to be equal to write ptr */
|
||||
tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
|
||||
|
||||
tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
|
||||
|
||||
tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
|
||||
|
||||
tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
|
||||
|
||||
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
|
||||
|
||||
/* disable dynamic power gating mode */
|
||||
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
|
||||
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vcn_v2_0_stop(struct amdgpu_device *adev)
|
||||
{
|
||||
uint32_t tmp;
|
||||
@ -941,6 +1225,14 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
|
||||
r = jpeg_v2_0_stop(adev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
|
||||
r = vcn_v2_0_stop_dpg_mode(adev);
|
||||
if (r)
|
||||
return r;
|
||||
goto power_off;
|
||||
}
|
||||
|
||||
/* wait for uvd idle */
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
|
||||
if (r)
|
||||
@ -990,6 +1282,7 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
|
||||
vcn_v2_0_enable_clock_gating(adev);
|
||||
vcn_v2_0_enable_static_power_gating(adev);
|
||||
|
||||
power_off:
|
||||
if (adev->pm.dpm_enabled)
|
||||
amdgpu_dpm_enable_uvd(adev, false);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user