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Code

clk: JZ4780: Reformat the code to align it.

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Reformat the code (add one level of indentation before the values),
to align the code in the macro definition section.

Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20200630163852.47267-3-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
周琰杰 (Zhou Yanjie) 2020-07-01 00:38:51 +08:00 committed by Stephen Boyd
parent dcd062a88e
commit beb61eb068
1 changed files with 45 additions and 45 deletions
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90
drivers/clk/ingenic/jz4780-cgu.c
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@ -20,50 +20,50 @@
/* CGU register offsets */ /* CGU register offsets */
#define CGU_REG_CLOCKCONTROL 0x00 #define CGU_REG_CLOCKCONTROL 0x00
#define CGU_REG_LCR 0x04 #define CGU_REG_LCR 0x04
#define CGU_REG_APLL 0x10 #define CGU_REG_APLL 0x10
#define CGU_REG_MPLL 0x14 #define CGU_REG_MPLL 0x14
#define CGU_REG_EPLL 0x18 #define CGU_REG_EPLL 0x18
#define CGU_REG_VPLL 0x1c #define CGU_REG_VPLL 0x1c
#define CGU_REG_CLKGR0 0x20 #define CGU_REG_CLKGR0 0x20
#define CGU_REG_OPCR 0x24 #define CGU_REG_OPCR 0x24
#define CGU_REG_CLKGR1 0x28 #define CGU_REG_CLKGR1 0x28
#define CGU_REG_DDRCDR 0x2c #define CGU_REG_DDRCDR 0x2c
#define CGU_REG_VPUCDR 0x30 #define CGU_REG_VPUCDR 0x30
#define CGU_REG_USBPCR 0x3c #define CGU_REG_USBPCR 0x3c
#define CGU_REG_USBRDT 0x40 #define CGU_REG_USBRDT 0x40
#define CGU_REG_USBVBFIL 0x44 #define CGU_REG_USBVBFIL 0x44
#define CGU_REG_USBPCR1 0x48 #define CGU_REG_USBPCR1 0x48
#define CGU_REG_LP0CDR 0x54 #define CGU_REG_LP0CDR 0x54
#define CGU_REG_I2SCDR 0x60 #define CGU_REG_I2SCDR 0x60
#define CGU_REG_LP1CDR 0x64 #define CGU_REG_LP1CDR 0x64
#define CGU_REG_MSC0CDR 0x68 #define CGU_REG_MSC0CDR 0x68
#define CGU_REG_UHCCDR 0x6c #define CGU_REG_UHCCDR 0x6c
#define CGU_REG_SSICDR 0x74 #define CGU_REG_SSICDR 0x74
#define CGU_REG_CIMCDR 0x7c #define CGU_REG_CIMCDR 0x7c
#define CGU_REG_PCMCDR 0x84 #define CGU_REG_PCMCDR 0x84
#define CGU_REG_GPUCDR 0x88 #define CGU_REG_GPUCDR 0x88
#define CGU_REG_HDMICDR 0x8c #define CGU_REG_HDMICDR 0x8c
#define CGU_REG_MSC1CDR 0xa4 #define CGU_REG_MSC1CDR 0xa4
#define CGU_REG_MSC2CDR 0xa8 #define CGU_REG_MSC2CDR 0xa8
#define CGU_REG_BCHCDR 0xac #define CGU_REG_BCHCDR 0xac
#define CGU_REG_CLOCKSTATUS 0xd4 #define CGU_REG_CLOCKSTATUS 0xd4
/* bits within the OPCR register */ /* bits within the OPCR register */
#define OPCR_SPENDN0 BIT(7) #define OPCR_SPENDN0 BIT(7)
#define OPCR_SPENDN1 BIT(6) #define OPCR_SPENDN1 BIT(6)
/* bits within the USBPCR register */ /* bits within the USBPCR register */
#define USBPCR_USB_MODE BIT(31) #define USBPCR_USB_MODE BIT(31)
#define USBPCR_IDPULLUP_MASK (0x3 << 28) #define USBPCR_IDPULLUP_MASK (0x3 << 28)
#define USBPCR_COMMONONN BIT(25) #define USBPCR_COMMONONN BIT(25)
#define USBPCR_VBUSVLDEXT BIT(24) #define USBPCR_VBUSVLDEXT BIT(24)
#define USBPCR_VBUSVLDEXTSEL BIT(23) #define USBPCR_VBUSVLDEXTSEL BIT(23)
#define USBPCR_POR BIT(22) #define USBPCR_POR BIT(22)
#define USBPCR_SIDDQ BIT(21) #define USBPCR_SIDDQ BIT(21)
#define USBPCR_OTG_DISABLE BIT(20) #define USBPCR_OTG_DISABLE BIT(20)
#define USBPCR_COMPDISTUNE_MASK (0x7 << 17) #define USBPCR_COMPDISTUNE_MASK (0x7 << 17)
#define USBPCR_OTGTUNE_MASK (0x7 << 14) #define USBPCR_OTGTUNE_MASK (0x7 << 14)
#define USBPCR_SQRXTUNE_MASK (0x7 << 11) #define USBPCR_SQRXTUNE_MASK (0x7 << 11)
#define USBPCR_TXFSLSTUNE_MASK (0xf << 7) #define USBPCR_TXFSLSTUNE_MASK (0xf << 7)
#define USBPCR_TXPREEMPHTUNE BIT(6) #define USBPCR_TXPREEMPHTUNE BIT(6)
@ -80,13 +80,13 @@
#define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT) #define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT) #define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT) #define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_USB_SEL BIT(28) #define USBPCR1_USB_SEL BIT(28)
#define USBPCR1_WORD_IF0 BIT(19) #define USBPCR1_WORD_IF0 BIT(19)
#define USBPCR1_WORD_IF1 BIT(18) #define USBPCR1_WORD_IF1 BIT(18)
/* bits within the USBRDT register */ /* bits within the USBRDT register */
#define USBRDT_VBFIL_LD_EN BIT(25) #define USBRDT_VBFIL_LD_EN BIT(25)
#define USBRDT_USBRDT_MASK 0x7fffff #define USBRDT_USBRDT_MASK 0x7fffff
/* bits within the USBVBFIL register */ /* bits within the USBVBFIL register */
#define USBVBFIL_IDDIGFIL_SHIFT 16 #define USBVBFIL_IDDIGFIL_SHIFT 16
@ -94,11 +94,11 @@
#define USBVBFIL_USBVBFIL_MASK (0xffff) #define USBVBFIL_USBVBFIL_MASK (0xffff)
/* bits within the LCR register */ /* bits within the LCR register */
#define LCR_PD_SCPU BIT(31) #define LCR_PD_SCPU BIT(31)
#define LCR_SCPUS BIT(27) #define LCR_SCPUS BIT(27)
/* bits within the CLKGR1 register */ /* bits within the CLKGR1 register */
#define CLKGR1_CORE1 BIT(15) #define CLKGR1_CORE1 BIT(15)
static struct ingenic_cgu *cgu; static struct ingenic_cgu *cgu;