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media: hantro: Add support for VP8 decoding on rk3288
Introduce VP8 decoding support in RK3288. Signed-off-by: ZhiChao Yu <zhichao.yu@rock-chips.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:
ZhiChao Yu
Mauro Carvalho Chehab
parent
298c62d385
commit
bdd034050a
@ -5,10 +5,12 @@ hantro-vpu-y += \
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hantro_v4l2.o \
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hantro_h1_jpeg_enc.o \
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hantro_g1_mpeg2_dec.o \
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hantro_g1_vp8_dec.o \
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rk3399_vpu_hw_jpeg_enc.o \
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rk3399_vpu_hw_mpeg2_dec.o \
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hantro_jpeg.o \
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hantro_mpeg2.o
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hantro_mpeg2.o \
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hantro_vp8.o
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hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \
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rk3288_vpu_hw.o \
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@ -25,6 +25,10 @@
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#include "hantro_hw.h"
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#define VP8_MB_DIM 16
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#define VP8_MB_WIDTH(w) DIV_ROUND_UP(w, VP8_MB_DIM)
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#define VP8_MB_HEIGHT(h) DIV_ROUND_UP(h, VP8_MB_DIM)
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#define MPEG2_MB_DIM 16
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#define MPEG2_MB_WIDTH(w) DIV_ROUND_UP(w, MPEG2_MB_DIM)
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#define MPEG2_MB_HEIGHT(h) DIV_ROUND_UP(h, MPEG2_MB_DIM)
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@ -40,6 +44,7 @@ struct hantro_codec_ops;
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#define HANTRO_ENCODERS 0x0000ffff
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#define HANTRO_MPEG2_DECODER BIT(16)
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#define HANTRO_VP8_DECODER BIT(17)
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#define HANTRO_DECODERS 0xffff0000
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/**
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@ -97,11 +102,13 @@ struct hantro_variant {
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* @HANTRO_MODE_NONE: No operating mode. Used for RAW video formats.
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* @HANTRO_MODE_JPEG_ENC: JPEG encoder.
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* @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
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* @HANTRO_MODE_VP8_DEC: VP8 decoder.
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*/
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enum hantro_codec_mode {
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HANTRO_MODE_NONE = -1,
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HANTRO_MODE_JPEG_ENC,
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HANTRO_MODE_MPEG2_DEC,
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HANTRO_MODE_VP8_DEC,
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};
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/*
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@ -215,6 +222,7 @@ struct hantro_dev {
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* @codec_ops: Set of operations related to codec mode.
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* @jpeg_enc: JPEG-encoding context.
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* @mpeg2_dec: MPEG-2-decoding context.
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* @vp8_dec: VP8-decoding context.
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*/
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struct hantro_ctx {
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struct hantro_dev *dev;
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@ -241,6 +249,7 @@ struct hantro_ctx {
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union {
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struct hantro_jpeg_enc_hw_ctx jpeg_enc;
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struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;
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struct hantro_vp8_dec_hw_ctx vp8_dec;
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};
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};
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@ -265,6 +274,12 @@ struct hantro_fmt {
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struct v4l2_frmsize_stepwise frmsize;
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};
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struct hantro_reg {
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u32 base;
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u32 shift;
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u32 mask;
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};
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/* Logging helpers */
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/**
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@ -343,6 +358,18 @@ static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
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return val;
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}
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static inline void hantro_reg_write(struct hantro_dev *vpu,
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const struct hantro_reg *reg,
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u32 val)
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{
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u32 v;
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v = vdpu_read(vpu, reg->base);
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v &= ~(reg->mask << reg->shift);
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v |= ((val & reg->mask) << reg->shift);
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vdpu_write_relaxed(vpu, v, reg->base);
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}
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bool hantro_is_encoder_ctx(const struct hantro_ctx *ctx);
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void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);
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@ -284,6 +284,12 @@ static struct hantro_ctrl controls[] = {
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.cfg = {
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.elem_size = sizeof(struct v4l2_ctrl_mpeg2_quantization),
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},
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}, {
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.id = V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER,
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.codec = HANTRO_VP8_DECODER,
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.cfg = {
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.elem_size = sizeof(struct v4l2_ctrl_vp8_frame_header),
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},
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},
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};
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526
drivers/staging/media/hantro/hantro_g1_vp8_dec.c
Normal file
526
drivers/staging/media/hantro/hantro_g1_vp8_dec.c
Normal file
@ -0,0 +1,526 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Hantro VP8 codec driver
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*
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* Copyright (C) 2019 Rockchip Electronics Co., Ltd.
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* ZhiChao Yu <zhichao.yu@rock-chips.com>
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*
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* Copyright (C) 2019 Google, Inc.
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* Tomasz Figa <tfiga@chromium.org>
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*/
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#include <media/v4l2-mem2mem.h>
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#include <media/vp8-ctrls.h>
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#include "hantro_hw.h"
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#include "hantro.h"
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#include "hantro_g1_regs.h"
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#define DEC_8190_ALIGN_MASK 0x07U
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/* DCT partition base address regs */
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static const struct hantro_reg vp8_dec_dct_base[8] = {
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{ G1_REG_ADDR_STR, 0, 0xffffffff },
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{ G1_REG_ADDR_REF(8), 0, 0xffffffff },
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{ G1_REG_ADDR_REF(9), 0, 0xffffffff },
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{ G1_REG_ADDR_REF(10), 0, 0xffffffff },
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{ G1_REG_ADDR_REF(11), 0, 0xffffffff },
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{ G1_REG_ADDR_REF(12), 0, 0xffffffff },
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{ G1_REG_ADDR_REF(14), 0, 0xffffffff },
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{ G1_REG_ADDR_REF(15), 0, 0xffffffff },
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};
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/* Loop filter level regs */
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static const struct hantro_reg vp8_dec_lf_level[4] = {
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{ G1_REG_REF_PIC(2), 18, 0x3f },
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{ G1_REG_REF_PIC(2), 12, 0x3f },
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{ G1_REG_REF_PIC(2), 6, 0x3f },
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{ G1_REG_REF_PIC(2), 0, 0x3f },
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};
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/* Macroblock loop filter level adjustment regs */
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static const struct hantro_reg vp8_dec_mb_adj[4] = {
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{ G1_REG_REF_PIC(0), 21, 0x7f },
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{ G1_REG_REF_PIC(0), 14, 0x7f },
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{ G1_REG_REF_PIC(0), 7, 0x7f },
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{ G1_REG_REF_PIC(0), 0, 0x7f },
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};
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/* Reference frame adjustment regs */
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static const struct hantro_reg vp8_dec_ref_adj[4] = {
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{ G1_REG_REF_PIC(1), 21, 0x7f },
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{ G1_REG_REF_PIC(1), 14, 0x7f },
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{ G1_REG_REF_PIC(1), 7, 0x7f },
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{ G1_REG_REF_PIC(1), 0, 0x7f },
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};
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/* Quantizer */
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static const struct hantro_reg vp8_dec_quant[4] = {
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{ G1_REG_REF_PIC(3), 11, 0x7ff },
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{ G1_REG_REF_PIC(3), 0, 0x7ff },
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{ G1_REG_BD_REF_PIC(4), 11, 0x7ff },
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{ G1_REG_BD_REF_PIC(4), 0, 0x7ff },
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};
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/* Quantizer delta regs */
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static const struct hantro_reg vp8_dec_quant_delta[5] = {
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{ G1_REG_REF_PIC(3), 27, 0x1f },
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{ G1_REG_REF_PIC(3), 22, 0x1f },
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{ G1_REG_BD_REF_PIC(4), 27, 0x1f },
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{ G1_REG_BD_REF_PIC(4), 22, 0x1f },
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{ G1_REG_BD_P_REF_PIC, 27, 0x1f },
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};
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/* DCT partition start bits regs */
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static const struct hantro_reg vp8_dec_dct_start_bits[8] = {
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{ G1_REG_DEC_CTRL2, 26, 0x3f }, { G1_REG_DEC_CTRL4, 26, 0x3f },
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{ G1_REG_DEC_CTRL4, 20, 0x3f }, { G1_REG_DEC_CTRL7, 24, 0x3f },
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{ G1_REG_DEC_CTRL7, 18, 0x3f }, { G1_REG_DEC_CTRL7, 12, 0x3f },
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{ G1_REG_DEC_CTRL7, 6, 0x3f }, { G1_REG_DEC_CTRL7, 0, 0x3f },
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};
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/* Precision filter tap regs */
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static const struct hantro_reg vp8_dec_pred_bc_tap[8][4] = {
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{
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{ G1_REG_PRED_FLT, 22, 0x3ff },
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{ G1_REG_PRED_FLT, 12, 0x3ff },
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{ G1_REG_PRED_FLT, 2, 0x3ff },
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{ G1_REG_REF_PIC(4), 22, 0x3ff },
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},
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{
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{ G1_REG_REF_PIC(4), 12, 0x3ff },
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{ G1_REG_REF_PIC(4), 2, 0x3ff },
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{ G1_REG_REF_PIC(5), 22, 0x3ff },
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{ G1_REG_REF_PIC(5), 12, 0x3ff },
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},
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{
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{ G1_REG_REF_PIC(5), 2, 0x3ff },
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{ G1_REG_REF_PIC(6), 22, 0x3ff },
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{ G1_REG_REF_PIC(6), 12, 0x3ff },
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{ G1_REG_REF_PIC(6), 2, 0x3ff },
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},
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{
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{ G1_REG_REF_PIC(7), 22, 0x3ff },
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{ G1_REG_REF_PIC(7), 12, 0x3ff },
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{ G1_REG_REF_PIC(7), 2, 0x3ff },
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{ G1_REG_LT_REF, 22, 0x3ff },
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},
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{
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{ G1_REG_LT_REF, 12, 0x3ff },
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{ G1_REG_LT_REF, 2, 0x3ff },
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{ G1_REG_VALID_REF, 22, 0x3ff },
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{ G1_REG_VALID_REF, 12, 0x3ff },
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},
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{
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{ G1_REG_VALID_REF, 2, 0x3ff },
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{ G1_REG_BD_REF_PIC(0), 22, 0x3ff },
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{ G1_REG_BD_REF_PIC(0), 12, 0x3ff },
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{ G1_REG_BD_REF_PIC(0), 2, 0x3ff },
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},
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{
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{ G1_REG_BD_REF_PIC(1), 22, 0x3ff },
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{ G1_REG_BD_REF_PIC(1), 12, 0x3ff },
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{ G1_REG_BD_REF_PIC(1), 2, 0x3ff },
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{ G1_REG_BD_REF_PIC(2), 22, 0x3ff },
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},
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{
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{ G1_REG_BD_REF_PIC(2), 12, 0x3ff },
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{ G1_REG_BD_REF_PIC(2), 2, 0x3ff },
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{ G1_REG_BD_REF_PIC(3), 22, 0x3ff },
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{ G1_REG_BD_REF_PIC(3), 12, 0x3ff },
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},
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};
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/*
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* filter taps taken to 7-bit precision,
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* reference RFC6386#Page-16, filters[8][6]
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*/
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static const u32 vp8_dec_mc_filter[8][6] = {
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{ 0, 0, 128, 0, 0, 0 },
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{ 0, -6, 123, 12, -1, 0 },
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{ 2, -11, 108, 36, -8, 1 },
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{ 0, -9, 93, 50, -6, 0 },
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{ 3, -16, 77, 77, -16, 3 },
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{ 0, -6, 50, 93, -9, 0 },
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{ 1, -8, 36, 108, -11, 2 },
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{ 0, -1, 12, 123, -6, 0 }
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};
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/*
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* Set loop filters
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*/
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static void cfg_lf(struct hantro_ctx *ctx,
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const struct v4l2_ctrl_vp8_frame_header *hdr)
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{
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const struct v4l2_vp8_segment_header *seg = &hdr->segment_header;
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const struct v4l2_vp8_loopfilter_header *lf = &hdr->lf_header;
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struct hantro_dev *vpu = ctx->dev;
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unsigned int i;
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u32 reg;
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if (!(seg->flags & V4L2_VP8_SEGMENT_HEADER_FLAG_ENABLED)) {
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hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level);
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} else if (seg->flags & V4L2_VP8_SEGMENT_HEADER_FLAG_DELTA_VALUE_MODE) {
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for (i = 0; i < 4; i++) {
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u32 lf_level = clamp(lf->level + seg->lf_update[i],
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0, 63);
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hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level);
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}
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} else {
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for (i = 0; i < 4; i++)
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hantro_reg_write(vpu, &vp8_dec_lf_level[i],
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seg->lf_update[i]);
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}
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reg = G1_REG_REF_PIC_FILT_SHARPNESS(lf->sharpness_level);
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if (lf->flags & V4L2_VP8_LF_FILTER_TYPE_SIMPLE)
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reg |= G1_REG_REF_PIC_FILT_TYPE_E;
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vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0));
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if (lf->flags & V4L2_VP8_LF_HEADER_ADJ_ENABLE) {
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for (i = 0; i < 4; i++) {
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hantro_reg_write(vpu, &vp8_dec_mb_adj[i],
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lf->mb_mode_delta[i]);
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hantro_reg_write(vpu, &vp8_dec_ref_adj[i],
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lf->ref_frm_delta[i]);
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}
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}
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}
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/*
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* Set quantization parameters
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*/
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static void cfg_qp(struct hantro_ctx *ctx,
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const struct v4l2_ctrl_vp8_frame_header *hdr)
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{
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const struct v4l2_vp8_quantization_header *q = &hdr->quant_header;
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const struct v4l2_vp8_segment_header *seg = &hdr->segment_header;
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struct hantro_dev *vpu = ctx->dev;
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unsigned int i;
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if (!(seg->flags & V4L2_VP8_SEGMENT_HEADER_FLAG_ENABLED)) {
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hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi);
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} else if (seg->flags & V4L2_VP8_SEGMENT_HEADER_FLAG_DELTA_VALUE_MODE) {
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for (i = 0; i < 4; i++) {
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u32 quant = clamp(q->y_ac_qi + seg->quant_update[i],
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0, 127);
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hantro_reg_write(vpu, &vp8_dec_quant[i], quant);
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}
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} else {
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for (i = 0; i < 4; i++)
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hantro_reg_write(vpu, &vp8_dec_quant[i],
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seg->quant_update[i]);
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}
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hantro_reg_write(vpu, &vp8_dec_quant_delta[0], q->y_dc_delta);
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hantro_reg_write(vpu, &vp8_dec_quant_delta[1], q->y2_dc_delta);
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hantro_reg_write(vpu, &vp8_dec_quant_delta[2], q->y2_ac_delta);
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hantro_reg_write(vpu, &vp8_dec_quant_delta[3], q->uv_dc_delta);
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hantro_reg_write(vpu, &vp8_dec_quant_delta[4], q->uv_ac_delta);
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}
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/*
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* set control partition and DCT partition regs
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*
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* VP8 frame stream data layout:
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*
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* first_part_size parttion_sizes[0]
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* ^ ^
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* src_dma | |
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* ^ +--------+------+ +-----+-----+
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* | | control part | | |
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* +--------+----------------+------------------+-----------+-----+-----------+
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* | tag 3B | extra 7B | hdr | mb_data | DCT sz | DCT part0 | ... | DCT partn |
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* +--------+-----------------------------------+-----------+-----+-----------+
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* | | | |
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* v +----+---+ v
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* mb_start | src_dma_end
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* v
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* DCT size part
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* (num_dct-1)*3B
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* Note:
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* 1. only key-frames have extra 7-bytes
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* 2. all offsets are base on src_dma
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* 3. number of DCT parts is 1, 2, 4 or 8
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* 4. the addresses set to the VPU must be 64-bits aligned
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*/
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static void cfg_parts(struct hantro_ctx *ctx,
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const struct v4l2_ctrl_vp8_frame_header *hdr)
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{
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struct hantro_dev *vpu = ctx->dev;
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struct vb2_v4l2_buffer *vb2_src;
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u32 first_part_offset = VP8_FRAME_IS_KEY_FRAME(hdr) ? 10 : 3;
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u32 mb_size, mb_offset_bytes, mb_offset_bits, mb_start_bits;
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u32 dct_size_part_size, dct_part_offset;
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struct hantro_reg reg;
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dma_addr_t src_dma;
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u32 dct_part_total_len = 0;
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u32 count = 0;
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unsigned int i;
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vb2_src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
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src_dma = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0);
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/*
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* Calculate control partition mb data info
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* @first_part_header_bits: bits offset of mb data from first
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||||
* part start pos
|
||||
* @mb_offset_bits: bits offset of mb data from src_dma
|
||||
* base addr
|
||||
* @mb_offset_byte: bytes offset of mb data from src_dma
|
||||
* base addr
|
||||
* @mb_start_bits: bits offset of mb data from mb data
|
||||
* 64bits alignment addr
|
||||
*/
|
||||
mb_offset_bits = first_part_offset * 8 +
|
||||
hdr->first_part_header_bits + 8;
|
||||
mb_offset_bytes = mb_offset_bits / 8;
|
||||
mb_start_bits = mb_offset_bits -
|
||||
(mb_offset_bytes & (~DEC_8190_ALIGN_MASK)) * 8;
|
||||
mb_size = hdr->first_part_size -
|
||||
(mb_offset_bytes - first_part_offset) +
|
||||
(mb_offset_bytes & DEC_8190_ALIGN_MASK);
|
||||
|
||||
/* Macroblock data aligned base addr */
|
||||
vdpu_write_relaxed(vpu, (mb_offset_bytes & (~DEC_8190_ALIGN_MASK))
|
||||
+ src_dma, G1_REG_ADDR_REF(13));
|
||||
|
||||
/* Macroblock data start bits */
|
||||
reg.base = G1_REG_DEC_CTRL2;
|
||||
reg.mask = 0x3f;
|
||||
reg.shift = 18;
|
||||
hantro_reg_write(vpu, ®, mb_start_bits);
|
||||
|
||||
/* Macroblock aligned data length */
|
||||
reg.base = G1_REG_DEC_CTRL6;
|
||||
reg.mask = 0x3fffff;
|
||||
reg.shift = 0;
|
||||
hantro_reg_write(vpu, ®, mb_size + 1);
|
||||
|
||||
/*
|
||||
* Calculate DCT partition info
|
||||
* @dct_size_part_size: Containing sizes of DCT part, every DCT part
|
||||
* has 3 bytes to store its size, except the last
|
||||
* DCT part
|
||||
* @dct_part_offset: bytes offset of DCT parts from src_dma base addr
|
||||
* @dct_part_total_len: total size of all DCT parts
|
||||
*/
|
||||
dct_size_part_size = (hdr->num_dct_parts - 1) * 3;
|
||||
dct_part_offset = first_part_offset + hdr->first_part_size;
|
||||
for (i = 0; i < hdr->num_dct_parts; i++)
|
||||
dct_part_total_len += hdr->dct_part_sizes[i];
|
||||
dct_part_total_len += dct_size_part_size;
|
||||
dct_part_total_len += (dct_part_offset & DEC_8190_ALIGN_MASK);
|
||||
|
||||
/* Number of DCT partitions */
|
||||
reg.base = G1_REG_DEC_CTRL6;
|
||||
reg.mask = 0xf;
|
||||
reg.shift = 24;
|
||||
hantro_reg_write(vpu, ®, hdr->num_dct_parts - 1);
|
||||
|
||||
/* DCT partition length */
|
||||
vdpu_write_relaxed(vpu,
|
||||
G1_REG_DEC_CTRL3_STREAM_LEN(dct_part_total_len),
|
||||
G1_REG_DEC_CTRL3);
|
||||
|
||||
/* DCT partitions base address */
|
||||
for (i = 0; i < hdr->num_dct_parts; i++) {
|
||||
u32 byte_offset = dct_part_offset + dct_size_part_size + count;
|
||||
u32 base_addr = byte_offset + src_dma;
|
||||
|
||||
hantro_reg_write(vpu, &vp8_dec_dct_base[i],
|
||||
base_addr & (~DEC_8190_ALIGN_MASK));
|
||||
|
||||
hantro_reg_write(vpu, &vp8_dec_dct_start_bits[i],
|
||||
(byte_offset & DEC_8190_ALIGN_MASK) * 8);
|
||||
|
||||
count += hdr->dct_part_sizes[i];
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* prediction filter taps
|
||||
* normal 6-tap filters
|
||||
*/
|
||||
static void cfg_tap(struct hantro_ctx *ctx,
|
||||
const struct v4l2_ctrl_vp8_frame_header *hdr)
|
||||
{
|
||||
struct hantro_dev *vpu = ctx->dev;
|
||||
struct hantro_reg reg;
|
||||
u32 val = 0;
|
||||
int i, j;
|
||||
|
||||
reg.base = G1_REG_BD_REF_PIC(3);
|
||||
reg.mask = 0xf;
|
||||
|
||||
if ((hdr->version & 0x03) != 0)
|
||||
return; /* Tap filter not used. */
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
val = (vp8_dec_mc_filter[i][0] << 2) | vp8_dec_mc_filter[i][5];
|
||||
|
||||
for (j = 0; j < 4; j++)
|
||||
hantro_reg_write(vpu, &vp8_dec_pred_bc_tap[i][j],
|
||||
vp8_dec_mc_filter[i][j + 1]);
|
||||
|
||||
switch (i) {
|
||||
case 2:
|
||||
reg.shift = 8;
|
||||
break;
|
||||
case 4:
|
||||
reg.shift = 4;
|
||||
break;
|
||||
case 6:
|
||||
reg.shift = 0;
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
|
||||
hantro_reg_write(vpu, ®, val);
|
||||
}
|
||||
}
|
||||
|
||||
static void cfg_ref(struct hantro_ctx *ctx,
|
||||
const struct v4l2_ctrl_vp8_frame_header *hdr)
|
||||
{
|
||||
struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q;
|
||||
struct hantro_dev *vpu = ctx->dev;
|
||||
struct vb2_v4l2_buffer *vb2_dst;
|
||||
dma_addr_t ref;
|
||||
|
||||
vb2_dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
|
||||
|
||||
ref = hantro_get_ref(cap_q, hdr->last_frame_ts);
|
||||
if (!ref)
|
||||
ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0);
|
||||
vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(0));
|
||||
|
||||
ref = hantro_get_ref(cap_q, hdr->golden_frame_ts);
|
||||
WARN_ON(!ref && hdr->golden_frame_ts);
|
||||
if (!ref)
|
||||
ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0);
|
||||
if (hdr->flags & V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_GOLDEN)
|
||||
ref |= G1_REG_ADDR_REF_TOPC_E;
|
||||
vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(4));
|
||||
|
||||
ref = hantro_get_ref(cap_q, hdr->alt_frame_ts);
|
||||
WARN_ON(!ref && hdr->alt_frame_ts);
|
||||
if (!ref)
|
||||
ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0);
|
||||
if (hdr->flags & V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_ALT)
|
||||
ref |= G1_REG_ADDR_REF_TOPC_E;
|
||||
vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(5));
|
||||
}
|
||||
|
||||
static void cfg_buffers(struct hantro_ctx *ctx,
|
||||
const struct v4l2_ctrl_vp8_frame_header *hdr)
|
||||
{
|
||||
const struct v4l2_vp8_segment_header *seg = &hdr->segment_header;
|
||||
struct hantro_dev *vpu = ctx->dev;
|
||||
struct vb2_v4l2_buffer *vb2_dst;
|
||||
dma_addr_t dst_dma;
|
||||
u32 reg;
|
||||
|
||||
vb2_dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
|
||||
|
||||
/* Set probability table buffer address */
|
||||
vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma,
|
||||
G1_REG_ADDR_QTABLE);
|
||||
|
||||
/* Set segment map address */
|
||||
reg = G1_REG_FWD_PIC1_SEGMENT_BASE(ctx->vp8_dec.segment_map.dma);
|
||||
if (seg->flags & V4L2_VP8_SEGMENT_HEADER_FLAG_ENABLED) {
|
||||
reg |= G1_REG_FWD_PIC1_SEGMENT_E;
|
||||
if (seg->flags & V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_MAP)
|
||||
reg |= G1_REG_FWD_PIC1_SEGMENT_UPD_E;
|
||||
}
|
||||
vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(0));
|
||||
|
||||
dst_dma = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0);
|
||||
vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DST);
|
||||
}
|
||||
|
||||
void hantro_g1_vp8_dec_run(struct hantro_ctx *ctx)
|
||||
{
|
||||
const struct v4l2_ctrl_vp8_frame_header *hdr;
|
||||
struct hantro_dev *vpu = ctx->dev;
|
||||
size_t height = ctx->dst_fmt.height;
|
||||
size_t width = ctx->dst_fmt.width;
|
||||
struct vb2_v4l2_buffer *vb2_src;
|
||||
u32 mb_width, mb_height;
|
||||
u32 reg;
|
||||
|
||||
vb2_src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
|
||||
v4l2_ctrl_request_setup(vb2_src->vb2_buf.req_obj.req,
|
||||
&ctx->ctrl_handler);
|
||||
|
||||
hdr = hantro_get_ctrl(ctx, V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER);
|
||||
if (WARN_ON(!hdr))
|
||||
return;
|
||||
|
||||
/* Reset segment_map buffer in keyframe */
|
||||
if (VP8_FRAME_IS_KEY_FRAME(hdr) && ctx->vp8_dec.segment_map.cpu)
|
||||
memset(ctx->vp8_dec.segment_map.cpu, 0,
|
||||
ctx->vp8_dec.segment_map.size);
|
||||
|
||||
hantro_vp8_prob_update(ctx, hdr);
|
||||
|
||||
reg = G1_REG_CONFIG_DEC_TIMEOUT_E |
|
||||
G1_REG_CONFIG_DEC_STRENDIAN_E |
|
||||
G1_REG_CONFIG_DEC_INSWAP32_E |
|
||||
G1_REG_CONFIG_DEC_STRSWAP32_E |
|
||||
G1_REG_CONFIG_DEC_OUTSWAP32_E |
|
||||
G1_REG_CONFIG_DEC_CLK_GATE_E |
|
||||
G1_REG_CONFIG_DEC_IN_ENDIAN |
|
||||
G1_REG_CONFIG_DEC_OUT_ENDIAN |
|
||||
G1_REG_CONFIG_DEC_MAX_BURST(16);
|
||||
vdpu_write_relaxed(vpu, reg, G1_REG_CONFIG);
|
||||
|
||||
reg = G1_REG_DEC_CTRL0_DEC_MODE(10);
|
||||
if (!VP8_FRAME_IS_KEY_FRAME(hdr))
|
||||
reg |= G1_REG_DEC_CTRL0_PIC_INTER_E;
|
||||
if (!(hdr->flags & V4L2_VP8_FRAME_HEADER_FLAG_MB_NO_SKIP_COEFF))
|
||||
reg |= G1_REG_DEC_CTRL0_SKIP_MODE;
|
||||
if (hdr->lf_header.level == 0)
|
||||
reg |= G1_REG_DEC_CTRL0_FILTERING_DIS;
|
||||
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0);
|
||||
|
||||
/* Frame dimensions */
|
||||
mb_width = VP8_MB_WIDTH(width);
|
||||
mb_height = VP8_MB_HEIGHT(height);
|
||||
reg = G1_REG_DEC_CTRL1_PIC_MB_WIDTH(mb_width) |
|
||||
G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(mb_height) |
|
||||
G1_REG_DEC_CTRL1_PIC_MB_W_EXT(mb_width >> 9) |
|
||||
G1_REG_DEC_CTRL1_PIC_MB_H_EXT(mb_height >> 8);
|
||||
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1);
|
||||
|
||||
/* Boolean decoder */
|
||||
reg = G1_REG_DEC_CTRL2_BOOLEAN_RANGE(hdr->coder_state.range)
|
||||
| G1_REG_DEC_CTRL2_BOOLEAN_VALUE(hdr->coder_state.value);
|
||||
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2);
|
||||
|
||||
reg = 0;
|
||||
if (hdr->version != 3)
|
||||
reg |= G1_REG_DEC_CTRL4_VC1_HEIGHT_EXT;
|
||||
if (hdr->version & 0x3)
|
||||
reg |= G1_REG_DEC_CTRL4_BILIN_MC_E;
|
||||
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4);
|
||||
|
||||
cfg_lf(ctx, hdr);
|
||||
cfg_qp(ctx, hdr);
|
||||
cfg_parts(ctx, hdr);
|
||||
cfg_tap(ctx, hdr);
|
||||
cfg_ref(ctx, hdr);
|
||||
cfg_buffers(ctx, hdr);
|
||||
|
||||
/* Controls no longer in-use, we can complete them */
|
||||
v4l2_ctrl_request_complete(vb2_src->vb2_buf.req_obj.req,
|
||||
&ctx->ctrl_handler);
|
||||
|
||||
schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000));
|
||||
|
||||
vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT);
|
||||
}
|
||||
@ -12,6 +12,7 @@
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/v4l2-controls.h>
|
||||
#include <media/mpeg2-ctrls.h>
|
||||
#include <media/vp8-ctrls.h>
|
||||
#include <media/videobuf2-core.h>
|
||||
|
||||
struct hantro_dev;
|
||||
@ -47,6 +48,16 @@ struct hantro_mpeg2_dec_hw_ctx {
|
||||
struct hantro_aux_buf qtable;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hantro_vp8d_hw_ctx
|
||||
* @segment_map: Segment map buffer.
|
||||
* @prob_tbl: Probability table buffer.
|
||||
*/
|
||||
struct hantro_vp8_dec_hw_ctx {
|
||||
struct hantro_aux_buf segment_map;
|
||||
struct hantro_aux_buf prob_tbl;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hantro_codec_ops - codec mode specific operations
|
||||
*
|
||||
@ -99,4 +110,10 @@ void hantro_mpeg2_dec_copy_qtable(u8 *qtable,
|
||||
int hantro_mpeg2_dec_init(struct hantro_ctx *ctx);
|
||||
void hantro_mpeg2_dec_exit(struct hantro_ctx *ctx);
|
||||
|
||||
void hantro_g1_vp8_dec_run(struct hantro_ctx *ctx);
|
||||
int hantro_vp8_dec_init(struct hantro_ctx *ctx);
|
||||
void hantro_vp8_dec_exit(struct hantro_ctx *ctx);
|
||||
void hantro_vp8_prob_update(struct hantro_ctx *ctx,
|
||||
const struct v4l2_ctrl_vp8_frame_header *hdr);
|
||||
|
||||
#endif /* HANTRO_HW_H_ */
|
||||
|
||||
@ -344,6 +344,7 @@ hantro_update_requires_request(struct hantro_ctx *ctx, u32 fourcc)
|
||||
ctx->fh.m2m_ctx->out_q_ctx.q.requires_requests = false;
|
||||
break;
|
||||
case V4L2_PIX_FMT_MPEG2_SLICE:
|
||||
case V4L2_PIX_FMT_VP8_FRAME:
|
||||
ctx->fh.m2m_ctx->out_q_ctx.q.requires_requests = true;
|
||||
break;
|
||||
default:
|
||||
|
||||
188
drivers/staging/media/hantro/hantro_vp8.c
Normal file
188
drivers/staging/media/hantro/hantro_vp8.c
Normal file
@ -0,0 +1,188 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Hantro VPU codec driver
|
||||
*
|
||||
* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "hantro.h"
|
||||
|
||||
/*
|
||||
* probs table with packed
|
||||
*/
|
||||
struct vp8_prob_tbl_packed {
|
||||
u8 prob_mb_skip_false;
|
||||
u8 prob_intra;
|
||||
u8 prob_ref_last;
|
||||
u8 prob_ref_golden;
|
||||
u8 prob_segment[3];
|
||||
u8 padding0;
|
||||
|
||||
u8 prob_luma_16x16_pred_mode[4];
|
||||
u8 prob_chroma_pred_mode[3];
|
||||
u8 padding1;
|
||||
|
||||
/* mv prob */
|
||||
u8 prob_mv_context[2][19];
|
||||
u8 padding2[2];
|
||||
|
||||
/* coeff probs */
|
||||
u8 prob_coeffs[4][8][3][11];
|
||||
u8 padding3[96];
|
||||
};
|
||||
|
||||
void hantro_vp8_prob_update(struct hantro_ctx *ctx,
|
||||
const struct v4l2_ctrl_vp8_frame_header *hdr)
|
||||
{
|
||||
const struct v4l2_vp8_entropy_header *entropy = &hdr->entropy_header;
|
||||
u32 i, j, k;
|
||||
u8 *dst;
|
||||
|
||||
/* first probs */
|
||||
dst = ctx->vp8_dec.prob_tbl.cpu;
|
||||
|
||||
dst[0] = hdr->prob_skip_false;
|
||||
dst[1] = hdr->prob_intra;
|
||||
dst[2] = hdr->prob_last;
|
||||
dst[3] = hdr->prob_gf;
|
||||
dst[4] = hdr->segment_header.segment_probs[0];
|
||||
dst[5] = hdr->segment_header.segment_probs[1];
|
||||
dst[6] = hdr->segment_header.segment_probs[2];
|
||||
dst[7] = 0;
|
||||
|
||||
dst += 8;
|
||||
dst[0] = entropy->y_mode_probs[0];
|
||||
dst[1] = entropy->y_mode_probs[1];
|
||||
dst[2] = entropy->y_mode_probs[2];
|
||||
dst[3] = entropy->y_mode_probs[3];
|
||||
dst[4] = entropy->uv_mode_probs[0];
|
||||
dst[5] = entropy->uv_mode_probs[1];
|
||||
dst[6] = entropy->uv_mode_probs[2];
|
||||
dst[7] = 0; /*unused */
|
||||
|
||||
/* mv probs */
|
||||
dst += 8;
|
||||
dst[0] = entropy->mv_probs[0][0]; /* is short */
|
||||
dst[1] = entropy->mv_probs[1][0];
|
||||
dst[2] = entropy->mv_probs[0][1]; /* sign */
|
||||
dst[3] = entropy->mv_probs[1][1];
|
||||
dst[4] = entropy->mv_probs[0][8 + 9];
|
||||
dst[5] = entropy->mv_probs[0][9 + 9];
|
||||
dst[6] = entropy->mv_probs[1][8 + 9];
|
||||
dst[7] = entropy->mv_probs[1][9 + 9];
|
||||
dst += 8;
|
||||
for (i = 0; i < 2; ++i) {
|
||||
for (j = 0; j < 8; j += 4) {
|
||||
dst[0] = entropy->mv_probs[i][j + 9 + 0];
|
||||
dst[1] = entropy->mv_probs[i][j + 9 + 1];
|
||||
dst[2] = entropy->mv_probs[i][j + 9 + 2];
|
||||
dst[3] = entropy->mv_probs[i][j + 9 + 3];
|
||||
dst += 4;
|
||||
}
|
||||
}
|
||||
for (i = 0; i < 2; ++i) {
|
||||
dst[0] = entropy->mv_probs[i][0 + 2];
|
||||
dst[1] = entropy->mv_probs[i][1 + 2];
|
||||
dst[2] = entropy->mv_probs[i][2 + 2];
|
||||
dst[3] = entropy->mv_probs[i][3 + 2];
|
||||
dst[4] = entropy->mv_probs[i][4 + 2];
|
||||
dst[5] = entropy->mv_probs[i][5 + 2];
|
||||
dst[6] = entropy->mv_probs[i][6 + 2];
|
||||
dst[7] = 0; /*unused */
|
||||
dst += 8;
|
||||
}
|
||||
|
||||
/* coeff probs (header part) */
|
||||
dst = ctx->vp8_dec.prob_tbl.cpu;
|
||||
dst += (8 * 7);
|
||||
for (i = 0; i < 4; ++i) {
|
||||
for (j = 0; j < 8; ++j) {
|
||||
for (k = 0; k < 3; ++k) {
|
||||
dst[0] = entropy->coeff_probs[i][j][k][0];
|
||||
dst[1] = entropy->coeff_probs[i][j][k][1];
|
||||
dst[2] = entropy->coeff_probs[i][j][k][2];
|
||||
dst[3] = entropy->coeff_probs[i][j][k][3];
|
||||
dst += 4;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* coeff probs (footer part) */
|
||||
dst = ctx->vp8_dec.prob_tbl.cpu;
|
||||
dst += (8 * 55);
|
||||
for (i = 0; i < 4; ++i) {
|
||||
for (j = 0; j < 8; ++j) {
|
||||
for (k = 0; k < 3; ++k) {
|
||||
dst[0] = entropy->coeff_probs[i][j][k][4];
|
||||
dst[1] = entropy->coeff_probs[i][j][k][5];
|
||||
dst[2] = entropy->coeff_probs[i][j][k][6];
|
||||
dst[3] = entropy->coeff_probs[i][j][k][7];
|
||||
dst[4] = entropy->coeff_probs[i][j][k][8];
|
||||
dst[5] = entropy->coeff_probs[i][j][k][9];
|
||||
dst[6] = entropy->coeff_probs[i][j][k][10];
|
||||
dst[7] = 0; /*unused */
|
||||
dst += 8;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int hantro_vp8_dec_init(struct hantro_ctx *ctx)
|
||||
{
|
||||
struct hantro_dev *vpu = ctx->dev;
|
||||
struct hantro_aux_buf *aux_buf;
|
||||
unsigned int mb_width, mb_height;
|
||||
size_t segment_map_size;
|
||||
int ret;
|
||||
|
||||
/* segment map table size calculation */
|
||||
mb_width = DIV_ROUND_UP(ctx->dst_fmt.width, 16);
|
||||
mb_height = DIV_ROUND_UP(ctx->dst_fmt.height, 16);
|
||||
segment_map_size = round_up(DIV_ROUND_UP(mb_width * mb_height, 4), 64);
|
||||
|
||||
/*
|
||||
* In context init the dma buffer for segment map must be allocated.
|
||||
* And the data in segment map buffer must be set to all zero.
|
||||
*/
|
||||
aux_buf = &ctx->vp8_dec.segment_map;
|
||||
aux_buf->size = segment_map_size;
|
||||
aux_buf->cpu = dma_alloc_coherent(vpu->dev, aux_buf->size,
|
||||
&aux_buf->dma, GFP_KERNEL);
|
||||
if (!aux_buf->cpu)
|
||||
return -ENOMEM;
|
||||
|
||||
memset(aux_buf->cpu, 0, aux_buf->size);
|
||||
|
||||
/*
|
||||
* Allocate probability table buffer,
|
||||
* total 1208 bytes, 4K page is far enough.
|
||||
*/
|
||||
aux_buf = &ctx->vp8_dec.prob_tbl;
|
||||
aux_buf->size = sizeof(struct vp8_prob_tbl_packed);
|
||||
aux_buf->cpu = dma_alloc_coherent(vpu->dev, aux_buf->size,
|
||||
&aux_buf->dma, GFP_KERNEL);
|
||||
if (!aux_buf->cpu) {
|
||||
ret = -ENOMEM;
|
||||
goto err_free_seg_map;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_seg_map:
|
||||
dma_free_coherent(vpu->dev, ctx->vp8_dec.segment_map.size,
|
||||
ctx->vp8_dec.segment_map.cpu,
|
||||
ctx->vp8_dec.segment_map.dma);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void hantro_vp8_dec_exit(struct hantro_ctx *ctx)
|
||||
{
|
||||
struct hantro_vp8_dec_hw_ctx *vp8_dec = &ctx->vp8_dec;
|
||||
struct hantro_dev *vpu = ctx->dev;
|
||||
|
||||
dma_free_coherent(vpu->dev, vp8_dec->segment_map.size,
|
||||
vp8_dec->segment_map.cpu, vp8_dec->segment_map.dma);
|
||||
dma_free_coherent(vpu->dev, vp8_dec->prob_tbl.size,
|
||||
vp8_dec->prob_tbl.cpu, vp8_dec->prob_tbl.dma);
|
||||
}
|
||||
@ -74,6 +74,19 @@ static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
|
||||
.step_height = MPEG2_MB_DIM,
|
||||
},
|
||||
},
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_VP8_FRAME,
|
||||
.codec_mode = HANTRO_MODE_VP8_DEC,
|
||||
.max_depth = 2,
|
||||
.frmsize = {
|
||||
.min_width = 48,
|
||||
.max_width = 3840,
|
||||
.step_width = VP8_MB_DIM,
|
||||
.min_height = 48,
|
||||
.max_height = 2160,
|
||||
.step_height = VP8_MB_DIM,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static irqreturn_t rk3288_vepu_irq(int irq, void *dev_id)
|
||||
@ -155,6 +168,12 @@ static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
|
||||
.init = hantro_mpeg2_dec_init,
|
||||
.exit = hantro_mpeg2_dec_exit,
|
||||
},
|
||||
[HANTRO_MODE_VP8_DEC] = {
|
||||
.run = hantro_g1_vp8_dec_run,
|
||||
.reset = rk3288_vpu_dec_reset,
|
||||
.init = hantro_vp8_dec_init,
|
||||
.exit = hantro_vp8_dec_exit,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
@ -177,7 +196,8 @@ const struct hantro_variant rk3288_vpu_variant = {
|
||||
.dec_offset = 0x400,
|
||||
.dec_fmts = rk3288_vpu_dec_fmts,
|
||||
.num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
|
||||
.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER,
|
||||
.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
|
||||
HANTRO_VP8_DECODER,
|
||||
.codec_ops = rk3288_vpu_codec_ops,
|
||||
.irqs = rk3288_irqs,
|
||||
.num_irqs = ARRAY_SIZE(rk3288_irqs),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user