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arm: Xilinx Zynq DT fixes for v3.18

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- Fix gem register size
 - Fix OPP
 - Add missing references
 - Trivial cleanup
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Merge tag 'zynq-dt-fixes-for-3.18' of https://github.com/Xilinx/linux-xlnx into fixes

Merge "Xilinx Zynq dt fixes for v3.18" from Michal Simek:

arm: Xilinx Zynq DT fixes for v3.18
- Fix gem register size
- Fix OPP
- Add missing references
- Trivial cleanup

* tag 'zynq-dt-fixes-for-3.18' of https://github.com/Xilinx/linux-xlnx:
  ARM: zynq: DT: trivial: Fix mc node
  ARM: zynq: DT: Add cadence watchdog node
  ARM: zynq: DT: Add missing reference for memory-controller
  ARM: zynq: DT: Add missing reference for ADC
  ARM: zynq: DT: Add missing address for L2 pl310
  ARM: zynq: DT: Remove 222 MHz OPP
  ARM: zynq: DT: Fix GEM register area size

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-10-23 21:01:02 -07:00
commit bcd09f17cb
1 changed files with 17 additions and 7 deletions
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24
arch/arm/boot/dts/zynq-7000.dtsi
View File

@ -30,7 +30,6 @@
/* kHz uV */
666667 1000000
333334 1000000
222223 1000000
>;
};
@ -65,7 +64,7 @@
interrupt-parent = <&intc>;
ranges;
adc@f8007100 {
adc: adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0 7 4>;
@ -137,7 +136,7 @@
<0xF8F00100 0x100>;
};
L2: cache-controller {
L2: cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
arm,data-latency = <3 2 2>;
@ -146,10 +145,10 @@
cache-level = <2>;
};
memory-controller@f8006000 {
mc: memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
} ;
};
uart0: serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
@ -195,7 +194,7 @@
gem0: ethernet@e000b000 {
compatible = "cdns,gem";
reg = <0xe000b000 0x4000>;
reg = <0xe000b000 0x1000>;
status = "disabled";
interrupts = <0 22 4>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
@ -206,7 +205,7 @@
gem1: ethernet@e000c000 {
compatible = "cdns,gem";
reg = <0xe000c000 0x4000>;
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0 45 4>;
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
@ -315,5 +314,16 @@
reg = <0xf8f00600 0x20>;
clocks = <&clkc 4>;
};
watchdog0: watchdog@f8005000 {
clocks = <&clkc 45>;
compatible = "xlnx,zynq-wdt-r1p2";
device_type = "watchdog";
interrupt-parent = <&intc>;
interrupts = <0 9 1>;
reg = <0xf8005000 0x1000>;
reset = <0>;
timeout-sec = <10>;
};
};
};