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Staging: cxt1e1: Fix no spaces at the start of a line in functions.c
This patch fixes the following checkpatch.pl warning in functions.c WARNING: please no spaces at the start of a line in Signed-off-by: Monam Agarwal <monamagarwal123@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Monam Agarwal
Greg Kroah-Hartman
parent
223eaa377d
commit
bc4d6dafa5
@ -25,7 +25,7 @@
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#include "pmcc4.h"
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#if defined(CONFIG_SBE_HDLC_V7) || defined(CONFIG_SBE_WAN256T3_HDLC_V7) || \
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defined(CONFIG_SBE_HDLC_V7_MODULE) || defined(CONFIG_SBE_WAN256T3_HDLC_V7_MODULE)
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defined(CONFIG_SBE_HDLC_V7_MODULE) || defined(CONFIG_SBE_WAN256T3_HDLC_V7_MODULE)
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#define _v7_hdlc_ 1
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#else
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#define _v7_hdlc_ 0
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@ -56,16 +56,16 @@ u_int32_t
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pci_read_32 (u_int32_t *p)
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{
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#ifdef FLOW_DEBUG
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u_int32_t v;
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u_int32_t v;
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FLUSH_PCI_READ ();
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v = le32_to_cpu (*p);
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if (cxt1e1_log_level >= LOG_DEBUG)
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pr_info("pci_read : %x = %x\n", (u_int32_t) p, v);
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return v;
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FLUSH_PCI_READ ();
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v = le32_to_cpu (*p);
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if (cxt1e1_log_level >= LOG_DEBUG)
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pr_info("pci_read : %x = %x\n", (u_int32_t) p, v);
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return v;
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#else
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FLUSH_PCI_READ (); /* */
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return le32_to_cpu (*p);
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FLUSH_PCI_READ (); /* */
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return le32_to_cpu (*p);
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#endif
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}
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@ -73,18 +73,18 @@ void
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pci_write_32 (u_int32_t *p, u_int32_t v)
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{
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#ifdef FLOW_DEBUG
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if (cxt1e1_log_level >= LOG_DEBUG)
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pr_info("pci_write: %x = %x\n", (u_int32_t) p, v);
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if (cxt1e1_log_level >= LOG_DEBUG)
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pr_info("pci_write: %x = %x\n", (u_int32_t) p, v);
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#endif
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*p = cpu_to_le32 (v);
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FLUSH_PCI_WRITE (); /* This routine is called from routines
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* which do multiple register writes
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* which themselves need flushing between
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* writes in order to guarantee write
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* ordering. It is less code-cumbersome
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* to flush here-in then to investigate
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* and code the many other register
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* writing routines. */
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*p = cpu_to_le32 (v);
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FLUSH_PCI_WRITE (); /* This routine is called from routines
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* which do multiple register writes
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* which themselves need flushing between
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* writes in order to guarantee write
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* ordering. It is less code-cumbersome
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* to flush here-in then to investigate
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* and code the many other register
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* writing routines. */
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}
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#endif
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@ -92,10 +92,10 @@ pci_write_32 (u_int32_t *p, u_int32_t v)
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void
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pci_flush_write (ci_t *ci)
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{
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volatile u_int32_t v;
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volatile u_int32_t v;
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/* issue a PCI read to flush PCI write thru bridge */
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v = *(u_int32_t *) &ci->reg->glcd; /* any address would do */
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v = *(u_int32_t *) &ci->reg->glcd; /* any address would do */
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/*
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* return nothing, this just reads PCI bridge interface to flush
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@ -107,53 +107,49 @@ pci_flush_write (ci_t *ci)
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static void
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watchdog_func (unsigned long arg)
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{
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struct watchdog *wd = (void *) arg;
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struct watchdog *wd = (void *) arg;
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if (drvr_state != SBE_DRVR_AVAILABLE)
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{
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if (cxt1e1_log_level >= LOG_MONITOR)
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pr_warning("%s: drvr not available (%x)\n", __func__, drvr_state);
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return;
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}
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schedule_work (&wd->work);
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mod_timer (&wd->h, jiffies + wd->ticks);
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if (drvr_state != SBE_DRVR_AVAILABLE) {
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if (cxt1e1_log_level >= LOG_MONITOR)
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pr_warning("%s: drvr not available (%x)\n", __func__, drvr_state);
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return;
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}
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schedule_work (&wd->work);
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mod_timer (&wd->h, jiffies + wd->ticks);
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}
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int OS_init_watchdog(struct watchdog *wdp, void (*f) (void *), void *c, int usec)
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{
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wdp->func = f;
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wdp->softc = c;
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wdp->ticks = (HZ) * (usec / 1000) / 1000;
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INIT_WORK(&wdp->work, (void *)f);
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init_timer (&wdp->h);
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{
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ci_t *ci = (ci_t *) c;
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wdp->func = f;
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wdp->softc = c;
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wdp->ticks = (HZ) * (usec / 1000) / 1000;
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INIT_WORK(&wdp->work, (void *)f);
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init_timer (&wdp->h);
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{
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ci_t *ci = (ci_t *) c;
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wdp->h.data = (unsigned long) &ci->wd;
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}
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wdp->h.function = watchdog_func;
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return 0;
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wdp->h.data = (unsigned long) &ci->wd;
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}
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wdp->h.function = watchdog_func;
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return 0;
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}
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void
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OS_uwait (int usec, char *description)
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{
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int tmp;
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int tmp;
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if (usec >= 1000)
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{
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mdelay (usec / 1000);
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/* now delay residual */
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tmp = (usec / 1000) * 1000; /* round */
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tmp = usec - tmp; /* residual */
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if (tmp)
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{ /* wait on residual */
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udelay (tmp);
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}
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} else
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{
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udelay (usec);
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}
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if (usec >= 1000) {
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mdelay (usec / 1000);
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/* now delay residual */
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tmp = (usec / 1000) * 1000; /* round */
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tmp = usec - tmp; /* residual */
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if (tmp) { /* wait on residual */
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udelay (tmp);
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}
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} else {
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udelay (usec);
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}
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}
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/* dummy short delay routine called as a subroutine so that compiler
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@ -164,9 +160,9 @@ void
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OS_uwait_dummy (void)
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{
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#ifndef USE_MAX_INT_DELAY
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dummy++;
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dummy++;
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#else
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udelay (1);
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udelay (1);
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#endif
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}
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@ -174,83 +170,82 @@ OS_uwait_dummy (void)
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void
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OS_sem_init (void *sem, int state)
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{
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switch (state)
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{
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case SEM_TAKEN:
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sema_init((struct semaphore *) sem, 0);
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break;
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case SEM_AVAILABLE:
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switch (state) {
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case SEM_TAKEN:
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sema_init((struct semaphore *) sem, 0);
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break;
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case SEM_AVAILABLE:
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sema_init((struct semaphore *) sem, 1);
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break;
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default: /* otherwise, set sem.count to state's
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* value */
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sema_init (sem, state);
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break;
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}
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break;
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default: /* otherwise, set sem.count to state's
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* value */
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sema_init (sem, state);
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break;
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}
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}
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int
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sd_line_is_ok (void *user)
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{
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struct net_device *ndev = (struct net_device *) user;
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struct net_device *ndev = (struct net_device *) user;
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return netif_carrier_ok (ndev);
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return netif_carrier_ok (ndev);
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}
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void
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sd_line_is_up (void *user)
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{
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struct net_device *ndev = (struct net_device *) user;
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struct net_device *ndev = (struct net_device *) user;
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netif_carrier_on (ndev);
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return;
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netif_carrier_on (ndev);
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return;
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}
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void
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sd_line_is_down (void *user)
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{
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struct net_device *ndev = (struct net_device *) user;
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struct net_device *ndev = (struct net_device *) user;
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netif_carrier_off (ndev);
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return;
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netif_carrier_off (ndev);
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return;
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}
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void
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sd_disable_xmit (void *user)
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{
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struct net_device *dev = (struct net_device *) user;
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struct net_device *dev = (struct net_device *) user;
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netif_stop_queue (dev);
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return;
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netif_stop_queue (dev);
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return;
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}
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void
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sd_enable_xmit (void *user)
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{
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struct net_device *dev = (struct net_device *) user;
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struct net_device *dev = (struct net_device *) user;
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netif_wake_queue (dev);
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return;
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netif_wake_queue (dev);
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return;
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}
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int
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sd_queue_stopped (void *user)
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{
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struct net_device *ndev = (struct net_device *) user;
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struct net_device *ndev = (struct net_device *) user;
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return netif_queue_stopped (ndev);
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return netif_queue_stopped (ndev);
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}
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void sd_recv_consume(void *token, size_t len, void *user)
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{
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struct net_device *ndev = user;
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struct sk_buff *skb = token;
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struct net_device *ndev = user;
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struct sk_buff *skb = token;
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skb->dev = ndev;
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skb_put (skb, len);
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skb->protocol = hdlc_type_trans(skb, ndev);
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netif_rx(skb);
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skb->dev = ndev;
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skb_put (skb, len);
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skb->protocol = hdlc_type_trans(skb, ndev);
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netif_rx(skb);
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}
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@ -265,75 +260,74 @@ extern ci_t *CI; /* dummy pointer to board ZERO's data */
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void
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VMETRO_TRIGGER (ci_t *ci, int x)
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{
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struct s_comet_reg *comet;
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volatile u_int32_t data;
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struct s_comet_reg *comet;
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volatile u_int32_t data;
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comet = ci->port[0].cometbase; /* default to COMET # 0 */
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comet = ci->port[0].cometbase; /* default to COMET # 0 */
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switch (x)
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{
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default:
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case 0:
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data = pci_read_32 ((u_int32_t *) &comet->__res24); /* 0x90 */
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break;
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case 1:
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data = pci_read_32 ((u_int32_t *) &comet->__res25); /* 0x94 */
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break;
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case 2:
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data = pci_read_32 ((u_int32_t *) &comet->__res26); /* 0x98 */
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break;
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case 3:
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data = pci_read_32 ((u_int32_t *) &comet->__res27); /* 0x9C */
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break;
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case 4:
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data = pci_read_32 ((u_int32_t *) &comet->__res88); /* 0x220 */
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break;
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case 5:
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data = pci_read_32 ((u_int32_t *) &comet->__res89); /* 0x224 */
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break;
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case 6:
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data = pci_read_32 ((u_int32_t *) &comet->__res8A); /* 0x228 */
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break;
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case 7:
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data = pci_read_32 ((u_int32_t *) &comet->__res8B); /* 0x22C */
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break;
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case 8:
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data = pci_read_32 ((u_int32_t *) &comet->__resA0); /* 0x280 */
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break;
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case 9:
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data = pci_read_32 ((u_int32_t *) &comet->__resA1); /* 0x284 */
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break;
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case 10:
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data = pci_read_32 ((u_int32_t *) &comet->__resA2); /* 0x288 */
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break;
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case 11:
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data = pci_read_32 ((u_int32_t *) &comet->__resA3); /* 0x28C */
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break;
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case 12:
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data = pci_read_32 ((u_int32_t *) &comet->__resA4); /* 0x290 */
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break;
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case 13:
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data = pci_read_32 ((u_int32_t *) &comet->__resA5); /* 0x294 */
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break;
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case 14:
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data = pci_read_32 ((u_int32_t *) &comet->__resA6); /* 0x298 */
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break;
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case 15:
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data = pci_read_32 ((u_int32_t *) &comet->__resA7); /* 0x29C */
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break;
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case 16:
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data = pci_read_32 ((u_int32_t *) &comet->__res74); /* 0x1D0 */
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break;
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case 17:
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data = pci_read_32 ((u_int32_t *) &comet->__res75); /* 0x1D4 */
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break;
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case 18:
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data = pci_read_32 ((u_int32_t *) &comet->__res76); /* 0x1D8 */
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break;
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case 19:
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data = pci_read_32 ((u_int32_t *) &comet->__res77); /* 0x1DC */
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break;
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}
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switch (x) {
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default:
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case 0:
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data = pci_read_32 ((u_int32_t *) &comet->__res24); /* 0x90 */
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break;
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case 1:
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data = pci_read_32 ((u_int32_t *) &comet->__res25); /* 0x94 */
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break;
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case 2:
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data = pci_read_32 ((u_int32_t *) &comet->__res26); /* 0x98 */
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break;
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case 3:
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data = pci_read_32 ((u_int32_t *) &comet->__res27); /* 0x9C */
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break;
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case 4:
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data = pci_read_32 ((u_int32_t *) &comet->__res88); /* 0x220 */
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break;
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case 5:
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data = pci_read_32 ((u_int32_t *) &comet->__res89); /* 0x224 */
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break;
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case 6:
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data = pci_read_32 ((u_int32_t *) &comet->__res8A); /* 0x228 */
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break;
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case 7:
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data = pci_read_32 ((u_int32_t *) &comet->__res8B); /* 0x22C */
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break;
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case 8:
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data = pci_read_32 ((u_int32_t *) &comet->__resA0); /* 0x280 */
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break;
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case 9:
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data = pci_read_32 ((u_int32_t *) &comet->__resA1); /* 0x284 */
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break;
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case 10:
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data = pci_read_32 ((u_int32_t *) &comet->__resA2); /* 0x288 */
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break;
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case 11:
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data = pci_read_32 ((u_int32_t *) &comet->__resA3); /* 0x28C */
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break;
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case 12:
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data = pci_read_32 ((u_int32_t *) &comet->__resA4); /* 0x290 */
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break;
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case 13:
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data = pci_read_32 ((u_int32_t *) &comet->__resA5); /* 0x294 */
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break;
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case 14:
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data = pci_read_32 ((u_int32_t *) &comet->__resA6); /* 0x298 */
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break;
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case 15:
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data = pci_read_32 ((u_int32_t *) &comet->__resA7); /* 0x29C */
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break;
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case 16:
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data = pci_read_32 ((u_int32_t *) &comet->__res74); /* 0x1D0 */
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break;
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case 17:
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data = pci_read_32 ((u_int32_t *) &comet->__res75); /* 0x1D4 */
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break;
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case 18:
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data = pci_read_32 ((u_int32_t *) &comet->__res76); /* 0x1D8 */
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break;
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case 19:
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data = pci_read_32 ((u_int32_t *) &comet->__res77); /* 0x1DC */
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break;
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}
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}
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