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https://github.com/edk2-porting/linux-next.git
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KVM: SVM: Implement VIRT_SPEC_CTRL support for SSBD
Expose the new virtualized architectural mechanism, VIRT_SSBD, for using speculative store bypass disable (SSBD) under SVM. This will allow guests to use SSBD on hardware that uses non-architectural mechanisms for enabling SSBD. [ tglx: Folded the migration fixup from Paolo Bonzini ] Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -924,7 +924,7 @@ struct kvm_x86_ops {
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int (*hardware_setup)(void); /* __init */
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int (*hardware_setup)(void); /* __init */
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void (*hardware_unsetup)(void); /* __exit */
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void (*hardware_unsetup)(void); /* __exit */
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bool (*cpu_has_accelerated_tpr)(void);
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bool (*cpu_has_accelerated_tpr)(void);
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bool (*cpu_has_high_real_mode_segbase)(void);
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bool (*has_emulated_msr)(int index);
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void (*cpuid_update)(struct kvm_vcpu *vcpu);
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void (*cpuid_update)(struct kvm_vcpu *vcpu);
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struct kvm *(*vm_alloc)(void);
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struct kvm *(*vm_alloc)(void);
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@ -767,7 +767,8 @@ static void init_speculation_control(struct cpuinfo_x86 *c)
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if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
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if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
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set_cpu_cap(c, X86_FEATURE_STIBP);
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set_cpu_cap(c, X86_FEATURE_STIBP);
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if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD))
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if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
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cpu_has(c, X86_FEATURE_VIRT_SSBD))
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set_cpu_cap(c, X86_FEATURE_SSBD);
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set_cpu_cap(c, X86_FEATURE_SSBD);
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if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
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if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
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@ -379,7 +379,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
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/* cpuid 0x80000008.ebx */
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/* cpuid 0x80000008.ebx */
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const u32 kvm_cpuid_8000_0008_ebx_x86_features =
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const u32 kvm_cpuid_8000_0008_ebx_x86_features =
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F(AMD_IBPB) | F(AMD_IBRS);
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F(AMD_IBPB) | F(AMD_IBRS) | F(VIRT_SSBD);
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/* cpuid 0xC0000001.edx */
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/* cpuid 0xC0000001.edx */
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const u32 kvm_cpuid_C000_0001_edx_x86_features =
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const u32 kvm_cpuid_C000_0001_edx_x86_features =
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@ -647,13 +647,20 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
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g_phys_as = phys_as;
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g_phys_as = phys_as;
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entry->eax = g_phys_as | (virt_as << 8);
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entry->eax = g_phys_as | (virt_as << 8);
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entry->edx = 0;
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entry->edx = 0;
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/* IBRS and IBPB aren't necessarily present in hardware cpuid */
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/*
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* IBRS, IBPB and VIRT_SSBD aren't necessarily present in
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* hardware cpuid
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*/
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if (boot_cpu_has(X86_FEATURE_AMD_IBPB))
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if (boot_cpu_has(X86_FEATURE_AMD_IBPB))
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entry->ebx |= F(AMD_IBPB);
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entry->ebx |= F(AMD_IBPB);
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if (boot_cpu_has(X86_FEATURE_AMD_IBRS))
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if (boot_cpu_has(X86_FEATURE_AMD_IBRS))
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entry->ebx |= F(AMD_IBRS);
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entry->ebx |= F(AMD_IBRS);
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if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
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entry->ebx |= F(VIRT_SSBD);
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entry->ebx &= kvm_cpuid_8000_0008_ebx_x86_features;
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entry->ebx &= kvm_cpuid_8000_0008_ebx_x86_features;
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cpuid_mask(&entry->ebx, CPUID_8000_0008_EBX);
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cpuid_mask(&entry->ebx, CPUID_8000_0008_EBX);
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if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
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entry->ebx |= F(VIRT_SSBD);
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break;
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break;
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}
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}
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case 0x80000019:
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case 0x80000019:
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@ -4120,6 +4120,13 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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msr_info->data = svm->spec_ctrl;
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msr_info->data = svm->spec_ctrl;
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break;
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break;
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case MSR_AMD64_VIRT_SPEC_CTRL:
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if (!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
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return 1;
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msr_info->data = svm->virt_spec_ctrl;
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break;
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case MSR_F15H_IC_CFG: {
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case MSR_F15H_IC_CFG: {
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int family, model;
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int family, model;
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@ -4251,6 +4258,16 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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break;
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break;
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set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
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set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
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break;
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break;
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case MSR_AMD64_VIRT_SPEC_CTRL:
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if (!msr->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
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return 1;
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if (data & ~SPEC_CTRL_SSBD)
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return 1;
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svm->virt_spec_ctrl = data;
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break;
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case MSR_STAR:
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case MSR_STAR:
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svm->vmcb->save.star = data;
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svm->vmcb->save.star = data;
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break;
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break;
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@ -5791,7 +5808,7 @@ static bool svm_cpu_has_accelerated_tpr(void)
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return false;
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return false;
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}
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}
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static bool svm_has_high_real_mode_segbase(void)
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static bool svm_has_emulated_msr(int index)
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{
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{
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return true;
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return true;
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}
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}
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@ -7017,7 +7034,7 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
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.hardware_enable = svm_hardware_enable,
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.hardware_enable = svm_hardware_enable,
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.hardware_disable = svm_hardware_disable,
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.hardware_disable = svm_hardware_disable,
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.cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
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.cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
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.cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
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.has_emulated_msr = svm_has_emulated_msr,
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.vcpu_create = svm_create_vcpu,
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.vcpu_create = svm_create_vcpu,
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.vcpu_free = svm_free_vcpu,
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.vcpu_free = svm_free_vcpu,
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@ -9477,9 +9477,21 @@ static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
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}
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}
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STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
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STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
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static bool vmx_has_high_real_mode_segbase(void)
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static bool vmx_has_emulated_msr(int index)
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{
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{
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switch (index) {
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case MSR_IA32_SMBASE:
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/*
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* We cannot do SMM unless we can run the guest in big
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* real mode.
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*/
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return enable_unrestricted_guest || emulate_invalid_guest_state;
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return enable_unrestricted_guest || emulate_invalid_guest_state;
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case MSR_AMD64_VIRT_SPEC_CTRL:
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/* This is AMD only. */
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return false;
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default:
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return true;
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}
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}
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}
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static bool vmx_mpx_supported(void)
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static bool vmx_mpx_supported(void)
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@ -12625,7 +12637,7 @@ static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
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.hardware_enable = hardware_enable,
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.hardware_enable = hardware_enable,
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.hardware_disable = hardware_disable,
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.hardware_disable = hardware_disable,
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.cpu_has_accelerated_tpr = report_flexpriority,
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.cpu_has_accelerated_tpr = report_flexpriority,
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.cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
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.has_emulated_msr = vmx_has_emulated_msr,
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.vm_init = vmx_vm_init,
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.vm_init = vmx_vm_init,
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.vm_alloc = vmx_vm_alloc,
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.vm_alloc = vmx_vm_alloc,
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@ -1058,6 +1058,7 @@ static u32 emulated_msrs[] = {
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MSR_SMI_COUNT,
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MSR_SMI_COUNT,
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MSR_PLATFORM_INFO,
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MSR_PLATFORM_INFO,
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MSR_MISC_FEATURES_ENABLES,
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MSR_MISC_FEATURES_ENABLES,
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MSR_AMD64_VIRT_SPEC_CTRL,
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};
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};
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static unsigned num_emulated_msrs;
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static unsigned num_emulated_msrs;
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@ -2903,7 +2904,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
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* fringe case that is not enabled except via specific settings
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* fringe case that is not enabled except via specific settings
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* of the module parameters.
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* of the module parameters.
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*/
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*/
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r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
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r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
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break;
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break;
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case KVM_CAP_VAPIC:
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case KVM_CAP_VAPIC:
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r = !kvm_x86_ops->cpu_has_accelerated_tpr();
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r = !kvm_x86_ops->cpu_has_accelerated_tpr();
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@ -4603,14 +4604,8 @@ static void kvm_init_msr_list(void)
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num_msrs_to_save = j;
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num_msrs_to_save = j;
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for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
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for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
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switch (emulated_msrs[i]) {
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if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
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case MSR_IA32_SMBASE:
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if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
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continue;
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continue;
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break;
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default:
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break;
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}
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if (j < i)
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if (j < i)
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emulated_msrs[j] = emulated_msrs[i];
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emulated_msrs[j] = emulated_msrs[i];
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