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dmaengine: stm32-mdma: Fix incomplete Hw descriptors allocator
Only 1 Hw Descriptor is allocated. Loop over required Hw descriptor for proper allocation. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Pierre-Yves MORDRET
Vinod Koul
parent
ee6de9ac52
commit
bbb5a4e1e7
@ -252,13 +252,17 @@ struct stm32_mdma_hwdesc {
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u32 cmdr;
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} __aligned(64);
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struct stm32_mdma_desc_node {
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struct stm32_mdma_hwdesc *hwdesc;
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dma_addr_t hwdesc_phys;
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};
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struct stm32_mdma_desc {
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struct virt_dma_desc vdesc;
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u32 ccr;
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struct stm32_mdma_hwdesc *hwdesc;
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dma_addr_t hwdesc_phys;
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bool cyclic;
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u32 count;
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struct stm32_mdma_desc_node node[];
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};
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struct stm32_mdma_chan {
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@ -344,30 +348,42 @@ static struct stm32_mdma_desc *stm32_mdma_alloc_desc(
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struct stm32_mdma_chan *chan, u32 count)
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{
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struct stm32_mdma_desc *desc;
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int i;
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desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
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desc = kzalloc(offsetof(typeof(*desc), node[count]), GFP_NOWAIT);
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if (!desc)
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return NULL;
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desc->hwdesc = dma_pool_alloc(chan->desc_pool, GFP_NOWAIT,
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&desc->hwdesc_phys);
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if (!desc->hwdesc) {
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dev_err(chan2dev(chan), "Failed to allocate descriptor\n");
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kfree(desc);
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return NULL;
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for (i = 0; i < count; i++) {
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desc->node[i].hwdesc =
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dma_pool_alloc(chan->desc_pool, GFP_NOWAIT,
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&desc->node[i].hwdesc_phys);
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if (!desc->node[i].hwdesc)
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goto err;
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}
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desc->count = count;
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return desc;
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err:
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dev_err(chan2dev(chan), "Failed to allocate descriptor\n");
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while (--i >= 0)
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dma_pool_free(chan->desc_pool, desc->node[i].hwdesc,
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desc->node[i].hwdesc_phys);
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kfree(desc);
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return NULL;
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}
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static void stm32_mdma_desc_free(struct virt_dma_desc *vdesc)
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{
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struct stm32_mdma_desc *desc = to_stm32_mdma_desc(vdesc);
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struct stm32_mdma_chan *chan = to_stm32_mdma_chan(vdesc->tx.chan);
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int i;
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dma_pool_free(chan->desc_pool, desc->hwdesc, desc->hwdesc_phys);
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for (i = 0; i < desc->count; i++)
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dma_pool_free(chan->desc_pool, desc->node[i].hwdesc,
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desc->node[i].hwdesc_phys);
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kfree(desc);
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}
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@ -666,18 +682,18 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan,
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}
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static void stm32_mdma_dump_hwdesc(struct stm32_mdma_chan *chan,
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struct stm32_mdma_hwdesc *hwdesc)
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struct stm32_mdma_desc_node *node)
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{
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dev_dbg(chan2dev(chan), "hwdesc: 0x%p\n", hwdesc);
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dev_dbg(chan2dev(chan), "CTCR: 0x%08x\n", hwdesc->ctcr);
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dev_dbg(chan2dev(chan), "CBNDTR: 0x%08x\n", hwdesc->cbndtr);
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dev_dbg(chan2dev(chan), "CSAR: 0x%08x\n", hwdesc->csar);
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dev_dbg(chan2dev(chan), "CDAR: 0x%08x\n", hwdesc->cdar);
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dev_dbg(chan2dev(chan), "CBRUR: 0x%08x\n", hwdesc->cbrur);
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dev_dbg(chan2dev(chan), "CLAR: 0x%08x\n", hwdesc->clar);
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dev_dbg(chan2dev(chan), "CTBR: 0x%08x\n", hwdesc->ctbr);
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dev_dbg(chan2dev(chan), "CMAR: 0x%08x\n", hwdesc->cmar);
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dev_dbg(chan2dev(chan), "CMDR: 0x%08x\n\n", hwdesc->cmdr);
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dev_dbg(chan2dev(chan), "hwdesc: %pad\n", &node->hwdesc_phys);
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dev_dbg(chan2dev(chan), "CTCR: 0x%08x\n", node->hwdesc->ctcr);
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dev_dbg(chan2dev(chan), "CBNDTR: 0x%08x\n", node->hwdesc->cbndtr);
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dev_dbg(chan2dev(chan), "CSAR: 0x%08x\n", node->hwdesc->csar);
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dev_dbg(chan2dev(chan), "CDAR: 0x%08x\n", node->hwdesc->cdar);
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dev_dbg(chan2dev(chan), "CBRUR: 0x%08x\n", node->hwdesc->cbrur);
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dev_dbg(chan2dev(chan), "CLAR: 0x%08x\n", node->hwdesc->clar);
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dev_dbg(chan2dev(chan), "CTBR: 0x%08x\n", node->hwdesc->ctbr);
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dev_dbg(chan2dev(chan), "CMAR: 0x%08x\n", node->hwdesc->cmar);
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dev_dbg(chan2dev(chan), "CMDR: 0x%08x\n\n", node->hwdesc->cmdr);
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}
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static void stm32_mdma_setup_hwdesc(struct stm32_mdma_chan *chan,
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@ -691,7 +707,7 @@ static void stm32_mdma_setup_hwdesc(struct stm32_mdma_chan *chan,
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struct stm32_mdma_hwdesc *hwdesc;
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u32 next = count + 1;
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hwdesc = &desc->hwdesc[count];
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hwdesc = desc->node[count].hwdesc;
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hwdesc->ctcr = ctcr;
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hwdesc->cbndtr &= ~(STM32_MDMA_CBNDTR_BRC_MK |
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STM32_MDMA_CBNDTR_BRDUM |
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@ -701,19 +717,20 @@ static void stm32_mdma_setup_hwdesc(struct stm32_mdma_chan *chan,
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hwdesc->csar = src_addr;
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hwdesc->cdar = dst_addr;
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hwdesc->cbrur = 0;
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hwdesc->clar = desc->hwdesc_phys + next * sizeof(*hwdesc);
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hwdesc->ctbr = ctbr;
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hwdesc->cmar = config->mask_addr;
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hwdesc->cmdr = config->mask_data;
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if (is_last) {
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if (is_cyclic)
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hwdesc->clar = desc->hwdesc_phys;
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hwdesc->clar = desc->node[0].hwdesc_phys;
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else
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hwdesc->clar = 0;
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} else {
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hwdesc->clar = desc->node[next].hwdesc_phys;
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}
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stm32_mdma_dump_hwdesc(chan, hwdesc);
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stm32_mdma_dump_hwdesc(chan, &desc->node[count]);
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}
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static int stm32_mdma_setup_xfer(struct stm32_mdma_chan *chan,
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@ -777,7 +794,7 @@ stm32_mdma_prep_slave_sg(struct dma_chan *c, struct scatterlist *sgl,
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{
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struct stm32_mdma_chan *chan = to_stm32_mdma_chan(c);
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struct stm32_mdma_desc *desc;
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int ret;
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int i, ret;
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/*
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* Once DMA is in setup cyclic mode the channel we cannot assign this
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@ -803,7 +820,9 @@ stm32_mdma_prep_slave_sg(struct dma_chan *c, struct scatterlist *sgl,
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return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
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xfer_setup_err:
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dma_pool_free(chan->desc_pool, &desc->hwdesc, desc->hwdesc_phys);
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for (i = 0; i < desc->count; i++)
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dma_pool_free(chan->desc_pool, desc->node[i].hwdesc,
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desc->node[i].hwdesc_phys);
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kfree(desc);
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return NULL;
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}
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@ -892,7 +911,9 @@ stm32_mdma_prep_dma_cyclic(struct dma_chan *c, dma_addr_t buf_addr,
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return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
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xfer_setup_err:
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dma_pool_free(chan->desc_pool, &desc->hwdesc, desc->hwdesc_phys);
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for (i = 0; i < desc->count; i++)
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dma_pool_free(chan->desc_pool, desc->node[i].hwdesc,
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desc->node[i].hwdesc_phys);
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kfree(desc);
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return NULL;
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}
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@ -1006,7 +1027,7 @@ stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
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ctcr |= STM32_MDMA_CTCR_PKE;
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/* Prepare hardware descriptor */
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hwdesc = desc->hwdesc;
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hwdesc = desc->node[0].hwdesc;
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hwdesc->ctcr = ctcr;
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hwdesc->cbndtr = cbndtr;
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hwdesc->csar = src;
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@ -1017,7 +1038,7 @@ stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
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hwdesc->cmar = 0;
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hwdesc->cmdr = 0;
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stm32_mdma_dump_hwdesc(chan, hwdesc);
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stm32_mdma_dump_hwdesc(chan, &desc->node[0]);
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} else {
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/* Setup a LLI transfer */
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ctcr |= STM32_MDMA_CTCR_TRGM(STM32_MDMA_LINKED_LIST) |
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@ -1117,7 +1138,7 @@ static void stm32_mdma_start_transfer(struct stm32_mdma_chan *chan)
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}
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chan->desc = to_stm32_mdma_desc(vdesc);
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hwdesc = chan->desc->hwdesc;
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hwdesc = chan->desc->node[0].hwdesc;
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chan->curr_hwdesc = 0;
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stm32_mdma_write(dmadev, STM32_MDMA_CCR(id), chan->desc->ccr);
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@ -1195,7 +1216,7 @@ static int stm32_mdma_resume(struct dma_chan *c)
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unsigned long flags;
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u32 status, reg;
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hwdesc = &chan->desc->hwdesc[chan->curr_hwdesc];
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hwdesc = chan->desc->node[chan->curr_hwdesc].hwdesc;
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spin_lock_irqsave(&chan->vchan.lock, flags);
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@ -1265,13 +1286,13 @@ static size_t stm32_mdma_desc_residue(struct stm32_mdma_chan *chan,
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u32 curr_hwdesc)
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{
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struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
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struct stm32_mdma_hwdesc *hwdesc = desc->node[0].hwdesc;
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u32 cbndtr, residue, modulo, burst_size;
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int i;
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residue = 0;
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for (i = curr_hwdesc + 1; i < desc->count; i++) {
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struct stm32_mdma_hwdesc *hwdesc = &desc->hwdesc[i];
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hwdesc = desc->node[i].hwdesc;
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residue += STM32_MDMA_CBNDTR_BNDT(hwdesc->cbndtr);
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}
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cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id));
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