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MIPS: Loongson: update cpu-feature-overrides.h

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Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts
(cpu_has_vint) and MIPSR2 external interrupt controller mode
(cpu_has_veic) are 0.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1112/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Wu Zhangjin 2010-04-13 13:16:34 +08:00 committed by Ralf Baechle
parent ed1bbdefc3
commit b8853aa3d9
1 changed files with 2 additions and 0 deletions
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2
arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
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@ -52,6 +52,8 @@
#define cpu_has_tx39_cache 0
#define cpu_has_userlocal 0
#define cpu_has_vce 0
#define cpu_has_veic 0
#define cpu_has_vint 0
#define cpu_has_vtag_icache 0
#define cpu_has_watch 1