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clk: socfpga: Look for the GPIO_DB_CLK by its offset
After the patch: "clk: socfpga: Map the clk manager base address in the clock driver" The clk->name field in socfpga_clk_recalc_rate() was getting cleared. Replace looking for the GPIO_DB_CLK by its divider offset instead. Also rename the define SOCFPGA_DB_CLK_OFFSET -> SOCFPGA_GPIO_DB_CLK_OFFSET, as this represents the GPIO_DB_CLK. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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@ -51,7 +51,7 @@
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#define SOCFPGA_NAND_CLK "nand_clk"
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#define SOCFPGA_NAND_X_CLK "nand_x_clk"
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#define SOCFPGA_MMC_CLK "sdmmc_clk"
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#define SOCFPGA_DB_CLK "gpio_db_clk"
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#define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
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#define div_mask(width) ((1 << (width)) - 1)
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#define streq(a, b) (strcmp((a), (b)) == 0)
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@ -234,7 +234,8 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
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else if (socfpgaclk->div_reg) {
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= div_mask(socfpgaclk->width);
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if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
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/* Check for GPIO_DB_CLK by its offset */
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if ((int)socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
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div = val + 1;
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else
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div = (1 << val);
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