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drm/sun4i: Implement A83T HDMI driver
A83T has DW HDMI IP block with a custom PHY similar to Synopsys gen2 HDMI PHY. Only video output was tested, while HW also supports audio and CEC. Support for them will be added later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180214200906.31509-11-jernej.skrabec@siol.net
This commit is contained in:
Jernej Skrabec
Maxime Ripard
parent
47095e1635
commit
b7c7436a5f
@ -40,6 +40,15 @@ config DRM_SUN4I_BACKEND
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do some alpha blending and feed graphics to TCON. If M is
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selected the module will be called sun4i-backend.
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config DRM_SUN8I_DW_HDMI
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tristate "Support for Allwinner version of DesignWare HDMI"
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depends on DRM_SUN4I
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select DRM_DW_HDMI
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help
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Choose this option if you have an Allwinner SoC with the
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DesignWare HDMI controller with custom HDMI PHY. If M is
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selected the module will be called sun8i_dw_hdmi.
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config DRM_SUN8I_MIXER
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tristate "Support for Allwinner Display Engine 2.0 Mixer"
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default MACH_SUN8I
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@ -10,6 +10,9 @@ sun4i-drm-hdmi-y += sun4i_hdmi_enc.o
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sun4i-drm-hdmi-y += sun4i_hdmi_i2c.o
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sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o
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sun8i-drm-hdmi-y += sun8i_dw_hdmi.o
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sun8i-drm-hdmi-y += sun8i_hdmi_phy.o
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sun8i-mixer-y += sun8i_mixer.o sun8i_ui_layer.o \
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sun8i_vi_layer.o sun8i_ui_scaler.o \
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sun8i_vi_scaler.o sun8i_csc.o
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@ -27,4 +30,5 @@ obj-$(CONFIG_DRM_SUN4I) += sun6i_drc.o
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obj-$(CONFIG_DRM_SUN4I_BACKEND) += sun4i-backend.o sun4i-frontend.o
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obj-$(CONFIG_DRM_SUN4I_HDMI) += sun4i-drm-hdmi.o
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obj-$(CONFIG_DRM_SUN8I_DW_HDMI) += sun8i-drm-hdmi.o
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obj-$(CONFIG_DRM_SUN8I_MIXER) += sun8i-mixer.o
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196
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
Normal file
196
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
Normal file
@ -0,0 +1,196 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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#include <linux/component.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <drm/drm_of.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include "sun8i_dw_hdmi.h"
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static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adj_mode)
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{
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struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder);
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clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);
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}
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static const struct drm_encoder_helper_funcs
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sun8i_dw_hdmi_encoder_helper_funcs = {
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.mode_set = sun8i_dw_hdmi_encoder_mode_set,
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};
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static const struct drm_encoder_funcs sun8i_dw_hdmi_encoder_funcs = {
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.destroy = drm_encoder_cleanup,
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};
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static enum drm_mode_status
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sun8i_dw_hdmi_mode_valid(struct drm_connector *connector,
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const struct drm_display_mode *mode)
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{
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if (mode->clock > 297000)
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return MODE_CLOCK_HIGH;
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return MODE_OK;
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}
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static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct dw_hdmi_plat_data *plat_data;
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struct drm_device *drm = data;
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struct device_node *phy_node;
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struct drm_encoder *encoder;
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struct sun8i_dw_hdmi *hdmi;
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int ret;
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if (!pdev->dev.of_node)
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return -ENODEV;
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hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
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if (!hdmi)
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return -ENOMEM;
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plat_data = &hdmi->plat_data;
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hdmi->dev = &pdev->dev;
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encoder = &hdmi->encoder;
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encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
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/*
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* If we failed to find the CRTC(s) which this encoder is
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* supposed to be connected to, it's because the CRTC has
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* not been registered yet. Defer probing, and hope that
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* the required CRTC is added later.
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*/
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if (encoder->possible_crtcs == 0)
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return -EPROBE_DEFER;
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hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl");
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if (IS_ERR(hdmi->rst_ctrl)) {
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dev_err(dev, "Could not get ctrl reset control\n");
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return PTR_ERR(hdmi->rst_ctrl);
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}
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hdmi->clk_tmds = devm_clk_get(dev, "tmds");
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if (IS_ERR(hdmi->clk_tmds)) {
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dev_err(dev, "Couldn't get the tmds clock\n");
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return PTR_ERR(hdmi->clk_tmds);
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}
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ret = reset_control_deassert(hdmi->rst_ctrl);
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if (ret) {
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dev_err(dev, "Could not deassert ctrl reset control\n");
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return ret;
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}
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ret = clk_prepare_enable(hdmi->clk_tmds);
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if (ret) {
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dev_err(dev, "Could not enable tmds clock\n");
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goto err_assert_ctrl_reset;
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}
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phy_node = of_parse_phandle(dev->of_node, "phys", 0);
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if (!phy_node) {
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dev_err(dev, "Can't found PHY phandle\n");
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goto err_disable_clk_tmds;
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}
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ret = sun8i_hdmi_phy_probe(hdmi, phy_node);
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of_node_put(phy_node);
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if (ret) {
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dev_err(dev, "Couldn't get the HDMI PHY\n");
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goto err_disable_clk_tmds;
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}
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drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs);
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drm_encoder_init(drm, encoder, &sun8i_dw_hdmi_encoder_funcs,
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DRM_MODE_ENCODER_TMDS, NULL);
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sun8i_hdmi_phy_init(hdmi->phy);
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plat_data->mode_valid = &sun8i_dw_hdmi_mode_valid;
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plat_data->phy_ops = sun8i_hdmi_phy_get_ops();
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plat_data->phy_name = "sun8i_dw_hdmi_phy";
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plat_data->phy_data = hdmi->phy;
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platform_set_drvdata(pdev, hdmi);
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hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
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/*
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* If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
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* which would have called the encoder cleanup. Do it manually.
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*/
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if (IS_ERR(hdmi->hdmi)) {
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ret = PTR_ERR(hdmi->hdmi);
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goto cleanup_encoder;
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}
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return 0;
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cleanup_encoder:
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drm_encoder_cleanup(encoder);
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sun8i_hdmi_phy_remove(hdmi);
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err_disable_clk_tmds:
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clk_disable_unprepare(hdmi->clk_tmds);
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err_assert_ctrl_reset:
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reset_control_assert(hdmi->rst_ctrl);
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return ret;
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}
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static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master,
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void *data)
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{
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struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev);
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dw_hdmi_unbind(hdmi->hdmi);
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sun8i_hdmi_phy_remove(hdmi);
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clk_disable_unprepare(hdmi->clk_tmds);
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reset_control_assert(hdmi->rst_ctrl);
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}
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static const struct component_ops sun8i_dw_hdmi_ops = {
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.bind = sun8i_dw_hdmi_bind,
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.unbind = sun8i_dw_hdmi_unbind,
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};
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static int sun8i_dw_hdmi_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &sun8i_dw_hdmi_ops);
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}
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static int sun8i_dw_hdmi_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &sun8i_dw_hdmi_ops);
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return 0;
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}
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static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
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{ .compatible = "allwinner,sun8i-a83t-dw-hdmi" },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, sun8i_dw_hdmi_dt_ids);
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struct platform_driver sun8i_dw_hdmi_pltfm_driver = {
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.probe = sun8i_dw_hdmi_probe,
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.remove = sun8i_dw_hdmi_remove,
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.driver = {
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.name = "sun8i-dw-hdmi",
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.of_match_table = sun8i_dw_hdmi_dt_ids,
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},
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};
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module_platform_driver(sun8i_dw_hdmi_pltfm_driver);
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MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
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MODULE_DESCRIPTION("Allwinner DW HDMI bridge");
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MODULE_LICENSE("GPL");
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44
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
Normal file
44
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
Normal file
@ -0,0 +1,44 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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#ifndef _SUN8I_DW_HDMI_H_
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#define _SUN8I_DW_HDMI_H_
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#include <drm/bridge/dw_hdmi.h>
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#include <drm/drm_encoder.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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struct sun8i_hdmi_phy {
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struct clk *clk_bus;
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struct clk *clk_mod;
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struct regmap *regs;
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struct reset_control *rst_phy;
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};
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struct sun8i_dw_hdmi {
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struct clk *clk_tmds;
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struct device *dev;
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struct dw_hdmi *hdmi;
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struct drm_encoder encoder;
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struct sun8i_hdmi_phy *phy;
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struct dw_hdmi_plat_data plat_data;
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struct reset_control *rst_ctrl;
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};
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static inline struct sun8i_dw_hdmi *
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encoder_to_sun8i_dw_hdmi(struct drm_encoder *encoder)
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{
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return container_of(encoder, struct sun8i_dw_hdmi, encoder);
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}
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int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node);
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void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi);
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void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
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const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);
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#endif /* _SUN8I_DW_HDMI_H_ */
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270
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
Normal file
270
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
Normal file
@ -0,0 +1,270 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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#include <linux/of_address.h>
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#include "sun8i_dw_hdmi.h"
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#define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000
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#define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0)
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#define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK GENMASK(15, 8)
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#define SUN8I_HDMI_PHY_DBG_CTRL_POL(val) (val << 8)
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#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK GENMASK(23, 16)
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#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr) (addr << 16)
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#define SUN8I_HDMI_PHY_REXT_CTRL_REG 0x0004
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#define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN BIT(31)
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#define SUN8I_HDMI_PHY_READ_EN_REG 0x0010
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#define SUN8I_HDMI_PHY_READ_EN_MAGIC 0x54524545
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#define SUN8I_HDMI_PHY_UNSCRAMBLE_REG 0x0014
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#define SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC 0x42494E47
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/*
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* Address can be actually any value. Here is set to same value as
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* it is set in BSP driver.
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*/
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#define I2C_ADDR 0x69
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static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
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struct drm_display_mode *mode)
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{
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struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
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u32 val = 0;
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if ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
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(mode->flags & DRM_MODE_FLAG_NHSYNC)) {
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val = 0x03;
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}
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
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SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK,
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SUN8I_HDMI_PHY_DBG_CTRL_POL(val));
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);
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/* power down */
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dw_hdmi_phy_gen2_txpwron(hdmi, 0);
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dw_hdmi_phy_gen2_pddq(hdmi, 1);
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dw_hdmi_phy_reset(hdmi);
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dw_hdmi_phy_gen2_pddq(hdmi, 0);
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dw_hdmi_phy_i2c_set_addr(hdmi, I2C_ADDR);
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/*
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* Values are taken from BSP HDMI driver. Although AW didn't
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* release any documentation, explanation of this values can
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* be found in i.MX 6Dual/6Quad Reference Manual.
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*/
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if (mode->crtc_clock <= 27000) {
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dw_hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x08da, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x0318, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
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} else if (mode->crtc_clock <= 74250) {
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dw_hdmi_phy_i2c_write(hdmi, 0x0540, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x02b5, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
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} else if (mode->crtc_clock <= 148500) {
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dw_hdmi_phy_i2c_write(hdmi, 0x04a0, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x0021, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x8029, 0x09);
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} else {
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x802b, 0x09);
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}
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x1e);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x17);
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dw_hdmi_phy_gen2_txpwron(hdmi, 1);
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return 0;
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};
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static void sun8i_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
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{
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struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
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dw_hdmi_phy_gen2_txpwron(hdmi, 0);
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dw_hdmi_phy_gen2_pddq(hdmi, 1);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0);
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}
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|
||||
static const struct dw_hdmi_phy_ops sun8i_hdmi_phy_ops = {
|
||||
.init = &sun8i_hdmi_phy_config,
|
||||
.disable = &sun8i_hdmi_phy_disable,
|
||||
.read_hpd = &dw_hdmi_phy_read_hpd,
|
||||
.update_hpd = &dw_hdmi_phy_update_hpd,
|
||||
.setup_hpd = &dw_hdmi_phy_setup_hpd,
|
||||
};
|
||||
|
||||
void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy)
|
||||
{
|
||||
/* enable read access to HDMI controller */
|
||||
regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG,
|
||||
SUN8I_HDMI_PHY_READ_EN_MAGIC);
|
||||
|
||||
/* unscramble register offsets */
|
||||
regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
|
||||
SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);
|
||||
|
||||
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
|
||||
SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK,
|
||||
SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK);
|
||||
|
||||
/*
|
||||
* Set PHY I2C address. It must match to the address set by
|
||||
* dw_hdmi_phy_set_slave_addr().
|
||||
*/
|
||||
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
|
||||
SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK,
|
||||
SUN8I_HDMI_PHY_DBG_CTRL_ADDR(I2C_ADDR));
|
||||
}
|
||||
|
||||
const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void)
|
||||
{
|
||||
return &sun8i_hdmi_phy_ops;
|
||||
}
|
||||
|
||||
static struct regmap_config sun8i_hdmi_phy_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
|
||||
.name = "phy"
|
||||
};
|
||||
|
||||
static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
|
||||
{ .compatible = "allwinner,sun8i-a83t-hdmi-phy" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
|
||||
{
|
||||
struct device *dev = hdmi->dev;
|
||||
struct sun8i_hdmi_phy *phy;
|
||||
struct resource res;
|
||||
void __iomem *regs;
|
||||
int ret;
|
||||
|
||||
if (!of_match_node(sun8i_hdmi_phy_of_table, node)) {
|
||||
dev_err(dev, "Incompatible HDMI PHY\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
|
||||
if (!phy)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = of_address_to_resource(node, 0, &res);
|
||||
if (ret) {
|
||||
dev_err(dev, "phy: Couldn't get our resources\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
regs = devm_ioremap_resource(dev, &res);
|
||||
if (IS_ERR(regs)) {
|
||||
dev_err(dev, "Couldn't map the HDMI PHY registers\n");
|
||||
return PTR_ERR(regs);
|
||||
}
|
||||
|
||||
phy->regs = devm_regmap_init_mmio(dev, regs,
|
||||
&sun8i_hdmi_phy_regmap_config);
|
||||
if (IS_ERR(phy->regs)) {
|
||||
dev_err(dev, "Couldn't create the HDMI PHY regmap\n");
|
||||
return PTR_ERR(phy->regs);
|
||||
}
|
||||
|
||||
phy->clk_bus = of_clk_get_by_name(node, "bus");
|
||||
if (IS_ERR(phy->clk_bus)) {
|
||||
dev_err(dev, "Could not get bus clock\n");
|
||||
return PTR_ERR(phy->clk_bus);
|
||||
}
|
||||
|
||||
phy->clk_mod = of_clk_get_by_name(node, "mod");
|
||||
if (IS_ERR(phy->clk_mod)) {
|
||||
dev_err(dev, "Could not get mod clock\n");
|
||||
ret = PTR_ERR(phy->clk_mod);
|
||||
goto err_put_clk_bus;
|
||||
}
|
||||
|
||||
phy->rst_phy = of_reset_control_get_shared(node, "phy");
|
||||
if (IS_ERR(phy->rst_phy)) {
|
||||
dev_err(dev, "Could not get phy reset control\n");
|
||||
ret = PTR_ERR(phy->rst_phy);
|
||||
goto err_put_clk_mod;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(phy->rst_phy);
|
||||
if (ret) {
|
||||
dev_err(dev, "Cannot deassert phy reset control: %d\n", ret);
|
||||
goto err_put_rst_phy;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(phy->clk_bus);
|
||||
if (ret) {
|
||||
dev_err(dev, "Cannot enable bus clock: %d\n", ret);
|
||||
goto err_deassert_rst_phy;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(phy->clk_mod);
|
||||
if (ret) {
|
||||
dev_err(dev, "Cannot enable mod clock: %d\n", ret);
|
||||
goto err_disable_clk_bus;
|
||||
}
|
||||
|
||||
hdmi->phy = phy;
|
||||
|
||||
return 0;
|
||||
|
||||
err_disable_clk_bus:
|
||||
clk_disable_unprepare(phy->clk_bus);
|
||||
err_deassert_rst_phy:
|
||||
reset_control_assert(phy->rst_phy);
|
||||
err_put_rst_phy:
|
||||
reset_control_put(phy->rst_phy);
|
||||
err_put_clk_mod:
|
||||
clk_put(phy->clk_mod);
|
||||
err_put_clk_bus:
|
||||
clk_put(phy->clk_bus);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
|
||||
{
|
||||
struct sun8i_hdmi_phy *phy = hdmi->phy;
|
||||
|
||||
clk_disable_unprepare(phy->clk_mod);
|
||||
clk_disable_unprepare(phy->clk_bus);
|
||||
|
||||
reset_control_assert(phy->rst_phy);
|
||||
|
||||
reset_control_put(phy->rst_phy);
|
||||
|
||||
clk_put(phy->clk_mod);
|
||||
clk_put(phy->clk_bus);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user