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clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2
R-Car V2H and E2 do not have the PLL0CR register, but use a fixed multiplier (depending on mode pins) and divider. This corrects the clock rate of "pll0" (PLL0 VCO after post divider) on R-Car V2H and E2 from 1.5 GHz to 1 GHz. Inspired by Sergei Shtylyov's work for the common R-Car Gen2 and RZ/G Clock Pulse Generator support core. Fixes:7c4163aae3
("ARM: dts: r8a7792: initial SoC device tree") Fixes:0dce5454d5
("ARM: shmobile: Initial r8a7794 SoC device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -272,11 +272,14 @@ struct cpg_pll_config {
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unsigned int extal_div;
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unsigned int pll1_mult;
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unsigned int pll3_mult;
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unsigned int pll0_mult; /* For R-Car V2H and E2 only */
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};
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static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
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{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
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{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
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{ 1, 208, 106, 200 }, { 1, 208, 88, 200 },
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{ 1, 156, 80, 150 }, { 1, 156, 66, 150 },
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{ 2, 240, 122, 230 }, { 2, 240, 102, 230 },
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{ 2, 208, 106, 200 }, { 2, 208, 88, 200 },
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};
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/* SDHI divisors */
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@ -298,6 +301,12 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
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static u32 cpg_mode __initdata;
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static const char * const pll0_mult_match[] = {
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"renesas,r8a7792-cpg-clocks",
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"renesas,r8a7794-cpg-clocks",
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NULL
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};
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static struct clk * __init
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rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
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const struct cpg_pll_config *config,
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@ -318,9 +327,15 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
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* clock implementation and we currently have no need to change
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* the multiplier value.
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*/
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u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
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if (of_device_compatible_match(np, pll0_mult_match)) {
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/* R-Car V2H and E2 do not have PLL0CR */
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mult = config->pll0_mult;
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div = 3;
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} else {
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u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
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mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
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}
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parent_name = "main";
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mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
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} else if (!strcmp(name, "pll1")) {
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parent_name = "main";
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mult = config->pll1_mult / 2;
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