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ARM: arm-soc soc updates, take 2

Browse Source 
This is the second batch of SoC updates for the 3.6 merge window,
 containing parts that arrived close to the merge window opening and
 thus needed to sit in linux-next for a while.
 
 Most contents is updates of Renesas shmobile, with a couple of
 Samsung Exynos patches in the mix.
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Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc soc updates from Olof Johansson:
 "This is the second batch of SoC updates for the 3.6 merge window,
  containing parts that arrived close to the merge window opening and
  thus needed to sit in linux-next for a while.

  Most contents is updates of Renesas shmobile, with a couple of Samsung
  Exynos patches in the mix."

* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits)
  ARM: S3C64XX: Add header file protection macros in pm-core.h
  [CPUFREQ] EXYNOS5250: Add support max 1.7GHz for EXYNOS5250
  ARM: EXYNOS: Add G2D related clock entries for SMDK4X12
  ARM: EXYNOS: Move G2D clock entries to clock-exynos4210.c file
  ARM: shmobile: Fix build problem in pm-sh7372.c for unusual .config
  ARM: shmobile: Take cpuidle dependencies into account correctly
  ARM: mach-shmobile: sh7377 generic board support via DT
  ARM: mach-shmobile: r8a7740 generic board support via DT
  ARM: shmobile: sh7372: completely switch over to using pm-rmobile API
  ARM: shmobile: ap4evb: switch to using pm-rmobile API
  ARM: shmobile: mackerel: switch to using pm-rmobile API
  ARM: shmobile: sh7372: add pm-rmobile domain support
  ARM: shmobile: r8a7740: add A4LC pm domain support
  ARM: shmobile: r8a7740: add A3SP pm domain support
  ARM: shmobile: r8a7740: add A4S pm domain support
  ARM: shmobile: r8a7740: fixup: MSEL1CR 7bit control
  ARM: shmobile: soc-core: add R-mobile PM domain common APIs
  ARM: shmobile: sh7372 A3SM CPUIdle support
  ARM: shmobile: Use INTCA with sh7372 A3SM power domain
  ARM: mach-shmobile: Convert sh_clk_mstp32_register to sh_clk_mstp_register
  ...
This commit is contained in:
Linus Torvalds 2012-07-30 09:45:53 -07:00
commit b7574a22a2
35 changed files with 1495 additions and 517 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
arch/arm/boot/dts/r8a7740.dtsi Normal file
View File

@ -0,0 +1,21 @@
/*
* Device Tree Source for the r8a7740 SoC
*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "renesas,r8a7740";
cpus {
cpu@0 {
compatible = "arm,cortex-a9";
};
};
};

21
arch/arm/boot/dts/sh7377.dtsi Normal file
View File

@ -0,0 +1,21 @@
/*
* Device Tree Source for the sh7377 SoC
*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "renesas,sh7377";
cpus {
cpu@0 {
compatible = "arm,cortex-a8";
};
};
};

41
arch/arm/mach-exynos/clock-exynos4.c
View File

@ -619,10 +619,6 @@ static struct clk exynos4_init_clocks_off[] = {
.devname = "samsung-ac97",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "fimg2d",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "mfc",
.devname = "s5p-mfc",
@ -819,47 +815,21 @@ static struct clk *exynos4_clkset_mout_g2d0_list[] = {
[1] = &exynos4_clk_sclk_apll.clk,
};
static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
struct clksrc_sources exynos4_clkset_mout_g2d0 = {
.sources = exynos4_clkset_mout_g2d0_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
};
static struct clksrc_clk exynos4_clk_mout_g2d0 = {
.clk = {
.name = "mout_g2d0",
},
.sources = &exynos4_clkset_mout_g2d0,
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
};
static struct clk *exynos4_clkset_mout_g2d1_list[] = {
[0] = &exynos4_clk_mout_epll.clk,
[1] = &exynos4_clk_sclk_vpll.clk,
};
static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
struct clksrc_sources exynos4_clkset_mout_g2d1 = {
.sources = exynos4_clkset_mout_g2d1_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
};
static struct clksrc_clk exynos4_clk_mout_g2d1 = {
.clk = {
.name = "mout_g2d1",
},
.sources = &exynos4_clkset_mout_g2d1,
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
};
static struct clk *exynos4_clkset_mout_g2d_list[] = {
[0] = &exynos4_clk_mout_g2d0.clk,
[1] = &exynos4_clk_mout_g2d1.clk,
};
static struct clksrc_sources exynos4_clkset_mout_g2d = {
.sources = exynos4_clkset_mout_g2d_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
};
static struct clk *exynos4_clkset_mout_mfc0_list[] = {
[0] = &exynos4_clk_mout_mpll.clk,
[1] = &exynos4_clk_sclk_apll.clk,
@ -1124,13 +1094,6 @@ static struct clksrc_clk exynos4_clksrcs[] = {
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_fimg2d",
},
.sources = &exynos4_clkset_mout_g2d,
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_mfc",

3
arch/arm/mach-exynos/clock-exynos4.h
View File

@ -23,6 +23,9 @@ extern struct clksrc_sources exynos4_clkset_group;
extern struct clk *exynos4_clkset_aclk_top_list[];
extern struct clk *exynos4_clkset_group_list[];
extern struct clksrc_sources exynos4_clkset_mout_g2d0;
extern struct clksrc_sources exynos4_clkset_mout_g2d1;
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);

37
arch/arm/mach-exynos/clock-exynos4210.c
View File

@ -48,6 +48,32 @@ static struct clksrc_clk *sysclks[] = {
/* nothing here yet */
};
static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
.clk = {
.name = "mout_g2d0",
},
.sources = &exynos4_clkset_mout_g2d0,
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
};
static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
.clk = {
.name = "mout_g2d1",
},
.sources = &exynos4_clkset_mout_g2d1,
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
};
static struct clk *exynos4210_clkset_mout_g2d_list[] = {
[0] = &exynos4210_clk_mout_g2d0.clk,
[1] = &exynos4210_clk_mout_g2d1.clk,
};
static struct clksrc_sources exynos4210_clkset_mout_g2d = {
.sources = exynos4210_clkset_mout_g2d_list,
.nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
};
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
@ -74,6 +100,13 @@ static struct clksrc_clk clksrcs[] = {
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_fimg2d",
},
.sources = &exynos4210_clkset_mout_g2d,
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
},
};
@ -105,6 +138,10 @@ static struct clk init_clocks_off[] = {
.devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "fimg2d",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 0),
},
};

41
arch/arm/mach-exynos/clock-exynos4212.c
View File

@ -68,12 +68,45 @@ static struct clksrc_clk clk_mout_mpll_user = {
.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
};
static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
.clk = {
.name = "mout_g2d0",
},
.sources = &exynos4_clkset_mout_g2d0,
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
};
static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
.clk = {
.name = "mout_g2d1",
},
.sources = &exynos4_clkset_mout_g2d1,
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
};
static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
[0] = &exynos4x12_clk_mout_g2d0.clk,
[1] = &exynos4x12_clk_mout_g2d1.clk,
};
static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
.sources = exynos4x12_clkset_mout_g2d_list,
.nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
};
static struct clksrc_clk *sysclks[] = {
&clk_mout_mpll_user,
};
static struct clksrc_clk clksrcs[] = {
/* nothing here yet */
{
.clk = {
.name = "sclk_fimg2d",
},
.sources = &exynos4x12_clkset_mout_g2d,
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
},
};
static struct clk init_clocks_off[] = {
@ -102,7 +135,11 @@ static struct clk init_clocks_off[] = {
.devname = "exynos-fimc-lite.1",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 3),
}
}, {
.name = "fimg2d",
.enable = exynos4_clk_ip_dmc_ctrl,
.ctrlbit = (1 << 23),
},
};
#ifdef CONFIG_PM_SLEEP

4
arch/arm/mach-s3c64xx/include/mach/pm-core.h
View File

@ -12,6 +12,9 @@
* published by the Free Software Foundation.
*/
#ifndef __MACH_S3C64XX_PM_CORE_H
#define __MACH_S3C64XX_PM_CORE_H __FILE__
#include <mach/regs-gpio.h>
static inline void s3c_pm_debug_init_uart(void)
@ -113,3 +116,4 @@ static inline void samsung_pm_saved_gpios(void)
__raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
}
#endif /* __MACH_S3C64XX_PM_CORE_H */

1
arch/arm/mach-shmobile/Kconfig
View File

@ -19,6 +19,7 @@ config ARCH_SH7372
select CPU_V7
select SH_CLK_CPG
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_CPU_SUSPEND if PM || CPU_IDLE
config ARCH_SH73A0
bool "SH-Mobile AG5 (R8A73A00)"

2
arch/arm/mach-shmobile/Makefile
View File

@ -39,7 +39,9 @@ obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o
# PM objects
obj-$(CONFIG_SUSPEND) += suspend.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_ARCH_SHMOBILE) += pm-rmobile.o
obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o
obj-$(CONFIG_ARCH_R8A7740) += pm-r8a7740.o
obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o
# Board objects

14
arch/arm/mach-shmobile/board-ap4evb.c
View File

@ -1447,14 +1447,14 @@ static void __init ap4evb_init(void)
platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc1_device);
sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc1_device);
rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device);
rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device);
hdmi_init_pm_clock();
fsi_init_pm_clock();

1
arch/arm/mach-shmobile/board-armadillo800eva.c
View File

@ -587,6 +587,7 @@ static void __init eva_init(void)
eva_clock_init();
r8a7740_pinmux_init();
r8a7740_meram_workaround();
/* SCIFA1 */
gpio_request(GPIO_FN_SCIFA1_RXD, NULL);

24
arch/arm/mach-shmobile/board-mackerel.c
View File

@ -1614,20 +1614,20 @@ static void __init mackerel_init(void)
platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4lc, &meram_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &nand_flash_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
rmobile_add_device_to_domain(&sh7372_pd_a4lc, &hdmi_lcdc_device);
rmobile_add_device_to_domain(&sh7372_pd_a4lc, &meram_device);
rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs0_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs1_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &nand_flash_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device);
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device);
#endif
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device);
sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi2_device);
rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device);
hdmi_init_pm_clock();
sh7372_pm_init();

150
arch/arm/mach-shmobile/clock-r8a7740.c
View File

@ -43,7 +43,10 @@
/* CPG registers */
#define FRQCRA 0xe6150000
#define FRQCRB 0xe6150004
#define VCLKCR1 0xE6150008
#define VCLKCR2 0xE615000c
#define FRQCRC 0xe61500e0
#define FSIACKCR 0xe6150018
#define PLLC01CR 0xe6150028
#define SUBCKCR 0xe6150080
@ -54,6 +57,8 @@
#define MSTPSR2 0xe6150040
#define MSTPSR3 0xe6150048
#define MSTPSR4 0xe615004c
#define FSIBCKCR 0xe6150090
#define HDMICKCR 0xe6150094
#define SMSTPCR0 0xe6150130
#define SMSTPCR1 0xe6150134
#define SMSTPCR2 0xe6150138
@ -271,6 +276,13 @@ static struct clk usb24_clk = {
.parent = &usb24s_clk,
};
/* External FSIACK/FSIBCK clock */
static struct clk fsiack_clk = {
};
static struct clk fsibck_clk = {
};
struct clk *main_clks[] = {
&extalr_clk,
&extal1_clk,
@ -288,6 +300,8 @@ struct clk *main_clks[] = {
&pllc1_div2_clk,
&usb24s_clk,
&usb24_clk,
&fsiack_clk,
&fsibck_clk,
};
static void div4_kick(struct clk *clk)
@ -313,6 +327,107 @@ static struct clk_div4_table div4_table = {
.kick = div4_kick,
};
/* DIV6 reparent */
enum {
DIV6_HDMI,
DIV6_VCLK1, DIV6_VCLK2,
DIV6_FSIA, DIV6_FSIB,
DIV6_REPARENT_NR,
};
static struct clk *hdmi_parent[] = {
[0] = &pllc1_div2_clk,
[1] = &system_clk,
[2] = &dv_clk
};
static struct clk *vclk_parents[8] = {
[0] = &pllc1_div2_clk,
[2] = &dv_clk,
[3] = &usb24s_clk,
[4] = &extal1_div2_clk,
[5] = &extalr_clk,
};
static struct clk *fsia_parents[] = {
[0] = &pllc1_div2_clk,
[1] = &fsiack_clk, /* external clock */
};
static struct clk *fsib_parents[] = {
[0] = &pllc1_div2_clk,
[1] = &fsibck_clk, /* external clock */
};
static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
[DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
[DIV6_VCLK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3),
[DIV6_VCLK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3),
[DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
[DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
};
/* HDMI1/2 clock */
static unsigned long hdmi12_recalc(struct clk *clk)
{
u32 val = __raw_readl(HDMICKCR);
int shift = (int)clk->priv;
val >>= shift;
val &= 0x3;
return clk->parent->rate / (1 << val);
};
static int hdmi12_set_rate(struct clk *clk, unsigned long rate)
{
u32 val, mask;
int i, shift;
for (i = 0; i < 3; i++)
if (rate == clk->parent->rate / (1 << i))
goto find;
return -ENODEV;
find:
shift = (int)clk->priv;
val = __raw_readl(HDMICKCR);
mask = ~(0x3 << shift);
val = (val & mask) | i << shift;
__raw_writel(val, HDMICKCR);
return 0;
};
static struct sh_clk_ops hdmi12_clk_ops = {
.recalc = hdmi12_recalc,
.set_rate = hdmi12_set_rate,
};
static struct clk hdmi1_clk = {
.ops = &hdmi12_clk_ops,
.priv = (void *)9,
.parent = &div6_reparent_clks[DIV6_HDMI], /* late install */
};
static struct clk hdmi2_clk = {
.ops = &hdmi12_clk_ops,
.priv = (void *)11,
.parent = &div6_reparent_clks[DIV6_HDMI], /* late install */
};
static struct clk *late_main_clks[] = {
&hdmi1_clk,
&hdmi2_clk,
};
/* MSTP */
enum {
DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
@ -343,11 +458,12 @@ static struct clk div6_clks[DIV6_NR] = {
};
enum {
MSTP125,
MSTP128, MSTP127, MSTP125,
MSTP116, MSTP111, MSTP100, MSTP117,
MSTP230,
MSTP222,
MSTP218, MSTP217, MSTP216, MSTP214,
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP329, MSTP328, MSTP323, MSTP320,
@ -360,6 +476,8 @@ enum {
};
static struct clk mstp_clks[MSTP_NR] = {
[MSTP128] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 28, 0), /* CEU21 */
[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */
[MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
[MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
[MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
@ -368,6 +486,10 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
[MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
[MSTP216] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
[MSTP214] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
[MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
[MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
@ -408,6 +530,12 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
CLKDEV_CON_ID("usb24s", &usb24s_clk),
CLKDEV_CON_ID("hdmi1", &hdmi1_clk),
CLKDEV_CON_ID("hdmi2", &hdmi2_clk),
CLKDEV_CON_ID("video1", &div6_reparent_clks[DIV6_VCLK1]),
CLKDEV_CON_ID("video2", &div6_reparent_clks[DIV6_VCLK2]),
CLKDEV_CON_ID("fsiack", &fsiack_clk),
CLKDEV_CON_ID("fsibck", &fsibck_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
@ -430,6 +558,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]),
CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]),
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
@ -438,7 +568,10 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]),
CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]),
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]),
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
@ -459,6 +592,10 @@ static struct clk_lookup lookups[] = {
CLKDEV_ICK_ID("phy", "renesas_usbhs", &mstp_clks[MSTP406]),
CLKDEV_ICK_ID("pci", "renesas_usbhs", &div4_clks[DIV4_USBP]),
CLKDEV_ICK_ID("usb24", "renesas_usbhs", &usb24_clk),
CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
};
void __init r8a7740_clock_init(u8 md_ck)
@ -495,7 +632,14 @@ void __init r8a7740_clock_init(u8 md_ck)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
ret = sh_clk_div6_reparent_register(div6_reparent_clks,
DIV6_REPARENT_NR);
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
ret = clk_register(late_main_clks[k]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));

2
arch/arm/mach-shmobile/clock-r8a7779.c
View File

@ -162,7 +162,7 @@ void __init r8a7779_clock_init(void)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
ret = clk_register(late_main_clks[k]);

2
arch/arm/mach-shmobile/clock-sh7367.c
View File

@ -344,7 +344,7 @@ void __init sh7367_clock_init(void)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));

2
arch/arm/mach-shmobile/clock-sh7372.c
View File

@ -704,7 +704,7 @@ void __init sh7372_clock_init(void)
ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
ret = clk_register(late_main_clks[k]);

2
arch/arm/mach-shmobile/clock-sh7377.c
View File

@ -355,7 +355,7 @@ void __init sh7377_clock_init(void)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));

12
arch/arm/mach-shmobile/clock-sh73a0.c
View File

@ -475,9 +475,9 @@ static struct clk *late_main_clks[] = {
enum { MSTP001,
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
MSTP219, MSTP218,
MSTP219, MSTP218, MSTP217,
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP331, MSTP329, MSTP325, MSTP323,
MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
MSTP314, MSTP313, MSTP312, MSTP311,
MSTP303, MSTP302, MSTP301, MSTP300,
MSTP411, MSTP410, MSTP403,
@ -498,6 +498,7 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
[MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
[MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
[MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* MP-DMAC */
[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
@ -507,8 +508,10 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
[MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
[MSTP328] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /*FSI*/
[MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
[MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
[MSTP322] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 22, 0), /* USB */
[MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
[MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
[MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
@ -553,6 +556,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* MP-DMAC */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
@ -562,8 +566,10 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
@ -612,7 +618,7 @@ void __init sh73a0_clock_init(void)
ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
ret = clk_register(late_main_clks[k]);

1
arch/arm/mach-shmobile/include/mach/common.h
View File

@ -77,6 +77,7 @@ extern void r8a7779_add_standard_devices(void);
extern void r8a7779_clock_init(void);
extern void r8a7779_pinmux_init(void);
extern void r8a7779_pm_init(void);
extern void r8a7740_meram_workaround(void);
extern unsigned int r8a7779_get_core_count(void);
extern int r8a7779_platform_cpu_kill(unsigned int cpu);

84
arch/arm/mach-shmobile/include/mach/dma-register.h Normal file
View File

@ -0,0 +1,84 @@
/*
* SH-ARM CPU-specific DMA definitions, used by both DMA drivers
*
* Copyright (C) 2012 Renesas Solutions Corp
*
* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* Based on arch/sh/include/cpu-sh4/cpu/dma-register.h
* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef DMA_REGISTER_H
#define DMA_REGISTER_H
/*
* Direct Memory Access Controller
*/
/* Transmit sizes and respective CHCR register values */
enum {
XMIT_SZ_8BIT = 0,
XMIT_SZ_16BIT = 1,
XMIT_SZ_32BIT = 2,
XMIT_SZ_64BIT = 7,
XMIT_SZ_128BIT = 3,
XMIT_SZ_256BIT = 4,
XMIT_SZ_512BIT = 5,
};
/* log2(size / 8) - used to calculate number of transfers */
static const unsigned int dma_ts_shift[] = {
[XMIT_SZ_8BIT] = 0,
[XMIT_SZ_16BIT] = 1,
[XMIT_SZ_32BIT] = 2,
[XMIT_SZ_64BIT] = 3,
[XMIT_SZ_128BIT] = 4,
[XMIT_SZ_256BIT] = 5,
[XMIT_SZ_512BIT] = 6,
};
#define TS_LOW_BIT 0x3 /* --xx */
#define TS_HI_BIT 0xc /* xx-- */
#define TS_LOW_SHIFT (3)
#define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */
#define TS_INDEX2VAL(i) \
((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
(((i) & TS_HI_BIT) << TS_HI_SHIFT))
#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
/*
* USB High-Speed DMAC
*/
/* Transmit sizes and respective CHCR register values */
enum {
USBTS_XMIT_SZ_8BYTE = 0,
USBTS_XMIT_SZ_16BYTE = 1,
USBTS_XMIT_SZ_32BYTE = 2,
};
/* log2(size / 8) - used to calculate number of transfers */
static const unsigned int dma_usbts_shift[] = {
[USBTS_XMIT_SZ_8BYTE] = 3,
[USBTS_XMIT_SZ_16BYTE] = 4,
[USBTS_XMIT_SZ_32BYTE] = 5,
};
#define USBTS_LOW_BIT 0x3 /* --xx */
#define USBTS_HI_BIT 0x0 /* ---- */
#define USBTS_LOW_SHIFT 6
#define USBTS_HI_SHIFT 0
#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
#endif /* DMA_REGISTER_H */

32
arch/arm/mach-shmobile/include/mach/gpio.h
View File

@ -13,6 +13,7 @@
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/sh_pfc.h>
#include <linux/io.h>
#ifdef CONFIG_GPIOLIB
@ -27,4 +28,35 @@ static inline int irq_to_gpio(unsigned int irq)
#endif /* CONFIG_GPIOLIB */
/*
* FIXME !!
*
* current gpio frame work doesn't have
* the method to control only pull up/down/free.
* this function should be replaced by correct gpio function
*/
static inline void __init gpio_direction_none(u32 addr)
{
__raw_writeb(0x00, addr);
}
static inline void __init gpio_request_pullup(u32 addr)
{
u8 data = __raw_readb(addr);
data &= 0x0F;
data |= 0xC0;
__raw_writeb(data, addr);
}
static inline void __init gpio_request_pulldown(u32 addr)
{
u8 data = __raw_readb(addr);
data &= 0x0F;
data |= 0xA0;
__raw_writeb(data, addr);
}
#endif /* __ASM_ARCH_GPIO_H */

44
arch/arm/mach-shmobile/include/mach/pm-rmobile.h Normal file
View File

@ -0,0 +1,44 @@
/*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef PM_RMOBILE_H
#define PM_RMOBILE_H
#include <linux/pm_domain.h>
struct platform_device;
struct rmobile_pm_domain {
struct generic_pm_domain genpd;
struct dev_power_governor *gov;
int (*suspend)(void);
void (*resume)(void);
unsigned int bit_shift;
bool no_debug;
};
static inline
struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d)
{
return container_of(d, struct rmobile_pm_domain, genpd);
}
#ifdef CONFIG_PM
extern void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd);
extern void rmobile_add_device_to_domain(struct rmobile_pm_domain *rmobile_pd,
struct platform_device *pdev);
extern void rmobile_pm_add_subdomain(struct rmobile_pm_domain *rmobile_pd,
struct rmobile_pm_domain *rmobile_sd);
#else
#define rmobile_init_pm_domain(pd) do { } while (0)
#define rmobile_add_device_to_domain(pd, pdev) do { } while (0)
#define rmobile_pm_add_subdomain(pd, sd) do { } while (0)
#endif /* CONFIG_PM */
#endif /* PM_RMOBILE_H */

33
arch/arm/mach-shmobile/include/mach/r8a7740.h
View File

@ -19,6 +19,8 @@
#ifndef __ASM_R8A7740_H__
#define __ASM_R8A7740_H__
#include <mach/pm-rmobile.h>
/*
* MD_CKx pin
*/
@ -139,7 +141,7 @@ enum {
GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20,
GPIO_FN_DBGMD21,
/* FSI */
/* FSI-A */
GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */
GPIO_FN_FSIAISLD_PORT5,
GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */
@ -150,6 +152,9 @@ enum {
GPIO_FN_FSIACK, GPIO_FN_FSIAILR,
GPIO_FN_FSIAIBT,
/* FSI-B */
GPIO_FN_FSIBCK,
/* FMSI */
GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
GPIO_FN_FMSISLD_PORT6,
@ -565,6 +570,10 @@ enum {
GPIO_FN_RESETP_PULLUP,
GPIO_FN_RESETP_PLAIN,
/* HDMI */
GPIO_FN_HDMI_HPD,
GPIO_FN_HDMI_CEC,
/* SDENC */
GPIO_FN_SDENC_CPG,
GPIO_FN_SDENC_DV_CLKI,
@ -581,4 +590,26 @@ enum {
GPIO_FN_TRACEAUD_FROM_MEMC,
};
/* DMA slave IDs */
enum {
SHDMA_SLAVE_INVALID,
SHDMA_SLAVE_SDHI0_RX,
SHDMA_SLAVE_SDHI0_TX,
SHDMA_SLAVE_SDHI1_RX,
SHDMA_SLAVE_SDHI1_TX,
SHDMA_SLAVE_SDHI2_RX,
SHDMA_SLAVE_SDHI2_TX,
SHDMA_SLAVE_FSIA_RX,
SHDMA_SLAVE_FSIA_TX,
SHDMA_SLAVE_FSIB_TX,
SHDMA_SLAVE_USBHS_TX,
SHDMA_SLAVE_USBHS_RX,
};
#ifdef CONFIG_PM
extern struct rmobile_pm_domain r8a7740_pd_a4s;
extern struct rmobile_pm_domain r8a7740_pd_a3sp;
extern struct rmobile_pm_domain r8a7740_pd_a4lc;
#endif /* CONFIG_PM */
#endif /* __ASM_R8A7740_H__ */

45
arch/arm/mach-shmobile/include/mach/sh7372.h
View File

@ -13,6 +13,7 @@
#include <linux/sh_clk.h>
#include <linux/pm_domain.h>
#include <mach/pm-rmobile.h>
/*
* Pin Function Controller:
@ -477,42 +478,16 @@ extern struct clk sh7372_fsibck_clk;
extern struct clk sh7372_fsidiva_clk;
extern struct clk sh7372_fsidivb_clk;
struct platform_device;
struct sh7372_pm_domain {
struct generic_pm_domain genpd;
struct dev_power_governor *gov;
int (*suspend)(void);
void (*resume)(void);
unsigned int bit_shift;
bool no_debug;
};
static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d)
{
return container_of(d, struct sh7372_pm_domain, genpd);
}
#ifdef CONFIG_PM
extern struct sh7372_pm_domain sh7372_a4lc;
extern struct sh7372_pm_domain sh7372_a4mp;
extern struct sh7372_pm_domain sh7372_d4;
extern struct sh7372_pm_domain sh7372_a4r;
extern struct sh7372_pm_domain sh7372_a3rv;
extern struct sh7372_pm_domain sh7372_a3ri;
extern struct sh7372_pm_domain sh7372_a4s;
extern struct sh7372_pm_domain sh7372_a3sp;
extern struct sh7372_pm_domain sh7372_a3sg;
extern void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd);
extern void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
struct platform_device *pdev);
extern void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
struct sh7372_pm_domain *sh7372_sd);
#else
#define sh7372_init_pm_domain(pd) do { } while(0)
#define sh7372_add_device_to_domain(pd, pdev) do { } while(0)
#define sh7372_pm_add_subdomain(pd, sd) do { } while(0)
extern struct rmobile_pm_domain sh7372_pd_a4lc;
extern struct rmobile_pm_domain sh7372_pd_a4mp;
extern struct rmobile_pm_domain sh7372_pd_d4;
extern struct rmobile_pm_domain sh7372_pd_a4r;
extern struct rmobile_pm_domain sh7372_pd_a3rv;
extern struct rmobile_pm_domain sh7372_pd_a3ri;
extern struct rmobile_pm_domain sh7372_pd_a4s;
extern struct rmobile_pm_domain sh7372_pd_a3sp;
extern struct rmobile_pm_domain sh7372_pd_a3sg;
#endif /* CONFIG_PM */
extern void sh7372_intcs_suspend(void);

7
arch/arm/mach-shmobile/include/mach/sh73a0.h
View File

@ -516,6 +516,13 @@ enum {
SHDMA_SLAVE_SDHI2_RX,
SHDMA_SLAVE_MMCIF_TX,
SHDMA_SLAVE_MMCIF_RX,
SHDMA_SLAVE_FSI2A_TX,
SHDMA_SLAVE_FSI2A_RX,
SHDMA_SLAVE_FSI2B_TX,
SHDMA_SLAVE_FSI2B_RX,
SHDMA_SLAVE_FSI2C_TX,
SHDMA_SLAVE_FSI2C_RX,
SHDMA_SLAVE_FSI2D_RX,
};
/*

13
arch/arm/mach-shmobile/intc-r8a7740.c
View File

@ -71,10 +71,12 @@ enum {
DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
HDMI,
USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
SPU2_0, SPU2_1,
FSI, FMSI,
HDMI_SSS, HDMI_KEY,
IPMMU,
AP_ARM_CTIIRQ, AP_ARM_PMURQ,
MFIS2,
@ -182,6 +184,7 @@ static struct intc_vect intca_vectors[] __initdata = {
INTC_VECT(USBH_EHCI, 0x1580),
INTC_VECT(USBH_PME, 0x15A0),
INTC_VECT(USBH_BIND, 0x15C0),
INTC_VECT(HDMI, 0x1700),
INTC_VECT(RSPI_OVRF, 0x1780),
INTC_VECT(RSPI_SPTEF, 0x17A0),
INTC_VECT(RSPI_SPRF, 0x17C0),
@ -189,6 +192,8 @@ static struct intc_vect intca_vectors[] __initdata = {
INTC_VECT(SPU2_1, 0x1820),
INTC_VECT(FSI, 0x1840),
INTC_VECT(FMSI, 0x1860),
INTC_VECT(HDMI_SSS, 0x18A0),
INTC_VECT(HDMI_KEY, 0x18C0),
INTC_VECT(IPMMU, 0x1920),
INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
INTC_VECT(AP_ARM_PMURQ, 0x19A0),
@ -304,11 +309,11 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
/* IMR3A3 / IMCR3A3 */
{ /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
{ 0, 0, 0, 0,
{ HDMI, 0, 0, 0,
RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
{ /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
{ SPU2_0, SPU2_1, FSI, FMSI,
0, 0, 0, 0 } },
0, HDMI_SSS, HDMI_KEY, 0 } },
{ /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
{ 0, IPMMU, 0, 0,
AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
@ -353,10 +358,10 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
{ 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
/* IPRGA3 */
/* IPRHA3 */
/* IPRIA3 */
{ 0xe6950020, 0, 16, 4, /* IPRIA3 */ { HDMI, 0, 0, 0 } },
{ 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
{ 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
/* IPRLA3 */
{ 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, HDMI_SSS, HDMI_KEY, 0 } },
{ 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
{ 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
{ 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,

24
arch/arm/mach-shmobile/pfc-r8a7740.c
View File

@ -169,7 +169,7 @@ enum {
DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
DBGMD21_MARK,
/* FSI */
/* FSI-A */
FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
FSIAISLD_PORT5_MARK,
FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
@ -178,6 +178,9 @@ enum {
FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
/* FSI-B */
FSIBCK_MARK,
/* FMSI */
FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
FMSISLD_PORT6_MARK,
@ -560,6 +563,9 @@ enum {
/* SDENC */
SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
/* HDMI */
HDMI_HPD_MARK, HDMI_CEC_MARK,
/* DEBUG */
EDEBGREQ_PULLUP_MARK, /* for JTAG */
EDEBGREQ_PULLDOWN_MARK,
@ -771,6 +777,7 @@ static pinmux_enum_t pinmux_data[] = {
/* Port11 */
PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
/* Port12 */
@ -1254,7 +1261,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(A21_MARK, PORT120_FN1),
PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0),
PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
/* Port121 */
PINMUX_DATA(A20_MARK, PORT121_FN1),
@ -1616,13 +1623,15 @@ static pinmux_enum_t pinmux_data[] = {
/* Port209 */
PINMUX_DATA(VBUS_MARK, PORT209_FN1),
PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1),
PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
/* Port210 */
PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
/* Port211 */
PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
/* LCDC select */
PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
@ -1691,7 +1700,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20),
GPIO_FN(DBGMD21),
/* FSI */
/* FSI-A */
GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */
GPIO_FN(FSIAISLD_PORT5),
GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */
@ -1700,6 +1709,9 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC),
GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT),
/* FSI-B */
GPIO_FN(FSIBCK),
/* FMSI */
GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
GPIO_FN(FMSISLD_PORT6),
@ -2097,6 +2109,10 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(SDENC_CPG),
GPIO_FN(SDENC_DV_CLKI),
/* HDMI */
GPIO_FN(HDMI_HPD),
GPIO_FN(HDMI_CEC),
/* SYSC */
GPIO_FN(RESETP_PULLUP),
GPIO_FN(RESETP_PLAIN),

54
arch/arm/mach-shmobile/pm-r8a7740.c Normal file
View File

@ -0,0 +1,54 @@
/*
* r8a7740 power management support
*
* Copyright (C) 2012 Renesas Solutions Corp.
* Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/console.h>
#include <mach/pm-rmobile.h>
#ifdef CONFIG_PM
static int r8a7740_pd_a4s_suspend(void)
{
/*
* The A4S domain contains the CPU core and therefore it should
* only be turned off if the CPU is in use.
*/
return -EBUSY;
}
struct rmobile_pm_domain r8a7740_pd_a4s = {
.genpd.name = "A4S",
.bit_shift = 10,
.gov = &pm_domain_always_on_gov,
.no_debug = true,
.suspend = r8a7740_pd_a4s_suspend,
};
static int r8a7740_pd_a3sp_suspend(void)
{
/*
* Serial consoles make use of SCIF hardware located in A3SP,
* keep such power domain on if "no_console_suspend" is set.
*/
return console_suspend_enabled ? 0 : -EBUSY;
}
struct rmobile_pm_domain r8a7740_pd_a3sp = {
.genpd.name = "A3SP",
.bit_shift = 11,
.gov = &pm_domain_always_on_gov,
.no_debug = true,
.suspend = r8a7740_pd_a3sp_suspend,
};
struct rmobile_pm_domain r8a7740_pd_a4lc = {
.genpd.name = "A4LC",
.bit_shift = 1,
};
#endif /* CONFIG_PM */

167
arch/arm/mach-shmobile/pm-rmobile.c Normal file
View File

@ -0,0 +1,167 @@
/*
* rmobile power management support
*
* Copyright (C) 2012 Renesas Solutions Corp.
* Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* based on pm-sh7372.c
* Copyright (C) 2011 Magnus Damm
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_clock.h>
#include <asm/io.h>
#include <mach/pm-rmobile.h>
/* SYSC */
#define SPDCR 0xe6180008
#define SWUCR 0xe6180014
#define PSTR 0xe6180080
#define PSTR_RETRIES 100
#define PSTR_DELAY_US 10
#ifdef CONFIG_PM
static int rmobile_pd_power_down(struct generic_pm_domain *genpd)
{
struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd);
unsigned int mask = 1 << rmobile_pd->bit_shift;
if (rmobile_pd->suspend) {
int ret = rmobile_pd->suspend();
if (ret)
return ret;
}
if (__raw_readl(PSTR) & mask) {
unsigned int retry_count;
__raw_writel(mask, SPDCR);
for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
if (!(__raw_readl(SPDCR) & mask))
break;
cpu_relax();
}
}
if (!rmobile_pd->no_debug)
pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n",
genpd->name, mask, __raw_readl(PSTR));
return 0;
}
static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd,
bool do_resume)
{
unsigned int mask = 1 << rmobile_pd->bit_shift;
unsigned int retry_count;
int ret = 0;
if (__raw_readl(PSTR) & mask)
goto out;
__raw_writel(mask, SWUCR);
for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
if (!(__raw_readl(SWUCR) & mask))
break;
if (retry_count > PSTR_RETRIES)
udelay(PSTR_DELAY_US);
else
cpu_relax();
}
if (!retry_count)
ret = -EIO;
if (!rmobile_pd->no_debug)
pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
rmobile_pd->genpd.name, mask, __raw_readl(PSTR));
out:
if (ret == 0 && rmobile_pd->resume && do_resume)
rmobile_pd->resume();
return ret;
}
static int rmobile_pd_power_up(struct generic_pm_domain *genpd)
{
return __rmobile_pd_power_up(to_rmobile_pd(genpd), true);
}
static bool rmobile_pd_active_wakeup(struct device *dev)
{
bool (*active_wakeup)(struct device *dev);
active_wakeup = dev_gpd_data(dev)->ops.active_wakeup;
return active_wakeup ? active_wakeup(dev) : true;
}
static int rmobile_pd_stop_dev(struct device *dev)
{
int (*stop)(struct device *dev);
stop = dev_gpd_data(dev)->ops.stop;
if (stop) {
int ret = stop(dev);
if (ret)
return ret;
}
return pm_clk_suspend(dev);
}
static int rmobile_pd_start_dev(struct device *dev)
{
int (*start)(struct device *dev);
int ret;
ret = pm_clk_resume(dev);
if (ret)
return ret;
start = dev_gpd_data(dev)->ops.start;
if (start)
ret = start(dev);
return ret;
}
void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
{
struct generic_pm_domain *genpd = &rmobile_pd->genpd;
struct dev_power_governor *gov = rmobile_pd->gov;
pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
genpd->dev_ops.stop = rmobile_pd_stop_dev;
genpd->dev_ops.start = rmobile_pd_start_dev;
genpd->dev_ops.active_wakeup = rmobile_pd_active_wakeup;
genpd->dev_irq_safe = true;
genpd->power_off = rmobile_pd_power_down;
genpd->power_on = rmobile_pd_power_up;
__rmobile_pd_power_up(rmobile_pd, false);
}
void rmobile_add_device_to_domain(struct rmobile_pm_domain *rmobile_pd,
struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
pm_genpd_add_device(&rmobile_pd->genpd, dev);
if (pm_clk_no_clocks(dev))
pm_clk_add(dev, NULL);
}
void rmobile_pm_add_subdomain(struct rmobile_pm_domain *rmobile_pd,
struct rmobile_pm_domain *rmobile_sd)
{
pm_genpd_add_subdomain(&rmobile_pd->genpd, &rmobile_sd->genpd);
}
#endif /* CONFIG_PM */

309
arch/arm/mach-shmobile/pm-sh7372.c
View File

@ -26,6 +26,7 @@
#include <asm/suspend.h>
#include <mach/common.h>
#include <mach/sh7372.h>
#include <mach/pm-rmobile.h>
/* DBG */
#define DBGREG1 0xe6100020
@ -41,13 +42,10 @@
#define PLLC01STPCR 0xe61500c8
/* SYSC */
#define SPDCR 0xe6180008
#define SWUCR 0xe6180014
#define SBAR 0xe6180020
#define WUPRMSK 0xe6180028
#define WUPSMSK 0xe618002c
#define WUPSMSK2 0xe6180048
#define PSTR 0xe6180080
#define WUPSFAC 0xe6180098
#define IRQCR 0xe618022c
#define IRQCR2 0xe6180238
@ -71,188 +69,48 @@
/* AP-System Core */
#define APARMBAREA 0xe6f10020
#define PSTR_RETRIES 100
#define PSTR_DELAY_US 10
#ifdef CONFIG_PM
static int pd_power_down(struct generic_pm_domain *genpd)
{
struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
unsigned int mask = 1 << sh7372_pd->bit_shift;
struct rmobile_pm_domain sh7372_pd_a4lc = {
.genpd.name = "A4LC",
.bit_shift = 1,
};
if (sh7372_pd->suspend) {
int ret = sh7372_pd->suspend();
struct rmobile_pm_domain sh7372_pd_a4mp = {
.genpd.name = "A4MP",
.bit_shift = 2,
};
if (ret)
return ret;
}
struct rmobile_pm_domain sh7372_pd_d4 = {
.genpd.name = "D4",
.bit_shift = 3,
};
if (__raw_readl(PSTR) & mask) {
unsigned int retry_count;
__raw_writel(mask, SPDCR);
for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
if (!(__raw_readl(SPDCR) & mask))
break;
cpu_relax();
}
}
if (!sh7372_pd->no_debug)
pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n",
genpd->name, mask, __raw_readl(PSTR));
return 0;
}
static int __pd_power_up(struct sh7372_pm_domain *sh7372_pd, bool do_resume)
{
unsigned int mask = 1 << sh7372_pd->bit_shift;
unsigned int retry_count;
int ret = 0;
if (__raw_readl(PSTR) & mask)
goto out;
__raw_writel(mask, SWUCR);
for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
if (!(__raw_readl(SWUCR) & mask))
break;
if (retry_count > PSTR_RETRIES)
udelay(PSTR_DELAY_US);
else
cpu_relax();
}
if (!retry_count)
ret = -EIO;
if (!sh7372_pd->no_debug)
pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
sh7372_pd->genpd.name, mask, __raw_readl(PSTR));
out:
if (ret == 0 && sh7372_pd->resume && do_resume)
sh7372_pd->resume();
return ret;
}
static int pd_power_up(struct generic_pm_domain *genpd)
{
return __pd_power_up(to_sh7372_pd(genpd), true);
}
static int sh7372_a4r_suspend(void)
static int sh7372_a4r_pd_suspend(void)
{
sh7372_intcs_suspend();
__raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
return 0;
}
static bool pd_active_wakeup(struct device *dev)
{
bool (*active_wakeup)(struct device *dev);
active_wakeup = dev_gpd_data(dev)->ops.active_wakeup;
return active_wakeup ? active_wakeup(dev) : true;
}
static int sh7372_stop_dev(struct device *dev)
{
int (*stop)(struct device *dev);
stop = dev_gpd_data(dev)->ops.stop;
if (stop) {
int ret = stop(dev);
if (ret)
return ret;
}
return pm_clk_suspend(dev);
}
static int sh7372_start_dev(struct device *dev)
{
int (*start)(struct device *dev);
int ret;
ret = pm_clk_resume(dev);
if (ret)
return ret;
start = dev_gpd_data(dev)->ops.start;
if (start)
ret = start(dev);
return ret;
}
void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
{
struct generic_pm_domain *genpd = &sh7372_pd->genpd;
struct dev_power_governor *gov = sh7372_pd->gov;
pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
genpd->dev_ops.stop = sh7372_stop_dev;
genpd->dev_ops.start = sh7372_start_dev;
genpd->dev_ops.active_wakeup = pd_active_wakeup;
genpd->dev_irq_safe = true;
genpd->power_off = pd_power_down;
genpd->power_on = pd_power_up;
__pd_power_up(sh7372_pd, false);
}
void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
pm_genpd_add_device(&sh7372_pd->genpd, dev);
if (pm_clk_no_clocks(dev))
pm_clk_add(dev, NULL);
}
void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
struct sh7372_pm_domain *sh7372_sd)
{
pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd);
}
struct sh7372_pm_domain sh7372_a4lc = {
.genpd.name = "A4LC",
.bit_shift = 1,
};
struct sh7372_pm_domain sh7372_a4mp = {
.genpd.name = "A4MP",
.bit_shift = 2,
};
struct sh7372_pm_domain sh7372_d4 = {
.genpd.name = "D4",
.bit_shift = 3,
};
struct sh7372_pm_domain sh7372_a4r = {
struct rmobile_pm_domain sh7372_pd_a4r = {
.genpd.name = "A4R",
.bit_shift = 5,
.suspend = sh7372_a4r_suspend,
.suspend = sh7372_a4r_pd_suspend,
.resume = sh7372_intcs_resume,
};
struct sh7372_pm_domain sh7372_a3rv = {
struct rmobile_pm_domain sh7372_pd_a3rv = {
.genpd.name = "A3RV",
.bit_shift = 6,
};
struct sh7372_pm_domain sh7372_a3ri = {
struct rmobile_pm_domain sh7372_pd_a3ri = {
.genpd.name = "A3RI",
.bit_shift = 8,
};
static int sh7372_a4s_suspend(void)
static int sh7372_pd_a4s_suspend(void)
{
/*
* The A4S domain contains the CPU core and therefore it should
@ -261,15 +119,15 @@ static int sh7372_a4s_suspend(void)
return -EBUSY;
}
struct sh7372_pm_domain sh7372_a4s = {
struct rmobile_pm_domain sh7372_pd_a4s = {
.genpd.name = "A4S",
.bit_shift = 10,
.gov = &pm_domain_always_on_gov,
.no_debug = true,
.suspend = sh7372_a4s_suspend,
.suspend = sh7372_pd_a4s_suspend,
};
static int sh7372_a3sp_suspend(void)
static int sh7372_a3sp_pd_suspend(void)
{
/*
* Serial consoles make use of SCIF hardware located in A3SP,
@ -278,32 +136,22 @@ static int sh7372_a3sp_suspend(void)
return console_suspend_enabled ? 0 : -EBUSY;
}
struct sh7372_pm_domain sh7372_a3sp = {
struct rmobile_pm_domain sh7372_pd_a3sp = {
.genpd.name = "A3SP",
.bit_shift = 11,
.gov = &pm_domain_always_on_gov,
.no_debug = true,
.suspend = sh7372_a3sp_suspend,
.suspend = sh7372_a3sp_pd_suspend,
};
struct sh7372_pm_domain sh7372_a3sg = {
struct rmobile_pm_domain sh7372_pd_a3sg = {
.genpd.name = "A3SG",
.bit_shift = 13,
};
#else /* !CONFIG_PM */
static inline void sh7372_a3sp_init(void) {}
#endif /* !CONFIG_PM */
#endif /* CONFIG_PM */
#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
static int sh7372_do_idle_core_standby(unsigned long unused)
{
cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
return 0;
}
static void sh7372_set_reset_vector(unsigned long address)
{
/* set reset vector, translate 4k */
@ -311,21 +159,6 @@ static void sh7372_set_reset_vector(unsigned long address)
__raw_writel(0, APARMBAREA);
}
static void sh7372_enter_core_standby(void)
{
sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
/* enter sleep mode with SYSTBCR to 0x10 */
__raw_writel(0x10, SYSTBCR);
cpu_suspend(0, sh7372_do_idle_core_standby);
__raw_writel(0, SYSTBCR);
/* disable reset vector translation */
__raw_writel(0, SBAR);
}
#endif
#ifdef CONFIG_SUSPEND
static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode)
{
if (pllc0_on)
@ -465,22 +298,42 @@ static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2)
static void sh7372_enter_a3sm_common(int pllc0_on)
{
/* use INTCA together with SYSC for wakeup */
sh7372_setup_sysc(1 << 0, 0);
sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
sh7372_enter_sysc(pllc0_on, 1 << 12);
}
static void sh7372_enter_a4s_common(int pllc0_on)
{
sh7372_intca_suspend();
memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
sh7372_set_reset_vector(SMFRAM);
sh7372_enter_sysc(pllc0_on, 1 << 10);
sh7372_intca_resume();
}
#endif
#endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
#ifdef CONFIG_CPU_IDLE
static int sh7372_do_idle_core_standby(unsigned long unused)
{
cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
return 0;
}
static void sh7372_enter_core_standby(void)
{
sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
/* enter sleep mode with SYSTBCR to 0x10 */
__raw_writel(0x10, SYSTBCR);
cpu_suspend(0, sh7372_do_idle_core_standby);
__raw_writel(0, SYSTBCR);
/* disable reset vector translation */
__raw_writel(0, SBAR);
}
static void sh7372_enter_a3sm_pll_on(void)
{
sh7372_enter_a3sm_common(1);
}
static void sh7372_enter_a3sm_pll_off(void)
{
sh7372_enter_a3sm_common(0);
}
static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
{
@ -492,7 +345,24 @@ static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
state->target_residency = 20 + 10;
state->flags = CPUIDLE_FLAG_TIME_VALID;
shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
drv->state_count++;
state = &drv->states[drv->state_count];
snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
strncpy(state->desc, "A3SM PLL ON", CPUIDLE_DESC_LEN);
state->exit_latency = 20;
state->target_residency = 30 + 20;
state->flags = CPUIDLE_FLAG_TIME_VALID;
shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_on;
drv->state_count++;
state = &drv->states[drv->state_count];
snprintf(state->name, CPUIDLE_NAME_LEN, "C4");
strncpy(state->desc, "A3SM PLL OFF", CPUIDLE_DESC_LEN);
state->exit_latency = 120;
state->target_residency = 30 + 120;
state->flags = CPUIDLE_FLAG_TIME_VALID;
shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_off;
drv->state_count++;
}
@ -505,6 +375,14 @@ static void sh7372_cpuidle_init(void) {}
#endif
#ifdef CONFIG_SUSPEND
static void sh7372_enter_a4s_common(int pllc0_on)
{
sh7372_intca_suspend();
memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
sh7372_set_reset_vector(SMFRAM);
sh7372_enter_sysc(pllc0_on, 1 << 10);
sh7372_intca_resume();
}
static int sh7372_enter_suspend(suspend_state_t suspend_state)
{
@ -512,24 +390,21 @@ static int sh7372_enter_suspend(suspend_state_t suspend_state)
/* check active clocks to determine potential wakeup sources */
if (sh7372_sysc_valid(&msk, &msk2)) {
/* convert INTC mask and sense to SYSC mask and sense */
sh7372_setup_sysc(msk, msk2);
if (!console_suspend_enabled &&
sh7372_a4s.genpd.status == GPD_STATE_POWER_OFF) {
sh7372_pd_a4s.genpd.status == GPD_STATE_POWER_OFF) {
/* convert INTC mask/sense to SYSC mask/sense */
sh7372_setup_sysc(msk, msk2);
/* enter A4S sleep with PLLC0 off */
pr_debug("entering A4S\n");
sh7372_enter_a4s_common(0);
} else {
/* enter A3SM sleep with PLLC0 off */
pr_debug("entering A3SM\n");
sh7372_enter_a3sm_common(0);
return 0;
}
} else {
/* default to Core Standby that supports all wakeup sources */
pr_debug("entering Core Standby\n");
sh7372_enter_core_standby();
}
/* default to enter A3SM sleep with PLLC0 off */
pr_debug("entering A3SM\n");
sh7372_enter_a3sm_common(0);
return 0;
}
@ -550,7 +425,7 @@ static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
* executed during system suspend and resume, respectively, so
* that those functions don't crash while accessing the INTCS.
*/
pm_genpd_poweron(&sh7372_a4r.genpd);
pm_genpd_poweron(&sh7372_pd_a4r.genpd);
break;
case PM_POST_SUSPEND:
pm_genpd_poweroff_unused();

360
arch/arm/mach-shmobile/setup-r8a7740.c
View File

@ -23,9 +23,14 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/serial_sci.h>
#include <linux/sh_dma.h>
#include <linux/sh_timer.h>
#include <linux/dma-mapping.h>
#include <mach/dma-register.h>
#include <mach/r8a7740.h>
#include <mach/pm-rmobile.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <asm/mach-types.h>
@ -276,6 +281,272 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
&cmt10_device,
};
/* DMA */
static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
{
.slave_id = SHDMA_SLAVE_SDHI0_TX,
.addr = 0xe6850030,
.chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xc1,
}, {
.slave_id = SHDMA_SLAVE_SDHI0_RX,
.addr = 0xe6850030,
.chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xc2,
}, {
.slave_id = SHDMA_SLAVE_SDHI1_TX,
.addr = 0xe6860030,
.chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xc9,
}, {
.slave_id = SHDMA_SLAVE_SDHI1_RX,
.addr = 0xe6860030,
.chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xca,
}, {
.slave_id = SHDMA_SLAVE_SDHI2_TX,
.addr = 0xe6870030,
.chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xcd,
}, {
.slave_id = SHDMA_SLAVE_SDHI2_RX,
.addr = 0xe6870030,
.chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xce,
}, {
.slave_id = SHDMA_SLAVE_FSIA_TX,
.addr = 0xfe1f0024,
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xb1,
}, {
.slave_id = SHDMA_SLAVE_FSIA_RX,
.addr = 0xfe1f0020,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0xb2,
}, {
.slave_id = SHDMA_SLAVE_FSIB_TX,
.addr = 0xfe1f0064,
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xb5,
},
};
#define DMA_CHANNEL(a, b, c) \
{ \
.offset = a, \
.dmars = b, \
.dmars_bit = c, \
.chclr_offset = (0x220 - 0x20) + a \
}
static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
DMA_CHANNEL(0x00, 0, 0),
DMA_CHANNEL(0x10, 0, 8),
DMA_CHANNEL(0x20, 4, 0),
DMA_CHANNEL(0x30, 4, 8),
DMA_CHANNEL(0x50, 8, 0),
DMA_CHANNEL(0x60, 8, 8),
};
static struct sh_dmae_pdata dma_platform_data = {
.slave = r8a7740_dmae_slaves,
.slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
.channel = r8a7740_dmae_channels,
.channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
.ts_low_shift = TS_LOW_SHIFT,
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
.ts_high_shift = TS_HI_SHIFT,
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
.ts_shift = dma_ts_shift,
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
.dmaor_init = DMAOR_DME,
.chclr_present = 1,
};
/* Resource order important! */
static struct resource r8a7740_dmae0_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xfe008020,
.end = 0xfe00828f,
.flags = IORESOURCE_MEM,
},
{
/* DMARSx */
.start = 0xfe009000,
.end = 0xfe00900b,
.flags = IORESOURCE_MEM,
},
{
.name = "error_irq",
.start = evt2irq(0x20c0),
.end = evt2irq(0x20c0),
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
.start = evt2irq(0x2000),
.end = evt2irq(0x20a0),
.flags = IORESOURCE_IRQ,
},
};
/* Resource order important! */
static struct resource r8a7740_dmae1_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xfe018020,
.end = 0xfe01828f,
.flags = IORESOURCE_MEM,
},
{
/* DMARSx */
.start = 0xfe019000,
.end = 0xfe01900b,
.flags = IORESOURCE_MEM,
},
{
.name = "error_irq",
.start = evt2irq(0x21c0),
.end = evt2irq(0x21c0),
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
.start = evt2irq(0x2100),
.end = evt2irq(0x21a0),
.flags = IORESOURCE_IRQ,
},
};
/* Resource order important! */
static struct resource r8a7740_dmae2_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xfe028020,
.end = 0xfe02828f,
.flags = IORESOURCE_MEM,
},
{
/* DMARSx */
.start = 0xfe029000,
.end = 0xfe02900b,
.flags = IORESOURCE_MEM,
},
{
.name = "error_irq",
.start = evt2irq(0x22c0),
.end = evt2irq(0x22c0),
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
.start = evt2irq(0x2200),
.end = evt2irq(0x22a0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dma0_device = {
.name = "sh-dma-engine",
.id = 0,
.resource = r8a7740_dmae0_resources,
.num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
.dev = {
.platform_data = &dma_platform_data,
},
};
static struct platform_device dma1_device = {
.name = "sh-dma-engine",
.id = 1,
.resource = r8a7740_dmae1_resources,
.num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
.dev = {
.platform_data = &dma_platform_data,
},
};
static struct platform_device dma2_device = {
.name = "sh-dma-engine",
.id = 2,
.resource = r8a7740_dmae2_resources,
.num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
.dev = {
.platform_data = &dma_platform_data,
},
};
/* USB-DMAC */
static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
{
.offset = 0,
}, {
.offset = 0x20,
},
};
static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
{
.slave_id = SHDMA_SLAVE_USBHS_TX,
.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
}, {
.slave_id = SHDMA_SLAVE_USBHS_RX,
.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
},
};
static struct sh_dmae_pdata usb_dma_platform_data = {
.slave = r8a7740_usb_dma_slaves,
.slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
.channel = r8a7740_usb_dma_channels,
.channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
.ts_low_shift = USBTS_LOW_SHIFT,
.ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
.ts_high_shift = USBTS_HI_SHIFT,
.ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
.ts_shift = dma_usbts_shift,
.ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
.dmaor_init = DMAOR_DME,
.chcr_offset = 0x14,
.chcr_ie_bit = 1 << 5,
.dmaor_is_32bit = 1,
.needs_tend_set = 1,
.no_dmars = 1,
.slave_only = 1,
};
static struct resource r8a7740_usb_dma_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xe68a0020,
.end = 0xe68a0064 - 1,
.flags = IORESOURCE_MEM,
},
{
/* VCR/SWR/DMICR */
.start = 0xe68a0000,
.end = 0xe68a0014 - 1,
.flags = IORESOURCE_MEM,
},
{
/* IRQ for channels */
.start = evt2irq(0x0a00),
.end = evt2irq(0x0a00),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device usb_dma_device = {
.name = "sh-dma-engine",
.id = 3,
.resource = r8a7740_usb_dma_resources,
.num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
.dev = {
.platform_data = &usb_dma_platform_data,
},
};
/* I2C */
static struct resource i2c0_resources[] = {
[0] = {
@ -322,8 +593,30 @@ static struct platform_device i2c1_device = {
static struct platform_device *r8a7740_late_devices[] __initdata = {
&i2c0_device,
&i2c1_device,
&dma0_device,
&dma1_device,
&dma2_device,
&usb_dma_device,
};
/*
* r8a7740 chip has lasting errata on MERAM buffer.
* this is work-around for it.
* see
* "Media RAM (MERAM)" on r8a7740 documentation
*/
#define MEBUFCNTR 0xFE950098
void r8a7740_meram_workaround(void)
{
void __iomem *reg;
reg = ioremap_nocache(MEBUFCNTR, 4);
if (reg) {
iowrite32(0x01600164, reg);
iounmap(reg);
}
}
#define ICCR 0x0004
#define ICSTART 0x0070
@ -380,10 +673,31 @@ void __init r8a7740_add_standard_devices(void)
r8a7740_i2c_workaround(&i2c0_device);
r8a7740_i2c_workaround(&i2c1_device);
/* PM domain */
rmobile_init_pm_domain(&r8a7740_pd_a4s);
rmobile_init_pm_domain(&r8a7740_pd_a3sp);
rmobile_init_pm_domain(&r8a7740_pd_a4lc);
rmobile_pm_add_subdomain(&r8a7740_pd_a4s, &r8a7740_pd_a3sp);
/* add devices */
platform_add_devices(r8a7740_early_devices,
ARRAY_SIZE(r8a7740_early_devices));
platform_add_devices(r8a7740_late_devices,
ARRAY_SIZE(r8a7740_late_devices));
/* add devices to PM domain */
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif0_device);
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif1_device);
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif2_device);
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif3_device);
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif4_device);
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif5_device);
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif6_device);
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif7_device);
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scifb_device);
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &i2c1_device);
}
static void __init r8a7740_earlytimer_init(void)
@ -403,3 +717,49 @@ void __init r8a7740_add_early_devices(void)
/* override timer setup with soc-specific code */
shmobile_timer.init = r8a7740_earlytimer_init;
}
#ifdef CONFIG_USE_OF
void __init r8a7740_add_early_devices_dt(void)
{
shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
early_platform_add_devices(r8a7740_early_devices,
ARRAY_SIZE(r8a7740_early_devices));
/* setup early console here as well */
shmobile_setup_console();
}
static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
{ }
};
void __init r8a7740_add_standard_devices_dt(void)
{
/* clocks are setup late during boot in the case of DT */
r8a7740_clock_init(0);
platform_add_devices(r8a7740_early_devices,
ARRAY_SIZE(r8a7740_early_devices));
of_platform_populate(NULL, of_default_bus_match_table,
r8a7740_auxdata_lookup, NULL);
}
static const char *r8a7740_boards_compat_dt[] __initdata = {
"renesas,r8a7740",
NULL,
};
DT_MACHINE_START(SH7372_DT, "Generic R8A7740 (Flattened Device Tree)")
.map_io = r8a7740_map_io,
.init_early = r8a7740_add_early_devices_dt,
.init_irq = r8a7740_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = r8a7740_add_standard_devices_dt,
.timer = &shmobile_timer,
.dt_compat = r8a7740_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */

205
arch/arm/mach-shmobile/setup-sh7372.c
View File

@ -33,6 +33,7 @@
#include <linux/sh_timer.h>
#include <linux/pm_domain.h>
#include <linux/dma-mapping.h>
#include <mach/dma-register.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/sh7372.h>
@ -335,151 +336,126 @@ static struct platform_device iic1_device = {
};
/* DMA */
/* Transmit sizes and respective CHCR register values */
enum {
XMIT_SZ_8BIT = 0,
XMIT_SZ_16BIT = 1,
XMIT_SZ_32BIT = 2,
XMIT_SZ_64BIT = 7,
XMIT_SZ_128BIT = 3,
XMIT_SZ_256BIT = 4,
XMIT_SZ_512BIT = 5,
};
/* log2(size / 8) - used to calculate number of transfers */
#define TS_SHIFT { \
[XMIT_SZ_8BIT] = 0, \
[XMIT_SZ_16BIT] = 1, \
[XMIT_SZ_32BIT] = 2, \
[XMIT_SZ_64BIT] = 3, \
[XMIT_SZ_128BIT] = 4, \
[XMIT_SZ_256BIT] = 5, \
[XMIT_SZ_512BIT] = 6, \
}
#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
(((i) & 0xc) << (20 - 2)))
static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
{
.slave_id = SHDMA_SLAVE_SCIF0_TX,
.addr = 0xe6c40020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x21,
}, {
.slave_id = SHDMA_SLAVE_SCIF0_RX,
.addr = 0xe6c40024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x22,
}, {
.slave_id = SHDMA_SLAVE_SCIF1_TX,
.addr = 0xe6c50020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x25,
}, {
.slave_id = SHDMA_SLAVE_SCIF1_RX,
.addr = 0xe6c50024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x26,
}, {
.slave_id = SHDMA_SLAVE_SCIF2_TX,
.addr = 0xe6c60020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x29,
}, {
.slave_id = SHDMA_SLAVE_SCIF2_RX,
.addr = 0xe6c60024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x2a,
}, {
.slave_id = SHDMA_SLAVE_SCIF3_TX,
.addr = 0xe6c70020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x2d,
}, {
.slave_id = SHDMA_SLAVE_SCIF3_RX,
.addr = 0xe6c70024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x2e,
}, {
.slave_id = SHDMA_SLAVE_SCIF4_TX,
.addr = 0xe6c80020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x39,
}, {
.slave_id = SHDMA_SLAVE_SCIF4_RX,
.addr = 0xe6c80024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x3a,
}, {
.slave_id = SHDMA_SLAVE_SCIF5_TX,
.addr = 0xe6cb0020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x35,
}, {
.slave_id = SHDMA_SLAVE_SCIF5_RX,
.addr = 0xe6cb0024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x36,
}, {
.slave_id = SHDMA_SLAVE_SCIF6_TX,
.addr = 0xe6c30040,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x3d,
}, {
.slave_id = SHDMA_SLAVE_SCIF6_RX,
.addr = 0xe6c30060,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x3e,
}, {
.slave_id = SHDMA_SLAVE_SDHI0_TX,
.addr = 0xe6850030,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
.chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xc1,
}, {
.slave_id = SHDMA_SLAVE_SDHI0_RX,
.addr = 0xe6850030,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
.chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xc2,
}, {
.slave_id = SHDMA_SLAVE_SDHI1_TX,
.addr = 0xe6860030,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
.chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xc9,
}, {
.slave_id = SHDMA_SLAVE_SDHI1_RX,
.addr = 0xe6860030,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
.chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xca,
}, {
.slave_id = SHDMA_SLAVE_SDHI2_TX,
.addr = 0xe6870030,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
.chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xcd,
}, {
.slave_id = SHDMA_SLAVE_SDHI2_RX,
.addr = 0xe6870030,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
.chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xce,
}, {
.slave_id = SHDMA_SLAVE_FSIA_TX,
.addr = 0xfe1f0024,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xb1,
}, {
.slave_id = SHDMA_SLAVE_FSIA_RX,
.addr = 0xfe1f0020,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0xb2,
}, {
.slave_id = SHDMA_SLAVE_MMCIF_TX,
.addr = 0xe6bd0034,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xd1,
}, {
.slave_id = SHDMA_SLAVE_MMCIF_RX,
.addr = 0xe6bd0034,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0xd2,
},
};
@ -520,19 +496,17 @@ static const struct sh_dmae_channel sh7372_dmae_channels[] = {
}
};
static const unsigned int ts_shift[] = TS_SHIFT;
static struct sh_dmae_pdata dma_platform_data = {
.slave = sh7372_dmae_slaves,
.slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
.channel = sh7372_dmae_channels,
.channel_num = ARRAY_SIZE(sh7372_dmae_channels),
.ts_low_shift = 3,
.ts_low_mask = 0x18,
.ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
.ts_high_mask = 0x00300000,
.ts_shift = ts_shift,
.ts_shift_num = ARRAY_SIZE(ts_shift),
.ts_low_shift = TS_LOW_SHIFT,
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
.ts_high_shift = TS_HI_SHIFT,
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
.ts_shift = dma_ts_shift,
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
.dmaor_init = DMAOR_DME,
.chclr_present = 1,
};
@ -654,17 +628,6 @@ static struct platform_device dma2_device = {
/*
* USB-DMAC
*/
unsigned int usbts_shift[] = {3, 4, 5};
enum {
XMIT_SZ_8BYTE = 0,
XMIT_SZ_16BYTE = 1,
XMIT_SZ_32BYTE = 2,
};
#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
{
.offset = 0,
@ -677,10 +640,10 @@ static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
{
.slave_id = SHDMA_SLAVE_USB0_TX,
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
}, {
.slave_id = SHDMA_SLAVE_USB0_RX,
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
},
};
@ -689,12 +652,12 @@ static struct sh_dmae_pdata usb_dma0_platform_data = {
.slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
.channel = sh7372_usb_dmae_channels,
.channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
.ts_low_shift = 6,
.ts_low_mask = 0xc0,
.ts_high_shift = 0,
.ts_high_mask = 0,
.ts_shift = usbts_shift,
.ts_shift_num = ARRAY_SIZE(usbts_shift),
.ts_low_shift = USBTS_LOW_SHIFT,
.ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
.ts_high_shift = USBTS_HI_SHIFT,
.ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
.ts_shift = dma_usbts_shift,
.ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
.dmaor_init = DMAOR_DME,
.chcr_offset = 0x14,
.chcr_ie_bit = 1 << 5,
@ -739,10 +702,10 @@ static struct platform_device usb_dma0_device = {
static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
{
.slave_id = SHDMA_SLAVE_USB1_TX,
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
}, {
.slave_id = SHDMA_SLAVE_USB1_RX,
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
},
};
@ -751,12 +714,12 @@ static struct sh_dmae_pdata usb_dma1_platform_data = {
.slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
.channel = sh7372_usb_dmae_channels,
.channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
.ts_low_shift = 6,
.ts_low_mask = 0xc0,
.ts_high_shift = 0,
.ts_high_mask = 0,
.ts_shift = usbts_shift,
.ts_shift_num = ARRAY_SIZE(usbts_shift),
.ts_low_shift = USBTS_LOW_SHIFT,
.ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
.ts_high_shift = USBTS_HI_SHIFT,
.ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
.ts_shift = dma_usbts_shift,
.ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
.dmaor_init = DMAOR_DME,
.chcr_offset = 0x14,
.chcr_ie_bit = 1 << 5,
@ -1038,21 +1001,21 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
void __init sh7372_add_standard_devices(void)
{
sh7372_init_pm_domain(&sh7372_a4lc);
sh7372_init_pm_domain(&sh7372_a4mp);
sh7372_init_pm_domain(&sh7372_d4);
sh7372_init_pm_domain(&sh7372_a4r);
sh7372_init_pm_domain(&sh7372_a3rv);
sh7372_init_pm_domain(&sh7372_a3ri);
sh7372_init_pm_domain(&sh7372_a4s);
sh7372_init_pm_domain(&sh7372_a3sp);
sh7372_init_pm_domain(&sh7372_a3sg);
rmobile_init_pm_domain(&sh7372_pd_a4lc);
rmobile_init_pm_domain(&sh7372_pd_a4mp);
rmobile_init_pm_domain(&sh7372_pd_d4);
rmobile_init_pm_domain(&sh7372_pd_a4r);
rmobile_init_pm_domain(&sh7372_pd_a3rv);
rmobile_init_pm_domain(&sh7372_pd_a3ri);
rmobile_init_pm_domain(&sh7372_pd_a4s);
rmobile_init_pm_domain(&sh7372_pd_a3sp);
rmobile_init_pm_domain(&sh7372_pd_a3sg);
sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
rmobile_pm_add_subdomain(&sh7372_pd_a4lc, &sh7372_pd_a3rv);
rmobile_pm_add_subdomain(&sh7372_pd_a4r, &sh7372_pd_a4lc);
sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sg);
rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sp);
platform_add_devices(sh7372_early_devices,
ARRAY_SIZE(sh7372_early_devices));
@ -1060,30 +1023,30 @@ void __init sh7372_add_standard_devices(void)
platform_add_devices(sh7372_late_devices,
ARRAY_SIZE(sh7372_late_devices));
sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device);
sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device);
rmobile_add_device_to_domain(&sh7372_pd_a3rv, &vpu_device);
rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu0_device);
rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu1_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif0_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif1_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif2_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif3_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif4_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif5_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif6_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &iic1_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma0_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma1_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma2_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma0_device);
rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma1_device);
rmobile_add_device_to_domain(&sh7372_pd_a4r, &iic0_device);
rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu0_device);
rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu1_device);
rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu2_device);
rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu3_device);
rmobile_add_device_to_domain(&sh7372_pd_a4r, &jpu_device);
rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu00_device);
rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu01_device);
}
static void __init sh7372_earlytimer_init(void)

47
arch/arm/mach-shmobile/setup-sh7377.c
View File

@ -22,6 +22,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/uio_driver.h>
#include <linux/delay.h>
#include <linux/input.h>
@ -500,3 +501,49 @@ void __init sh7377_add_early_devices(void)
/* override timer setup with soc-specific code */
shmobile_timer.init = sh7377_earlytimer_init;
}
#ifdef CONFIG_USE_OF
void __init sh7377_add_early_devices_dt(void)
{
shmobile_setup_delay(600, 1, 3); /* Cortex-A8 @ 600MHz */
early_platform_add_devices(sh7377_early_devices,
ARRAY_SIZE(sh7377_early_devices));
/* setup early console here as well */
shmobile_setup_console();
}
static const struct of_dev_auxdata sh7377_auxdata_lookup[] __initconst = {
{ }
};
void __init sh7377_add_standard_devices_dt(void)
{
/* clocks are setup late during boot in the case of DT */
sh7377_clock_init();
platform_add_devices(sh7377_early_devices,
ARRAY_SIZE(sh7377_early_devices));
of_platform_populate(NULL, of_default_bus_match_table,
sh7377_auxdata_lookup, NULL);
}
static const char *sh7377_boards_compat_dt[] __initdata = {
"renesas,sh7377",
NULL,
};
DT_MACHINE_START(SH7377_DT, "Generic SH7377 (Flattened Device Tree)")
.map_io = sh7377_map_io,
.init_early = sh7377_add_early_devices_dt,
.init_irq = sh7377_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = sh7377_add_standard_devices_dt,
.timer = &shmobile_timer,
.dt_compat = sh7377_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */

152
arch/arm/mach-shmobile/setup-sh73a0.c
View File

@ -30,6 +30,7 @@
#include <linux/sh_dma.h>
#include <linux/sh_intc.h>
#include <linux/sh_timer.h>
#include <mach/dma-register.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/sh73a0.h>
@ -415,32 +416,6 @@ static struct platform_device i2c4_device = {
.num_resources = ARRAY_SIZE(i2c4_resources),
};
/* Transmit sizes and respective CHCR register values */
enum {
XMIT_SZ_8BIT = 0,
XMIT_SZ_16BIT = 1,
XMIT_SZ_32BIT = 2,
XMIT_SZ_64BIT = 7,
XMIT_SZ_128BIT = 3,
XMIT_SZ_256BIT = 4,
XMIT_SZ_512BIT = 5,
};
/* log2(size / 8) - used to calculate number of transfers */
#define TS_SHIFT { \
[XMIT_SZ_8BIT] = 0, \
[XMIT_SZ_16BIT] = 1, \
[XMIT_SZ_32BIT] = 2, \
[XMIT_SZ_64BIT] = 3, \
[XMIT_SZ_128BIT] = 4, \
[XMIT_SZ_256BIT] = 5, \
[XMIT_SZ_512BIT] = 6, \
}
#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
{
.slave_id = SHDMA_SLAVE_SCIF0_TX,
@ -604,19 +579,17 @@ static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
DMAE_CHANNEL(0x8980),
};
static const unsigned int ts_shift[] = TS_SHIFT;
static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
.slave = sh73a0_dmae_slaves,
.slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
.channel = sh73a0_dmae_channels,
.channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
.ts_low_shift = 3,
.ts_low_mask = 0x18,
.ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
.ts_high_mask = 0x00300000,
.ts_shift = ts_shift,
.ts_shift_num = ARRAY_SIZE(ts_shift),
.ts_low_shift = TS_LOW_SHIFT,
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
.ts_high_shift = TS_HI_SHIFT,
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
.ts_shift = dma_ts_shift,
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
.dmaor_init = DMAOR_DME,
};
@ -651,6 +624,116 @@ static struct platform_device dma0_device = {
},
};
/* MPDMAC */
static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
{
.slave_id = SHDMA_SLAVE_FSI2A_RX,
.addr = 0xec230020,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0xd6, /* CHECK ME */
}, {
.slave_id = SHDMA_SLAVE_FSI2A_TX,
.addr = 0xec230024,
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xd5, /* CHECK ME */
}, {
.slave_id = SHDMA_SLAVE_FSI2C_RX,
.addr = 0xec230060,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0xda, /* CHECK ME */
}, {
.slave_id = SHDMA_SLAVE_FSI2C_TX,
.addr = 0xec230064,
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xd9, /* CHECK ME */
}, {
.slave_id = SHDMA_SLAVE_FSI2B_RX,
.addr = 0xec240020,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0x8e, /* CHECK ME */
}, {
.slave_id = SHDMA_SLAVE_FSI2B_TX,
.addr = 0xec240024,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0x8d, /* CHECK ME */
}, {
.slave_id = SHDMA_SLAVE_FSI2D_RX,
.addr = 0xec240060,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0x9a, /* CHECK ME */
},
};
#define MPDMA_CHANNEL(a, b, c) \
{ \
.offset = a, \
.dmars = b, \
.dmars_bit = c, \
.chclr_offset = (0x220 - 0x20) + a \
}
static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
MPDMA_CHANNEL(0x00, 0, 0),
MPDMA_CHANNEL(0x10, 0, 8),
MPDMA_CHANNEL(0x20, 4, 0),
MPDMA_CHANNEL(0x30, 4, 8),
MPDMA_CHANNEL(0x50, 8, 0),
MPDMA_CHANNEL(0x70, 8, 8),
};
static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
.slave = sh73a0_mpdma_slaves,
.slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
.channel = sh73a0_mpdma_channels,
.channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
.ts_low_shift = TS_LOW_SHIFT,
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
.ts_high_shift = TS_HI_SHIFT,
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
.ts_shift = dma_ts_shift,
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
.dmaor_init = DMAOR_DME,
.chclr_present = 1,
};
/* Resource order important! */
static struct resource sh73a0_mpdma_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xec618020,
.end = 0xec61828f,
.flags = IORESOURCE_MEM,
},
{
/* DMARSx */
.start = 0xec619000,
.end = 0xec61900b,
.flags = IORESOURCE_MEM,
},
{
.name = "error_irq",
.start = gic_spi(181),
.end = gic_spi(181),
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
.start = gic_spi(175),
.end = gic_spi(180),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mpdma0_device = {
.name = "sh-dma-engine",
.id = 1,
.resource = sh73a0_mpdma_resources,
.num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
.dev = {
.platform_data = &sh73a0_mpdma_platform_data,
},
};
static struct platform_device *sh73a0_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
@ -673,6 +756,7 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
&i2c3_device,
&i2c4_device,
&dma0_device,
&mpdma0_device,
};
#define SRCR2 0xe61580b0

55
drivers/cpufreq/exynos5250-cpufreq.c
View File

@ -65,20 +65,20 @@ static unsigned int clkdiv_cpu0_5250[CPUFREQ_LEVEL_END][8] = {
* Clock divider value for following
* { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 }
*/
{ 0, 3, 7, 7, 6, 1, 3, 0 }, /* 1700 MHz - N/A */
{ 0, 3, 7, 7, 6, 1, 3, 0 }, /* 1600 MHz - N/A */
{ 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1500 MHz - N/A */
{ 0, 3, 7, 7, 6, 1, 3, 0 }, /* 1400 MHz */
{ 0, 3, 7, 7, 6, 1, 3, 0 }, /* 1300 MHz */
{ 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1200 MHz */
{ 0, 2, 7, 7, 5, 1, 2, 0 }, /* 1100 MHz */
{ 0, 2, 7, 7, 4, 1, 2, 0 }, /* 1000 MHz */
{ 0, 2, 7, 7, 4, 1, 2, 0 }, /* 900 MHz */
{ 0, 2, 7, 7, 3, 1, 1, 0 }, /* 800 MHz */
{ 0, 3, 7, 7, 7, 3, 5, 0 }, /* 1700 MHz */
{ 0, 3, 7, 7, 7, 1, 4, 0 }, /* 1600 MHz */
{ 0, 2, 7, 7, 7, 1, 4, 0 }, /* 1500 MHz */
{ 0, 2, 7, 7, 6, 1, 4, 0 }, /* 1400 MHz */
{ 0, 2, 7, 7, 6, 1, 3, 0 }, /* 1300 MHz */
{ 0, 2, 7, 7, 5, 1, 3, 0 }, /* 1200 MHz */
{ 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1100 MHz */
{ 0, 1, 7, 7, 4, 1, 2, 0 }, /* 1000 MHz */
{ 0, 1, 7, 7, 4, 1, 2, 0 }, /* 900 MHz */
{ 0, 1, 7, 7, 4, 1, 2, 0 }, /* 800 MHz */
{ 0, 1, 7, 7, 3, 1, 1, 0 }, /* 700 MHz */
{ 0, 1, 7, 7, 2, 1, 1, 0 }, /* 600 MHz */
{ 0, 1, 7, 7, 3, 1, 1, 0 }, /* 600 MHz */
{ 0, 1, 7, 7, 2, 1, 1, 0 }, /* 500 MHz */
{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 400 MHz */
{ 0, 1, 7, 7, 2, 1, 1, 0 }, /* 400 MHz */
{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 300 MHz */
{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 200 MHz */
};
@ -87,9 +87,9 @@ static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
/* Clock divider value for following
* { COPY, HPM }
*/
{ 0, 2 }, /* 1700 MHz - N/A */
{ 0, 2 }, /* 1600 MHz - N/A */
{ 0, 2 }, /* 1500 MHz - N/A */
{ 0, 2 }, /* 1700 MHz */
{ 0, 2 }, /* 1600 MHz */
{ 0, 2 }, /* 1500 MHz */
{ 0, 2 }, /* 1400 MHz */
{ 0, 2 }, /* 1300 MHz */
{ 0, 2 }, /* 1200 MHz */
@ -106,10 +106,10 @@ static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
};
static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
(0), /* 1700 MHz - N/A */
(0), /* 1600 MHz - N/A */
(0), /* 1500 MHz - N/A */
(0), /* 1400 MHz */
((425 << 16) | (6 << 8) | 0), /* 1700 MHz */
((200 << 16) | (3 << 8) | 0), /* 1600 MHz */
((250 << 16) | (4 << 8) | 0), /* 1500 MHz */
((175 << 16) | (3 << 8) | 0), /* 1400 MHz */
((325 << 16) | (6 << 8) | 0), /* 1300 MHz */
((200 << 16) | (4 << 8) | 0), /* 1200 MHz */
((275 << 16) | (6 << 8) | 0), /* 1100 MHz */
@ -126,9 +126,10 @@ static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
/* ASV group voltage table */
static const unsigned int asv_voltage_5250[CPUFREQ_LEVEL_END] = {
0, 0, 0, 0, 0, 0, 0, /* 1700 MHz ~ 1100 MHz Not supported */
1175000, 1125000, 1075000, 1050000, 1000000,
950000, 925000, 925000, 900000
1300000, 1250000, 1225000, 1200000, 1150000,
1125000, 1100000, 1075000, 1050000, 1025000,
1012500, 1000000, 975000, 950000, 937500,
925000
};
static void set_clkdiv(unsigned int div_index)
@ -248,15 +249,7 @@ static void __init set_volt_table(void)
{
unsigned int i;
exynos5250_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
exynos5250_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID;
exynos5250_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID;
exynos5250_freq_table[L3].frequency = CPUFREQ_ENTRY_INVALID;
exynos5250_freq_table[L4].frequency = CPUFREQ_ENTRY_INVALID;
exynos5250_freq_table[L5].frequency = CPUFREQ_ENTRY_INVALID;
exynos5250_freq_table[L6].frequency = CPUFREQ_ENTRY_INVALID;
max_support_idx = L7;
max_support_idx = L0;
for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
exynos5250_volt_table[i] = asv_voltage_5250[i];