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ARM: S3C24XX: add get_rate for clk_h on S3C2416/2443
Currently the rate of clk_h is calculated once and set through the s3c24xx_setup_clocks call. As the clk_h is a child of the prediv we can evaluate its divider and calculate the rate in get_rate. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -168,6 +168,25 @@ static struct clk clk_prediv = {
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},
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};
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/* hclk divider
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*
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* divides the prediv and provides the hclk.
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*/
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static unsigned long s3c2443_hclkdiv_getrate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
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clkdiv0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
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return rate / (clkdiv0 + 1);
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}
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static struct clk_ops clk_h_ops = {
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.get_rate = s3c2443_hclkdiv_getrate,
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};
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/* armdiv
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*
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* this clock is sourced from msysclk and can have a number of
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@ -524,13 +543,6 @@ static struct clk hsmmc1_clk = {
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.ctrlbit = S3C2443_HCLKCON_HSMMC,
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};
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static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
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{
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clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
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return clkcon0 + 1;
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}
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/* EPLLCON compatible enough to get on/off information */
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void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
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@ -554,8 +566,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
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clk_msysclk.clk.rate = pll;
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fclk = clk_get_rate(&clk_armdiv);
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hclk = s3c2443_prediv_getrate(&clk_prediv);
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hclk /= s3c2443_get_hdiv(clkdiv0);
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hclk = clk_get_rate(&clk_h);
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pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
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s3c24xx_setup_clocks(fclk, hclk, pclk);
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@ -621,6 +632,8 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
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/* s3c2443 parents h and p clocks from prediv */
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clk_h.parent = &clk_prediv;
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clk_h.ops = &clk_h_ops;
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clk_p.parent = &clk_prediv;
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clk_usb_bus.parent = &clk_usb_bus_host.clk;
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