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ACPI / PMIC: CrystalCove: Extend PMOP support to support all possible fields

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Prior to this commit the CRC PMOP handler only supported the X285 and V18X
PMOP fields. Leading to errors like these on device using the VBUS field:

[  765.766489] ACPI Error: AE_BAD_PARAMETER, Returned by Handler for [UserDefinedRegion] (20180531/evregion-266)
[  765.766526] ACPI Error: Method parse/execution failed \_SB.I2C1.BATC._BST, AE_BAD_PARAMETER (20180531/psparse-516)
[  765.766586] ACPI Error: AE_BAD_PARAMETER, Evaluating _BST (20180531/battery-577)

This commit adds support for all known fields to the CRC PMOP OpRegion
handler, the name and register info in this commit comes from:

https://github.com/01org/ProductionKernelQuilts/blob/master/uefi/cht-m1stable/patches/0002-ACPI-Adding-support-for-WC-and-CRC-opregion.patch

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Hans de Goede 2018-08-12 18:33:44 +02:00 committed by Rafael J. Wysocki
parent 2c20443ec2
commit b5c16c7925
1 changed files with 107 additions and 2 deletions
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109
drivers/acpi/pmic/intel_pmic_crc.c
View File

@ -25,16 +25,121 @@
#define PMIC_A0LOCK_REG 0xc5
static struct pmic_table power_table[] = {
/* {
.address = 0x00,
.reg = ??,
.bit = ??,
}, ** VSYS */
{
.address = 0x04,
.reg = 0x63,
.bit = 0x00,
}, /* SYSX -> VSYS_SX */
{
.address = 0x08,
.reg = 0x62,
.bit = 0x00,
}, /* SYSU -> VSYS_U */
{
.address = 0x0c,
.reg = 0x64,
.bit = 0x00,
}, /* SYSS -> VSYS_S */
{
.address = 0x10,
.reg = 0x6a,
.bit = 0x00,
}, /* V50S -> V5P0S */
{
.address = 0x14,
.reg = 0x6b,
.bit = 0x00,
}, /* HOST -> VHOST, USB2/3 host */
{
.address = 0x18,
.reg = 0x6c,
.bit = 0x00,
}, /* VBUS -> VBUS, USB2/3 OTG */
{
.address = 0x1c,
.reg = 0x6d,
.bit = 0x00,
}, /* HDMI -> VHDMI */
/* {
.address = 0x20,
.reg = ??,
.bit = ??,
}, ** S285 */
{
.address = 0x24,
.reg = 0x66,
.bit = 0x00,
},
}, /* X285 -> V2P85SX, camera */
/* {
.address = 0x28,
.reg = ??,
.bit = ??,
}, ** V33A */
{
.address = 0x2c,
.reg = 0x69,
.bit = 0x00,
}, /* V33S -> V3P3S, display/ssd/audio */
{
.address = 0x30,
.reg = 0x68,
.bit = 0x00,
}, /* V33U -> V3P3U, SDIO wifi&bt */
/* {
.address = 0x34 .. 0x40,
.reg = ??,
.bit = ??,
}, ** V33I, V18A, REFQ, V12A */
{
.address = 0x44,
.reg = 0x5c,
.bit = 0x00,
}, /* V18S -> V1P8S, SOC/USB PHY/SIM */
{
.address = 0x48,
.reg = 0x5d,
.bit = 0x00,
},
}, /* V18X -> V1P8SX, eMMC/camara/audio */
{
.address = 0x4c,
.reg = 0x5b,
.bit = 0x00,
}, /* V18U -> V1P8U, LPDDR */
{
.address = 0x50,
.reg = 0x61,
.bit = 0x00,
}, /* V12X -> V1P2SX, SOC SFR */
{
.address = 0x54,
.reg = 0x60,
.bit = 0x00,
}, /* V12S -> V1P2S, MIPI */
/* {
.address = 0x58,
.reg = ??,
.bit = ??,
}, ** V10A */
{
.address = 0x5c,
.reg = 0x56,
.bit = 0x00,
}, /* V10S -> V1P0S, SOC GFX */
{
.address = 0x60,
.reg = 0x57,
.bit = 0x00,
}, /* V10X -> V1P0SX, SOC display/DDR IO/PCIe */
{
.address = 0x64,
.reg = 0x59,
.bit = 0x00,
}, /* V105 -> V1P05S, L2 SRAM */
};
static struct pmic_table thermal_table[] = {