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powerpc: Use SPRN_xxx rather than xxx for SPR numbers
This changes symbols like HID0, SPRG3, SRR0, SRR1 etc. that refer to special purpose registers to SPRN_HID0, SPRN_SPRG3, etc. Using the SPRN_ symbols clutters the namespace less, and the forthcoming merge of asm/processor.h and asm/reg.h is going to remove the non-SPRN_ versions. Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
parent
05f62a5c04
commit
b5bbeb2373
@ -25,7 +25,7 @@
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#include <linux/config.h>
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#include <linux/threads.h>
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#include <asm/processor.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/systemcfg.h>
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@ -201,22 +201,22 @@ exception_marker:
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#define EX_CCR 60
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#define EXCEPTION_PROLOG_PSERIES(area, label) \
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mfspr r13,SPRG3; /* get paca address into r13 */ \
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mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
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std r9,area+EX_R9(r13); /* save r9 - r12 */ \
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std r10,area+EX_R10(r13); \
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std r11,area+EX_R11(r13); \
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std r12,area+EX_R12(r13); \
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mfspr r9,SPRG1; \
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mfspr r9,SPRN_SPRG1; \
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std r9,area+EX_R13(r13); \
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mfcr r9; \
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clrrdi r12,r13,32; /* get high part of &label */ \
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mfmsr r10; \
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mfspr r11,SRR0; /* save SRR0 */ \
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mfspr r11,SPRN_SRR0; /* save SRR0 */ \
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ori r12,r12,(label)@l; /* virt addr of handler */ \
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ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
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mtspr SRR0,r12; \
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mfspr r12,SRR1; /* and SRR1 */ \
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mtspr SRR1,r10; \
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mtspr SPRN_SRR0,r12; \
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mfspr r12,SPRN_SRR1; /* and SRR1 */ \
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mtspr SPRN_SRR1,r10; \
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rfid; \
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b . /* prevent speculative execution */
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@ -225,12 +225,12 @@ exception_marker:
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* This code runs with relocation on.
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*/
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#define EXCEPTION_PROLOG_ISERIES_1(area) \
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mfspr r13,SPRG3; /* get paca address into r13 */ \
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mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
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std r9,area+EX_R9(r13); /* save r9 - r12 */ \
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std r10,area+EX_R10(r13); \
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std r11,area+EX_R11(r13); \
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std r12,area+EX_R12(r13); \
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mfspr r9,SPRG1; \
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mfspr r9,SPRN_SPRG1; \
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std r9,area+EX_R13(r13); \
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mfcr r9
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@ -283,7 +283,7 @@ exception_marker:
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std r9,_LINK(r1); \
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mfctr r10; /* save CTR in stackframe */ \
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std r10,_CTR(r1); \
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mfspr r11,XER; /* save XER in stackframe */ \
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mfspr r11,SPRN_XER; /* save XER in stackframe */ \
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std r11,_XER(r1); \
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li r9,(n)+1; \
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std r9,_TRAP(r1); /* set trap number */ \
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@ -300,7 +300,7 @@ exception_marker:
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.globl label##_pSeries; \
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label##_pSeries: \
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HMT_MEDIUM; \
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mtspr SPRG1,r13; /* save r13 */ \
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mtspr SPRN_SPRG1,r13; /* save r13 */ \
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RUNLATCH_ON(r13); \
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EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
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@ -308,7 +308,7 @@ label##_pSeries: \
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.globl label##_iSeries; \
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label##_iSeries: \
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HMT_MEDIUM; \
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mtspr SPRG1,r13; /* save r13 */ \
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mtspr SPRN_SPRG1,r13; /* save r13 */ \
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RUNLATCH_ON(r13); \
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EXCEPTION_PROLOG_ISERIES_1(area); \
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EXCEPTION_PROLOG_ISERIES_2; \
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@ -318,7 +318,7 @@ label##_iSeries: \
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.globl label##_iSeries; \
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label##_iSeries: \
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HMT_MEDIUM; \
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mtspr SPRG1,r13; /* save r13 */ \
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mtspr SPRN_SPRG1,r13; /* save r13 */ \
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RUNLATCH_ON(r13); \
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EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
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lbz r10,PACAPROCENABLED(r13); \
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@ -388,7 +388,7 @@ __start_interrupts:
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. = 0x200
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_machine_check_pSeries:
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HMT_MEDIUM
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mtspr SPRG1,r13 /* save r13 */
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mtspr SPRN_SPRG1,r13 /* save r13 */
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RUNLATCH_ON(r13)
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EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
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@ -396,18 +396,18 @@ _machine_check_pSeries:
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.globl data_access_pSeries
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data_access_pSeries:
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HMT_MEDIUM
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mtspr SPRG1,r13
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mtspr SPRN_SPRG1,r13
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BEGIN_FTR_SECTION
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mtspr SPRG2,r12
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mfspr r13,DAR
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mfspr r12,DSISR
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mtspr SPRN_SPRG2,r12
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mfspr r13,SPRN_DAR
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mfspr r12,SPRN_DSISR
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srdi r13,r13,60
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rlwimi r13,r12,16,0x20
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mfcr r12
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cmpwi r13,0x2c
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beq .do_stab_bolted_pSeries
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mtcrf 0x80,r12
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mfspr r12,SPRG2
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mfspr r12,SPRN_SPRG2
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END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
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EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
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@ -415,19 +415,19 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
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.globl data_access_slb_pSeries
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data_access_slb_pSeries:
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HMT_MEDIUM
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mtspr SPRG1,r13
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mtspr SPRN_SPRG1,r13
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RUNLATCH_ON(r13)
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mfspr r13,SPRG3 /* get paca address into r13 */
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mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
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std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
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std r10,PACA_EXSLB+EX_R10(r13)
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std r11,PACA_EXSLB+EX_R11(r13)
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std r12,PACA_EXSLB+EX_R12(r13)
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std r3,PACA_EXSLB+EX_R3(r13)
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mfspr r9,SPRG1
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mfspr r9,SPRN_SPRG1
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std r9,PACA_EXSLB+EX_R13(r13)
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mfcr r9
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mfspr r12,SRR1 /* and SRR1 */
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mfspr r3,DAR
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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mfspr r3,SPRN_DAR
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b .do_slb_miss /* Rel. branch works in real mode */
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STD_EXCEPTION_PSERIES(0x400, instruction_access)
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@ -436,19 +436,19 @@ data_access_slb_pSeries:
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.globl instruction_access_slb_pSeries
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instruction_access_slb_pSeries:
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HMT_MEDIUM
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mtspr SPRG1,r13
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mtspr SPRN_SPRG1,r13
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RUNLATCH_ON(r13)
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mfspr r13,SPRG3 /* get paca address into r13 */
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mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
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std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
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std r10,PACA_EXSLB+EX_R10(r13)
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std r11,PACA_EXSLB+EX_R11(r13)
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std r12,PACA_EXSLB+EX_R12(r13)
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std r3,PACA_EXSLB+EX_R3(r13)
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mfspr r9,SPRG1
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mfspr r9,SPRN_SPRG1
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std r9,PACA_EXSLB+EX_R13(r13)
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mfcr r9
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mfspr r12,SRR1 /* and SRR1 */
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mfspr r3,SRR0 /* SRR0 is faulting address */
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
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b .do_slb_miss /* Rel. branch works in real mode */
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STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
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@ -466,15 +466,15 @@ system_call_pSeries:
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RUNLATCH_ON(r9)
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mr r9,r13
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mfmsr r10
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mfspr r13,SPRG3
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mfspr r11,SRR0
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mfspr r13,SPRN_SPRG3
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mfspr r11,SPRN_SRR0
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clrrdi r12,r13,32
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oris r12,r12,system_call_common@h
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ori r12,r12,system_call_common@l
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mtspr SRR0,r12
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mtspr SPRN_SRR0,r12
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ori r10,r10,MSR_IR|MSR_DR|MSR_RI
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mfspr r12,SRR1
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mtspr SRR1,r10
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mfspr r12,SPRN_SRR1
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mtspr SPRN_SRR1,r10
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rfid
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b . /* prevent speculative execution */
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@ -504,7 +504,7 @@ system_call_pSeries:
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.align 7
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_GLOBAL(do_stab_bolted_pSeries)
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mtcrf 0x80,r12
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mfspr r12,SPRG2
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mfspr r12,SPRN_SPRG2
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EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
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/*
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@ -513,14 +513,14 @@ _GLOBAL(do_stab_bolted_pSeries)
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.globl system_reset_fwnmi
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system_reset_fwnmi:
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HMT_MEDIUM
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mtspr SPRG1,r13 /* save r13 */
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mtspr SPRN_SPRG1,r13 /* save r13 */
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RUNLATCH_ON(r13)
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EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
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.globl machine_check_fwnmi
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machine_check_fwnmi:
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HMT_MEDIUM
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mtspr SPRG1,r13 /* save r13 */
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mtspr SPRN_SPRG1,r13 /* save r13 */
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RUNLATCH_ON(r13)
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EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
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@ -531,18 +531,18 @@ machine_check_fwnmi:
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.globl data_access_iSeries
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data_access_iSeries:
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mtspr SPRG1,r13
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mtspr SPRN_SPRG1,r13
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BEGIN_FTR_SECTION
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mtspr SPRG2,r12
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mfspr r13,DAR
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mfspr r12,DSISR
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mtspr SPRN_SPRG2,r12
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mfspr r13,SPRN_DAR
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mfspr r12,SPRN_DSISR
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srdi r13,r13,60
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rlwimi r13,r12,16,0x20
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mfcr r12
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cmpwi r13,0x2c
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beq .do_stab_bolted_iSeries
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mtcrf 0x80,r12
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mfspr r12,SPRG2
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mfspr r12,SPRN_SPRG2
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END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
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EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
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EXCEPTION_PROLOG_ISERIES_2
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@ -550,25 +550,25 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
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.do_stab_bolted_iSeries:
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mtcrf 0x80,r12
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mfspr r12,SPRG2
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mfspr r12,SPRN_SPRG2
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EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
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EXCEPTION_PROLOG_ISERIES_2
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b .do_stab_bolted
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.globl data_access_slb_iSeries
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data_access_slb_iSeries:
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mtspr SPRG1,r13 /* save r13 */
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mtspr SPRN_SPRG1,r13 /* save r13 */
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EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
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std r3,PACA_EXSLB+EX_R3(r13)
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ld r12,PACALPPACA+LPPACASRR1(r13)
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mfspr r3,DAR
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mfspr r3,SPRN_DAR
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b .do_slb_miss
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STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
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.globl instruction_access_slb_iSeries
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instruction_access_slb_iSeries:
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mtspr SPRG1,r13 /* save r13 */
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mtspr SPRN_SPRG1,r13 /* save r13 */
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EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
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std r3,PACA_EXSLB+EX_R3(r13)
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ld r12,PACALPPACA+LPPACASRR1(r13)
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@ -586,7 +586,7 @@ instruction_access_slb_iSeries:
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.globl system_call_iSeries
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system_call_iSeries:
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mr r9,r13
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mfspr r13,SPRG3
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mfspr r13,SPRN_SPRG3
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EXCEPTION_PROLOG_ISERIES_2
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b system_call_common
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@ -596,7 +596,7 @@ system_call_iSeries:
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.globl system_reset_iSeries
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system_reset_iSeries:
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mfspr r13,SPRG3 /* Get paca address */
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mfspr r13,SPRN_SPRG3 /* Get paca address */
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mfmsr r24
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ori r24,r24,MSR_RI
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mtmsrd r24 /* RI on */
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@ -639,7 +639,7 @@ iSeries_secondary_smp_loop:
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#endif /* CONFIG_SMP */
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li r0,-1 /* r0=-1 indicates a Hypervisor call */
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sc /* Invoke the hypervisor via a system call */
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mfspr r13,SPRG3 /* Put r13 back ???? */
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mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
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b 1b /* If SMP not configured, secondaries
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* loop forever */
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@ -656,8 +656,8 @@ hardware_interrupt_iSeries_masked:
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mtcrf 0x80,r9 /* Restore regs */
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ld r11,PACALPPACA+LPPACASRR0(r13)
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ld r12,PACALPPACA+LPPACASRR1(r13)
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mtspr SRR0,r11
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mtspr SRR1,r12
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR1,r12
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ld r9,PACA_EXGEN+EX_R9(r13)
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ld r10,PACA_EXGEN+EX_R10(r13)
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ld r11,PACA_EXGEN+EX_R11(r13)
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@ -713,8 +713,8 @@ bad_stack:
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std r10,GPR1(r1)
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std r11,_NIP(r1)
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std r12,_MSR(r1)
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mfspr r11,DAR
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mfspr r12,DSISR
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mfspr r11,SPRN_DAR
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mfspr r12,SPRN_DSISR
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std r11,_DAR(r1)
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std r12,_DSISR(r1)
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mflr r10
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@ -766,8 +766,8 @@ fast_exception_return:
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clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
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mtmsrd r10,1
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mtspr SRR1,r12
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mtspr SRR0,r11
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mtspr SPRN_SRR1,r12
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mtspr SPRN_SRR0,r11
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REST_4GPRS(10, r1)
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ld r1,GPR1(r1)
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rfid
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@ -788,9 +788,9 @@ unrecov_fer:
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.globl data_access_common
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data_access_common:
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RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */
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mfspr r10,DAR
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mfspr r10,SPRN_DAR
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std r10,PACA_EXGEN+EX_DAR(r13)
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mfspr r10,DSISR
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mfspr r10,SPRN_DSISR
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stw r10,PACA_EXGEN+EX_DSISR(r13)
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EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
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ld r3,PACA_EXGEN+EX_DAR(r13)
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@ -821,9 +821,9 @@ hardware_interrupt_entry:
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.align 7
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.globl alignment_common
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alignment_common:
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mfspr r10,DAR
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mfspr r10,SPRN_DAR
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std r10,PACA_EXGEN+EX_DAR(r13)
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mfspr r10,DSISR
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mfspr r10,SPRN_DSISR
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stw r10,PACA_EXGEN+EX_DSISR(r13)
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EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
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ld r3,PACA_EXGEN+EX_DAR(r13)
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@ -1064,7 +1064,7 @@ _GLOBAL(do_stab_bolted)
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/* Hash to the primary group */
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ld r10,PACASTABVIRT(r13)
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mfspr r11,DAR
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mfspr r11,SPRN_DAR
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srdi r11,r11,28
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rldimi r10,r11,7,52 /* r10 = first ste of the group */
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@ -1106,7 +1106,7 @@ _GLOBAL(do_stab_bolted)
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2: std r9,8(r10) /* Store the vsid part of the ste */
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eieio
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mfspr r11,DAR /* Get the new esid */
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mfspr r11,SPRN_DAR /* Get the new esid */
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clrrdi r11,r11,28 /* Permits a full 32b of ESID */
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ori r11,r11,0x90 /* Turn on valid and kp */
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std r11,0(r10) /* Put new entry back into the stab */
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@ -1126,8 +1126,8 @@ _GLOBAL(do_stab_bolted)
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clrrdi r10,r10,2
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mtmsrd r10,1
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mtspr SRR0,r11
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mtspr SRR1,r12
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR1,r12
|
||||
ld r9,PACA_EXSLB+EX_R9(r13)
|
||||
ld r10,PACA_EXSLB+EX_R10(r13)
|
||||
ld r11,PACA_EXSLB+EX_R11(r13)
|
||||
@ -1173,8 +1173,8 @@ _GLOBAL(do_slb_miss)
|
||||
.machine pop
|
||||
|
||||
#ifdef CONFIG_PPC_ISERIES
|
||||
mtspr SRR0,r11
|
||||
mtspr SRR1,r12
|
||||
mtspr SPRN_SRR0,r11
|
||||
mtspr SPRN_SRR1,r12
|
||||
#endif /* CONFIG_PPC_ISERIES */
|
||||
ld r9,PACA_EXSLB+EX_R9(r13)
|
||||
ld r10,PACA_EXSLB+EX_R10(r13)
|
||||
@ -1260,7 +1260,7 @@ _GLOBAL(pSeries_secondary_smp_init)
|
||||
mr r3,r24 /* not found, copy phys to r3 */
|
||||
b .kexec_wait /* next kernel might do better */
|
||||
|
||||
2: mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
|
||||
2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
|
||||
/* From now on, r24 is expected to be logical cpuid */
|
||||
mr r24,r5
|
||||
3: HMT_LOW
|
||||
@ -1531,7 +1531,7 @@ _GLOBAL(pmac_secondary_start)
|
||||
LOADADDR(r4, paca) /* Get base vaddr of paca array */
|
||||
mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
|
||||
add r13,r13,r4 /* for this processor. */
|
||||
mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
|
||||
mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
|
||||
|
||||
/* Create a temp kernel stack for use before relocation is on. */
|
||||
ld r1,PACAEMERGSP(r13)
|
||||
@ -1566,7 +1566,7 @@ _GLOBAL(__secondary_start)
|
||||
/* Initialize the page table pointer register. */
|
||||
LOADADDR(r6,_SDR1)
|
||||
ld r6,0(r6) /* get the value of _SDR1 */
|
||||
mtspr SDR1,r6 /* set the htab location */
|
||||
mtspr SPRN_SDR1,r6 /* set the htab location */
|
||||
#endif
|
||||
/* Initialize the first segment table (or SLB) entry */
|
||||
ld r3,PACASTABVIRT(r13) /* get addr of segment table */
|
||||
@ -1595,7 +1595,7 @@ _GLOBAL(__secondary_start)
|
||||
lwz r3,PLATFORM(r3) /* r3 = platform flags */
|
||||
andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */
|
||||
beq 98f /* branch if result is 0 */
|
||||
mfspr r3,PVR
|
||||
mfspr r3,SPRN_PVR
|
||||
srwi r3,r3,16
|
||||
cmpwi r3,0x37 /* SStar */
|
||||
beq 97f
|
||||
@ -1619,8 +1619,8 @@ _GLOBAL(__secondary_start)
|
||||
#ifdef DO_SOFT_DISABLE
|
||||
ori r4,r4,MSR_EE
|
||||
#endif
|
||||
mtspr SRR0,r3
|
||||
mtspr SRR1,r4
|
||||
mtspr SPRN_SRR0,r3
|
||||
mtspr SPRN_SRR1,r4
|
||||
rfid
|
||||
b . /* prevent speculative execution */
|
||||
|
||||
@ -1682,7 +1682,7 @@ _STATIC(start_here_multiplatform)
|
||||
|
||||
#ifdef CONFIG_HMT
|
||||
/* Start up the second thread on cpu 0 */
|
||||
mfspr r3,PVR
|
||||
mfspr r3,SPRN_PVR
|
||||
srwi r3,r3,16
|
||||
cmpwi r3,0x34 /* Pulsar */
|
||||
beq 90f
|
||||
@ -1742,7 +1742,7 @@ _STATIC(start_here_multiplatform)
|
||||
mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
|
||||
add r13,r13,r24 /* for this processor. */
|
||||
sub r13,r13,r26 /* convert to physical addr */
|
||||
mtspr SPRG3,r13 /* PPPBBB: Temp... -Peter */
|
||||
mtspr SPRN_SPRG3,r13 /* PPPBBB: Temp... -Peter */
|
||||
|
||||
/* Do very early kernel initializations, including initial hash table,
|
||||
* stab and slb setup before we turn on relocation. */
|
||||
@ -1759,7 +1759,7 @@ _STATIC(start_here_multiplatform)
|
||||
lwz r3,PLATFORM(r3) /* r3 = platform flags */
|
||||
andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */
|
||||
beq 98f /* branch if result is 0 */
|
||||
mfspr r3,PVR
|
||||
mfspr r3,SPRN_PVR
|
||||
srwi r3,r3,16
|
||||
cmpwi r3,0x37 /* SStar */
|
||||
beq 97f
|
||||
@ -1783,12 +1783,12 @@ _STATIC(start_here_multiplatform)
|
||||
LOADADDR(r6,_SDR1) /* Only if NOT LPAR */
|
||||
sub r6,r6,r26
|
||||
ld r6,0(r6) /* get the value of _SDR1 */
|
||||
mtspr SDR1,r6 /* set the htab location */
|
||||
mtspr SPRN_SDR1,r6 /* set the htab location */
|
||||
98:
|
||||
LOADADDR(r3,.start_here_common)
|
||||
SET_REG_TO_CONST(r4, MSR_KERNEL)
|
||||
mtspr SRR0,r3
|
||||
mtspr SRR1,r4
|
||||
mtspr SPRN_SRR0,r3
|
||||
mtspr SPRN_SRR1,r4
|
||||
rfid
|
||||
b . /* prevent speculative execution */
|
||||
#endif /* CONFIG_PPC_MULTIPLATFORM */
|
||||
@ -1819,7 +1819,7 @@ _STATIC(start_here_common)
|
||||
LOADADDR(r24, paca) /* Get base vaddr of paca array */
|
||||
mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
|
||||
add r13,r13,r24 /* for this processor. */
|
||||
mtspr SPRG3,r13
|
||||
mtspr SPRN_SPRG3,r13
|
||||
|
||||
/* ptr to current */
|
||||
LOADADDR(r4,init_task)
|
||||
@ -1846,7 +1846,7 @@ _STATIC(start_here_common)
|
||||
_GLOBAL(hmt_init)
|
||||
#ifdef CONFIG_HMT
|
||||
LOADADDR(r5, hmt_thread_data)
|
||||
mfspr r7,PVR
|
||||
mfspr r7,SPRN_PVR
|
||||
srwi r7,r7,16
|
||||
cmpwi r7,0x34 /* Pulsar */
|
||||
beq 90f
|
||||
@ -1855,10 +1855,10 @@ _GLOBAL(hmt_init)
|
||||
cmpwi r7,0x37 /* SStar */
|
||||
beq 91f
|
||||
b 101f
|
||||
90: mfspr r6,PIR
|
||||
90: mfspr r6,SPRN_PIR
|
||||
andi. r6,r6,0x1f
|
||||
b 92f
|
||||
91: mfspr r6,PIR
|
||||
91: mfspr r6,SPRN_PIR
|
||||
andi. r6,r6,0x3ff
|
||||
92: sldi r4,r24,3
|
||||
stwx r6,r5,r4
|
||||
@ -1869,8 +1869,8 @@ __hmt_secondary_hold:
|
||||
LOADADDR(r5, hmt_thread_data)
|
||||
clrldi r5,r5,4
|
||||
li r7,0
|
||||
mfspr r6,PIR
|
||||
mfspr r8,PVR
|
||||
mfspr r6,SPRN_PIR
|
||||
mfspr r8,SPRN_PVR
|
||||
srwi r8,r8,16
|
||||
cmpwi r8,0x34
|
||||
bne 93f
|
||||
@ -1896,19 +1896,19 @@ __hmt_secondary_hold:
|
||||
_GLOBAL(hmt_start_secondary)
|
||||
LOADADDR(r4,__hmt_secondary_hold)
|
||||
clrldi r4,r4,4
|
||||
mtspr NIADORM, r4
|
||||
mfspr r4, MSRDORM
|
||||
mtspr SPRN_NIADORM, r4
|
||||
mfspr r4, SPRN_MSRDORM
|
||||
li r5, -65
|
||||
and r4, r4, r5
|
||||
mtspr MSRDORM, r4
|
||||
mtspr SPRN_MSRDORM, r4
|
||||
lis r4,0xffef
|
||||
ori r4,r4,0x7403
|
||||
mtspr TSC, r4
|
||||
mtspr SPRN_TSC, r4
|
||||
li r4,0x1f4
|
||||
mtspr TST, r4
|
||||
mfspr r4, HID0
|
||||
mtspr SPRN_TST, r4
|
||||
mfspr r4, SPRN_HID0
|
||||
ori r4, r4, 0x1
|
||||
mtspr HID0, r4
|
||||
mtspr SPRN_HID0, r4
|
||||
mfspr r4, SPRN_CTRLF
|
||||
oris r4, r4, 0x40
|
||||
mtspr SPRN_CTRLT, r4
|
||||
|
@ -70,7 +70,7 @@ void power4_enable_pmcs(void)
|
||||
{
|
||||
unsigned long hid0;
|
||||
|
||||
hid0 = mfspr(HID0);
|
||||
hid0 = mfspr(SPRN_HID0);
|
||||
hid0 |= 1UL << (63 - 20);
|
||||
|
||||
/* POWER4 requires the following sequence */
|
||||
@ -83,6 +83,6 @@ void power4_enable_pmcs(void)
|
||||
"mfspr %0, %1\n"
|
||||
"mfspr %0, %1\n"
|
||||
"mfspr %0, %1\n"
|
||||
"isync" : "=&r" (hid0) : "i" (HID0), "0" (hid0):
|
||||
"isync" : "=&r" (hid0) : "i" (SPRN_HID0), "0" (hid0):
|
||||
"memory");
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user