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staging: rtl8188eu: refactor rtl88eu_dm_update_rx_idle_ant()

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Refactor rtl88eu_dm_update_rx_idle_ant() to reduce indentation level
and clear line over 80 characters checkpatch warnings.

Signed-off-by: Michael Straube <straube.linux@gmail.com>
Link: https://lore.kernel.org/r/20200105194936.5477-2-straube.linux@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Michael Straube 2020-01-05 20:49:36 +01:00 committed by Greg Kroah-Hartman
parent 0c5e99c920
commit b4cf24cc93
1 changed files with 29 additions and 27 deletions
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56
drivers/staging/rtl8188eu/hal/odm_rtl8188e.c
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@ -154,35 +154,37 @@ void rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct *dm_odm, u8 ant)
struct adapter *adapter = dm_odm->Adapter;
u32 default_ant, optional_ant;
if (dm_fat_tbl->RxIdleAnt != ant) {
if (ant == MAIN_ANT) {
default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
} else {
default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
}
if (dm_fat_tbl->RxIdleAnt == ant)
return;
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT(5) | BIT(4) | BIT(3), default_ant);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT(8) | BIT(7) | BIT(6), optional_ant);
phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N,
BIT(14) | BIT(13) | BIT(12), default_ant);
phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N,
BIT(6) | BIT(7), default_ant);
} else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT(5) | BIT(4) | BIT(3), default_ant);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT(8) | BIT(7) | BIT(6), optional_ant);
}
if (ant == MAIN_ANT) {
default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
} else {
default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
}
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT(5) | BIT(4) | BIT(3), default_ant);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT(8) | BIT(7) | BIT(6), optional_ant);
phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N,
BIT(14) | BIT(13) | BIT(12), default_ant);
phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N,
BIT(6) | BIT(7), default_ant);
} else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT(5) | BIT(4) | BIT(3), default_ant);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT(8) | BIT(7) | BIT(6), optional_ant);
}
dm_fat_tbl->RxIdleAnt = ant;
}