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iommu/arm-smmu: clean up use of `flags' in page table handling code
Commit 972157cac5
("arm/smmu: Use irqsafe spinlock for domain lock")
fixed our page table locks to be the irq{save,restore} variants, since
the DMA mapping API can be invoked from interrupt context.
This patch cleans up our use of the flags variable so we can distinguish
between IRQ flags (now `flags') and pte protection bits (now `prot').
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
parent
0c9d70d724
commit
b410aed932
@ -1254,7 +1254,7 @@ static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
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static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
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unsigned long addr, unsigned long end,
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unsigned long pfn, int flags, int stage)
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unsigned long pfn, int prot, int stage)
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{
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pte_t *pte, *start;
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pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
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@ -1276,28 +1276,28 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
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if (stage == 1) {
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pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
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if (!(flags & IOMMU_WRITE) && (flags & IOMMU_READ))
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if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
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pteval |= ARM_SMMU_PTE_AP_RDONLY;
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if (flags & IOMMU_CACHE)
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if (prot & IOMMU_CACHE)
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pteval |= (MAIR_ATTR_IDX_CACHE <<
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ARM_SMMU_PTE_ATTRINDX_SHIFT);
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} else {
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pteval |= ARM_SMMU_PTE_HAP_FAULT;
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if (flags & IOMMU_READ)
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if (prot & IOMMU_READ)
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pteval |= ARM_SMMU_PTE_HAP_READ;
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if (flags & IOMMU_WRITE)
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if (prot & IOMMU_WRITE)
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pteval |= ARM_SMMU_PTE_HAP_WRITE;
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if (flags & IOMMU_CACHE)
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if (prot & IOMMU_CACHE)
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pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
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else
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pteval |= ARM_SMMU_PTE_MEMATTR_NC;
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}
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/* If no access, create a faulting entry to avoid TLB fills */
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if (flags & IOMMU_EXEC)
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if (prot & IOMMU_EXEC)
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pteval &= ~ARM_SMMU_PTE_XN;
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else if (!(flags & (IOMMU_READ | IOMMU_WRITE)))
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else if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
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pteval &= ~ARM_SMMU_PTE_PAGE;
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pteval |= ARM_SMMU_PTE_SH_IS;
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@ -1359,7 +1359,7 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
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static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
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unsigned long addr, unsigned long end,
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phys_addr_t phys, int flags, int stage)
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phys_addr_t phys, int prot, int stage)
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{
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int ret;
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pmd_t *pmd;
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@ -1383,7 +1383,7 @@ static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
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do {
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next = pmd_addr_end(addr, end);
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ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn,
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flags, stage);
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prot, stage);
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phys += next - addr;
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} while (pmd++, addr = next, addr < end);
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@ -1392,7 +1392,7 @@ static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
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static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
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unsigned long addr, unsigned long end,
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phys_addr_t phys, int flags, int stage)
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phys_addr_t phys, int prot, int stage)
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{
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int ret = 0;
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pud_t *pud;
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@ -1416,7 +1416,7 @@ static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
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do {
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next = pud_addr_end(addr, end);
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ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
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flags, stage);
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prot, stage);
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phys += next - addr;
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} while (pud++, addr = next, addr < end);
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@ -1425,7 +1425,7 @@ static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
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static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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unsigned long iova, phys_addr_t paddr,
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size_t size, int flags)
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size_t size, int prot)
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{
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int ret, stage;
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unsigned long end;
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@ -1433,7 +1433,7 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
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pgd_t *pgd = root_cfg->pgd;
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struct arm_smmu_device *smmu = root_cfg->smmu;
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unsigned long irqflags;
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unsigned long flags;
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if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) {
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stage = 2;
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@ -1456,14 +1456,14 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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if (paddr & ~output_mask)
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return -ERANGE;
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spin_lock_irqsave(&smmu_domain->lock, irqflags);
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spin_lock_irqsave(&smmu_domain->lock, flags);
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pgd += pgd_index(iova);
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end = iova + size;
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do {
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unsigned long next = pgd_addr_end(iova, end);
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ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
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flags, stage);
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prot, stage);
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if (ret)
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goto out_unlock;
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@ -1472,13 +1472,13 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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} while (pgd++, iova != end);
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out_unlock:
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spin_unlock_irqrestore(&smmu_domain->lock, irqflags);
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spin_unlock_irqrestore(&smmu_domain->lock, flags);
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return ret;
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}
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static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
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phys_addr_t paddr, size_t size, int flags)
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phys_addr_t paddr, size_t size, int prot)
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{
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struct arm_smmu_domain *smmu_domain = domain->priv;
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@ -1489,7 +1489,7 @@ static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
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if ((phys_addr_t)iova & ~smmu_domain->output_mask)
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return -ERANGE;
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return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, flags);
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return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot);
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}
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static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
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