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Merge tag 'amd-drm-next-5.14-2021-06-22-1' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

Browse Source 
amd-drm-next-5.14-2021-06-22-1:

amdgpu:
- Userptr BO fixes
- RAS fixes
- Beige Goby fixes
- Add some missing freesync documentation
- Aldebaran fixes
- SR-IOV fixes
- Potential memory corruption fix in framebuffer handling
- Revert GFX9, 10 doorbell fixes, we just
  end up trading one bug for another
- Multi-plane cursor fixes with rotation
- LTTPR fixes
- Backlight fixes
- eDP fix
- Fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN
- Misc code cleanups

amdkfd:
- Topology fix
- Locking fix

radeon:
- Misc code cleanup

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210622210345.27297-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie 2021-06-24 07:57:40 +10:00
commit b322a50d17
110 changed files with 491 additions and 542 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/gpu/amdgpu-dc.rst
View File

@ -66,3 +66,9 @@ Display Core
============
**WIP**
FreeSync Video
--------------
.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
:doc: FreeSync Video

8
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
View File

@ -373,6 +373,14 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int n
return -EINVAL;
}
int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance,
int *major, int *minor, int *revision)
{
return amdgpu_discovery_get_ip_version(adev, VCN_HWID,
vcn_instance, major, minor, revision);
}
void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
{
struct binary_header *bhdr;

3
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
View File

@ -32,6 +32,9 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev);
int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
int *major, int *minor, int *revision);
int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance,
int *major, int *minor, int *revision);
int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
#endif /* __AMDGPU_DISCOVERY__ */

12
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
View File

@ -1046,11 +1046,12 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev,
rfb->base.obj[0] = obj;
drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
if (ret)
goto err;
ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
if (ret)
goto err;
@ -1070,9 +1071,6 @@ int amdgpu_display_gem_fb_verify_and_init(
rfb->base.obj[0] = obj;
drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
if (ret)
goto err;
/* Verify that the modifier is supported. */
if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
mode_cmd->modifier[0])) {
@ -1088,6 +1086,10 @@ int amdgpu_display_gem_fb_verify_and_init(
if (ret)
goto err;
ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
if (ret)
goto err;
return 0;
err:
drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);

19
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View File

@ -837,8 +837,23 @@ module_param_named(tmz, amdgpu_tmz, int, 0444);
/**
* DOC: freesync_video (uint)
* Enabled the optimization to adjust front porch timing to achieve seamless mode change experience
* when setting a freesync supported mode for which full modeset is not needed.
* Enable the optimization to adjust front porch timing to achieve seamless
* mode change experience when setting a freesync supported mode for which full
* modeset is not needed.
*
* The Display Core will add a set of modes derived from the base FreeSync
* video mode into the corresponding connector's mode list based on commonly
* used refresh rates and VRR range of the connected display, when users enable
* this feature. From the userspace perspective, they can see a seamless mode
* change experience when the change between different refresh rates under the
* same resolution. Additionally, userspace applications such as Video playback
* can read this modeset list and change the refresh rate based on the video
* frame rate. Finally, the userspace can also derive an appropriate mode for a
* particular refresh rate based on the FreeSync Mode and add it to the
* connector's mode list.
*
* Note: This is an experimental feature.
*
* The default value: 0 (off).
*/
MODULE_PARM_DESC(

3
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
View File

@ -300,7 +300,6 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
* @adev: amdgpu_device pointer
* @offset: offset into the GPU's gart aperture
* @pages: number of pages to bind
* @pagelist: pages to bind
* @dma_addr: DMA addresses of pages
* @flags: page table entry flags
*
@ -309,7 +308,7 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
* Returns 0 for success, -EINVAL for failure.
*/
int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
int pages, struct page **pagelist, dma_addr_t *dma_addr,
int pages, dma_addr_t *dma_addr,
uint64_t flags)
{
if (!adev->gart.ready) {

3
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
View File

@ -64,7 +64,6 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
int pages, dma_addr_t *dma_addr, uint64_t flags,
void *dst);
int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
int pages, struct page **pagelist,
dma_addr_t *dma_addr, uint64_t flags);
int pages, dma_addr_t *dma_addr, uint64_t flags);
void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev);
#endif

7
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
View File

@ -1984,6 +1984,9 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
ret = amdgpu_ras_load_bad_pages(adev);
if (ret)
goto free;
if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
}
return 0;
@ -2063,7 +2066,9 @@ static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
return;
if (strnstr(ctx->vbios_version, "D16406",
sizeof(ctx->vbios_version)))
sizeof(ctx->vbios_version)) ||
strnstr(ctx->vbios_version, "D36002",
sizeof(ctx->vbios_version)))
adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
}

13
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
View File

@ -841,7 +841,7 @@ static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
uint64_t page_idx = 1;
r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
ttm->pages, gtt->ttm.dma_address, flags);
gtt->ttm.dma_address, flags);
if (r)
goto gart_bind_fail;
@ -855,11 +855,10 @@ static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
r = amdgpu_gart_bind(adev,
gtt->offset + (page_idx << PAGE_SHIFT),
ttm->num_pages - page_idx,
&ttm->pages[page_idx],
&(gtt->ttm.dma_address[page_idx]), flags);
} else {
r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
ttm->pages, gtt->ttm.dma_address, flags);
gtt->ttm.dma_address, flags);
}
gart_bind_fail:
@ -935,7 +934,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
/* bind pages into GART page tables */
gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
ttm->pages, gtt->ttm.dma_address, flags);
gtt->ttm.dma_address, flags);
if (r)
DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
@ -1129,8 +1128,6 @@ static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
if (!ttm->sg)
return -ENOMEM;
ttm->page_flags |= TTM_PAGE_FLAG_SG;
return 0;
}
@ -1156,7 +1153,6 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
amdgpu_ttm_tt_set_user_pages(ttm, NULL);
kfree(ttm->sg);
ttm->sg = NULL;
ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
return;
}
@ -1190,6 +1186,9 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
return -ENOMEM;
}
/* Set TTM_PAGE_FLAG_SG before populate but after create. */
bo->ttm->page_flags |= TTM_PAGE_FLAG_SG;
gtt = (void *)bo->ttm;
gtt->userptr = addr;
gtt->userflags = flags;

4
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
View File

@ -94,6 +94,7 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry)
{
struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
if (adev->umc.ras_funcs &&
@ -131,6 +132,9 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
err_data->err_addr_cnt);
amdgpu_ras_save_bad_pages(adev);
if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
}
amdgpu_ras_reset_gpu(adev);

5
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
View File

@ -21,6 +21,11 @@
#ifndef __AMDGPU_UMC_H__
#define __AMDGPU_UMC_H__
/*
* (addr / 256) * 4096, the higher 26 bits in ErrorAddr
* is the index of 4KB block
*/
#define ADDR_OF_4KB_BLOCK(addr) (((addr) & ~0xffULL) << 4)
/*
* (addr / 256) * 8192, the higher 26 bits in ErrorAddr
* is the index of 8KB block

23
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
View File

@ -288,6 +288,29 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
return 0;
}
bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
{
bool ret = false;
int major;
int minor;
int revision;
/* if cannot find IP data, then this VCN does not exist */
if (amdgpu_discovery_get_vcn_version(adev, vcn_instance, &major, &minor, &revision) != 0)
return true;
if ((type == VCN_ENCODE_RING) && (revision & VCN_BLOCK_ENCODE_DISABLE_MASK)) {
ret = true;
} else if ((type == VCN_DECODE_RING) && (revision & VCN_BLOCK_DECODE_DISABLE_MASK)) {
ret = true;
} else if ((type == VCN_UNIFIED_RING) && (revision & VCN_BLOCK_QUEUE_DISABLE_MASK)) {
ret = true;
}
return ret;
}
int amdgpu_vcn_suspend(struct amdgpu_device *adev)
{
unsigned size;

13
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
View File

@ -280,6 +280,16 @@ struct amdgpu_vcn_decode_buffer {
uint32_t pad[30];
};
#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
#define VCN_BLOCK_DECODE_DISABLE_MASK 0x40
#define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0
enum vcn_ring_type {
VCN_ENCODE_RING,
VCN_DECODE_RING,
VCN_UNIFIED_RING,
};
int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
@ -287,6 +297,9 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev);
void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev,
enum vcn_ring_type type, uint32_t vcn_instance);
int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);

6
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
View File

@ -6970,12 +6970,8 @@ static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
if (ring->use_doorbell) {
WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
(adev->doorbell_index.kiq * 2) << 2);
/* If GC has entered CGPG, ringing doorbell > first page doesn't
* wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
* this issue.
*/
WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
(adev->doorbell.size - 4));
(adev->doorbell_index.userqueue_end * 2) << 2);
}
WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

6
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@ -3675,12 +3675,8 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
if (ring->use_doorbell) {
WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
(adev->doorbell_index.kiq * 2) << 2);
/* If GC has entered CGPG, ringing doorbell > first page doesn't
* wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
* this issue.
*/
WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
(adev->doorbell.size - 4));
(adev->doorbell_index.userqueue_end * 2) << 2);
}
WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

5
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
View File

@ -782,11 +782,6 @@ void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1);
WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp);
WREG32_SOC15(GC, 0, regDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
tmp = 0;
tmp = REG_SET_FIELD(tmp, DIDT_SQ_THROTTLE_CTRL, PWRBRK_STALL_EN, 1);
WREG32_SOC15(GC, 0, regDIDT_IND_DATA, tmp);
WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
tmp = 0;
tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12);

2
drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
View File

@ -234,7 +234,7 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev,
err_addr &= ~((0x1ULL << lsb) - 1);
/* translate umc channel address to soc pa, 3 parts are included */
retired_page = ADDR_OF_8KB_BLOCK(err_addr) |
retired_page = ADDR_OF_4KB_BLOCK(err_addr) |
ADDR_OF_256B_BLOCK(channel_index) |
OFFSET_IN_256B_BLOCK(err_addr);

58
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
View File

@ -87,21 +87,18 @@ static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
static int vcn_v3_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i;
if (amdgpu_sriov_vf(adev)) {
adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
for (i = 0; i < VCN_INSTANCES_SIENNA_CICHLID; i++)
if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i))
adev->vcn.num_vcn_inst++;
adev->vcn.harvest_config = 0;
adev->vcn.num_enc_rings = 1;
if (adev->asic_type == CHIP_BEIGE_GOBY) {
adev->vcn.num_vcn_inst = 1;
adev->vcn.num_enc_rings = 0;
}
} else {
if (adev->asic_type == CHIP_SIENNA_CICHLID) {
u32 harvest;
int i;
adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
@ -156,7 +153,8 @@ static int vcn_v3_0_sw_init(void *handle)
adev->firmware.fw_size +=
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) {
if ((adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) ||
(amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)) {
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
adev->firmware.fw_size +=
@ -330,19 +328,17 @@ static int vcn_v3_0_hw_init(void *handle)
continue;
ring = &adev->vcn.inst[i].ring_dec;
if (ring->sched.ready) {
ring->wptr = 0;
ring->wptr_old = 0;
vcn_v3_0_dec_ring_set_wptr(ring);
}
ring->wptr = 0;
ring->wptr_old = 0;
vcn_v3_0_dec_ring_set_wptr(ring);
ring->sched.ready = true;
for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
ring = &adev->vcn.inst[i].ring_enc[j];
if (ring->sched.ready) {
ring->wptr = 0;
ring->wptr_old = 0;
vcn_v3_0_enc_ring_set_wptr(ring);
}
ring->wptr = 0;
ring->wptr_old = 0;
vcn_v3_0_enc_ring_set_wptr(ring);
ring->sched.ready = true;
}
}
} else {
@ -1309,8 +1305,6 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
uint32_t table_size;
uint32_t size, size_dw;
bool is_vcn_ready;
struct mmsch_v3_0_cmd_direct_write
direct_wt = { {0} };
struct mmsch_v3_0_cmd_direct_read_modify_write
@ -1502,30 +1496,6 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
}
}
/* 6, check each VCN's init_status
* if it remains as 0, then this VCN is not assigned to current VF
* do not start ring for this VCN
*/
size = sizeof(struct mmsch_v3_0_init_header);
table_loc = (uint32_t *)table->cpu_addr;
memcpy(&header, (void *)table_loc, size);
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
if (adev->vcn.harvest_config & (1 << i))
continue;
is_vcn_ready = (header.inst[i].init_status == 1);
if (!is_vcn_ready)
DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i);
ring = &adev->vcn.inst[i].ring_dec;
ring->sched.ready = is_vcn_ready;
for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
ring = &adev->vcn.inst[i].ring_enc[j];
ring->sched.ready = is_vcn_ready;
}
}
return 0;
}

26
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
View File

@ -1709,7 +1709,7 @@ static int process_termination_cpsch(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
{
int retval;
struct queue *q, *next;
struct queue *q;
struct kernel_queue *kq, *kq_next;
struct mqd_manager *mqd_mgr;
struct device_process_node *cur, *next_dpn;
@ -1766,6 +1766,19 @@ static int process_termination_cpsch(struct device_queue_manager *dqm,
qpd->reset_wavefronts = false;
}
/* Lastly, free mqd resources.
* Do free_mqd() after dqm_unlock to avoid circular locking.
*/
while (!list_empty(&qpd->queues_list)) {
q = list_first_entry(&qpd->queues_list, struct queue, list);
mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
q->properties.type)];
list_del(&q->list);
qpd->queue_count--;
dqm_unlock(dqm);
mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
dqm_lock(dqm);
}
dqm_unlock(dqm);
/* Outside the DQM lock because under the DQM lock we can't do
@ -1774,17 +1787,6 @@ static int process_termination_cpsch(struct device_queue_manager *dqm,
if (found)
kfd_dec_compute_active(dqm->dev);
/* Lastly, free mqd resources.
* Do free_mqd() after dqm_unlock to avoid circular locking.
*/
list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
q->properties.type)];
list_del(&q->list);
qpd->queue_count--;
mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
}
return retval;
}

23
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
View File

@ -1222,6 +1222,28 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev,
}
}
static void kfd_set_iolink_non_coherent(struct kfd_topology_device *to_dev,
struct kfd_iolink_properties *outbound_link,
struct kfd_iolink_properties *inbound_link)
{
/* CPU -> GPU with PCIe */
if (!to_dev->gpu &&
inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS)
inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
if (to_dev->gpu) {
/* GPU <-> GPU with PCIe and
* Vega20 with XGMI
*/
if (inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS ||
(inbound_link->iolink_type == CRAT_IOLINK_TYPE_XGMI &&
to_dev->gpu->device_info->asic_family == CHIP_VEGA20)) {
outbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
}
}
}
static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)
{
struct kfd_iolink_properties *link, *inbound_link;
@ -1247,6 +1269,7 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)
inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED;
kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link);
kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);
}
}
}

7
drivers/gpu/drm/amd/display/Kconfig
View File

@ -31,13 +31,6 @@ config DRM_AMD_DC_SI
by default. This includes Tahiti, Pitcairn, Cape Verde, Oland.
Hainan is not supported by AMD DC and it has no physical DCE6.
config DRM_AMD_DC_DCN3_1
bool "DCN 3.1 family"
depends on DRM_AMD_DC_DCN
help
Choose this option if you want to have
DCN3.1 family support for display engine
config DEBUG_KERNEL_DC
bool "Enable kgdb break in DC"
depends on DRM_AMD_DC

62
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -110,10 +110,8 @@ MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
#define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
#endif
#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@ -1145,16 +1143,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
init_data.flags.disable_dmcu = true;
break;
#if defined(CONFIG_DRM_AMD_DC_DCN)
case CHIP_VANGOGH:
init_data.flags.gpu_vm_support = true;
break;
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case CHIP_YELLOW_CARP:
init_data.flags.gpu_vm_support = true;
break;
#endif
default:
break;
}
@ -1411,9 +1403,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
case CHIP_VANGOGH:
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case CHIP_YELLOW_CARP:
#endif
return 0;
case CHIP_NAVI12:
fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
@ -1532,12 +1522,10 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
dmub_asic = DMUB_ASIC_DCN303;
fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
break;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case CHIP_YELLOW_CARP:
dmub_asic = DMUB_ASIC_DCN31;
fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
break;
#endif
default:
/* ASIC doesn't support DMUB. */
@ -2232,7 +2220,7 @@ static int dm_resume(void *handle)
= 0xffffffff;
}
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
/*
* Resource allocation happens for link encoders for newer ASIC in
* dc_validate_global_state, so we need to revalidate it.
@ -3786,9 +3774,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case CHIP_YELLOW_CARP:
#endif
case CHIP_RENOIR:
if (register_outbox_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
@ -3893,9 +3879,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
case CHIP_VANGOGH:
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case CHIP_YELLOW_CARP:
#endif
if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
goto fail;
@ -4067,13 +4051,11 @@ static int dm_early_init(void *handle)
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case CHIP_YELLOW_CARP:
adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 4;
adev->mode_info.num_dig = 4;
break;
#endif
case CHIP_NAVI14:
case CHIP_DIMGREY_CAVEFISH:
adev->mode_info.num_crtc = 5;
@ -4311,9 +4293,7 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
adev->asic_type == CHIP_NAVY_FLOUNDER ||
adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
adev->asic_type == CHIP_BEIGE_GOBY ||
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
adev->asic_type == CHIP_YELLOW_CARP ||
#endif
adev->asic_type == CHIP_VANGOGH)
tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
}
@ -5646,6 +5626,36 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
}
#endif
/**
* DOC: FreeSync Video
*
* When a userspace application wants to play a video, the content follows a
* standard format definition that usually specifies the FPS for that format.
* The below list illustrates some video format and the expected FPS,
* respectively:
*
* - TV/NTSC (23.976 FPS)
* - Cinema (24 FPS)
* - TV/PAL (25 FPS)
* - TV/NTSC (29.97 FPS)
* - TV/NTSC (30 FPS)
* - Cinema HFR (48 FPS)
* - TV/PAL (50 FPS)
* - Commonly used (60 FPS)
* - Multiples of 24 (48,72,96 FPS)
*
* The list of standards video format is not huge and can be added to the
* connector modeset list beforehand. With that, userspace can leverage
* FreeSync to extends the front porch in order to attain the target refresh
* rate. Such a switch will happen seamlessly, without screen blanking or
* reprogramming of the output in any other way. If the userspace requests a
* modesetting change compatible with FreeSync modes that only differ in the
* refresh rate, DC will skip the full update and avoid blink during the
* transition. For example, the video player can change the modesetting from
* 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
* causing any display blink. This same concept can be applied to a mode
* setting change.
*/
static struct drm_display_mode *
get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
bool use_probed_modes)
@ -5870,6 +5880,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
stream->use_vsc_sdp_for_colorimetry = true;
}
mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
}
finish:
dc_sink_release(sink);
@ -8683,7 +8695,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
acrtc_state->stream->link->psr_settings.psr_feature_enabled &&
!acrtc_state->stream->link->psr_settings.psr_allow_active) {
amdgpu_dm_psr_enable(acrtc_state->stream);
struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)
acrtc_state->stream->dm_stream_context;
if (aconn->psr_skip_count > 0)
aconn->psr_skip_count--;
else
amdgpu_dm_psr_enable(acrtc_state->stream);
}
mutex_unlock(&dm->dc_lock);

2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
View File

@ -509,6 +509,8 @@ struct amdgpu_dm_connector {
struct dsc_preferred_settings dsc_settings;
/* Cached display modes */
struct drm_display_mode freesync_vid_base;
int psr_skip_count;
};
#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)

4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
View File

@ -467,13 +467,11 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
display->dig_fe = config->dig_fe;
link->dig_be = config->dig_be;
link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
display->stream_enc_idx = config->stream_enc_idx;
link->link_enc_idx = config->link_enc_idx;
link->phy_idx = config->phy_idx;
link->hdcp_supported_informational = dc_link_is_hdcp14(aconnector->dc_link,
aconnector->dc_sink->sink_signal) ? 1 : 0;
#endif
link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
link->dp.assr_enabled = config->assr_enabled;
link->dp.mst_enabled = config->mst_enabled;
@ -657,12 +655,10 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct
INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate);
hdcp_work[i].hdcp.config.psp.handle = &adev->psp;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
if (dc->ctx->dce_version == DCN_VERSION_3_1) {
hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;
hdcp_work[i].hdcp.config.psp.caps.opm_state_query_supported = false;
}
#endif
hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);
hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;
hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;

2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
View File

@ -67,14 +67,12 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
struct dc_link *link = NULL;
struct psr_config psr_config = {0};
struct psr_context psr_context = {0};
struct dc *dc = NULL;
bool ret = false;
if (stream == NULL)
return false;
link = stream->link;
dc = link->ctx->dc;
psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;

3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
View File

@ -28,6 +28,9 @@
#include "amdgpu.h"
/* the number of pageflips before enabling psr */
#define AMDGPU_DM_PSR_ENTRY_DELAY 5
void amdgpu_dm_set_psr_caps(struct dc_link *link);
bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);

2
drivers/gpu/drm/amd/display/dc/Makefile
View File

@ -34,10 +34,8 @@ DC_LIBS += dcn30
DC_LIBS += dcn301
DC_LIBS += dcn302
DC_LIBS += dcn303
ifdef CONFIG_DRM_AMD_DC_DCN3_1
DC_LIBS += dcn31
endif
endif
DC_LIBS += dce120

9
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
View File

@ -576,13 +576,11 @@ static struct device_id device_type_from_device_id(uint16_t device_id)
result_device_id.device_type = DEVICE_TYPE_LCD;
result_device_id.enum_id = 1;
break;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case ATOM_DISPLAY_LCD2_SUPPORT:
result_device_id.device_type = DEVICE_TYPE_LCD;
result_device_id.enum_id = 2;
break;
#endif
case ATOM_DISPLAY_DFP1_SUPPORT:
result_device_id.device_type = DEVICE_TYPE_DFP;
@ -2140,7 +2138,7 @@ static enum bp_result get_integrated_info_v2_1(
info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
info->edp1_info.edp_panel_bpc =
info_v2_1->edp1_info.edp_panel_bpc;
info->edp1_info.edp_bootup_bl_level =
info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level;
info->edp2_info.edp_backlight_pwm_hz =
le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz);
@ -2162,7 +2160,6 @@ static enum bp_result get_integrated_info_v2_1(
return BP_RESULT_OK;
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
static enum bp_result get_integrated_info_v2_2(
struct bios_parser *bp,
struct integrated_info *info)
@ -2262,7 +2259,7 @@ static enum bp_result get_integrated_info_v2_2(
return BP_RESULT_OK;
}
#endif
/*
* construct_integrated_info
*
@ -2310,11 +2307,9 @@ static enum bp_result construct_integrated_info(
case 1:
result = get_integrated_info_v2_1(bp, info);
break;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case 2:
result = get_integrated_info_v2_2(bp, info);
break;
#endif
default:
return result;
}

6
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
View File

@ -72,13 +72,9 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
case DCN_VERSION_2_1:
case DCN_VERSION_3_0:
case DCN_VERSION_3_01:
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case DCN_VERSION_3_1:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
#endif
case DCN_VERSION_3_02:
case DCN_VERSION_3_03:
case DCN_VERSION_3_1:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
#endif

2
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
View File

@ -135,9 +135,7 @@ endif
AMD_DAL_CLK_MGR_DCN301 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301))
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)
endif
ifdef CONFIG_DRM_AMD_DC_DCN3_1
###############################################################################
# DCN31
###############################################################################

7
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
View File

@ -41,9 +41,7 @@
#include "dcn21/rn_clk_mgr.h"
#include "dcn30/dcn30_clk_mgr.h"
#include "dcn301/vg_clk_mgr.h"
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#include "dcn31/dcn31_clk_mgr.h"
#endif
int clk_mgr_helper_get_active_display_cnt(
@ -273,9 +271,6 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
return &clk_mgr->base.base;
}
break;
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case FAMILY_YELLOW_CARP: {
struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
@ -325,12 +320,10 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
vg_clk_mgr_destroy(clk_mgr);
break;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case FAMILY_YELLOW_CARP:
if (ASICREV_IS_YELLOW_CARP(clk_mgr_base->ctx->asic_id.hw_internal_rev))
dcn31_clk_mgr_destroy(clk_mgr);
break;
#endif
default:
break;

2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
View File

@ -386,10 +386,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
// Both fclk and ref_dppclk run on the same scemi clock.
clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
/* TODO: set dtbclk in correct place */
clk_mgr->clks.dtbclk_en = false;
#endif
dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
}

8
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -1524,7 +1524,7 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
return stream_mask;
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
void dc_z10_restore(struct dc *dc)
{
if (dc->hwss.z10_restore)
@ -1544,9 +1544,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
#if defined(CONFIG_DRM_AMD_DC_DCN)
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
dc_z10_restore(dc);
#endif
dc_allow_idle_optimizations(dc, false);
#endif
@ -2626,7 +2624,7 @@ static void commit_planes_for_stream(struct dc *dc,
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_z10_restore(dc);
#endif
@ -3085,7 +3083,7 @@ void dc_set_power_state(
case DC_ACPI_CM_POWER_STATE_D0:
dc_resource_state_construct(dc, dc->current_state);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_z10_restore(dc);
#endif
if (dc->ctx->dmub_srv)

8
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -821,7 +821,7 @@ static bool dc_link_detect_helper(struct dc_link *link,
{
struct dc_sink_init_data sink_init_data = { 0 };
struct display_sink_capability sink_caps = { 0 };
uint8_t i;
uint32_t i;
bool converter_disable_audio = false;
struct audio_support *aud_support = &link->dc->res_pool->audio_support;
bool same_edid = false;
@ -2661,7 +2661,7 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
return false;
link->psr_settings.psr_allow_active = allow_active;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (!allow_active)
dc_z10_restore(dc);
#endif
@ -2842,7 +2842,7 @@ bool dc_link_setup_psr(struct dc_link *link,
psr_context->psr_level.u32all = 0;
/*skip power down the single pipe since it blocks the cstate*/
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10)
@ -3191,7 +3191,7 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
/*stream_enc_inst*/
config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
config.link_enc_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
config.phy_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;

70
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View File

@ -1664,6 +1664,7 @@ static enum link_training_result dp_perform_8b_10b_link_training(
uint8_t repeater_cnt;
uint8_t repeater_id;
uint8_t lane = 0;
if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
start_clock_recovery_pattern_early(link, lt_settings, DPRX);
@ -1694,6 +1695,9 @@ static enum link_training_result dp_perform_8b_10b_link_training(
repeater_training_done(link, repeater_id);
}
for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
lt_settings->lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
}
if (status == LINK_TRAINING_SUCCESS) {
@ -1756,42 +1760,6 @@ enum link_training_result dc_link_dp_perform_link_training(
return status;
}
static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
{
struct dc_link *link = stream->link;
enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
#ifdef CONFIG_DRM_AMD_DC_HDCP
struct cp_psp *cp_psp = &stream->ctx->cp_psp;
#endif
/* ASSR must be supported on the panel */
if (panel_mode == DP_PANEL_MODE_DEFAULT)
return panel_mode;
/* eDP or internal DP only */
if (link->connector_signal != SIGNAL_TYPE_EDP &&
!(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
link->is_internal_display))
return DP_PANEL_MODE_DEFAULT;
#ifdef CONFIG_DRM_AMD_DC_HDCP
if (cp_psp && cp_psp->funcs.enable_assr) {
if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
/* since eDP implies ASSR on, change panel
* mode to disable ASSR
*/
panel_mode = DP_PANEL_MODE_DEFAULT;
}
} else
panel_mode = DP_PANEL_MODE_DEFAULT;
#else
/* turn off ASSR if the implementation is not compiled in */
panel_mode = DP_PANEL_MODE_DEFAULT;
#endif
return panel_mode;
}
bool perform_link_training_with_retries(
const struct dc_link_settings *link_setting,
bool skip_video_pattern,
@ -1800,11 +1768,11 @@ bool perform_link_training_with_retries(
enum signal_type signal,
bool do_fallback)
{
uint8_t j;
int j;
uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
enum dp_panel_mode panel_mode;
enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
struct link_encoder *link_enc;
enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
struct dc_link_settings current_setting = *link_setting;
@ -1841,11 +1809,23 @@ bool perform_link_training_with_retries(
msleep(delay_dp_power_up_in_ms);
}
panel_mode = try_enable_assr(stream);
#ifdef CONFIG_DRM_AMD_DC_HDCP
if (panel_mode == DP_PANEL_MODE_EDP) {
struct cp_psp *cp_psp = &stream->ctx->cp_psp;
if (cp_psp && cp_psp->funcs.enable_assr) {
if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
/* since eDP implies ASSR on, change panel
* mode to disable ASSR
*/
panel_mode = DP_PANEL_MODE_DEFAULT;
}
} else
panel_mode = DP_PANEL_MODE_DEFAULT;
}
#endif
dp_set_panel_mode(link, panel_mode);
DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
link->link_index,
panel_mode != DP_PANEL_MODE_DEFAULT);
if (link->aux_access_disabled) {
dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
@ -2327,7 +2307,7 @@ bool dp_verify_link_cap_with_retries(
struct dc_link_settings *known_limit_link_setting,
int attempts)
{
uint8_t i = 0;
int i = 0;
bool success = false;
for (i = 0; i < attempts; i++) {
@ -3675,6 +3655,10 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
lttpr_dpcd_data,
sizeof(lttpr_dpcd_data));
if (status != DC_OK) {
dm_error("%s: Read LTTPR caps data failed.\n", __func__);
return false;
}
link->dpcd_caps.lttpr_caps.revision.raw =
lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -

2
drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
View File

@ -152,7 +152,7 @@ static void dpcd_reduce_address_range(
const uint32_t reduced_size)
{
const uint32_t reduced_end_address = END_ADDRESS(reduced_address, reduced_size);
const uint32_t extended_end_address = END_ADDRESS(reduced_address, extended_size);
const uint32_t extended_end_address = END_ADDRESS(extended_address, extended_size);
const uint32_t offset = reduced_address - extended_address;
if (extended_end_address == reduced_end_address && extended_address == reduced_address)

10
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -58,9 +58,7 @@
#include "dcn301/dcn301_resource.h"
#include "dcn302/dcn302_resource.h"
#include "dcn303/dcn303_resource.h"
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#include "../dcn31/dcn31_resource.h"
#endif
#include "dcn31/dcn31_resource.h"
#endif
#define DC_LOGGER_INIT(logger)
@ -141,9 +139,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
case FAMILY_VGH:
dc_version = DCN_VERSION_3_01;
break;
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case FAMILY_YELLOW_CARP:
if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_3_1;
@ -233,11 +229,9 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
case DCN_VERSION_3_03:
res_pool = dcn303_create_resource_pool(init_data, dc);
break;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case DCN_VERSION_3_1:
res_pool = dcn31_create_resource_pool(init_data, dc);
break;
#endif
#endif
default:
break;
@ -2142,7 +2136,7 @@ enum dc_status dc_validate_global_state(
if (!new_ctx)
return DC_ERROR_UNEXPECTED;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
/*
* Update link encoder to stream assignment.

4
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
View File

@ -294,9 +294,7 @@ bool dc_stream_set_cursor_attributes(
stream->cursor_attributes = *attributes;
#if defined(CONFIG_DRM_AMD_DC_DCN)
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
dc_z10_restore(dc);
#endif
/* disable idle optimizations while updating cursor */
if (dc->idle_optimizations_allowed) {
dc_allow_idle_optimizations(dc, false);
@ -358,9 +356,7 @@ bool dc_stream_set_cursor_position(
dc = stream->ctx->dc;
res_ctx = &dc->current_state->res_ctx;
#if defined(CONFIG_DRM_AMD_DC_DCN)
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
dc_z10_restore(dc);
#endif
/* disable idle optimizations if enabling cursor */
if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {

16
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -45,7 +45,7 @@
/* forward declaration */
struct aux_payload;
#define DC_VER "3.2.140"
#define DC_VER "3.2.141"
#define MAX_SURFACES 3
#define MAX_PLANES 6
@ -352,7 +352,7 @@ enum dcn_pwr_state {
DCN_PWR_STATE_LOW_POWER = 3,
};
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dcn_z9_support_state {
DCN_Z9_SUPPORT_UNKNOWN,
DCN_Z9_SUPPORT_ALLOW,
@ -376,7 +376,7 @@ struct dc_clocks {
int phyclk_khz;
int dramclk_khz;
bool p_state_change_support;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dcn_z9_support_state z9_support;
bool dtbclk_en;
#endif
@ -501,7 +501,7 @@ struct dc_debug_options {
bool disable_pplib_clock_request;
bool disable_clock_gate;
bool disable_mem_low_power;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool pstate_enabled;
#endif
bool disable_dmcu;
@ -522,8 +522,6 @@ struct dc_debug_options {
unsigned int force_odm_combine; //bit vector based on otg inst
#if defined(CONFIG_DRM_AMD_DC_DCN)
unsigned int force_odm_combine_4to1; //bit vector based on otg inst
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
bool disable_z9_mpc;
#endif
unsigned int force_fclk_khz;
@ -567,7 +565,7 @@ struct dc_debug_options {
bool force_enable_edp_fec;
/* FEC/PSR1 sequence enable delay in 100us */
uint8_t fec_enable_delay_in100us;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool disable_z10;
bool enable_sw_cntl_psr;
#endif
@ -595,7 +593,7 @@ struct dc_phy_addr_space_config {
uint64_t page_table_start_addr;
uint64_t page_table_end_addr;
uint64_t page_table_base_addr;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool base_addr_is_mc_addr;
#endif
} gart_config;
@ -1335,7 +1333,7 @@ void dc_hardware_release(struct dc *dc);
#endif
bool dc_set_psr_allow_active(struct dc *dc, bool enable);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
void dc_z10_restore(struct dc *dc);
#endif

3
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
View File

@ -185,7 +185,7 @@ bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
stream_mask, timeout) == DMUB_STATUS_OK;
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
{
struct dmub_srv *dmub;
@ -207,7 +207,6 @@ bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
return boot_status.bits.restore_required;
}
#endif
bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
{

3
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
View File

@ -62,9 +62,8 @@ bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub
bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
unsigned int stream_mask);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv);
#endif
bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry);
void dc_dmub_trace_event_control(struct dc *dc, bool enable);

2
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
View File

@ -668,7 +668,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
/* polling_timeout_period is in us */
defer_time_in_ms += aux110->polling_timeout_period / 1000;
++aux_defer_retries;
/* fall through */
fallthrough;
case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
retry_on_defer = true;
fallthrough;

6
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
View File

@ -1106,22 +1106,18 @@ struct dce_hwseq_registers {
type PANEL_DIGON_OVRD;\
type PANEL_PWRSEQ_TARGET_STATE_R;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#define HWSEQ_DCN31_REG_FIELD_LIST(type) \
type DOMAIN_POWER_FORCEON;\
type DOMAIN_POWER_GATE;\
type DOMAIN_PGFSM_PWR_STATUS;\
type HPO_HDMISTREAMCLK_G_GATE_DIS;
#endif
struct dce_hwseq_shift {
HWSEQ_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN3_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN301_REG_FIELD_LIST(uint8_t)
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
HWSEQ_DCN31_REG_FIELD_LIST(uint8_t)
#endif
};
struct dce_hwseq_mask {
@ -1129,9 +1125,7 @@ struct dce_hwseq_mask {
HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
HWSEQ_DCN3_REG_FIELD_LIST(uint32_t)
HWSEQ_DCN301_REG_FIELD_LIST(uint32_t)
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
HWSEQ_DCN31_REG_FIELD_LIST(uint32_t)
#endif
};

13
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
View File

@ -264,18 +264,25 @@ static void set_speed(
struct dce_i2c_hw *dce_i2c_hw,
uint32_t speed)
{
uint32_t xtal_ref_div = 0;
uint32_t xtal_ref_div = 0, ref_base_div = 0;
uint32_t prescale = 0;
uint32_t i2c_ref_clock = 0;
if (speed == 0)
return;
REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
REG_GET_2(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, &ref_base_div,
XTAL_REF_DIV, &xtal_ref_div);
if (xtal_ref_div == 0)
xtal_ref_div = 2;
prescale = ((dce_i2c_hw->reference_frequency * 2) / xtal_ref_div) / speed;
if (ref_base_div == 0)
i2c_ref_clock = (dce_i2c_hw->reference_frequency * 2);
else
i2c_ref_clock = ref_base_div * 1000;
prescale = (i2c_ref_clock / xtal_ref_div) / speed;
if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
REG_UPDATE_N(SPEED, 3,

3
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
View File

@ -139,6 +139,7 @@ enum {
I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\
I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\
I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\
I2C_SF(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, mask_sh),\
I2C_SF(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, mask_sh)
#define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
@ -182,6 +183,7 @@ struct dce_i2c_shift {
uint8_t DC_I2C_INDEX;
uint8_t DC_I2C_INDEX_WRITE;
uint8_t XTAL_REF_DIV;
uint8_t MICROSECOND_TIME_BASE_DIV;
uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
uint8_t DC_I2C_REG_RW_CNTL_STATUS;
uint8_t I2C_LIGHT_SLEEP_FORCE;
@ -225,6 +227,7 @@ struct dce_i2c_mask {
uint32_t DC_I2C_INDEX;
uint32_t DC_I2C_INDEX_WRITE;
uint32_t XTAL_REF_DIV;
uint32_t MICROSECOND_TIME_BASE_DIV;
uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
uint32_t DC_I2C_REG_RW_CNTL_STATUS;
uint32_t I2C_LIGHT_SLEEP_FORCE;

4
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -48,7 +48,7 @@
#include "link_encoder.h"
#include "link_hwss.h"
#include "dc_link_dp.h"
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "dccg.h"
#endif
#include "clock_source.h"
@ -2090,7 +2090,7 @@ static void dce110_setup_audio_dto(
build_audio_output(context, pipe_ctx, &audio_output);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
/* disable audio DTBCLK DTO */

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
View File

@ -1497,8 +1497,6 @@ void dpp1_cnv_setup (
enum dc_color_space input_color_space,
struct cnv_alpha_2bit_lut *alpha_2bit_lut);
void dpp1_full_bypass(struct dpp *dpp_base);
void dpp1_dppclk_control(
struct dpp *dpp_base,
bool dppclk_div,

9
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
View File

@ -139,7 +139,6 @@ struct dcn_hubbub_registers {
uint32_t DCHVM_CLK_CTRL;
uint32_t DCHVM_RIOMMU_CTRL0;
uint32_t DCHVM_RIOMMU_STAT0;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
uint32_t DCHUBBUB_DET0_CTRL;
uint32_t DCHUBBUB_DET1_CTRL;
uint32_t DCHUBBUB_DET2_CTRL;
@ -155,7 +154,6 @@ struct dcn_hubbub_registers {
uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;
uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;
uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;
#endif
};
/* set field name */
@ -292,7 +290,7 @@ struct dcn_hubbub_registers {
type HOSTVM_POWERSTATUS; \
type RIOMMU_ACTIVE; \
type HOSTVM_PREFETCH_DONE
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#define HUBBUB_RET_REG_FIELD_LIST(type) \
type DET_DEPTH;\
type DET0_SIZE;\
@ -315,25 +313,20 @@ struct dcn_hubbub_registers {
type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;\
type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;\
type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D
#endif
struct dcn_hubbub_shift {
DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
HUBBUB_RET_REG_FIELD_LIST(uint8_t);
#endif
};
struct dcn_hubbub_mask {
DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);
HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
HUBBUB_RET_REG_FIELD_LIST(uint32_t);
#endif
};
struct dc;

15
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -3245,10 +3245,17 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
* about the actual size being incorrect, that's a limitation of
* the hardware.
*/
x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /
pipe_ctx->plane_state->dst_rect.width;
y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /
pipe_ctx->plane_state->dst_rect.height;
if (param.rotation == ROTATION_ANGLE_90 || param.rotation == ROTATION_ANGLE_270) {
x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.height /
pipe_ctx->plane_state->dst_rect.width;
y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.width /
pipe_ctx->plane_state->dst_rect.height;
} else {
x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /
pipe_ctx->plane_state->dst_rect.width;
y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /
pipe_ctx->plane_state->dst_rect.height;
}
/**
* If the cursor's source viewport is clipped then we need to

9
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
View File

@ -160,14 +160,12 @@ struct dcn10_link_enc_registers {
uint32_t PHYA_LINK_CNTL2;
uint32_t PHYB_LINK_CNTL2;
uint32_t PHYC_LINK_CNTL2;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
uint32_t DIO_LINKA_CNTL;
uint32_t DIO_LINKB_CNTL;
uint32_t DIO_LINKC_CNTL;
uint32_t DIO_LINKD_CNTL;
uint32_t DIO_LINKE_CNTL;
uint32_t DIO_LINKF_CNTL;
#endif
};
#define LE_SF(reg_name, field_name, post_fix)\
@ -467,29 +465,24 @@ struct dcn10_link_enc_registers {
type DPCS_TX_DATA_SWAP_10_BIT;\
type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\
type RDPCS_TX_CLK_EN
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#define DCN31_LINK_ENCODER_REG_FIELD_LIST(type) \
type ENC_TYPE_SEL;\
type HPO_DP_ENC_SEL;\
type HPO_HDMI_ENC_SEL
#endif
struct dcn10_link_enc_shift {
DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
#endif
};
struct dcn10_link_enc_mask {
DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
#endif
};
struct dcn10_link_encoder {

8
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
View File

@ -140,7 +140,6 @@
type PHYCSYMCLK_FORCE_EN;\
type PHYCSYMCLK_FORCE_SRC_SEL;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#define DCCG31_REG_FIELD_LIST(type) \
type PHYDSYMCLK_FORCE_EN;\
type PHYDSYMCLK_FORCE_SRC_SEL;\
@ -171,22 +170,17 @@
type DCCG_AUDIO_DTO_SEL;\
type DCCG_AUDIO_DTO0_SOURCE_SEL;\
type DENTIST_DISPCLK_CHG_MODE;
#endif
struct dccg_shift {
DCCG_REG_FIELD_LIST(uint8_t)
DCCG3_REG_FIELD_LIST(uint8_t)
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
DCCG31_REG_FIELD_LIST(uint8_t)
#endif
};
struct dccg_mask {
DCCG_REG_FIELD_LIST(uint32_t)
DCCG3_REG_FIELD_LIST(uint32_t)
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
DCCG31_REG_FIELD_LIST(uint32_t)
#endif
};
struct dccg_registers {
@ -199,7 +193,6 @@ struct dccg_registers {
uint32_t PHYASYMCLK_CLOCK_CNTL;
uint32_t PHYBSYMCLK_CLOCK_CNTL;
uint32_t PHYCSYMCLK_CLOCK_CNTL;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
uint32_t PHYDSYMCLK_CLOCK_CNTL;
uint32_t PHYESYMCLK_CLOCK_CNTL;
uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
@ -212,7 +205,6 @@ struct dccg_registers {
uint32_t SYMCLK32_SE_CNTL;
uint32_t SYMCLK32_LE_CNTL;
uint32_t DENTIST_DISPCLK_CNTL;
#endif
};
struct dcn_dccg {

2
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
View File

@ -83,7 +83,6 @@ struct dcn20_hubbub {
int num_vmid;
struct dcn20_vmid vmid[16];
unsigned int detile_buf_size;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
unsigned int crb_size_segs;
unsigned int compbuf_size_segments;
unsigned int pixel_chunk_size;
@ -91,7 +90,6 @@ struct dcn20_hubbub {
unsigned int det1_size;
unsigned int det2_size;
unsigned int det3_size;
#endif
};
void hubbub2_construct(struct dcn20_hubbub *hubbub,

10
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
View File

@ -216,32 +216,22 @@
type ROW_TTU_MODE; \
type NUM_PKRS
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
#define DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type) \
DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type);\
type HUBP_UNBOUNDED_REQ_MODE;\
type CURSOR_REQ_MODE;\
type HUBP_SOFT_RESET
#endif
struct dcn_hubp2_registers {
DCN30_HUBP_REG_COMMON_VARIABLE_LIST;
};
struct dcn_hubp2_shift {
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
#else
DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
#endif
};
struct dcn_hubp2_mask {
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
#else
DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
#endif
};
struct dcn20_hubp {

19
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@ -1270,9 +1270,7 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx
new_pipe->update_flags.bits.gamut_remap = 1;
new_pipe->update_flags.bits.scaler = 1;
new_pipe->update_flags.bits.viewport = 1;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
new_pipe->update_flags.bits.det_size = 1;
#endif
if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
new_pipe->update_flags.bits.odm = 1;
new_pipe->update_flags.bits.global_sync = 1;
@ -1307,10 +1305,9 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx
new_pipe->update_flags.bits.global_sync = 1;
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb)
new_pipe->update_flags.bits.det_size = 1;
#endif
/*
* Detect opp / tg change, only set on change, not on enable
* Assume mpcc inst = pipe index, if not this code needs to be updated
@ -1426,10 +1423,9 @@ static void dcn20_update_dchubp_dpp(
&pipe_ctx->ttu_regs,
&pipe_ctx->rq_regs,
&pipe_ctx->pipe_dlg_param);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
if (hubp->funcs->set_unbounded_requesting)
hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);
#endif
}
if (pipe_ctx->update_flags.bits.hubp_interdependent)
hubp->funcs->hubp_setup_interdependent(
@ -1609,11 +1605,9 @@ static void dcn20_program_pipe(
dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size)
dc->res_pool->hubbub->funcs->program_det_size(
dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
#endif
if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
@ -1705,12 +1699,10 @@ void dcn20_program_front_end_for_ctx(
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
struct hubbub *hubbub = dc->res_pool->hubbub;
if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
#endif
hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
}
@ -1828,11 +1820,9 @@ void dcn20_prepare_bandwidth(
&context->bw_ctx.bw.dcn.watermarks,
dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
false);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
/* decrease compbuf size */
if (hubbub->funcs->program_compbuf_size)
hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, false);
#endif
}
void dcn20_optimize_bandwidth(
@ -1851,11 +1841,9 @@ void dcn20_optimize_bandwidth(
dc->clk_mgr,
context,
true);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
/* increase compbuf size */
if (hubbub->funcs->program_compbuf_size)
hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
#endif
}
bool dcn20_update_bandwidth(
@ -2561,10 +2549,9 @@ void dcn20_fpga_init_hw(struct dc *dc)
tg->funcs->tg_init(tg);
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
if (dc->res_pool->hubbub->funcs->init_crb)
dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
#endif
}
#ifndef TRIM_FSFT
bool dcn20_optimize_timing_for_fsft(struct dc *dc,

16
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
View File

@ -3069,7 +3069,6 @@ static void dcn20_calculate_wm(
context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
{
int i;
@ -3079,7 +3078,6 @@ static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
}
return false;
}
#endif
void dcn20_calculate_dlg_params(
struct dc *dc, struct dc_state *context,
@ -3088,9 +3086,7 @@ void dcn20_calculate_dlg_params(
int vlevel)
{
int i, pipe_idx;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
int plane_count;
#endif
/* Writeback MCIF_WB arbitration parameters */
dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
@ -3105,7 +3101,7 @@ void dcn20_calculate_dlg_params(
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
!= dm_dram_clock_change_unsupported;
context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
context->bw_ctx.bw.dcn.clk.z9_support = (context->bw_ctx.dml.vba.StutterPeriod > 5000.0) ?
DCN_Z9_SUPPORT_ALLOW : DCN_Z9_SUPPORT_DISALLOW;
@ -3119,7 +3115,6 @@ void dcn20_calculate_dlg_params(
context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW;
context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
#endif
if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
@ -3131,10 +3126,9 @@ void dcn20_calculate_dlg_params(
pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
#endif
context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
@ -3148,10 +3142,8 @@ void dcn20_calculate_dlg_params(
context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
- context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
#endif
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;

2
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
View File

@ -655,10 +655,8 @@ void dcn30_init_hw(struct dc *dc)
if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
dc->res_pool->hubbub->funcs->force_pstate_change_control(
dc->res_pool->hubbub, false, false);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
if (dc->res_pool->hubbub->funcs->init_crb)
dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
#endif
}

24
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
View File

@ -164,8 +164,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = {
.min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
.num_states = 1,
.sr_exit_time_us = 15.5,
.sr_enter_plus_exit_time_us = 20,
.sr_exit_time_us = 26.5,
.sr_enter_plus_exit_time_us = 31,
.urgent_latency_us = 4.0,
.urgent_latency_pixel_data_only_us = 4.0,
.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
@ -1102,6 +1102,26 @@ static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)
loaded_ip->max_num_dpp = pool->pipe_count;
loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
dcn20_patch_bounding_box(dc, loaded_bb);
if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
struct bp_soc_bb_info bb_info = { 0 };
if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
if (bb_info.dram_clock_change_latency_100ns > 0)
dcn3_02_soc.dram_clock_change_latency_us =
bb_info.dram_clock_change_latency_100ns * 10;
if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
dcn3_02_soc.sr_enter_plus_exit_time_us =
bb_info.dram_sr_enter_exit_latency_100ns * 10;
if (bb_info.dram_sr_exit_latency_100ns > 0)
dcn3_02_soc.sr_exit_time_us =
bb_info.dram_sr_exit_latency_100ns * 10;
}
}
return true;
}

24
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
View File

@ -146,8 +146,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc = {
.min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
.num_states = 1,
.sr_exit_time_us = 15.5,
.sr_enter_plus_exit_time_us = 20,
.sr_exit_time_us = 26.5,
.sr_enter_plus_exit_time_us = 31,
.urgent_latency_us = 4.0,
.urgent_latency_pixel_data_only_us = 4.0,
.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
@ -1028,6 +1028,26 @@ static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)
loaded_ip->max_num_dpp = pool->pipe_count;
loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
dcn20_patch_bounding_box(dc, loaded_bb);
if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
struct bp_soc_bb_info bb_info = { 0 };
if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
if (bb_info.dram_clock_change_latency_100ns > 0)
dcn3_03_soc.dram_clock_change_latency_us =
bb_info.dram_clock_change_latency_100ns * 10;
if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
dcn3_03_soc.sr_enter_plus_exit_time_us =
bb_info.dram_sr_enter_exit_latency_100ns * 10;
if (bb_info.dram_sr_exit_latency_100ns > 0)
dcn3_03_soc.sr_exit_time_us =
bb_info.dram_sr_exit_latency_100ns * 10;
}
}
return true;
}

2
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
View File

@ -299,10 +299,8 @@ void dcn31_init_hw(struct dc *dc)
if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
dc->res_pool->hubbub->funcs->force_pstate_change_control(
dc->res_pool->hubbub, false, false);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
if (dc->res_pool->hubbub->funcs->init_crb)
dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
#endif
}
void dcn31_dsc_pg_control(

2
drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
View File

@ -32,11 +32,9 @@ struct cp_psp_stream_config {
uint8_t otg_inst;
uint8_t dig_be;
uint8_t dig_fe;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
uint8_t link_enc_idx;
uint8_t stream_enc_idx;
uint8_t phy_idx;
#endif
uint8_t assr_enabled;
uint8_t mst_enabled;
void *dm_stream_ctx;

6
drivers/gpu/drm/amd/display/dc/dml/Makefile
View File

@ -62,10 +62,8 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) -Wframe-larger-than=2048
CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)
ifdef CONFIG_DRM_AMD_DC_DCN3_1
CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) -Wframe-larger-than=2048
CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags)
endif
CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_rcflags)
@ -76,10 +74,8 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags)
ifdef CONFIG_DRM_AMD_DC_DCN3_1
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_rcflags)
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcflags)
endif
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags)
endif
CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags)
@ -94,10 +90,8 @@ DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_
DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
DML += dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o
ifdef CONFIG_DRM_AMD_DC_DCN3_1
DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o
endif
endif
AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))

6
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
View File

@ -23,7 +23,6 @@
*
*/
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
#include "dc.h"
#include "dc_link.h"
#include "../display_mode_lib.h"
@ -2668,6 +2667,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
(double) v->WritebackDelay[v->VoltageLevel][k]
/ (v->HTotal[k] / v->PixelClock[k]),
1));
if (v->MaxVStartupLines[k] > 1023)
v->MaxVStartupLines[k] = 1023;
#ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
@ -5064,6 +5065,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
/ (v->HTotal[k]
/ v->PixelClock[k]),
1.0));
if (v->MaximumVStartup[i][j][k] > 1023)
v->MaximumVStartup[i][j][k] = 1023;
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
}
}
@ -7505,4 +7508,3 @@ static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedReques
return (ret_val);
}
#endif /* CONFIG_DRM_AMD_DC_DCN3_1 */

5
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
View File

@ -23,8 +23,6 @@
*
*/
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
#include "../display_mode_lib.h"
#include "../display_mode_vba.h"
#include "../dml_inline_defs.h"
@ -52,7 +50,7 @@ static bool CalculateBytePerPixelAnd256BBlockSizes(
*BytePerPixelDETC = 0;
*BytePerPixelY = 4;
*BytePerPixelC = 0;
} else if (SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_16) {
} else if (SourcePixelFormat == dm_444_16) {
*BytePerPixelDETY = 2;
*BytePerPixelDETC = 0;
*BytePerPixelY = 2;
@ -1724,4 +1722,3 @@ void dml31_rq_dlg_get_dlg_reg(
dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
}
#endif

9
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
View File

@ -33,11 +33,9 @@
#include "dcn21/display_rq_dlg_calc_21.h"
#include "dcn30/display_mode_vba_30.h"
#include "dcn30/display_rq_dlg_calc_30.h"
#include "dml_logger.h"
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
#include "dcn31/display_mode_vba_31.h"
#include "dcn31/display_rq_dlg_calc_31.h"
#endif
#include "dml_logger.h"
const struct dml_funcs dml20_funcs = {
.validate = dml20_ModeSupportAndSystemConfigurationFull,
@ -66,14 +64,13 @@ const struct dml_funcs dml30_funcs = {
.rq_dlg_get_dlg_reg = dml30_rq_dlg_get_dlg_reg,
.rq_dlg_get_rq_reg = dml30_rq_dlg_get_rq_reg
};
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
const struct dml_funcs dml31_funcs = {
.validate = dml31_ModeSupportAndSystemConfigurationFull,
.recalculate = dml31_recalculate,
.rq_dlg_get_dlg_reg = dml31_rq_dlg_get_dlg_reg,
.rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg
};
#endif
void dml_init_instance(struct display_mode_lib *lib,
const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
@ -96,13 +93,11 @@ void dml_init_instance(struct display_mode_lib *lib,
case DML_PROJECT_DCN30:
lib->funcs = dml30_funcs;
break;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case DML_PROJECT_DCN31:
case DML_PROJECT_DCN31_FPGA:
lib->funcs = dml31_funcs;
break;
#endif
default:
break;
}

2
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
View File

@ -38,10 +38,8 @@ enum dml_project {
DML_PROJECT_NAVI10v2,
DML_PROJECT_DCN21,
DML_PROJECT_DCN30,
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
DML_PROJECT_DCN31,
DML_PROJECT_DCN31_FPGA,
#endif
};
struct display_mode_lib;

4
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
View File

@ -74,10 +74,8 @@ struct _vcs_dpi_soc_bounding_box_st {
unsigned int num_states;
double sr_exit_time_us;
double sr_enter_plus_exit_time_us;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
double sr_exit_z8_time_us;
double sr_enter_plus_exit_z8_time_us;
#endif
double urgent_latency_us;
double urgent_latency_pixel_data_only_us;
double urgent_latency_pixel_mixed_with_vm_data_us;
@ -213,14 +211,12 @@ struct _vcs_dpi_ip_params_st {
unsigned int is_line_buffer_bpp_fixed;
unsigned int line_buffer_fixed_bpp;
unsigned int dcc_supported;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
unsigned int config_return_buffer_size_in_kbytes;
unsigned int compressed_buffer_segment_size_in_kbytes;
unsigned int meta_fifo_size_in_kentries;
unsigned int zero_size_buffer_entries;
unsigned int compbuf_reserved_space_64b;
unsigned int compbuf_reserved_space_zs;
#endif
unsigned int IsLineBufferBppFixed;
unsigned int LineBufferFixedBpp;

12
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
View File

@ -89,12 +89,10 @@ dml_get_attr_func(wm_memory_trip, mode_lib->vba.UrgentLatency);
dml_get_attr_func(wm_writeback_urgent, mode_lib->vba.WritebackUrgentWatermark);
dml_get_attr_func(wm_stutter_exit, mode_lib->vba.StutterExitWatermark);
dml_get_attr_func(wm_stutter_enter_exit, mode_lib->vba.StutterEnterPlusExitWatermark);
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
dml_get_attr_func(wm_z8_stutter_exit, mode_lib->vba.Z8StutterExitWatermark);
dml_get_attr_func(wm_z8_stutter_enter_exit, mode_lib->vba.Z8StutterEnterPlusExitWatermark);
dml_get_attr_func(stutter_efficiency_z8, mode_lib->vba.Z8StutterEfficiency);
dml_get_attr_func(stutter_num_bursts_z8, mode_lib->vba.Z8NumberOfStutterBurstsPerFrame);
#endif
dml_get_attr_func(wm_dram_clock_change, mode_lib->vba.DRAMClockChangeWatermark);
dml_get_attr_func(wm_writeback_dram_clock_change, mode_lib->vba.WritebackDRAMClockChangeWatermark);
dml_get_attr_func(stutter_efficiency, mode_lib->vba.StutterEfficiency);
@ -163,10 +161,8 @@ dml_get_pipe_attr_func(vstartup, mode_lib->vba.VStartup);
dml_get_pipe_attr_func(vupdate_offset, mode_lib->vba.VUpdateOffsetPix);
dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix);
dml_get_pipe_attr_func(vready_offset, mode_lib->vba.VReadyOffsetPix);
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
dml_get_pipe_attr_func(vready_at_or_after_vsync, mode_lib->vba.VREADY_AT_OR_AFTER_VSYNC);
dml_get_pipe_attr_func(min_dst_y_next_start, mode_lib->vba.MIN_DST_Y_NEXT_START);
#endif
double get_total_immediate_flip_bytes(
struct display_mode_lib *mode_lib,
@ -235,7 +231,6 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
mode_lib->vba.WritebackLatency = soc->writeback_latency_us;
mode_lib->vba.SRExitTime = soc->sr_exit_time_us;
mode_lib->vba.SREnterPlusExitTime = soc->sr_enter_plus_exit_time_us;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
mode_lib->vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency = soc->pct_ideal_sdp_bw_after_urgent;
mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData = soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly = soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_only;
@ -244,7 +239,6 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
soc->max_avg_sdp_bw_use_normal_percent;
mode_lib->vba.SRExitZ8Time = soc->sr_exit_z8_time_us;
mode_lib->vba.SREnterPlusExitZ8Time = soc->sr_enter_plus_exit_z8_time_us;
#endif
mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us;
mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support ||
@ -319,7 +313,6 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib)
mode_lib->vba.MaxPSCLToLBThroughput = ip->max_pscl_lb_bw_pix_per_clk;
mode_lib->vba.ROBBufferSizeInKByte = ip->rob_buffer_size_kbytes;
mode_lib->vba.DETBufferSizeInKByte[0] = ip->det_buffer_size_kbytes;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
mode_lib->vba.ConfigReturnBufferSizeInKByte = ip->config_return_buffer_size_in_kbytes;
mode_lib->vba.CompressedBufferSegmentSizeInkByte = ip->compressed_buffer_segment_size_in_kbytes;
mode_lib->vba.MetaFIFOSizeInKEntries = ip->meta_fifo_size_in_kentries;
@ -328,7 +321,6 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib)
mode_lib->vba.COMPBUF_RESERVED_SPACE_ZS = ip->compbuf_reserved_space_zs;
mode_lib->vba.MaximumDSCBitsPerComponent = ip->maximum_dsc_bits_per_component;
mode_lib->vba.DSC422NativeSupport = ip->dsc422_native_support;
#endif
mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes;
mode_lib->vba.MetaChunkSize = ip->meta_chunk_size_kbytes;
@ -457,11 +449,9 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
mode_lib->vba.VTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps_c;
mode_lib->vba.HTotal[mode_lib->vba.NumberOfActivePlanes] = dst->htotal;
mode_lib->vba.VTotal[mode_lib->vba.NumberOfActivePlanes] = dst->vtotal;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
mode_lib->vba.VFrontPorch[mode_lib->vba.NumberOfActivePlanes] = dst->vfront_porch;
mode_lib->vba.DCCFractionOfZeroSizeRequestsLuma[mode_lib->vba.NumberOfActivePlanes] = src->dcc_fraction_of_zs_req_luma;
mode_lib->vba.DCCFractionOfZeroSizeRequestsChroma[mode_lib->vba.NumberOfActivePlanes] = src->dcc_fraction_of_zs_req_chroma;
#endif
mode_lib->vba.DCCEnable[mode_lib->vba.NumberOfActivePlanes] =
src->dcc_use_global ?
ip->dcc_supported : src->dcc && ip->dcc_supported;
@ -708,13 +698,11 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
}
}
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting;
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
if (pipes[k].pipe.src.unbounded_req_mode == 0)
mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting_disable;
}
#endif
// TODO: ODMCombineEnabled => 2 * DPPPerPlane...actually maybe not since all pipes are specified
// Do we want the dscclk to automatically be halved? Guess not since the value is specified
mode_lib->vba.SynchronizedVBlank = pipes[0].pipe.dest.synchronized_vblank_all_planes;

6
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
View File

@ -39,12 +39,10 @@ dml_get_attr_decl(wm_memory_trip);
dml_get_attr_decl(wm_writeback_urgent);
dml_get_attr_decl(wm_stutter_exit);
dml_get_attr_decl(wm_stutter_enter_exit);
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
dml_get_attr_decl(wm_z8_stutter_exit);
dml_get_attr_decl(wm_z8_stutter_enter_exit);
dml_get_attr_decl(stutter_efficiency_z8);
dml_get_attr_decl(stutter_num_bursts_z8);
#endif
dml_get_attr_decl(wm_dram_clock_change);
dml_get_attr_decl(wm_writeback_dram_clock_change);
dml_get_attr_decl(stutter_efficiency_no_vblank);
@ -108,10 +106,8 @@ dml_get_pipe_attr_decl(vstartup);
dml_get_pipe_attr_decl(vupdate_offset);
dml_get_pipe_attr_decl(vupdate_width);
dml_get_pipe_attr_decl(vready_offset);
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
dml_get_pipe_attr_decl(vready_at_or_after_vsync);
dml_get_pipe_attr_decl(min_dst_y_next_start);
#endif
double get_total_immediate_flip_bytes(
struct display_mode_lib *mode_lib,
@ -933,7 +929,6 @@ struct vba_vars_st {
bool ClampMinDCFCLK;
bool AllowDramClockChangeOneDisplayVactive;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation;
double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency;
double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData;
@ -974,7 +969,6 @@ struct vba_vars_st {
int Z8NumberOfStutterBurstsPerFrame;
unsigned int MaximumDSCBitsPerComponent;
unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
#endif
};
bool CalculateMinAndMaxPrefetchMode(

2
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
View File

@ -112,9 +112,7 @@ bool dal_hw_factory_init(
case DCN_VERSION_3_01:
case DCN_VERSION_3_02:
case DCN_VERSION_3_03:
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case DCN_VERSION_3_1:
#endif
dal_hw_factory_dcn30_init(factory);
return true;
#endif

2
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
View File

@ -107,9 +107,7 @@ bool dal_hw_translate_init(
case DCN_VERSION_3_01:
case DCN_VERSION_3_02:
case DCN_VERSION_3_03:
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case DCN_VERSION_3_1:
#endif
dal_hw_translate_dcn30_init(translate);
return true;
#endif

6
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View File

@ -338,9 +338,7 @@ union pipe_update_flags {
uint32_t scaler : 1;
uint32_t viewport : 1;
uint32_t plane_changed : 1;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
uint32_t det_size : 1;
#endif
} bits;
uint32_t raw;
};
@ -368,10 +366,8 @@ struct pipe_ctx {
struct _vcs_dpi_display_ttu_regs_st ttu_regs;
struct _vcs_dpi_display_rq_regs_st rq_regs;
struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
int det_buffer_size_kb;
bool unbounded_req;
#endif
#endif
union pipe_update_flags update_flags;
struct dwbc *dwbc;
@ -422,9 +418,7 @@ struct dcn_bw_output {
struct dc_clocks clk;
struct dcn_watermark_set watermarks;
struct dcn_bw_writeback bw_writeback;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
int compbuf_size_kb;
#endif
};
union bw_output {

2
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
View File

@ -91,9 +91,7 @@ struct clk_limit_table_entry {
unsigned int dispclk_mhz;
unsigned int dppclk_mhz;
unsigned int phyclk_mhz;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
unsigned int wck_ratio;
#endif
};
/* This table is contiguous */

6
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
View File

@ -29,7 +29,6 @@
#include "dc_types.h"
#include "hw_shared.h"
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
enum phyd32clk_clock_source {
PHYD32CLKA,
PHYD32CLKB,
@ -55,18 +54,15 @@ enum dentist_dispclk_change_mode {
DISPCLK_CHANGE_MODE_IMMEDIATE,
DISPCLK_CHANGE_MODE_RAMPING,
};
#endif
struct dccg {
struct dc_context *ctx;
const struct dccg_funcs *funcs;
int pipe_dppclk_khz[MAX_PIPES];
int ref_dppclk;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
int dtbclk_khz[MAX_PIPES];
int audio_dtbclk_khz;
int ref_dtbclk_khz;
#endif
};
struct dccg_funcs {
@ -83,7 +79,6 @@ struct dccg_funcs {
void (*otg_drop_pixel)(struct dccg *dccg,
uint32_t otg_inst);
void (*dccg_init)(struct dccg *dccg);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
void (*set_physymclk)(
struct dccg *dccg,
@ -105,7 +100,6 @@ struct dccg_funcs {
void (*set_dispclk_change_mode)(
struct dccg *dccg,
enum dentist_dispclk_change_mode change_mode);
#endif
};
#endif //__DAL_DCCG_H__

2
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
View File

@ -152,11 +152,9 @@ struct hubbub_funcs {
void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow);
void (*init_watermarks)(struct hubbub *hubbub);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte);
void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase);
void (*init_crb)(struct hubbub *hubbub);
#endif
};
struct hubbub {

14
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
View File

@ -127,13 +127,11 @@ struct link_enc_state {
};
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
enum encoder_type_select {
ENCODER_TYPE_DIG = 0,
ENCODER_TYPE_HDMI_FRL = 1,
ENCODER_TYPE_DP_128B132B = 2
};
#endif
enum encoder_type_select {
ENCODER_TYPE_DIG = 0,
ENCODER_TYPE_HDMI_FRL = 1,
ENCODER_TYPE_DP_128B132B = 2
};
struct link_encoder_funcs {
void (*read_state)(
@ -193,12 +191,10 @@ struct link_encoder_funcs {
enum signal_type (*get_dig_mode)(
struct link_encoder *enc);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
void (*set_dio_phy_mux)(
struct link_encoder *enc,
enum encoder_type_select sel,
uint32_t hpo_inst);
#endif
};
/*

2
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
View File

@ -33,10 +33,8 @@
struct dchub_init_data;
struct cstate_pstate_watermarks_st {
uint32_t cstate_exit_ns;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
uint32_t cstate_exit_z8_ns;
uint32_t cstate_enter_plus_exit_z8_ns;
#endif
uint32_t cstate_enter_plus_exit_ns;
uint32_t pstate_change_ns;
};

2
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
View File

@ -173,9 +173,7 @@ struct timing_generator_funcs {
bool (*enable_crtc)(struct timing_generator *tg);
bool (*disable_crtc)(struct timing_generator *tg);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
bool (*immediate_disable_crtc)(struct timing_generator *tg);
#endif
bool (*is_counter_moving)(struct timing_generator *tg);
void (*get_position)(struct timing_generator *tg,
struct crtc_position *position);

2
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
View File

@ -236,9 +236,7 @@ struct hw_sequencer_funcs {
const struct tg_color *solid_color,
int width, int height, int offset);
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
void (*z10_restore)(struct dc *dc);
#endif
void (*update_visual_confirm_color)(struct dc *dc,
struct pipe_ctx *pipe_ctx,

2
drivers/gpu/drm/amd/display/dc/irq/Makefile
View File

@ -117,9 +117,7 @@ IRQ_DCN3_03 = irq_service_dcn303.o
AMD_DAL_IRQ_DCN3_03 = $(addprefix $(AMDDALPATH)/dc/irq/dcn303/,$(IRQ_DCN3_03))
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN3_03)
endif
ifdef CONFIG_DRM_AMD_DC_DCN3_1
###############################################################################
# DCN 31
###############################################################################

3
drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.h
View File

@ -23,8 +23,6 @@
*
*/
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#ifndef __DAL_IRQ_SERVICE_DCN31_H__
#define __DAL_IRQ_SERVICE_DCN31_H__
@ -34,4 +32,3 @@ struct irq_service *dal_irq_service_dcn31_create(
struct irq_service_init_data *init_data);
#endif /* __DAL_IRQ_SERVICE_DCN31_H__ */
#endif /* CONFIG_DRM_AMD_DC_DCN3_1 */

8
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
View File

@ -73,9 +73,7 @@ extern "C" {
/* Forward declarations */
struct dmub_srv;
struct dmub_srv_common_regs;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
struct dmub_srv_dcn31_regs;
#endif
struct dmcub_trace_buf_entry;
@ -97,9 +95,7 @@ enum dmub_asic {
DMUB_ASIC_DCN301,
DMUB_ASIC_DCN302,
DMUB_ASIC_DCN303,
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
DMUB_ASIC_DCN31,
#endif
DMUB_ASIC_MAX,
};
@ -238,9 +234,7 @@ struct dmub_srv_hw_params {
uint32_t psp_version;
bool load_inst_const;
bool skip_panel_power_sequence;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
bool disable_z10;
#endif
};
/**
@ -400,9 +394,7 @@ struct dmub_srv {
/* private: internal use only */
const struct dmub_srv_common_regs *regs;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
const struct dmub_srv_dcn31_regs *regs_dcn31;
#endif
struct dmub_srv_base_funcs funcs;
struct dmub_srv_hw_funcs hw_funcs;

104
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
View File

@ -47,10 +47,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
#define DMUB_FW_VERSION_GIT_HASH 0x5cac099d3
#define DMUB_FW_VERSION_GIT_HASH 0xf3da2b656
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
#define DMUB_FW_VERSION_REVISION 70
#define DMUB_FW_VERSION_REVISION 71
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
@ -309,6 +309,7 @@ struct dmcub_trace_buf_entry {
* Current scratch register usage is as follows:
*
* SCRATCH0: FW Boot Status register
* SCRATCH5: LVTMA Status Register
* SCRATCH15: FW Boot Options register
*/
@ -335,6 +336,21 @@ enum dmub_fw_boot_status_bit {
DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
};
/* Register bit definition for SCRATCH5 */
union dmub_lvtma_status {
struct {
uint32_t psp_ok : 1;
uint32_t edp_on : 1;
uint32_t reserved : 30;
} bits;
uint32_t all;
};
enum dmub_lvtma_status_bit {
DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
};
/**
* union dmub_fw_boot_options - Boot option definitions for SCRATCH15
*/
@ -346,11 +362,7 @@ union dmub_fw_boot_options {
uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
uint32_t z10_disable: 1; /**< 1 to disable z10 */
#else
uint32_t reserved_unreleased: 1; /**< reserved for an unreleased feature */
#endif
uint32_t reserved : 25; /**< reserved */
} bits; /**< boot bits */
uint32_t all; /**< 32-bit access to bits */
@ -615,7 +627,6 @@ enum dmub_cmd_type {
* Command type used for OUTBOX1 notification enable
*/
DMUB_CMD__OUTBOX1_ENABLE = 71,
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
/**
* Command type used for all idle optimization commands.
*/
@ -628,7 +639,10 @@ enum dmub_cmd_type {
* Command type used for all panel control commands.
*/
DMUB_CMD__PANEL_CNTL = 74,
#endif
/**
* Command type used for EDID CEA parsing
*/
DMUB_CMD__EDID_CEA = 79,
/**
* Command type used for all VBIOS interface commands.
*/
@ -834,8 +848,6 @@ struct dmub_rb_cmd_mall {
uint8_t reserved2; /**< Reserved bits */
};
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
/**
* enum dmub_cmd_idle_opt_type - Idle optimization command type.
*/
@ -880,7 +892,7 @@ struct dmub_rb_cmd_clk_mgr_notify_clocks {
struct dmub_cmd_header header; /**< header */
struct dmub_clocks clocks; /**< clock data */
};
#endif
/**
* struct dmub_cmd_digx_encoder_control_data - Encoder control data.
*/
@ -2091,7 +2103,6 @@ struct dmub_rb_cmd_drr_update {
struct dmub_optc_state dmub_optc_state_req;
};
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
/**
* enum dmub_cmd_panel_cntl_type - Panel control command.
*/
@ -2126,7 +2137,6 @@ struct dmub_rb_cmd_panel_cntl {
struct dmub_cmd_header header; /**< header */
struct dmub_cmd_panel_cntl_data data; /**< payload */
};
#endif
/**
* Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
@ -2152,6 +2162,68 @@ struct dmub_rb_cmd_lvtma_control {
struct dmub_cmd_lvtma_control_data data;
};
/**
* Maximum number of bytes a chunk sent to DMUB for parsing
*/
#define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
/**
* Represent a chunk of CEA blocks sent to DMUB for parsing
*/
struct dmub_cmd_send_edid_cea {
uint16_t offset; /**< offset into the CEA block */
uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
uint16_t total_length; /**< total length of the CEA block */
uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
uint8_t pad[3]; /**< padding and for future expansion */
};
/**
* Result of VSDB parsing from CEA block
*/
struct dmub_cmd_edid_cea_amd_vsdb {
uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
uint8_t freesync_supported; /**< 1 if Freesync is supported */
uint16_t amd_vsdb_version; /**< AMD VSDB version */
uint16_t min_frame_rate; /**< Maximum frame rate */
uint16_t max_frame_rate; /**< Minimum frame rate */
};
/**
* Result of sending a CEA chunk
*/
struct dmub_cmd_edid_cea_ack {
uint16_t offset; /**< offset of the chunk into the CEA block */
uint8_t success; /**< 1 if this sending of chunk succeeded */
uint8_t pad; /**< padding and for future expansion */
};
/**
* Specify whether the result is an ACK/NACK or the parsing has finished
*/
enum dmub_cmd_edid_cea_reply_type {
DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
};
/**
* Definition of a DMUB_CMD__EDID_CEA command.
*/
struct dmub_rb_cmd_edid_cea {
struct dmub_cmd_header header; /**< Command header */
union dmub_cmd_edid_cea_data {
struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
struct dmub_cmd_edid_cea_output { /**< output with results */
uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
union {
struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
struct dmub_cmd_edid_cea_ack ack;
};
} output; /**< output to retrieve ACK/NACK or VSDB parsing results */
} data; /**< Command data */
};
/**
* union dmub_rb_cmd - DMUB inbox command.
*/
@ -2225,7 +2297,6 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__MALL command.
*/
struct dmub_rb_cmd_mall mall;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
/**
* Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
*/
@ -2240,7 +2311,6 @@ union dmub_rb_cmd {
* Definition of DMUB_CMD__PANEL_CNTL commands.
*/
struct dmub_rb_cmd_panel_cntl panel_cntl;
#endif
/**
* Definition of a DMUB_CMD__ABM_SET_PIPE command.
*/
@ -2290,6 +2360,10 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
*/
struct dmub_rb_cmd_lvtma_control lvtma_control;
/**
* Definition of a DMUB_CMD__EDID_CEA command.
*/
struct dmub_rb_cmd_edid_cea edid_cea;
};
/**

6
drivers/gpu/drm/amd/display/dmub/src/Makefile
View File

@ -21,12 +21,8 @@
#
DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
DMUB += dmub_dcn30.o dmub_dcn301.o
DMUB += dmub_dcn302.o
DMUB += dmub_dcn303.o
ifdef CONFIG_DRM_AMD_DC_DCN3_1
DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o
DMUB += dmub_dcn31.o
endif
AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))

4
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
View File

@ -31,9 +31,7 @@
#include "dmub_dcn301.h"
#include "dmub_dcn302.h"
#include "dmub_dcn303.h"
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
#include "dmub_dcn31.h"
#endif
#include "os_types.h"
/*
* Note: the DMUB service is standalone. No additional headers should be
@ -208,7 +206,6 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
funcs->setup_windows = dmub_dcn30_setup_windows;
}
break;
#ifdef CONFIG_DRM_AMD_DC_DCN3_1
case DMUB_ASIC_DCN31:
funcs->reset = dmub_dcn31_reset;
@ -241,7 +238,6 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
funcs->get_current_time = dmub_dcn31_get_current_time;
break;
#endif
default:
return false;

2
drivers/gpu/drm/amd/display/include/dal_asic_id.h
View File

@ -224,7 +224,6 @@ enum {
#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
#define FAMILY_YELLOW_CARP 146
#define YELLOW_CARP_A0 0x01
@ -234,7 +233,6 @@ enum {
#ifndef ASICREV_IS_YELLOW_CARP
#define ASICREV_IS_YELLOW_CARP(eChipRev) ((eChipRev >= YELLOW_CARP_A0) && (eChipRev < YELLOW_CARP_UNKNOWN))
#endif
#endif
/*

2
drivers/gpu/drm/amd/display/include/dal_types.h
View File

@ -55,9 +55,7 @@ enum dce_version {
DCN_VERSION_3_01,
DCN_VERSION_3_02,
DCN_VERSION_3_03,
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
DCN_VERSION_3_1,
#endif
DCN_VERSION_MAX
};

2
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
View File

@ -172,10 +172,8 @@ char *mod_hdcp_status_to_str(int32_t status)
return "MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE";
case MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE:
return "MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE";
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
case MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE:
return "MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE";
#endif
default:
return "MOD_HDCP_STATUS_UNKNOWN";
}

18
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
View File

@ -44,13 +44,9 @@ static void hdcp2_message_init(struct mod_hdcp *hdcp,
in->process.msg3_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
in->process.msg3_desc.msg_size = 0;
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
static enum mod_hdcp_status mod_hdcp_remove_display_from_topology_v2(
struct mod_hdcp *hdcp, uint8_t index)
#else
enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
struct mod_hdcp *hdcp, uint8_t index)
#endif
{
struct psp_context *psp = hdcp->config.psp.handle;
struct ta_dtm_shared_memory *dtm_cmd;
@ -84,7 +80,7 @@ enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
mutex_unlock(&psp->dtm_context.mutex);
return status;
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
static enum mod_hdcp_status mod_hdcp_remove_display_from_topology_v3(
struct mod_hdcp *hdcp, uint8_t index)
{
@ -136,14 +132,9 @@ enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
return status;
}
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
static enum mod_hdcp_status mod_hdcp_add_display_to_topology_v2(
struct mod_hdcp *hdcp, struct mod_hdcp_display *display)
#else
enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp,
struct mod_hdcp_display *display)
#endif
{
struct psp_context *psp = hdcp->config.psp.handle;
struct ta_dtm_shared_memory *dtm_cmd;
@ -189,7 +180,6 @@ enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp,
return status;
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
static enum mod_hdcp_status mod_hdcp_add_display_to_topology_v3(
struct mod_hdcp *hdcp, struct mod_hdcp_display *display)
{
@ -254,7 +244,7 @@ enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp,
return status;
}
#endif
enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp)
{

13
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
View File

@ -44,12 +44,8 @@ enum bgd_security_hdcp2_content_type {
enum ta_dtm_command {
TA_DTM_COMMAND__UNUSED_1 = 1,
TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2,
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE,
TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3
#else
TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE
#endif
};
/* DTM related enumerations */
@ -91,7 +87,6 @@ struct ta_dtm_topology_update_input_v2 {
uint32_t max_hdcp_supported_version;
};
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
/* For security reason/HW may change value, these encoder type enum values are not HW register values */
/* Security code will check real HW register values and these SW enum values */
enum ta_dtm_encoder_type {
@ -117,7 +112,7 @@ struct ta_dtm_topology_update_input_v3 {
uint32_t phy_id;
uint32_t link_hdcp_cap;
};
#endif
struct ta_dtm_topology_assr_enable {
uint32_t display_topology_dig_be_index;
};
@ -131,9 +126,7 @@ struct ta_dtm_topology_assr_enable {
union ta_dtm_cmd_input {
struct ta_dtm_topology_update_input_v2 topology_update_v2;
struct ta_dtm_topology_assr_enable topology_assr_enable;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
struct ta_dtm_topology_update_input_v3 topology_update_v3;
#endif
};
union ta_dtm_cmd_output {
@ -313,10 +306,8 @@ enum ta_hdcp2_version {
TA_HDCP2_VERSION_UNKNOWN = 0,
TA_HDCP2_VERSION_2_0 = 20,
TA_HDCP2_VERSION_2_1 = 21,
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
TA_HDCP2_VERSION_2_2 = 22,
TA_HDCP2_VERSION_2_3 = 23,
#endif
TA_HDCP2_VERSION_2_2 = 22
};
/* input/output structures for HDCP commands */

10
drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
View File

@ -97,9 +97,7 @@ enum mod_hdcp_status {
MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST,
MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE,
MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE,
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE,
#endif
};
struct mod_hdcp_displayport {
@ -123,13 +121,11 @@ enum mod_hdcp_display_state {
MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED
};
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
struct mod_hdcp_psp_caps {
uint8_t dtm_v3_supported;
uint8_t opm_state_query_supported;
};
#endif
enum mod_hdcp_display_disable_option {
MOD_HDCP_DISPLAY_NOT_DISABLE = 0,
MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION,
@ -162,9 +158,7 @@ struct mod_hdcp_ddc {
struct mod_hdcp_psp {
void *handle;
void *funcs;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
struct mod_hdcp_psp_caps caps;
#endif
};
struct mod_hdcp_display_adjustment {
@ -240,9 +234,7 @@ struct mod_hdcp_display {
uint8_t index;
uint8_t controller;
uint8_t dig_fe;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
uint8_t stream_enc_idx;
#endif
union {
uint8_t vc_id;
};
@ -255,11 +247,9 @@ struct mod_hdcp_link {
enum mod_hdcp_operation_mode mode;
uint8_t dig_be;
uint8_t ddc_line;
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
uint8_t link_enc_idx;
uint8_t phy_idx;
uint8_t hdcp_supported_informational;
#endif
union {
struct mod_hdcp_displayport dp;
struct mod_hdcp_hdmi hdmi;

27
drivers/gpu/drm/amd/pm/amdgpu_pm.c
View File

@ -411,7 +411,8 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
struct amdgpu_device *adev = drm_to_adev(ddev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
struct pp_states_info data;
int i, buf_len, ret;
uint32_t i;
int buf_len, ret;
if (amdgpu_in_reset(adev))
return -EPERM;
@ -433,9 +434,9 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
for (i = 0; i < data.nums; i++)
buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
(data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
(data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
(data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
@ -923,7 +924,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf+size);
} else {
size = snprintf(buf, PAGE_SIZE, "\n");
size = sysfs_emit(buf, "\n");
}
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@ -1009,7 +1010,7 @@ static ssize_t amdgpu_get_pp_features(struct device *dev,
if (adev->powerplay.pp_funcs->get_ppfeature_status)
size = amdgpu_dpm_get_ppfeature_status(adev, buf);
else
size = snprintf(buf, PAGE_SIZE, "\n");
size = sysfs_emit(buf, "\n");
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@ -1070,7 +1071,7 @@ static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
if (adev->powerplay.pp_funcs->print_clock_levels)
size = amdgpu_dpm_print_clock_levels(adev, type, buf);
else
size = snprintf(buf, PAGE_SIZE, "\n");
size = sysfs_emit(buf, "\n");
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@ -1469,7 +1470,7 @@ static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
if (adev->powerplay.pp_funcs->get_power_profile_mode)
size = amdgpu_dpm_get_power_profile_mode(adev, buf);
else
size = snprintf(buf, PAGE_SIZE, "\n");
size = sysfs_emit(buf, "\n");
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@ -2931,9 +2932,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
r = -ENODATA;
if (!r)
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
size = sysfs_emit(buf, "%u\n", limit * 1000000);
else
size = snprintf(buf, PAGE_SIZE, "\n");
size = sysfs_emit(buf, "\n");
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@ -2971,9 +2972,9 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
r = -ENODATA;
if (!r)
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
size = sysfs_emit(buf, "%u\n", limit * 1000000);
else
size = snprintf(buf, PAGE_SIZE, "\n");
size = sysfs_emit(buf, "\n");
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@ -3011,9 +3012,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
r = -ENODATA;
if (!r)
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
size = sysfs_emit(buf, "%u\n", limit * 1000000);
else
size = snprintf(buf, PAGE_SIZE, "\n");
size = sysfs_emit(buf, "\n");
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);

6
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
View File

@ -1232,6 +1232,12 @@ struct pptable_funcs {
*/
int (*wait_for_event)(struct smu_context *smu,
enum smu_event_type event, uint64_t event_arg);
/**
* @sned_hbm_bad_pages_num: message SMU to update bad page number
* of SMUBUS table.
*/
int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);
};
typedef enum {

8
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
View File

@ -80,10 +80,10 @@ static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 0),
MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 0),
MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0),
MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0),
MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),

15
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
View File

@ -1923,6 +1923,20 @@ static int aldebaran_set_mp1_state(struct smu_context *smu,
}
}
static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
uint32_t size)
{
int ret = 0;
/* message SMU to update the bad page number on SMUBUS */
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
if (ret)
dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
__func__);
return ret;
}
static const struct pptable_funcs aldebaran_ppt_funcs = {
/* init dpm */
.get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
@ -1985,6 +1999,7 @@ static const struct pptable_funcs aldebaran_ppt_funcs = {
.wait_for_event = smu_v13_0_wait_for_event,
.i2c_init = aldebaran_i2c_control_init,
.i2c_fini = aldebaran_i2c_control_fini,
.send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
};
void aldebaran_set_ppt_funcs(struct smu_context *smu)

4
drivers/gpu/drm/radeon/cik.c
View File

@ -8584,9 +8584,7 @@ int cik_init(struct radeon_device *rdev)
radeon_get_clock_info(rdev->ddev);
/* Fence driver */
r = radeon_fence_driver_init(rdev);
if (r)
return r;
radeon_fence_driver_init(rdev);
/* initialize memory controller */
r = cik_mc_init(rdev);

4
drivers/gpu/drm/radeon/evergreen.c
View File

@ -5208,9 +5208,7 @@ int evergreen_init(struct radeon_device *rdev)
/* Initialize clocks */
radeon_get_clock_info(rdev->ddev);
/* Fence driver */
r = radeon_fence_driver_init(rdev);
if (r)
return r;
radeon_fence_driver_init(rdev);
/* initialize AGP */
if (rdev->flags & RADEON_IS_AGP) {
r = radeon_agp_init(rdev);

4
drivers/gpu/drm/radeon/ni.c
View File

@ -2375,9 +2375,7 @@ int cayman_init(struct radeon_device *rdev)
/* Initialize clocks */
radeon_get_clock_info(rdev->ddev);
/* Fence driver */
r = radeon_fence_driver_init(rdev);
if (r)
return r;
radeon_fence_driver_init(rdev);
/* initialize memory controller */
r = evergreen_mc_init(rdev);
if (r)

4
drivers/gpu/drm/radeon/r100.c
View File

@ -4056,9 +4056,7 @@ int r100_init(struct radeon_device *rdev)
/* initialize VRAM */
r100_mc_init(rdev);
/* Fence driver */
r = radeon_fence_driver_init(rdev);
if (r)
return r;
radeon_fence_driver_init(rdev);
/* Memory manager */
r = radeon_bo_init(rdev);
if (r)

4
drivers/gpu/drm/radeon/r300.c
View File

@ -1549,9 +1549,7 @@ int r300_init(struct radeon_device *rdev)
/* initialize memory controller */
r300_mc_init(rdev);
/* Fence driver */
r = radeon_fence_driver_init(rdev);
if (r)
return r;
radeon_fence_driver_init(rdev);
/* Memory manager */
r = radeon_bo_init(rdev);
if (r)

5
drivers/gpu/drm/radeon/r420.c
View File

@ -425,10 +425,7 @@ int r420_init(struct radeon_device *rdev)
r300_mc_init(rdev);
r420_debugfs(rdev);
/* Fence driver */
r = radeon_fence_driver_init(rdev);
if (r) {
return r;
}
radeon_fence_driver_init(rdev);
/* Memory manager */
r = radeon_bo_init(rdev);
if (r) {

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