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iwlwifi: move tx queue related code to separate file
Multiple iwlagn based devices shared the same tansmit queue functions. Move tx queue related code from iwl-5000.c to iwl-agn-tx.c file. Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
This commit is contained in:
parent
7dc77dba6a
commit
b305a08058
@ -10,7 +10,7 @@ CFLAGS_iwl-devtrace.o := -I$(src)
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# AGN
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obj-$(CONFIG_IWLAGN) += iwlagn.o
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iwlagn-objs := iwl-agn.o iwl-agn-rs.o iwl-agn-led.o iwl-agn-ict.o
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iwlagn-objs += iwl-agn-ucode.o iwl-agn-hcmd.o
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iwlagn-objs += iwl-agn-ucode.o iwl-agn-hcmd.o iwl-agn-tx.o
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iwlagn-$(CONFIG_IWL4965) += iwl-4965.o
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iwlagn-$(CONFIG_IWL5000) += iwl-5000.o
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@ -162,11 +162,11 @@ static int iwl1000_hw_set_hw_params(struct iwl_priv *priv)
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static struct iwl_lib_ops iwl1000_lib = {
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.set_hw_params = iwl1000_hw_set_hw_params,
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.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
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.txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
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.txq_set_sched = iwl5000_txq_set_sched,
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.txq_agg_enable = iwl5000_txq_agg_enable,
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.txq_agg_disable = iwl5000_txq_agg_disable,
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.txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
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.txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
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.txq_set_sched = iwlagn_txq_set_sched,
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.txq_agg_enable = iwlagn_txq_agg_enable,
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.txq_agg_disable = iwlagn_txq_agg_disable,
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.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
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.txq_free_tfd = iwl_hw_txq_free_tfd,
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.txq_init = iwl_hw_tx_queue_init,
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@ -358,34 +358,6 @@ restart:
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queue_work(priv->workqueue, &priv->restart);
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}
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static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
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int txq_id, u32 index)
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{
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iwl_write_direct32(priv, HBUS_TARG_WRPTR,
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(index & 0xff) | (txq_id << 8));
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iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
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}
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static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
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struct iwl_tx_queue *txq,
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int tx_fifo_id, int scd_retry)
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{
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int txq_id = txq->q.id;
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int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
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iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
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(active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
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(tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
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(1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
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IWL50_SCD_QUEUE_STTS_REG_MSK);
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txq->sched_retry = scd_retry;
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IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
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active ? "Activate" : "Deactivate",
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scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
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}
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int iwl5000_alive_notify(struct iwl_priv *priv)
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{
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u32 a;
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@ -448,7 +420,7 @@ int iwl5000_alive_notify(struct iwl_priv *priv)
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/* Activate all Tx DMA/FIFO channels */
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priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
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iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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iwlagn_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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/* make sure all queue are not stopped */
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memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
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@ -468,7 +440,7 @@ int iwl5000_alive_notify(struct iwl_priv *priv)
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if (ac == IWL_TX_FIFO_UNUSED)
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continue;
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iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
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iwlagn_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
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}
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spin_unlock_irqrestore(&priv->lock, flags);
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@ -539,207 +511,6 @@ int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
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return 0;
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}
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/**
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* iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
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*/
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void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
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struct iwl_tx_queue *txq,
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u16 byte_cnt)
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{
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struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
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int write_ptr = txq->q.write_ptr;
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int txq_id = txq->q.id;
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u8 sec_ctl = 0;
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u8 sta_id = 0;
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u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
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__le16 bc_ent;
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WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
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if (txq_id != IWL_CMD_QUEUE_NUM) {
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sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
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sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
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switch (sec_ctl & TX_CMD_SEC_MSK) {
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case TX_CMD_SEC_CCM:
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len += CCMP_MIC_LEN;
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break;
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case TX_CMD_SEC_TKIP:
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len += TKIP_ICV_LEN;
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break;
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case TX_CMD_SEC_WEP:
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len += WEP_IV_LEN + WEP_ICV_LEN;
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break;
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}
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}
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bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
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scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
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if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
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scd_bc_tbl[txq_id].
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tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
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}
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void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
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struct iwl_tx_queue *txq)
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{
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struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
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int txq_id = txq->q.id;
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int read_ptr = txq->q.read_ptr;
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u8 sta_id = 0;
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__le16 bc_ent;
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WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
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if (txq_id != IWL_CMD_QUEUE_NUM)
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sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
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bc_ent = cpu_to_le16(1 | (sta_id << 12));
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scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
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if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
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scd_bc_tbl[txq_id].
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tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
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}
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static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
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u16 txq_id)
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{
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u32 tbl_dw_addr;
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u32 tbl_dw;
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u16 scd_q2ratid;
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scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
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tbl_dw_addr = priv->scd_base_addr +
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IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
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tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
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if (txq_id & 0x1)
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tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
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else
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tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
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iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
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return 0;
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}
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static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
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{
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/* Simply stop the queue, but don't change any configuration;
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* the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
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iwl_write_prph(priv,
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IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
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(0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
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(1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
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}
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int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
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int tx_fifo, int sta_id, int tid, u16 ssn_idx)
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{
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unsigned long flags;
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u16 ra_tid;
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if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
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(IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
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<= txq_id)) {
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IWL_WARN(priv,
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"queue number out of range: %d, must be %d to %d\n",
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txq_id, IWL50_FIRST_AMPDU_QUEUE,
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IWL50_FIRST_AMPDU_QUEUE +
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priv->cfg->num_of_ampdu_queues - 1);
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return -EINVAL;
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}
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ra_tid = BUILD_RAxTID(sta_id, tid);
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/* Modify device's station table to Tx this TID */
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iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
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spin_lock_irqsave(&priv->lock, flags);
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/* Stop this Tx queue before configuring it */
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iwl5000_tx_queue_stop_scheduler(priv, txq_id);
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/* Map receiver-address / traffic-ID to this queue */
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iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
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/* Set this queue as a chain-building queue */
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iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
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/* enable aggregations for the queue */
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iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
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/* Place first TFD at index corresponding to start sequence number.
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* Assumes that ssn_idx is valid (!= 0xFFF) */
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priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
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priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
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iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
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/* Set up Tx window size and frame limit for this queue */
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iwl_write_targ_mem(priv, priv->scd_base_addr +
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IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
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sizeof(u32),
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((SCD_WIN_SIZE <<
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IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
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IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
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((SCD_FRAME_LIMIT <<
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IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
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IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
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iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
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/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
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iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
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u16 ssn_idx, u8 tx_fifo)
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{
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if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
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(IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
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<= txq_id)) {
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IWL_ERR(priv,
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"queue number out of range: %d, must be %d to %d\n",
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txq_id, IWL50_FIRST_AMPDU_QUEUE,
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IWL50_FIRST_AMPDU_QUEUE +
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priv->cfg->num_of_ampdu_queues - 1);
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return -EINVAL;
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}
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iwl5000_tx_queue_stop_scheduler(priv, txq_id);
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iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
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priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
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priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
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/* supposes that ssn_idx is valid (!= 0xFFF) */
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iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
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iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
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iwl_txq_ctx_deactivate(priv, txq_id);
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iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
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return 0;
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}
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/*
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* Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
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* must be called under priv->lock and mac access
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*/
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void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
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{
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iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
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}
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static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
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{
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return le32_to_cpup((__le32 *)&tx_resp->status +
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@ -1063,11 +834,11 @@ static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
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struct iwl_lib_ops iwl5000_lib = {
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.set_hw_params = iwl5000_hw_set_hw_params,
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.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
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.txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
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.txq_set_sched = iwl5000_txq_set_sched,
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.txq_agg_enable = iwl5000_txq_agg_enable,
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.txq_agg_disable = iwl5000_txq_agg_disable,
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.txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
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.txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
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.txq_set_sched = iwlagn_txq_set_sched,
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.txq_agg_enable = iwlagn_txq_agg_enable,
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.txq_agg_disable = iwlagn_txq_agg_disable,
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.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
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.txq_free_tfd = iwl_hw_txq_free_tfd,
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.txq_init = iwl_hw_tx_queue_init,
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@ -1121,11 +892,11 @@ struct iwl_lib_ops iwl5000_lib = {
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static struct iwl_lib_ops iwl5150_lib = {
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.set_hw_params = iwl5000_hw_set_hw_params,
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.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
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.txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
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.txq_set_sched = iwl5000_txq_set_sched,
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.txq_agg_enable = iwl5000_txq_agg_enable,
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.txq_agg_disable = iwl5000_txq_agg_disable,
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.txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
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.txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
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.txq_set_sched = iwlagn_txq_set_sched,
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.txq_agg_enable = iwlagn_txq_agg_enable,
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.txq_agg_disable = iwlagn_txq_agg_disable,
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.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
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.txq_free_tfd = iwl_hw_txq_free_tfd,
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.txq_init = iwl_hw_tx_queue_init,
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@ -226,11 +226,11 @@ static int iwl6000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
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static struct iwl_lib_ops iwl6000_lib = {
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.set_hw_params = iwl6000_hw_set_hw_params,
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.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
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.txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
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.txq_set_sched = iwl5000_txq_set_sched,
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.txq_agg_enable = iwl5000_txq_agg_enable,
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.txq_agg_disable = iwl5000_txq_agg_disable,
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.txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
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.txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
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.txq_set_sched = iwlagn_txq_set_sched,
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.txq_agg_enable = iwlagn_txq_agg_enable,
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.txq_agg_disable = iwlagn_txq_agg_disable,
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.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
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.txq_free_tfd = iwl_hw_txq_free_tfd,
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.txq_init = iwl_hw_tx_queue_init,
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@ -293,11 +293,11 @@ static const struct iwl_ops iwl6000_ops = {
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static struct iwl_lib_ops iwl6050_lib = {
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.set_hw_params = iwl6000_hw_set_hw_params,
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.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
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.txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
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.txq_set_sched = iwl5000_txq_set_sched,
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.txq_agg_enable = iwl5000_txq_agg_enable,
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.txq_agg_disable = iwl5000_txq_agg_disable,
|
||||
.txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
|
||||
.txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
|
||||
.txq_set_sched = iwlagn_txq_set_sched,
|
||||
.txq_agg_enable = iwlagn_txq_agg_enable,
|
||||
.txq_agg_disable = iwlagn_txq_agg_disable,
|
||||
.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
|
||||
.txq_free_tfd = iwl_hw_txq_free_tfd,
|
||||
.txq_init = iwl_hw_tx_queue_init,
|
||||
|
268
drivers/net/wireless/iwlwifi/iwl-agn-tx.c
Normal file
268
drivers/net/wireless/iwlwifi/iwl-agn-tx.c
Normal file
@ -0,0 +1,268 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
|
||||
* USA
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.GPL.
|
||||
*
|
||||
* Contact Information:
|
||||
* Intel Linux Wireless <ilw@linux.intel.com>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/sched.h>
|
||||
|
||||
#include "iwl-dev.h"
|
||||
#include "iwl-core.h"
|
||||
#include "iwl-sta.h"
|
||||
#include "iwl-io.h"
|
||||
#include "iwl-5000-hw.h"
|
||||
|
||||
/**
|
||||
* iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
|
||||
*/
|
||||
void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
|
||||
struct iwl_tx_queue *txq,
|
||||
u16 byte_cnt)
|
||||
{
|
||||
struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
|
||||
int write_ptr = txq->q.write_ptr;
|
||||
int txq_id = txq->q.id;
|
||||
u8 sec_ctl = 0;
|
||||
u8 sta_id = 0;
|
||||
u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
|
||||
__le16 bc_ent;
|
||||
|
||||
WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
|
||||
|
||||
if (txq_id != IWL_CMD_QUEUE_NUM) {
|
||||
sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
|
||||
sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
|
||||
|
||||
switch (sec_ctl & TX_CMD_SEC_MSK) {
|
||||
case TX_CMD_SEC_CCM:
|
||||
len += CCMP_MIC_LEN;
|
||||
break;
|
||||
case TX_CMD_SEC_TKIP:
|
||||
len += TKIP_ICV_LEN;
|
||||
break;
|
||||
case TX_CMD_SEC_WEP:
|
||||
len += WEP_IV_LEN + WEP_ICV_LEN;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
|
||||
|
||||
scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
|
||||
|
||||
if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
|
||||
scd_bc_tbl[txq_id].
|
||||
tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
|
||||
}
|
||||
|
||||
void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
|
||||
struct iwl_tx_queue *txq)
|
||||
{
|
||||
struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
|
||||
int txq_id = txq->q.id;
|
||||
int read_ptr = txq->q.read_ptr;
|
||||
u8 sta_id = 0;
|
||||
__le16 bc_ent;
|
||||
|
||||
WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
|
||||
|
||||
if (txq_id != IWL_CMD_QUEUE_NUM)
|
||||
sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
|
||||
|
||||
bc_ent = cpu_to_le16(1 | (sta_id << 12));
|
||||
scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
|
||||
|
||||
if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
|
||||
scd_bc_tbl[txq_id].
|
||||
tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
|
||||
}
|
||||
|
||||
static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
|
||||
u16 txq_id)
|
||||
{
|
||||
u32 tbl_dw_addr;
|
||||
u32 tbl_dw;
|
||||
u16 scd_q2ratid;
|
||||
|
||||
scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
|
||||
|
||||
tbl_dw_addr = priv->scd_base_addr +
|
||||
IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
|
||||
|
||||
tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
|
||||
|
||||
if (txq_id & 0x1)
|
||||
tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
|
||||
else
|
||||
tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
|
||||
|
||||
iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
|
||||
{
|
||||
/* Simply stop the queue, but don't change any configuration;
|
||||
* the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
|
||||
iwl_write_prph(priv,
|
||||
IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
|
||||
(0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
|
||||
(1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
|
||||
}
|
||||
|
||||
void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
|
||||
int txq_id, u32 index)
|
||||
{
|
||||
iwl_write_direct32(priv, HBUS_TARG_WRPTR,
|
||||
(index & 0xff) | (txq_id << 8));
|
||||
iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
|
||||
}
|
||||
|
||||
void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
|
||||
struct iwl_tx_queue *txq,
|
||||
int tx_fifo_id, int scd_retry)
|
||||
{
|
||||
int txq_id = txq->q.id;
|
||||
int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
|
||||
|
||||
iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
|
||||
(active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
|
||||
(tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
|
||||
(1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
|
||||
IWL50_SCD_QUEUE_STTS_REG_MSK);
|
||||
|
||||
txq->sched_retry = scd_retry;
|
||||
|
||||
IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
|
||||
active ? "Activate" : "Deactivate",
|
||||
scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
|
||||
}
|
||||
|
||||
int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id,
|
||||
int tx_fifo, int sta_id, int tid, u16 ssn_idx)
|
||||
{
|
||||
unsigned long flags;
|
||||
u16 ra_tid;
|
||||
|
||||
if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
|
||||
(IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
|
||||
<= txq_id)) {
|
||||
IWL_WARN(priv,
|
||||
"queue number out of range: %d, must be %d to %d\n",
|
||||
txq_id, IWL50_FIRST_AMPDU_QUEUE,
|
||||
IWL50_FIRST_AMPDU_QUEUE +
|
||||
priv->cfg->num_of_ampdu_queues - 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ra_tid = BUILD_RAxTID(sta_id, tid);
|
||||
|
||||
/* Modify device's station table to Tx this TID */
|
||||
iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
|
||||
/* Stop this Tx queue before configuring it */
|
||||
iwlagn_tx_queue_stop_scheduler(priv, txq_id);
|
||||
|
||||
/* Map receiver-address / traffic-ID to this queue */
|
||||
iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
|
||||
|
||||
/* Set this queue as a chain-building queue */
|
||||
iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
|
||||
|
||||
/* enable aggregations for the queue */
|
||||
iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
|
||||
|
||||
/* Place first TFD at index corresponding to start sequence number.
|
||||
* Assumes that ssn_idx is valid (!= 0xFFF) */
|
||||
priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
|
||||
priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
|
||||
iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
|
||||
|
||||
/* Set up Tx window size and frame limit for this queue */
|
||||
iwl_write_targ_mem(priv, priv->scd_base_addr +
|
||||
IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
|
||||
sizeof(u32),
|
||||
((SCD_WIN_SIZE <<
|
||||
IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
|
||||
IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
|
||||
((SCD_FRAME_LIMIT <<
|
||||
IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
|
||||
IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
|
||||
|
||||
iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
|
||||
|
||||
/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
|
||||
iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
|
||||
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
|
||||
u16 ssn_idx, u8 tx_fifo)
|
||||
{
|
||||
if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
|
||||
(IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
|
||||
<= txq_id)) {
|
||||
IWL_ERR(priv,
|
||||
"queue number out of range: %d, must be %d to %d\n",
|
||||
txq_id, IWL50_FIRST_AMPDU_QUEUE,
|
||||
IWL50_FIRST_AMPDU_QUEUE +
|
||||
priv->cfg->num_of_ampdu_queues - 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
iwlagn_tx_queue_stop_scheduler(priv, txq_id);
|
||||
|
||||
iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
|
||||
|
||||
priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
|
||||
priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
|
||||
/* supposes that ssn_idx is valid (!= 0xFFF) */
|
||||
iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
|
||||
|
||||
iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
|
||||
iwl_txq_ctx_deactivate(priv, txq_id);
|
||||
iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
|
||||
* must be called under priv->lock and mac access
|
||||
*/
|
||||
void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask)
|
||||
{
|
||||
iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
|
||||
}
|
@ -80,4 +80,21 @@ bool iwl_good_ack_health(struct iwl_priv *priv,
|
||||
/* uCode */
|
||||
int iwlagn_load_ucode(struct iwl_priv *priv);
|
||||
|
||||
/* tx queue */
|
||||
void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
|
||||
int txq_id, u32 index);
|
||||
void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
|
||||
struct iwl_tx_queue *txq,
|
||||
int tx_fifo_id, int scd_retry);
|
||||
void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
|
||||
struct iwl_tx_queue *txq,
|
||||
u16 byte_cnt);
|
||||
void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
|
||||
struct iwl_tx_queue *txq);
|
||||
int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id,
|
||||
int tx_fifo, int sta_id, int tid, u16 ssn_idx);
|
||||
int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
|
||||
u16 ssn_idx, u8 tx_fifo);
|
||||
void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask);
|
||||
|
||||
#endif /* __iwl_agn_h__ */
|
||||
|
Loading…
Reference in New Issue
Block a user