mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 21:54:06 +08:00
drm/nouveau/dmaobj: switch to a slightly saner design
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
bc98540b7b
commit
b2c817031b
@ -30,22 +30,43 @@
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#include "priv.h"
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static int
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nouveau_dmaobj_ctor(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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nvkm_dmaobj_bind(struct nouveau_dmaobj *dmaobj, struct nouveau_object *parent,
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struct nouveau_gpuobj **pgpuobj)
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{
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struct nouveau_dmaeng *dmaeng = (void *)engine;
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const struct nvkm_dmaeng_impl *impl = (void *)
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nv_oclass(nv_object(dmaobj)->engine);
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int ret = 0;
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if (nv_object(dmaobj) == parent) { /* ctor bind */
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if (nv_mclass(parent->parent) == NV_DEVICE) {
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/* delayed, or no, binding */
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return 0;
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}
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ret = impl->bind(dmaobj, parent, pgpuobj);
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if (ret == 0)
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nouveau_object_ref(NULL, &parent);
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return ret;
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}
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return impl->bind(dmaobj, parent, pgpuobj);
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}
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int
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nvkm_dmaobj_create_(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void **pdata, u32 *psize,
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int length, void **pobject)
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{
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struct nv_dma_class *args = *pdata;
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struct nouveau_dmaobj *dmaobj;
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struct nouveau_gpuobj *gpuobj;
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struct nv_dma_class *args = data;
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int ret;
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if (size < sizeof(*args))
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if (*psize < sizeof(*args))
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return -EINVAL;
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*pdata = &args->conf0;
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ret = nouveau_object_create(parent, engine, oclass, 0, &dmaobj);
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*pobject = nv_object(dmaobj);
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ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject);
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dmaobj = *pobject;
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if (ret)
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return ret;
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@ -87,39 +108,9 @@ nouveau_dmaobj_ctor(struct nouveau_object *parent,
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dmaobj->start = args->start;
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dmaobj->limit = args->limit;
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dmaobj->conf0 = args->conf0;
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switch (nv_mclass(parent)) {
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case NV_DEVICE:
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/* delayed, or no, binding */
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break;
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default:
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ret = dmaeng->bind(dmaeng, *pobject, dmaobj, &gpuobj);
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if (ret == 0) {
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nouveau_object_ref(NULL, pobject);
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*pobject = nv_object(gpuobj);
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}
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break;
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}
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return ret;
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}
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static struct nouveau_ofuncs
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nouveau_dmaobj_ofuncs = {
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.ctor = nouveau_dmaobj_ctor,
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.dtor = nouveau_object_destroy,
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.init = nouveau_object_init,
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.fini = nouveau_object_fini,
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};
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static struct nouveau_oclass
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nouveau_dmaobj_sclass[] = {
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{ NV_DMA_FROM_MEMORY_CLASS, &nouveau_dmaobj_ofuncs },
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{ NV_DMA_TO_MEMORY_CLASS, &nouveau_dmaobj_ofuncs },
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{ NV_DMA_IN_MEMORY_CLASS, &nouveau_dmaobj_ofuncs },
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{}
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};
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int
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_nvkm_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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@ -135,7 +126,7 @@ _nvkm_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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if (ret)
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return ret;
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nv_engine(dmaeng)->sclass = nouveau_dmaobj_sclass;
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dmaeng->bind = impl->bind;
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nv_engine(dmaeng)->sclass = impl->sclass;
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dmaeng->bind = nvkm_dmaobj_bind;
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return 0;
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}
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@ -30,19 +30,23 @@
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#include "priv.h"
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struct nv04_dmaobj_priv {
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struct nouveau_dmaobj base;
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bool clone;
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u32 flags0;
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u32 flags2;
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};
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static int
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nv04_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
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nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
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struct nouveau_object *parent,
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struct nouveau_dmaobj *dmaobj,
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struct nouveau_gpuobj **pgpuobj)
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{
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struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaeng);
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struct nv04_dmaobj_priv *priv = (void *)dmaobj;
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struct nouveau_gpuobj *gpuobj;
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u32 flags0 = nv_mclass(dmaobj);
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u32 flags2 = 0x00000000;
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u64 offset = dmaobj->start & 0xfffff000;
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u64 adjust = dmaobj->start & 0x00000fff;
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u32 length = dmaobj->limit - dmaobj->start;
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u64 offset = priv->base.start & 0xfffff000;
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u64 adjust = priv->base.start & 0x00000fff;
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u32 length = priv->base.limit - priv->base.start;
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int ret;
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if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
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@ -57,58 +61,96 @@ nv04_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
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}
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}
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if (dmaobj->target == NV_MEM_TARGET_VM) {
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if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass) {
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struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0];
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if (!dmaobj->start)
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return nouveau_gpuobj_dup(parent, pgt, pgpuobj);
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offset = nv_ro32(pgt, 8 + (offset >> 10));
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offset &= 0xfffff000;
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}
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dmaobj->target = NV_MEM_TARGET_PCI;
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dmaobj->access = NV_MEM_ACCESS_RW;
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}
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switch (dmaobj->target) {
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case NV_MEM_TARGET_VRAM:
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flags0 |= 0x00003000;
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break;
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case NV_MEM_TARGET_PCI:
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flags0 |= 0x00023000;
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break;
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case NV_MEM_TARGET_PCI_NOSNOOP:
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flags0 |= 0x00033000;
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break;
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default:
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return -EINVAL;
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}
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switch (dmaobj->access) {
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case NV_MEM_ACCESS_RO:
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flags0 |= 0x00004000;
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break;
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case NV_MEM_ACCESS_WO:
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flags0 |= 0x00008000;
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case NV_MEM_ACCESS_RW:
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flags2 |= 0x00000002;
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break;
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default:
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return -EINVAL;
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if (priv->clone) {
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struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaobj);
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struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0];
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if (!dmaobj->start)
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return nouveau_gpuobj_dup(parent, pgt, pgpuobj);
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offset = nv_ro32(pgt, 8 + (offset >> 10));
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offset &= 0xfffff000;
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}
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ret = nouveau_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj);
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*pgpuobj = gpuobj;
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if (ret == 0) {
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nv_wo32(*pgpuobj, 0x00, flags0 | (adjust << 20));
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nv_wo32(*pgpuobj, 0x00, priv->flags0 | (adjust << 20));
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nv_wo32(*pgpuobj, 0x04, length);
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nv_wo32(*pgpuobj, 0x08, flags2 | offset);
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nv_wo32(*pgpuobj, 0x0c, flags2 | offset);
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nv_wo32(*pgpuobj, 0x08, priv->flags2 | offset);
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nv_wo32(*pgpuobj, 0x0c, priv->flags2 | offset);
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}
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return ret;
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}
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static int
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nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nouveau_dmaeng *dmaeng = (void *)engine;
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struct nv04_vmmgr_priv *vmm = nv04_vmmgr(engine);
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struct nv04_dmaobj_priv *priv;
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int ret;
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ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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if (priv->base.target == NV_MEM_TARGET_VM) {
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if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass)
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priv->clone = true;
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priv->base.target = NV_MEM_TARGET_PCI;
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priv->base.access = NV_MEM_ACCESS_RW;
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}
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priv->flags0 = nv_mclass(priv);
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switch (priv->base.target) {
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case NV_MEM_TARGET_VRAM:
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priv->flags0 |= 0x00003000;
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break;
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case NV_MEM_TARGET_PCI:
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priv->flags0 |= 0x00023000;
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break;
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case NV_MEM_TARGET_PCI_NOSNOOP:
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priv->flags0 |= 0x00033000;
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break;
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default:
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return -EINVAL;
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}
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switch (priv->base.access) {
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case NV_MEM_ACCESS_RO:
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priv->flags0 |= 0x00004000;
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break;
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case NV_MEM_ACCESS_WO:
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priv->flags0 |= 0x00008000;
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case NV_MEM_ACCESS_RW:
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priv->flags2 |= 0x00000002;
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break;
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default:
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return -EINVAL;
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}
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return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
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}
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static struct nouveau_ofuncs
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nv04_dmaobj_ofuncs = {
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.ctor = nv04_dmaobj_ctor,
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.dtor = _nvkm_dmaobj_dtor,
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.init = _nvkm_dmaobj_init,
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.fini = _nvkm_dmaobj_fini,
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};
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static struct nouveau_oclass
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nv04_dmaeng_sclass[] = {
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{ NV_DMA_FROM_MEMORY_CLASS, &nv04_dmaobj_ofuncs },
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{ NV_DMA_TO_MEMORY_CLASS, &nv04_dmaobj_ofuncs },
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{ NV_DMA_IN_MEMORY_CLASS, &nv04_dmaobj_ofuncs },
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{}
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};
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struct nouveau_oclass *
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nv04_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
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.base.handle = NV_ENGINE(DMAOBJ, 0x04),
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@ -118,5 +160,6 @@ nv04_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
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.init = _nvkm_dmaeng_init,
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.fini = _nvkm_dmaeng_fini,
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},
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.sclass = nv04_dmaeng_sclass,
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.bind = nv04_dmaobj_bind,
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}.base;
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@ -29,14 +29,18 @@
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#include "priv.h"
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struct nv50_dmaobj_priv {
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struct nouveau_dmaobj base;
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u32 flags0;
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u32 flags5;
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};
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static int
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nv50_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
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nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
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struct nouveau_object *parent,
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struct nouveau_dmaobj *dmaobj,
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struct nouveau_gpuobj **pgpuobj)
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{
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u32 flags0 = nv_mclass(dmaobj);
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u32 flags5 = 0x00000000;
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struct nv50_dmaobj_priv *priv = (void *)dmaobj;
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int ret;
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if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
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@ -66,68 +70,107 @@ nv50_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
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}
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}
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if (!(dmaobj->conf0 & NV50_DMA_CONF0_ENABLE)) {
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if (dmaobj->target == NV_MEM_TARGET_VM) {
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dmaobj->conf0 = NV50_DMA_CONF0_PRIV_VM;
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dmaobj->conf0 |= NV50_DMA_CONF0_PART_VM;
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dmaobj->conf0 |= NV50_DMA_CONF0_COMP_VM;
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dmaobj->conf0 |= NV50_DMA_CONF0_TYPE_VM;
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ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
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if (ret == 0) {
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nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
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nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
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nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start));
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nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 |
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upper_32_bits(priv->base.start));
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nv_wo32(*pgpuobj, 0x10, 0x00000000);
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nv_wo32(*pgpuobj, 0x14, priv->flags5);
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}
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return ret;
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}
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static int
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nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nouveau_dmaeng *dmaeng = (void *)engine;
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struct nv50_dmaobj_priv *priv;
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union {
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u32 conf0;
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} *args;
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int ret;
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ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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args = data;
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if (!(args->conf0 & NV50_DMA_CONF0_ENABLE)) {
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if (priv->base.target == NV_MEM_TARGET_VM) {
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args->conf0 = NV50_DMA_CONF0_PRIV_VM;
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args->conf0 |= NV50_DMA_CONF0_PART_VM;
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args->conf0 |= NV50_DMA_CONF0_COMP_VM;
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args->conf0 |= NV50_DMA_CONF0_TYPE_VM;
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} else {
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dmaobj->conf0 = NV50_DMA_CONF0_PRIV_US;
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dmaobj->conf0 |= NV50_DMA_CONF0_PART_256;
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dmaobj->conf0 |= NV50_DMA_CONF0_COMP_NONE;
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dmaobj->conf0 |= NV50_DMA_CONF0_TYPE_LINEAR;
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args->conf0 = NV50_DMA_CONF0_PRIV_US;
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args->conf0 |= NV50_DMA_CONF0_PART_256;
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args->conf0 |= NV50_DMA_CONF0_COMP_NONE;
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args->conf0 |= NV50_DMA_CONF0_TYPE_LINEAR;
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}
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}
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flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_COMP) << 22;
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flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_TYPE) << 22;
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flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_PRIV);
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flags5 |= (dmaobj->conf0 & NV50_DMA_CONF0_PART);
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priv->flags0 |= (args->conf0 & NV50_DMA_CONF0_COMP) << 22;
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priv->flags0 |= (args->conf0 & NV50_DMA_CONF0_TYPE) << 22;
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priv->flags0 |= (args->conf0 & NV50_DMA_CONF0_PRIV);
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priv->flags5 |= (args->conf0 & NV50_DMA_CONF0_PART);
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switch (dmaobj->target) {
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switch (priv->base.target) {
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case NV_MEM_TARGET_VM:
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flags0 |= 0x00000000;
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priv->flags0 |= 0x00000000;
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break;
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case NV_MEM_TARGET_VRAM:
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flags0 |= 0x00010000;
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priv->flags0 |= 0x00010000;
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break;
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case NV_MEM_TARGET_PCI:
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flags0 |= 0x00020000;
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priv->flags0 |= 0x00020000;
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break;
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case NV_MEM_TARGET_PCI_NOSNOOP:
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flags0 |= 0x00030000;
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priv->flags0 |= 0x00030000;
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break;
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default:
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return -EINVAL;
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}
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switch (dmaobj->access) {
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switch (priv->base.access) {
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case NV_MEM_ACCESS_VM:
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break;
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case NV_MEM_ACCESS_RO:
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flags0 |= 0x00040000;
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priv->flags0 |= 0x00040000;
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break;
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case NV_MEM_ACCESS_WO:
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case NV_MEM_ACCESS_RW:
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flags0 |= 0x00080000;
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priv->flags0 |= 0x00080000;
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break;
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default:
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return -EINVAL;
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}
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ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
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if (ret == 0) {
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nv_wo32(*pgpuobj, 0x00, flags0);
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nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->limit));
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nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->start));
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nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->limit) << 24 |
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upper_32_bits(dmaobj->start));
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nv_wo32(*pgpuobj, 0x10, 0x00000000);
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nv_wo32(*pgpuobj, 0x14, flags5);
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}
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return ret;
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return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
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}
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static struct nouveau_ofuncs
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nv50_dmaobj_ofuncs = {
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.ctor = nv50_dmaobj_ctor,
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.dtor = _nvkm_dmaobj_dtor,
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.init = _nvkm_dmaobj_init,
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.fini = _nvkm_dmaobj_fini,
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};
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static struct nouveau_oclass
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nv50_dmaeng_sclass[] = {
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{ NV_DMA_FROM_MEMORY_CLASS, &nv50_dmaobj_ofuncs },
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{ NV_DMA_TO_MEMORY_CLASS, &nv50_dmaobj_ofuncs },
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{ NV_DMA_IN_MEMORY_CLASS, &nv50_dmaobj_ofuncs },
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{}
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};
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struct nouveau_oclass *
|
||||
nv50_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
|
||||
.base.handle = NV_ENGINE(DMAOBJ, 0x50),
|
||||
@ -137,5 +180,6 @@ nv50_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
|
||||
.init = _nvkm_dmaeng_init,
|
||||
.fini = _nvkm_dmaeng_fini,
|
||||
},
|
||||
.sclass = nv50_dmaeng_sclass,
|
||||
.bind = nv50_dmaobj_bind,
|
||||
}.base;
|
||||
|
||||
@ -30,14 +30,18 @@
|
||||
|
||||
#include "priv.h"
|
||||
|
||||
struct nvc0_dmaobj_priv {
|
||||
struct nouveau_dmaobj base;
|
||||
u32 flags0;
|
||||
u32 flags5;
|
||||
};
|
||||
|
||||
static int
|
||||
nvc0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
|
||||
nvc0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
|
||||
struct nouveau_object *parent,
|
||||
struct nouveau_dmaobj *dmaobj,
|
||||
struct nouveau_gpuobj **pgpuobj)
|
||||
{
|
||||
u32 flags0 = nv_mclass(dmaobj);
|
||||
u32 flags5 = 0x00000000;
|
||||
struct nvc0_dmaobj_priv *priv = (void *)dmaobj;
|
||||
int ret;
|
||||
|
||||
if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
|
||||
@ -52,64 +56,101 @@ nvc0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
|
||||
} else
|
||||
return 0;
|
||||
|
||||
if (!(dmaobj->conf0 & NVC0_DMA_CONF0_ENABLE)) {
|
||||
if (dmaobj->target == NV_MEM_TARGET_VM) {
|
||||
dmaobj->conf0 = NVC0_DMA_CONF0_PRIV_VM;
|
||||
dmaobj->conf0 |= NVC0_DMA_CONF0_TYPE_VM;
|
||||
ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
|
||||
if (ret == 0) {
|
||||
nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
|
||||
nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
|
||||
nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start));
|
||||
nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 |
|
||||
upper_32_bits(priv->base.start));
|
||||
nv_wo32(*pgpuobj, 0x10, 0x00000000);
|
||||
nv_wo32(*pgpuobj, 0x14, priv->flags5);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
nvc0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
struct nouveau_oclass *oclass, void *data, u32 size,
|
||||
struct nouveau_object **pobject)
|
||||
{
|
||||
struct nouveau_dmaeng *dmaeng = (void *)engine;
|
||||
struct nvc0_dmaobj_priv *priv;
|
||||
union {
|
||||
u32 conf0;
|
||||
} *args;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
args = data;
|
||||
|
||||
if (!(args->conf0 & NVC0_DMA_CONF0_ENABLE)) {
|
||||
if (priv->base.target == NV_MEM_TARGET_VM) {
|
||||
args->conf0 = NVC0_DMA_CONF0_PRIV_VM;
|
||||
args->conf0 |= NVC0_DMA_CONF0_TYPE_VM;
|
||||
} else {
|
||||
dmaobj->conf0 = NVC0_DMA_CONF0_PRIV_US;
|
||||
dmaobj->conf0 |= NVC0_DMA_CONF0_TYPE_LINEAR;
|
||||
dmaobj->conf0 |= 0x00020000;
|
||||
args->conf0 = NVC0_DMA_CONF0_PRIV_US;
|
||||
args->conf0 |= NVC0_DMA_CONF0_TYPE_LINEAR;
|
||||
args->conf0 |= 0x00020000;
|
||||
}
|
||||
}
|
||||
|
||||
flags0 |= (dmaobj->conf0 & NVC0_DMA_CONF0_TYPE) << 22;
|
||||
flags0 |= (dmaobj->conf0 & NVC0_DMA_CONF0_PRIV);
|
||||
flags5 |= (dmaobj->conf0 & NVC0_DMA_CONF0_UNKN);
|
||||
priv->flags0 |= (args->conf0 & NVC0_DMA_CONF0_TYPE) << 22;
|
||||
priv->flags0 |= (args->conf0 & NVC0_DMA_CONF0_PRIV);
|
||||
priv->flags5 |= (args->conf0 & NVC0_DMA_CONF0_UNKN);
|
||||
|
||||
switch (dmaobj->target) {
|
||||
switch (priv->base.target) {
|
||||
case NV_MEM_TARGET_VM:
|
||||
flags0 |= 0x00000000;
|
||||
priv->flags0 |= 0x00000000;
|
||||
break;
|
||||
case NV_MEM_TARGET_VRAM:
|
||||
flags0 |= 0x00010000;
|
||||
priv->flags0 |= 0x00010000;
|
||||
break;
|
||||
case NV_MEM_TARGET_PCI:
|
||||
flags0 |= 0x00020000;
|
||||
priv->flags0 |= 0x00020000;
|
||||
break;
|
||||
case NV_MEM_TARGET_PCI_NOSNOOP:
|
||||
flags0 |= 0x00030000;
|
||||
priv->flags0 |= 0x00030000;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (dmaobj->access) {
|
||||
switch (priv->base.access) {
|
||||
case NV_MEM_ACCESS_VM:
|
||||
break;
|
||||
case NV_MEM_ACCESS_RO:
|
||||
flags0 |= 0x00040000;
|
||||
priv->flags0 |= 0x00040000;
|
||||
break;
|
||||
case NV_MEM_ACCESS_WO:
|
||||
case NV_MEM_ACCESS_RW:
|
||||
flags0 |= 0x00080000;
|
||||
priv->flags0 |= 0x00080000;
|
||||
break;
|
||||
}
|
||||
|
||||
ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
|
||||
if (ret == 0) {
|
||||
nv_wo32(*pgpuobj, 0x00, flags0);
|
||||
nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->limit));
|
||||
nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->start));
|
||||
nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->limit) << 24 |
|
||||
upper_32_bits(dmaobj->start));
|
||||
nv_wo32(*pgpuobj, 0x10, 0x00000000);
|
||||
nv_wo32(*pgpuobj, 0x14, flags5);
|
||||
}
|
||||
|
||||
return ret;
|
||||
return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
|
||||
}
|
||||
|
||||
static struct nouveau_ofuncs
|
||||
nvc0_dmaobj_ofuncs = {
|
||||
.ctor = nvc0_dmaobj_ctor,
|
||||
.dtor = _nvkm_dmaobj_dtor,
|
||||
.init = _nvkm_dmaobj_init,
|
||||
.fini = _nvkm_dmaobj_fini,
|
||||
};
|
||||
|
||||
static struct nouveau_oclass
|
||||
nvc0_dmaeng_sclass[] = {
|
||||
{ NV_DMA_FROM_MEMORY_CLASS, &nvc0_dmaobj_ofuncs },
|
||||
{ NV_DMA_TO_MEMORY_CLASS, &nvc0_dmaobj_ofuncs },
|
||||
{ NV_DMA_IN_MEMORY_CLASS, &nvc0_dmaobj_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nouveau_oclass *
|
||||
nvc0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
|
||||
.base.handle = NV_ENGINE(DMAOBJ, 0xc0),
|
||||
@ -119,5 +160,6 @@ nvc0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
|
||||
.init = _nvkm_dmaeng_init,
|
||||
.fini = _nvkm_dmaeng_fini,
|
||||
},
|
||||
.sclass = nvc0_dmaeng_sclass,
|
||||
.bind = nvc0_dmaobj_bind,
|
||||
}.base;
|
||||
|
||||
@ -30,17 +30,17 @@
|
||||
|
||||
#include "priv.h"
|
||||
|
||||
struct nvd0_dmaeng_priv {
|
||||
struct nouveau_dmaeng base;
|
||||
struct nvd0_dmaobj_priv {
|
||||
struct nouveau_dmaobj base;
|
||||
u32 flags0;
|
||||
};
|
||||
|
||||
static int
|
||||
nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
|
||||
nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
|
||||
struct nouveau_object *parent,
|
||||
struct nouveau_dmaobj *dmaobj,
|
||||
struct nouveau_gpuobj **pgpuobj)
|
||||
{
|
||||
u32 flags0 = 0x00000000;
|
||||
struct nvd0_dmaobj_priv *priv = (void *)dmaobj;
|
||||
int ret;
|
||||
|
||||
if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
|
||||
@ -64,33 +64,11 @@ nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
|
||||
} else
|
||||
return 0;
|
||||
|
||||
if (!(dmaobj->conf0 & NVD0_DMA_CONF0_ENABLE)) {
|
||||
if (dmaobj->target == NV_MEM_TARGET_VM) {
|
||||
dmaobj->conf0 |= NVD0_DMA_CONF0_TYPE_VM;
|
||||
dmaobj->conf0 |= NVD0_DMA_CONF0_PAGE_LP;
|
||||
} else {
|
||||
dmaobj->conf0 |= NVD0_DMA_CONF0_TYPE_LINEAR;
|
||||
dmaobj->conf0 |= NVD0_DMA_CONF0_PAGE_SP;
|
||||
}
|
||||
}
|
||||
|
||||
flags0 |= (dmaobj->conf0 & NVD0_DMA_CONF0_TYPE) << 20;
|
||||
flags0 |= (dmaobj->conf0 & NVD0_DMA_CONF0_PAGE) >> 4;
|
||||
|
||||
switch (dmaobj->target) {
|
||||
case NV_MEM_TARGET_VRAM:
|
||||
flags0 |= 0x00000009;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
|
||||
if (ret == 0) {
|
||||
nv_wo32(*pgpuobj, 0x00, flags0);
|
||||
nv_wo32(*pgpuobj, 0x04, dmaobj->start >> 8);
|
||||
nv_wo32(*pgpuobj, 0x08, dmaobj->limit >> 8);
|
||||
nv_wo32(*pgpuobj, 0x00, priv->flags0);
|
||||
nv_wo32(*pgpuobj, 0x04, priv->base.start >> 8);
|
||||
nv_wo32(*pgpuobj, 0x08, priv->base.limit >> 8);
|
||||
nv_wo32(*pgpuobj, 0x0c, 0x00000000);
|
||||
nv_wo32(*pgpuobj, 0x10, 0x00000000);
|
||||
nv_wo32(*pgpuobj, 0x14, 0x00000000);
|
||||
@ -99,6 +77,73 @@ nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
nvd0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
struct nouveau_oclass *oclass, void *data, u32 size,
|
||||
struct nouveau_object **pobject)
|
||||
{
|
||||
struct nouveau_dmaeng *dmaeng = (void *)engine;
|
||||
struct nvd0_dmaobj_priv *priv;
|
||||
union {
|
||||
u32 conf0;
|
||||
} *args;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
args = data;
|
||||
|
||||
if (!(args->conf0 & NVD0_DMA_CONF0_ENABLE)) {
|
||||
if (priv->base.target == NV_MEM_TARGET_VM) {
|
||||
args->conf0 |= NVD0_DMA_CONF0_TYPE_VM;
|
||||
args->conf0 |= NVD0_DMA_CONF0_PAGE_LP;
|
||||
} else {
|
||||
args->conf0 |= NVD0_DMA_CONF0_TYPE_LINEAR;
|
||||
args->conf0 |= NVD0_DMA_CONF0_PAGE_SP;
|
||||
}
|
||||
}
|
||||
|
||||
priv->flags0 |= (args->conf0 & NVD0_DMA_CONF0_TYPE) << 20;
|
||||
priv->flags0 |= (args->conf0 & NVD0_DMA_CONF0_PAGE) >> 4;
|
||||
|
||||
switch (priv->base.target) {
|
||||
case NV_MEM_TARGET_VRAM:
|
||||
priv->flags0 |= 0x00000009;
|
||||
break;
|
||||
case NV_MEM_TARGET_VM:
|
||||
case NV_MEM_TARGET_PCI:
|
||||
case NV_MEM_TARGET_PCI_NOSNOOP:
|
||||
/* XXX: don't currently know how to construct a real one
|
||||
* of these. we only use them to represent pushbufs
|
||||
* on these chipsets, and the classes that use them
|
||||
* deal with the target themselves.
|
||||
*/
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
|
||||
}
|
||||
|
||||
static struct nouveau_ofuncs
|
||||
nvd0_dmaobj_ofuncs = {
|
||||
.ctor = nvd0_dmaobj_ctor,
|
||||
.dtor = _nvkm_dmaobj_dtor,
|
||||
.init = _nvkm_dmaobj_init,
|
||||
.fini = _nvkm_dmaobj_fini,
|
||||
};
|
||||
|
||||
static struct nouveau_oclass
|
||||
nvd0_dmaeng_sclass[] = {
|
||||
{ NV_DMA_FROM_MEMORY_CLASS, &nvd0_dmaobj_ofuncs },
|
||||
{ NV_DMA_TO_MEMORY_CLASS, &nvd0_dmaobj_ofuncs },
|
||||
{ NV_DMA_IN_MEMORY_CLASS, &nvd0_dmaobj_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nouveau_oclass *
|
||||
nvd0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
|
||||
.base.handle = NV_ENGINE(DMAOBJ, 0xd0),
|
||||
@ -108,5 +153,6 @@ nvd0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
|
||||
.init = _nvkm_dmaeng_init,
|
||||
.fini = _nvkm_dmaeng_fini,
|
||||
},
|
||||
.sclass = nvd0_dmaeng_sclass,
|
||||
.bind = nvd0_dmaobj_bind,
|
||||
}.base;
|
||||
|
||||
@ -3,6 +3,16 @@
|
||||
|
||||
#include <engine/dmaobj.h>
|
||||
|
||||
#define nvkm_dmaobj_create(p,e,c,pa,sa,d) \
|
||||
nvkm_dmaobj_create_((p), (e), (c), (pa), (sa), sizeof(**d), (void **)d)
|
||||
|
||||
int nvkm_dmaobj_create_(struct nouveau_object *, struct nouveau_object *,
|
||||
struct nouveau_oclass *, void **, u32 *,
|
||||
int, void **);
|
||||
#define _nvkm_dmaobj_dtor nouveau_object_destroy
|
||||
#define _nvkm_dmaobj_init nouveau_object_init
|
||||
#define _nvkm_dmaobj_fini nouveau_object_fini
|
||||
|
||||
int _nvkm_dmaeng_ctor(struct nouveau_object *, struct nouveau_object *,
|
||||
struct nouveau_oclass *, void *, u32,
|
||||
struct nouveau_object **);
|
||||
@ -12,8 +22,9 @@ int _nvkm_dmaeng_ctor(struct nouveau_object *, struct nouveau_object *,
|
||||
|
||||
struct nvkm_dmaeng_impl {
|
||||
struct nouveau_oclass base;
|
||||
int (*bind)(struct nouveau_dmaeng *, struct nouveau_object *,
|
||||
struct nouveau_dmaobj *, struct nouveau_gpuobj **);
|
||||
struct nouveau_oclass *sclass;
|
||||
int (*bind)(struct nouveau_dmaobj *, struct nouveau_object *,
|
||||
struct nouveau_gpuobj **);
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@ -83,7 +83,7 @@ nouveau_fifo_channel_create_(struct nouveau_object *parent,
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = dmaeng->bind(dmaeng, parent, chan->pushdma, &chan->pushgpu);
|
||||
ret = dmaeng->bind(chan->pushdma, parent, &chan->pushgpu);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
||||
@ -19,9 +19,8 @@ struct nouveau_dmaeng {
|
||||
struct nouveau_engine base;
|
||||
|
||||
/* creates a "physical" dma object from a struct nouveau_dmaobj */
|
||||
int (*bind)(struct nouveau_dmaeng *dmaeng,
|
||||
int (*bind)(struct nouveau_dmaobj *dmaobj,
|
||||
struct nouveau_object *parent,
|
||||
struct nouveau_dmaobj *dmaobj,
|
||||
struct nouveau_gpuobj **);
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user