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https://github.com/edk2-porting/linux-next.git
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gpio: omap: use BIT() macro instead of shifting bits
Using the BIT() macro instead of shifting bits makes the code less error prone and also more readable. Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Javier Martinez Canillas
Linus Walleij
parent
459b81808f
commit
b1e9fec2b8
@ -83,11 +83,11 @@ struct gpio_bank {
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};
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#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
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#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
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#define GPIO_BIT(bank, gpio) (BIT(GPIO_INDEX(bank, gpio)))
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#define GPIO_MOD_CTRL_BIT BIT(0)
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#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
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#define LINE_USED(line, offset) (line & (1 << offset))
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#define LINE_USED(line, offset) (line & (BIT(offset)))
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static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
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{
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@ -108,9 +108,9 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
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reg += bank->regs->direction;
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l = readl_relaxed(reg);
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if (is_input)
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l |= 1 << gpio;
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l |= BIT(gpio);
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else
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l &= ~(1 << gpio);
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l &= ~(BIT(gpio));
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writel_relaxed(l, reg);
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bank->context.oe = l;
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}
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@ -153,14 +153,14 @@ static int _get_gpio_datain(struct gpio_bank *bank, int offset)
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{
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void __iomem *reg = bank->base + bank->regs->datain;
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return (readl_relaxed(reg) & (1 << offset)) != 0;
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return (readl_relaxed(reg) & (BIT(offset))) != 0;
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}
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static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
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{
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void __iomem *reg = bank->base + bank->regs->dataout;
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return (readl_relaxed(reg) & (1 << offset)) != 0;
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return (readl_relaxed(reg) & (BIT(offset))) != 0;
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}
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static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
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@ -297,7 +297,7 @@ static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
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unsigned trigger)
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{
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void __iomem *base = bank->base;
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u32 gpio_bit = 1 << gpio;
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u32 gpio_bit = BIT(gpio);
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_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
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trigger & IRQ_TYPE_LEVEL_LOW);
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@ -366,9 +366,9 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
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l = readl_relaxed(reg);
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if ((l >> gpio) & 1)
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l &= ~(1 << gpio);
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l &= ~(BIT(gpio));
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else
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l |= 1 << gpio;
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l |= BIT(gpio);
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writel_relaxed(l, reg);
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}
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@ -390,11 +390,11 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
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l = readl_relaxed(reg);
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if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
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bank->toggle_mask |= 1 << gpio;
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bank->toggle_mask |= BIT(gpio);
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if (trigger & IRQ_TYPE_EDGE_RISING)
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l |= 1 << gpio;
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l |= BIT(gpio);
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else if (trigger & IRQ_TYPE_EDGE_FALLING)
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l &= ~(1 << gpio);
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l &= ~(BIT(gpio));
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else
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return -EINVAL;
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@ -411,10 +411,10 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
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if (trigger & IRQ_TYPE_EDGE_RISING)
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l |= 2 << (gpio << 1);
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if (trigger & IRQ_TYPE_EDGE_FALLING)
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l |= 1 << (gpio << 1);
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l |= BIT(gpio << 1);
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/* Enable wake-up during idle for dynamic tick */
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_gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
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_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
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bank->context.wake_en =
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readl_relaxed(bank->base + bank->regs->wkup_en);
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writel_relaxed(l, reg);
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@ -428,7 +428,7 @@ static void _enable_gpio_module(struct gpio_bank *bank, unsigned offset)
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void __iomem *reg = bank->base + bank->regs->pinctrl;
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/* Claim the pin for MPU */
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writel_relaxed(readl_relaxed(reg) | (1 << offset), reg);
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writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
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}
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if (bank->regs->ctrl && !BANK_USED(bank)) {
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@ -451,7 +451,7 @@ static void _disable_gpio_module(struct gpio_bank *bank, unsigned offset)
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!LINE_USED(bank->mod_usage, offset) &&
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!LINE_USED(bank->irq_usage, offset)) {
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/* Disable wake-up during idle for dynamic tick */
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_gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
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_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
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bank->context.wake_en =
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readl_relaxed(bank->base + bank->regs->wkup_en);
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}
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@ -507,12 +507,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
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if (!LINE_USED(bank->mod_usage, offset)) {
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_enable_gpio_module(bank, offset);
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_set_gpio_direction(bank, offset, 1);
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} else if (!gpio_is_input(bank, 1 << offset)) {
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} else if (!gpio_is_input(bank, BIT(offset))) {
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spin_unlock_irqrestore(&bank->lock, flags);
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return -EINVAL;
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}
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bank->irq_usage |= 1 << GPIO_INDEX(bank, gpio);
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bank->irq_usage |= BIT(GPIO_INDEX(bank, gpio));
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spin_unlock_irqrestore(&bank->lock, flags);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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@ -549,7 +549,7 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
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{
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void __iomem *reg = bank->base;
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u32 l;
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u32 mask = (1 << bank->width) - 1;
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u32 mask = (BIT(bank->width)) - 1;
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reg += bank->regs->irqenable;
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l = readl_relaxed(reg);
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@ -681,7 +681,7 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
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_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
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_enable_gpio_module(bank, offset);
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}
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bank->mod_usage |= 1 << offset;
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bank->mod_usage |= BIT(offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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@ -693,7 +693,7 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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bank->mod_usage &= ~(1 << offset);
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bank->mod_usage &= ~(BIT(offset));
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_disable_gpio_module(bank, offset);
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_reset_gpio(bank, bank->chip.base + offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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@ -763,7 +763,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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while (isr) {
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bit = __ffs(isr);
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isr &= ~(1 << bit);
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isr &= ~(BIT(bit));
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/*
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* Some chips can't respond to both rising and falling
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@ -772,7 +772,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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* to respond to the IRQ for the opposite direction.
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* This will be indicated in the bank toggle_mask.
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*/
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if (bank->toggle_mask & (1 << bit))
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if (bank->toggle_mask & (BIT(bit)))
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_toggle_gpio_edge_triggering(bank, bit);
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generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
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@ -798,7 +798,7 @@ static void gpio_irq_shutdown(struct irq_data *d)
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spin_lock_irqsave(&bank->lock, flags);
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gpio_unlock_as_irq(&bank->chip, offset);
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bank->irq_usage &= ~(1 << offset);
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bank->irq_usage &= ~(BIT(offset));
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_disable_gpio_module(bank, offset);
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_reset_gpio(bank, gpio);
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spin_unlock_irqrestore(&bank->lock, flags);
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@ -961,7 +961,7 @@ static int gpio_get(struct gpio_chip *chip, unsigned offset)
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u32 mask;
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bank = container_of(chip, struct gpio_bank, chip);
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mask = (1 << offset);
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mask = (BIT(offset));
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if (gpio_is_input(bank, mask))
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return _get_gpio_datain(bank, offset);
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