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net: dsa: felix: support half-duplex link modes
Ping tested: [ 11.808455] mscc_felix 0000:00:00.5 swp0: Link is Up - 1Gbps/Full - flow control rx/tx [ 11.816497] IPv6: ADDRCONF(NETDEV_CHANGE): swp0: link becomes ready [root@LS1028ARDB ~] # ethtool -s swp0 advertise 0x4 [ 18.844591] mscc_felix 0000:00:00.5 swp0: Link is Down [ 22.048337] mscc_felix 0000:00:00.5 swp0: Link is Up - 100Mbps/Half - flow control off [root@LS1028ARDB ~] # ip addr add 192.168.1.1/24 dev swp0 [root@LS1028ARDB ~] # ping 192.168.1.2 PING 192.168.1.2 (192.168.1.2): 56 data bytes (...) ^C--- 192.168.1.2 ping statistics --- 3 packets transmitted, 3 packets received, 0% packet loss round-trip min/avg/max = 0.383/0.611/1.051 ms [root@LS1028ARDB ~] # ethtool -s swp0 advertise 0x10 [ 355.637747] mscc_felix 0000:00:00.5 swp0: Link is Down [ 358.788034] mscc_felix 0000:00:00.5 swp0: Link is Up - 1Gbps/Half - flow control off [root@LS1028ARDB ~] # ping 192.168.1.2 PING 192.168.1.2 (192.168.1.2): 56 data bytes (...) ^C --- 192.168.1.2 ping statistics --- 16 packets transmitted, 16 packets received, 0% packet loss round-trip min/avg/max = 0.301/0.384/1.138 ms Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -194,13 +194,15 @@ static void felix_phylink_validate(struct dsa_switch *ds, int port,
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return;
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}
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/* No half-duplex. */
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phylink_set_port_modes(mask);
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phylink_set(mask, Autoneg);
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phylink_set(mask, Pause);
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phylink_set(mask, Asym_Pause);
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phylink_set(mask, 10baseT_Half);
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phylink_set(mask, 10baseT_Full);
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phylink_set(mask, 100baseT_Half);
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phylink_set(mask, 100baseT_Full);
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phylink_set(mask, 1000baseT_Half);
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phylink_set(mask, 1000baseT_Full);
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if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
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@ -817,12 +817,9 @@ static void vsc9959_pcs_init_sgmii(struct phy_device *pcs,
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phy_set_bits(pcs, MII_BMCR, BMCR_ANENABLE);
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} else {
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u16 if_mode = ENETC_PCS_IF_MODE_SGMII_EN;
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int speed;
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if (state->duplex == DUPLEX_HALF) {
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phydev_err(pcs, "Half duplex not supported\n");
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return;
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}
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switch (state->speed) {
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case SPEED_1000:
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speed = ENETC_PCS_SPEED_1000;
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@ -841,9 +838,9 @@ static void vsc9959_pcs_init_sgmii(struct phy_device *pcs,
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return;
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}
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phy_write(pcs, ENETC_PCS_IF_MODE,
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ENETC_PCS_IF_MODE_SGMII_EN |
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ENETC_PCS_IF_MODE_SGMII_SPEED(speed));
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if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(speed);
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if (state->duplex == DUPLEX_HALF)
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if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF;
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phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
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}
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@ -870,15 +867,18 @@ static void vsc9959_pcs_init_2500basex(struct phy_device *pcs,
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unsigned int link_an_mode,
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const struct phylink_link_state *state)
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{
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u16 if_mode = ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500) |
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ENETC_PCS_IF_MODE_SGMII_EN;
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if (link_an_mode == MLO_AN_INBAND) {
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phydev_err(pcs, "AN not supported on 3.125GHz SerDes lane\n");
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return;
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}
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phy_write(pcs, ENETC_PCS_IF_MODE,
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ENETC_PCS_IF_MODE_SGMII_EN |
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ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500));
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if (state->duplex == DUPLEX_HALF)
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if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF;
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phy_write(pcs, ENETC_PCS_IF_MODE, if_mode);
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phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
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}
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@ -919,8 +919,11 @@ static void vsc9959_pcs_init(struct ocelot *ocelot, int port,
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linkmode_set_bit_array(phy_basic_ports_array,
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ARRAY_SIZE(phy_basic_ports_array),
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pcs->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, pcs->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, pcs->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, pcs->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pcs->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, pcs->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, pcs->supported);
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if (pcs->interface == PHY_INTERFACE_MODE_2500BASEX ||
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pcs->interface == PHY_INTERFACE_MODE_USXGMII)
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@ -15,6 +15,7 @@
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#define ENETC_PCS_IF_MODE_SGMII_EN BIT(0)
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#define ENETC_PCS_IF_MODE_USE_SGMII_AN BIT(1)
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#define ENETC_PCS_IF_MODE_SGMII_SPEED(x) (((x) << 2) & GENMASK(3, 2))
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#define ENETC_PCS_IF_MODE_DUPLEX_HALF BIT(3)
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/* Not a mistake, the SerDes PLL needs to be set at 3.125 GHz by Reset
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* Configuration Word (RCW, outside Linux control) for 2.5G SGMII mode. The PCS
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