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Merge branches 'pci/host-mvebu' and 'pci/host-spear' into next
* pci/host-mvebu: PCI: mvebu: Fix uninitialized variable in mvebu_get_tgt_attr() * pci/host-spear: PCI: spear: Pass config resource through reg property
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commit
b1bf295778
@ -85,7 +85,8 @@
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pcie0: pcie@b1000000 {
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compatible = "st,spear1340-pcie", "snps,dw-pcie";
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reg = <0xb1000000 0x4000>;
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reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
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reg-names = "dbi", "config";
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interrupts = <0 68 0x4>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 0 68 0x4>;
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@ -95,15 +96,15 @@
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
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0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
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ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
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status = "disabled";
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};
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pcie1: pcie@b1800000 {
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compatible = "st,spear1340-pcie", "snps,dw-pcie";
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reg = <0xb1800000 0x4000>;
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reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
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reg-names = "dbi", "config";
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interrupts = <0 69 0x4>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 0 69 0x4>;
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@ -113,15 +114,15 @@
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */
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0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
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ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
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status = "disabled";
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};
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pcie2: pcie@b4000000 {
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compatible = "st,spear1340-pcie", "snps,dw-pcie";
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reg = <0xb4000000 0x4000>;
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reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
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reg-names = "dbi", "config";
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interrupts = <0 70 0x4>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 0 70 0x4>;
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@ -131,8 +132,7 @@
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */
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0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
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ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
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status = "disabled";
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};
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@ -50,7 +50,8 @@
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pcie0: pcie@b1000000 {
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compatible = "st,spear1340-pcie", "snps,dw-pcie";
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reg = <0xb1000000 0x4000>;
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reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
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reg-names = "dbi", "config";
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interrupts = <0 68 0x4>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 0 68 0x4>;
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@ -60,8 +61,7 @@
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
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0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
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ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
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status = "disabled";
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};
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@ -873,7 +873,7 @@ static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
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rangesz = pna + na + ns;
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nranges = rlen / sizeof(__be32) / rangesz;
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for (i = 0; i < nranges; i++) {
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for (i = 0; i < nranges; i++, range += rangesz) {
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u32 flags = of_read_number(range, 1);
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u32 slot = of_read_number(range + 1, 1);
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u64 cpuaddr = of_read_number(range + na, pna);
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@ -883,14 +883,14 @@ static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
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rtype = IORESOURCE_IO;
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else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
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rtype = IORESOURCE_MEM;
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else
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continue;
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if (slot == PCI_SLOT(devfn) && type == rtype) {
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*tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
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*attr = DT_CPUADDR_TO_ATTR(cpuaddr);
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return 0;
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}
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range += rangesz;
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}
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return -ENOENT;
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@ -340,7 +340,7 @@ static int __init spear13xx_pcie_probe(struct platform_device *pdev)
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pp->dev = dev;
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dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
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pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
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if (IS_ERR(pp->dbi_base)) {
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dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
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