Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (27 commits)
  sh: Fix up L2 cache probe.
  sh: Fix up SH-4A part probe.
  sh: Add support for SH7723 CPU subtype.
  sh: Fix up SH7763 build.
  sh: Add migor_ts support to MigoR
  sh: Add rs5c732b RTC support to MigoR
  sh: Add I2C support to MigoR
  sh: Add I2C platform data to sh7722
  sh: MigoR NAND flash support using gen_flash
  sh: MigoR NOR flash support using physmap-flash
  sh: Fix up mach-types formatting from merge damage.
  sh: r7780rp: Hook up the I2C and SMBus platform devices.
  sh: Use phyical addresses for MigoR smc91x resources
  sh: Use physical addresses for sh7722 USBF resources
  sh: Add MigoR header file
  Fix sh_keysc double free
  sh: Fix up __access_ok() check for nommu.
  sh: Allow optimized clear/copy page routines to be used on SH-2.
  sh: Hook up the rest of the SH7770 serial ports.
  sh: Add support for Solution Engine SH7721 board
  ...

arch/sh/Kconfig

@@ -167,6 +167,12 @@ config CPU_SUBTYPE_SH7263
 	select CPU_SH2A
 	select CPU_HAS_FPU
 
+config CPU_SUBTYPE_MXG
+	bool "Support MX-G processor"
+	select CPU_SH2A
+	help
+	  Select MX-G if running on an R8A03022BG part.
+
 # SH-3 Processor Support
 
 config CPU_SUBTYPE_SH7705
@@ -270,6 +276,15 @@ config CPU_SUBTYPE_SH4_202
 
 # SH-4A Processor Support
 
+config CPU_SUBTYPE_SH7723
+	bool "Support SH7723 processor"
+	select CPU_SH4A
+	select CPU_SHX2
+	select ARCH_SPARSEMEM_ENABLE
+	select SYS_SUPPORTS_NUMA
+	help
+	  Select SH7723 if you have an SH-MobileR2 CPU.
+
 config CPU_SUBTYPE_SH7763
 	bool "Support SH7763 processor"
 	select CPU_SH4A
@@ -366,6 +381,14 @@ config SH_7619_SOLUTION_ENGINE
 	  Select 7619 SolutionEngine if configuring for a Hitachi SH7619
 	  evaluation board.
 	
+config SH_7721_SOLUTION_ENGINE
+	bool "SolutionEngine7721"
+	select SOLUTION_ENGINE
+	depends on CPU_SUBTYPE_SH7721
+	help
+	  Select 7721 SolutionEngine if configuring for a Hitachi SH7721
+	  evaluation board.
+
 config SH_7722_SOLUTION_ENGINE
 	bool "SolutionEngine7722"
 	select SOLUTION_ENGINE
@@ -560,7 +583,7 @@ config SH_TMU
 config SH_CMT
 	def_bool y
 	prompt "CMT timer support"
-	depends on CPU_SH2
+	depends on CPU_SH2 && !CPU_SUBTYPE_MXG
 	help
 	  This enables the use of the CMT as the system timer.
 
@@ -578,6 +601,7 @@ config SH_TIMER_IRQ
 	default "86" if CPU_SUBTYPE_SH7619
 	default "140" if CPU_SUBTYPE_SH7206
 	default "142" if CPU_SUBTYPE_SH7203
+	default "238" if CPU_SUBTYPE_MXG
 	default "16"
 
 config SH_PCLK_FREQ
@@ -585,10 +609,10 @@ config SH_PCLK_FREQ
 	default "27000000" if CPU_SUBTYPE_SH7343
 	default "31250000" if CPU_SUBTYPE_SH7619
 	default "32000000" if CPU_SUBTYPE_SH7722
-	default "33333333" if CPU_SUBTYPE_SH7770 || \
+	default "33333333" if CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7723 || \
 			      CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
 			      CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
-			      CPU_SUBTYPE_SH7263
+			      CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG
 	default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
 	default "66000000" if CPU_SUBTYPE_SH4_202
 	default "50000000"

arch/sh/Kconfig.debug

@@ -29,16 +29,17 @@ config EARLY_SCIF_CONSOLE
 config EARLY_SCIF_CONSOLE_PORT
 	hex
 	depends on EARLY_SCIF_CONSOLE
-	default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763
+	default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
-	default "0xffe00000" if CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
+	default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
+	default "0xf8420000" if CPU_SUBTYPE_SH7619
+	default "0xff804000" if CPU_SUBTYPE_MXG
+	default "0xffc30000" if CPU_SUBTYPE_SHX3
+	default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
+				CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
+	default "0xffe80000" if CPU_SH4
 	default "0xffea0000" if CPU_SUBTYPE_SH7785
 	default "0xfffe8000" if CPU_SUBTYPE_SH7203
 	default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
-	default "0xf8420000" if CPU_SUBTYPE_SH7619
-	default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
-	default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
-	default "0xffc30000" if CPU_SUBTYPE_SHX3
-	default "0xffe80000" if CPU_SH4
 	default "0x00000000"
 
 config EARLY_PRINTK

arch/sh/Makefile

@@ -107,6 +107,7 @@ machdir-$(CONFIG_SH_7722_SOLUTION_ENGINE)	+= se/7722
 machdir-$(CONFIG_SH_7751_SOLUTION_ENGINE)	+= se/7751
 machdir-$(CONFIG_SH_7780_SOLUTION_ENGINE)	+= se/7780
 machdir-$(CONFIG_SH_7343_SOLUTION_ENGINE)	+= se/7343
+machdir-$(CONFIG_SH_7721_SOLUTION_ENGINE)	+= se/7721
 machdir-$(CONFIG_SH_HP6XX)			+= hp6xx
 machdir-$(CONFIG_SH_DREAMCAST)			+= dreamcast
 machdir-$(CONFIG_SH_MPC1211)			+= mpc1211

arch/sh/boards/renesas/migor/setup.c

@@ -10,8 +10,14 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/i2c.h>
 #include <asm/machvec.h>
 #include <asm/io.h>
+#include <asm/sh_keysc.h>
+#include <asm/migor.h>
 
 /* Address     IRQ  Size  Bus  Description
  * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
@@ -23,9 +29,9 @@
 
 static struct resource smc91x_eth_resources[] = {
 	[0] = {
-		.name   = "smc91x-regs" ,
+		.name   = "SMC91C111" ,
-		.start  = P2SEGADDR(0x10000300),
+		.start  = 0x10000300,
-		.end    = P2SEGADDR(0x1000030f),
+		.end    = 0x1000030f,
 		.flags  = IORESOURCE_MEM,
 	},
 	[1] = {
@@ -40,19 +46,202 @@ static struct platform_device smc91x_eth_device = {
 	.resource       = smc91x_eth_resources,
 };
 
+static struct sh_keysc_info sh_keysc_info = {
+	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
+	.scan_timing = 3,
+	.delay = 5,
+	.keycodes = {
+		0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
+		0, KEY_F, KEY_C, KEY_D,	KEY_H, KEY_1,
+		0, KEY_2, KEY_3, KEY_4,	KEY_5, KEY_6,
+		0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
+		0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
+	},
+};
+
+static struct resource sh_keysc_resources[] = {
+	[0] = {
+		.start  = 0x044b0000,
+		.end    = 0x044b000f,
+		.flags  = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start  = 79,
+		.flags  = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device sh_keysc_device = {
+	.name           = "sh_keysc",
+	.num_resources  = ARRAY_SIZE(sh_keysc_resources),
+	.resource       = sh_keysc_resources,
+	.dev	= {
+		.platform_data	= &sh_keysc_info,
+	},
+};
+
+static struct mtd_partition migor_nor_flash_partitions[] =
+{
+	{
+		.name = "uboot",
+		.offset = 0,
+		.size = (1 * 1024 * 1024),
+		.mask_flags = MTD_WRITEABLE,	/* Read-only */
+	},
+	{
+		.name = "rootfs",
+		.offset = MTDPART_OFS_APPEND,
+		.size = (15 * 1024 * 1024),
+	},
+	{
+		.name = "other",
+		.offset = MTDPART_OFS_APPEND,
+		.size = MTDPART_SIZ_FULL,
+	},
+};
+
+static struct physmap_flash_data migor_nor_flash_data = {
+	.width		= 2,
+	.parts		= migor_nor_flash_partitions,
+	.nr_parts	= ARRAY_SIZE(migor_nor_flash_partitions),
+};
+
+static struct resource migor_nor_flash_resources[] = {
+	[0] = {
+		.name		= "NOR Flash",
+		.start		= 0x00000000,
+		.end		= 0x03ffffff,
+		.flags		= IORESOURCE_MEM,
+	}
+};
+
+static struct platform_device migor_nor_flash_device = {
+	.name		= "physmap-flash",
+	.resource	= migor_nor_flash_resources,
+	.num_resources	= ARRAY_SIZE(migor_nor_flash_resources),
+	.dev		= {
+		.platform_data = &migor_nor_flash_data,
+	},
+};
+
+static struct mtd_partition migor_nand_flash_partitions[] = {
+	{
+		.name		= "nanddata1",
+		.offset		= 0x0,
+		.size		= 512 * 1024 * 1024,
+	},
+	{
+		.name		= "nanddata2",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= 512 * 1024 * 1024,
+	},
+};
+
+static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
+				     unsigned int ctrl)
+{
+	struct nand_chip *chip = mtd->priv;
+
+	if (cmd == NAND_CMD_NONE)
+		return;
+
+	if (ctrl & NAND_CLE)
+		writeb(cmd, chip->IO_ADDR_W + 0x00400000);
+	else if (ctrl & NAND_ALE)
+		writeb(cmd, chip->IO_ADDR_W + 0x00800000);
+	else
+		writeb(cmd, chip->IO_ADDR_W);
+}
+
+static int migor_nand_flash_ready(struct mtd_info *mtd)
+{
+	return ctrl_inb(PORT_PADR) & 0x02; /* PTA1 */
+}
+
+struct platform_nand_data migor_nand_flash_data = {
+	.chip = {
+		.nr_chips = 1,
+		.partitions = migor_nand_flash_partitions,
+		.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
+		.chip_delay = 20,
+		.part_probe_types = (const char *[]) { "cmdlinepart", NULL },
+	},
+	.ctrl = {
+		.dev_ready = migor_nand_flash_ready,
+		.cmd_ctrl = migor_nand_flash_cmd_ctl,
+	},
+};
+
+static struct resource migor_nand_flash_resources[] = {
+	[0] = {
+		.name		= "NAND Flash",
+		.start		= 0x18000000,
+		.end		= 0x18ffffff,
+		.flags		= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device migor_nand_flash_device = {
+	.name		= "gen_nand",
+	.resource	= migor_nand_flash_resources,
+	.num_resources	= ARRAY_SIZE(migor_nand_flash_resources),
+	.dev		= {
+		.platform_data = &migor_nand_flash_data,
+	}
+};
+
 static struct platform_device *migor_devices[] __initdata = {
 	&smc91x_eth_device,
+	&sh_keysc_device,
+	&migor_nor_flash_device,
+	&migor_nand_flash_device,
+};
+
+static struct i2c_board_info __initdata migor_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("rtc-rs5c372", 0x32),
+		.type   = "rs5c372b",
+	},
+	{
+		I2C_BOARD_INFO("migor_ts", 0x51),
+		.irq = 38, /* IRQ6 */
+	},
 };
 
 static int __init migor_devices_setup(void)
 {
+	i2c_register_board_info(0, migor_i2c_devices,
+				ARRAY_SIZE(migor_i2c_devices));
+ 
 	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
 }
 __initcall(migor_devices_setup);
 
 static void __init migor_setup(char **cmdline_p)
 {
-	ctrl_outw(0x1000, 0xa4050110); /* Enable IRQ0 in PJCR */
+	/* SMC91C111 - Enable IRQ0 */
+	ctrl_outw(ctrl_inw(PORT_PJCR) & ~0x0003, PORT_PJCR);
+
+	/* KEYSC */
+	ctrl_outw(ctrl_inw(PORT_PYCR) & ~0x0fff, PORT_PYCR);
+	ctrl_outw(ctrl_inw(PORT_PZCR) & ~0x0ff0, PORT_PZCR);
+	ctrl_outw(ctrl_inw(PORT_PSELA) & ~0x4100, PORT_PSELA);
+	ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
+	ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
+	ctrl_outl(ctrl_inl(MSTPCR2) & ~0x00004000, MSTPCR2);
+
+	/* NAND Flash */
+	ctrl_outw(ctrl_inw(PORT_PXCR) & 0x0fff, PORT_PXCR);
+	ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x00000600) | 0x00000200,
+		  BSC_CS6ABCR);
+
+	/* I2C */
+	ctrl_outl(ctrl_inl(MSTPCR1) & ~0x00000200, MSTPCR1);
+
+	/* Touch Panel - Enable IRQ6 */
+	ctrl_outw(ctrl_inw(PORT_PZCR) & ~0xc, PORT_PZCR);
+	ctrl_outw((ctrl_inw(PORT_PSELA) | 0x8000), PORT_PSELA);
+	ctrl_outw((ctrl_inw(PORT_HIZCRC) & ~0x4000), PORT_HIZCRC);
 }
 
 static struct sh_machine_vector mv_migor __initmv = {

arch/sh/boards/renesas/r7780rp/irq-r7780mp.c

@@ -18,31 +18,44 @@ enum {
 	UNUSED = 0,
 
 	/* board specific interrupt sources */
-	AX88796,          /* Ethernet controller */
+	CF,		/* Compact Flash */
-	CF,               /* Compact Flash */
+	TP,		/* Touch panel */
-	PSW,              /* Push Switch */
+	SCIF1,		/* FPGA SCIF1 */
-	EXT1,             /* EXT1n IRQ */
+	SCIF0,		/* FPGA SCIF0 */
-	EXT4,             /* EXT4n IRQ */
+	SMBUS,		/* SMBUS */
+	RTC,		/* RTC Alarm */
+	AX88796,	/* Ethernet controller */
+	PSW,		/* Push Switch */
+
+	/* external bus connector */
+	EXT1, EXT2, EXT4, EXT5, EXT6,
 };
 
 static struct intc_vect vectors[] __initdata = {
 	INTC_IRQ(CF, IRQ_CF),
-	INTC_IRQ(PSW, IRQ_PSW),
+	INTC_IRQ(TP, IRQ_TP),
+	INTC_IRQ(SCIF1, IRQ_SCIF1),
+	INTC_IRQ(SCIF0, IRQ_SCIF0),
+	INTC_IRQ(SMBUS, IRQ_SMBUS),
+	INTC_IRQ(RTC, IRQ_RTC),
 	INTC_IRQ(AX88796, IRQ_AX88796),
-	INTC_IRQ(EXT1, IRQ_EXT1),
+	INTC_IRQ(PSW, IRQ_PSW),
-	INTC_IRQ(EXT4, IRQ_EXT4),
+
+	INTC_IRQ(EXT1, IRQ_EXT1), INTC_IRQ(EXT2, IRQ_EXT2),
+	INTC_IRQ(EXT4, IRQ_EXT4), INTC_IRQ(EXT5, IRQ_EXT5),
+	INTC_IRQ(EXT6, IRQ_EXT6),
 };
 
 static struct intc_mask_reg mask_registers[] __initdata = {
 	{ 0xa4000000, 0, 16, /* IRLMSK */
-	  { 0, 0, 0, 0, CF, 0, 0, 0,
+	  { SCIF0, SCIF1, RTC, 0, CF, 0, TP, SMBUS,
-	    0, 0, 0, EXT4, 0, EXT1, PSW, AX88796 } },
+	    0, EXT6, EXT5, EXT4, EXT2, EXT1, PSW, AX88796 } },
 };
 
 static unsigned char irl2irq[HL_NR_IRL] __initdata = {
-	0, IRQ_CF, 0, 0,
+	0, IRQ_CF, IRQ_TP, IRQ_SCIF1,
-	0, 0, 0, 0,
+	IRQ_SCIF0, IRQ_SMBUS, IRQ_RTC, IRQ_EXT6,
-	0, IRQ_EXT4, 0, IRQ_EXT1,
+	IRQ_EXT5, IRQ_EXT4, IRQ_EXT2, IRQ_EXT1,
 	0, IRQ_AX88796, IRQ_PSW,
 };
 

arch/sh/boards/renesas/r7780rp/setup.c

@@ -4,7 +4,7 @@
  * Renesas Solutions Highlander Support.
  *
  * Copyright (C) 2002 Atom Create Engineering Co., Ltd.
- * Copyright (C) 2005 - 2007 Paul Mundt
+ * Copyright (C) 2005 - 2008 Paul Mundt
  *
  * This contains support for the R7780RP-1, R7780MP, and R7785RP
  * Highlander modules.
@@ -17,6 +17,7 @@
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <linux/types.h>
+#include <linux/i2c.h>
 #include <net/ax88796.h>
 #include <asm/machvec.h>
 #include <asm/r7780rp.h>
@@ -176,11 +177,38 @@ static struct platform_device ax88796_device = {
 	.resource       = ax88796_resources,
 };
 
+static struct resource smbus_resources[] = {
+	[0] = {
+		.start	= PA_SMCR,
+		.end	= PA_SMCR + 0x100 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_SMBUS,
+		.end	= IRQ_SMBUS,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device smbus_device = {
+	.name		= "i2c-highlander",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(smbus_resources),
+	.resource	= smbus_resources,
+};
+
+static struct i2c_board_info __initdata highlander_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("rtc-rs5c372", 0x32),
+		.type	= "r2025sd",
+	},
+};
 
 static struct platform_device *r7780rp_devices[] __initdata = {
 	&r8a66597_usb_host_device,
 	&m66592_usb_peripheral_device,
 	&heartbeat_device,
+	&smbus_device,
 #ifndef CONFIG_SH_R7780RP
 	&ax88796_device,
 #endif
@@ -199,12 +227,20 @@ static struct trapped_io cf_trapped_io = {
 
 static int __init r7780rp_devices_setup(void)
 {
+	int ret = 0;
+
 #ifndef CONFIG_SH_R7780RP
 	if (register_trapped_io(&cf_trapped_io) == 0)
-		platform_device_register(&cf_ide_device);
+		ret |= platform_device_register(&cf_ide_device);
 #endif
-	return platform_add_devices(r7780rp_devices,
+
+	ret |= platform_add_devices(r7780rp_devices,
 				    ARRAY_SIZE(r7780rp_devices));
+
+	ret |= i2c_register_board_info(0, highlander_i2c_devices,
+				       ARRAY_SIZE(highlander_i2c_devices));
+
+	return ret;
 }
 device_initcall(r7780rp_devices_setup);
 

arch/sh/boards/se/7721/Makefile

@@ -0,0 +1 @@
+obj-y	 := setup.o irq.o

arch/sh/boards/se/7721/irq.c

@@ -0,0 +1,45 @@
+/*
+ * linux/arch/sh/boards/se/7721/irq.c
+ *
+ * Copyright (C) 2008  Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <asm/se7721.h>
+
+enum {
+	UNUSED = 0,
+
+	/* board specific interrupt sources */
+	MRSHPC,
+};
+
+static struct intc_vect vectors[] __initdata = {
+	INTC_IRQ(MRSHPC, MRSHPC_IRQ0),
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+	{ FPGA_ILSR6, 0, 8, 4, /* IRLMSK */
+	  { 0, MRSHPC } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "SE7721", vectors,
+			 NULL, NULL, prio_registers, NULL);
+
+/*
+ * Initialize IRQ setting
+ */
+void __init init_se7721_IRQ(void)
+{
+	/* PPCR */
+	ctrl_outw(ctrl_inw(0xa4050118) & ~0x00ff, 0xa4050118);
+
+	register_intc_controller(&intc_desc);
+	intc_set_priority(MRSHPC_IRQ0, 0xf - MRSHPC_IRQ0);
+}

arch/sh/boards/se/7721/setup.c

@@ -0,0 +1,99 @@
+/*
+ * linux/arch/sh/boards/se/7721/setup.c
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * Hitachi UL SolutionEngine 7721 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <asm/machvec.h>
+#include <asm/se7721.h>
+#include <asm/io.h>
+#include <asm/heartbeat.h>
+
+static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
+
+static struct heartbeat_data heartbeat_data = {
+	.bit_pos	= heartbeat_bit_pos,
+	.nr_bits	= ARRAY_SIZE(heartbeat_bit_pos),
+	.regsize	= 16,
+};
+
+static struct resource heartbeat_resources[] = {
+	[0] = {
+		.start	= PA_LED,
+		.end	= PA_LED,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device heartbeat_device = {
+	.name		= "heartbeat",
+	.id		= -1,
+	.dev	= {
+		.platform_data	= &heartbeat_data,
+	},
+	.num_resources	= ARRAY_SIZE(heartbeat_resources),
+	.resource	= heartbeat_resources,
+};
+
+static struct resource cf_ide_resources[] = {
+	[0] = {
+		.start	= PA_MRSHPC_IO + 0x1f0,
+		.end	= PA_MRSHPC_IO + 0x1f0 + 8 ,
+		.flags	= IORESOURCE_IO,
+	},
+	[1] = {
+		.start	= PA_MRSHPC_IO + 0x1f0 + 0x206,
+		.end	= PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8,
+		.flags	= IORESOURCE_IO,
+	},
+	[2] = {
+		.start  = MRSHPC_IRQ0,
+		.flags  = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device cf_ide_device = {
+	.name		= "pata_platform",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(cf_ide_resources),
+	.resource	= cf_ide_resources,
+};
+
+static struct platform_device *se7721_devices[] __initdata = {
+	&cf_ide_device,
+	&heartbeat_device
+};
+
+static int __init se7721_devices_setup(void)
+{
+	return platform_add_devices(se7721_devices,
+		ARRAY_SIZE(se7721_devices));
+}
+device_initcall(se7721_devices_setup);
+
+static void __init se7721_setup(char **cmdline_p)
+{
+	/* for USB */
+	ctrl_outw(0x0000, 0xA405010C);	/* PGCR */
+	ctrl_outw(0x0000, 0xA405010E);	/* PHCR */
+	ctrl_outw(0x00AA, 0xA4050118);	/* PPCR */
+	ctrl_outw(0x0000, 0xA4050124);	/* PSELA */
+}
+
+/*
+ * The Machine Vector
+ */
+struct sh_machine_vector mv_se7721 __initmv = {
+	.mv_name		= "Solution Engine 7721",
+	.mv_setup		= se7721_setup,
+	.mv_nr_irqs		= 109,
+	.mv_init_irq		= init_se7721_IRQ,
+};

arch/sh/boards/se/7722/setup.c

@@ -13,10 +13,12 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
+#include <linux/input.h>
 #include <asm/machvec.h>
 #include <asm/se7722.h>
 #include <asm/io.h>
 #include <asm/heartbeat.h>
+#include <asm/sh_keysc.h>
 
 /* Heartbeat */
 static struct heartbeat_data heartbeat_data = {
@@ -92,10 +94,47 @@ static struct platform_device cf_ide_device  = {
 	.resource       = cf_ide_resources,
 };
 
+static struct sh_keysc_info sh_keysc_info = {
+	.mode = SH_KEYSC_MODE_1, /* KEYOUT0->5, KEYIN0->4 */
+	.scan_timing = 3,
+	.delay = 5,
+	.keycodes = { /* SW1 -> SW30 */
+		KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
+		KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
+		KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
+		KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T,
+		KEY_U, KEY_V, KEY_W, KEY_X, KEY_Y,
+		KEY_Z,
+		KEY_HOME, KEY_SLEEP, KEY_WAKEUP, KEY_COFFEE, /* life */
+	},
+};
+
+static struct resource sh_keysc_resources[] = {
+	[0] = {
+		.start  = 0x044b0000,
+		.end    = 0x044b000f,
+		.flags  = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start  = 79,
+		.flags  = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device sh_keysc_device = {
+	.name           = "sh_keysc",
+	.num_resources  = ARRAY_SIZE(sh_keysc_resources),
+	.resource       = sh_keysc_resources,
+	.dev	= {
+		.platform_data	= &sh_keysc_info,
+	},
+};
+
 static struct platform_device *se7722_devices[] __initdata = {
 	&heartbeat_device,
 	&smc91x_eth_device,
 	&cf_ide_device,
+	&sh_keysc_device,
 };
 
 static int __init se7722_devices_setup(void)
@@ -136,6 +175,8 @@ static void __init se7722_setup(char **cmdline_p)
 	ctrl_outw(0x0A10, PORT_PSELA); /* BS,SHHID2 */
 	ctrl_outw(0x0000, PORT_PYCR);
 	ctrl_outw(0x0000, PORT_PZCR);
+	ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
+	ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
 }
 
 /*

arch/sh/kernel/cf-enabler.c

@@ -83,6 +83,8 @@ static int __init cf_init_default(void)
 #include <asm/se.h>
 #elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
 #include <asm/se7722.h>
+#elif defined(CONFIG_SH_7721_SOLUTION_ENGINE)
+#include <asm/se7721.h>
 #endif
 
 /*
@@ -99,7 +101,9 @@ static int __init cf_init_default(void)
  * 0xB0600000 : I/O
  */
 
-#if defined(CONFIG_SH_SOLUTION_ENGINE) || defined(CONFIG_SH_7722_SOLUTION_ENGINE) 
+#if defined(CONFIG_SH_SOLUTION_ENGINE) || \
+    defined(CONFIG_SH_7722_SOLUTION_ENGINE) || \
+    defined(CONFIG_SH_7721_SOLUTION_ENGINE)
 static int __init cf_init_se(void)
 {
 	if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0)
@@ -112,7 +116,7 @@ static int __init cf_init_se(void)
 	}
 
 	/*
-	 *  PC-Card window open 
+	 *  PC-Card window open
 	 *  flag == COMMON/ATTRIBUTE/IO
 	 */
 	/* common window open */
@@ -122,7 +126,7 @@ static int __init cf_init_se(void)
 		ctrl_outw(0x0b00, MRSHPC_MW0CR2);
 	else
 		/* common mode & bus width 16bit SWAP = 0*/
-		ctrl_outw(0x0300, MRSHPC_MW0CR2); 
+		ctrl_outw(0x0300, MRSHPC_MW0CR2);
 
 	/* attribute window open */
 	ctrl_outw(0x8a85, MRSHPC_MW1CR1);
@@ -155,10 +159,9 @@ static int __init cf_init_se(void)
 
 int __init cf_init(void)
 {
-	if( mach_is_se() || mach_is_7722se() ){
+	if (mach_is_se() || mach_is_7722se() || mach_is_7721se())
 		return cf_init_se();
-	}
+
-	
 	return cf_init_default();
 }
 

arch/sh/kernel/cpu/sh2a/Makefile

@@ -8,6 +8,7 @@ common-y	+= $(addprefix ../sh2/, ex.o entry.o)
 
 obj-$(CONFIG_SH_FPU)	+= fpu.o
 
-obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7206)	+= setup-sh7206.o clock-sh7206.o
-obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7203)	+= setup-sh7203.o clock-sh7203.o
-obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7263)	+= setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_MXG)		+= setup-mxg.o clock-sh7206.o

arch/sh/kernel/cpu/sh2a/probe.c

@@ -29,6 +29,9 @@ int __init detect_cpu_and_cache_system(void)
 	boot_cpu_data.type			= CPU_SH7206;
 	/* While SH7206 has a DSP.. */
 	boot_cpu_data.flags			|= CPU_HAS_DSP;
+#elif defined(CONFIG_CPU_SUBTYPE_MXG)
+	boot_cpu_data.type			= CPU_MXG;
+	boot_cpu_data.flags			|= CPU_HAS_DSP;
 #endif
 
 	boot_cpu_data.dcache.ways		= 4;

arch/sh/kernel/cpu/sh2a/setup-mxg.c

@@ -0,0 +1,168 @@
+/*
+ * Renesas MX-G (R8A03022BG) Setup
+ *
+ *  Copyright (C) 2008  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/serial_sci.h>
+
+enum {
+	UNUSED = 0,
+
+	/* interrupt sources */
+	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+	IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
+
+	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
+
+	SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
+
+	SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
+	SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
+
+	MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
+	MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
+	MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
+	MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
+	MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
+	MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
+	MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
+
+	/* interrupt groups */
+	PINT, SCIF0, SCIF1,
+	MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
+};
+
+static struct intc_vect vectors[] __initdata = {
+	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
+	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
+	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
+	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
+	INTC_IRQ(IRQ8, 72), INTC_IRQ(IRQ9, 73),
+	INTC_IRQ(IRQ10, 74), INTC_IRQ(IRQ11, 75),
+	INTC_IRQ(IRQ12, 76), INTC_IRQ(IRQ13, 77),
+	INTC_IRQ(IRQ14, 78), INTC_IRQ(IRQ15, 79),
+
+	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
+	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
+	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
+	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
+
+	INTC_IRQ(SINT8, 94), INTC_IRQ(SINT7, 95),
+	INTC_IRQ(SINT6, 96), INTC_IRQ(SINT5, 97),
+	INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
+	INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
+
+	INTC_IRQ(SCIF0_RXI, 220), INTC_IRQ(SCIF0_TXI, 221),
+	INTC_IRQ(SCIF0_BRI, 222), INTC_IRQ(SCIF0_ERI, 223),
+	INTC_IRQ(SCIF1_RXI, 224), INTC_IRQ(SCIF1_TXI, 225),
+	INTC_IRQ(SCIF1_BRI, 226), INTC_IRQ(SCIF1_ERI, 227),
+
+	INTC_IRQ(MTU2_TGI0A, 228), INTC_IRQ(MTU2_TGI0B, 229),
+	INTC_IRQ(MTU2_TGI0C, 230), INTC_IRQ(MTU2_TGI0D, 231),
+	INTC_IRQ(MTU2_TCI0V, 232), INTC_IRQ(MTU2_TGI0E, 233),
+
+	INTC_IRQ(MTU2_TGI0F, 234), INTC_IRQ(MTU2_TGI1A, 235),
+	INTC_IRQ(MTU2_TGI1B, 236), INTC_IRQ(MTU2_TCI1V, 237),
+	INTC_IRQ(MTU2_TCI1U, 238), INTC_IRQ(MTU2_TGI2A, 239),
+
+	INTC_IRQ(MTU2_TGI2B, 240), INTC_IRQ(MTU2_TCI2V, 241),
+	INTC_IRQ(MTU2_TCI2U, 242), INTC_IRQ(MTU2_TGI3A, 243),
+
+	INTC_IRQ(MTU2_TGI3B, 244),
+	INTC_IRQ(MTU2_TGI3C, 245),
+
+	INTC_IRQ(MTU2_TGI3D, 246), INTC_IRQ(MTU2_TCI3V, 247),
+	INTC_IRQ(MTU2_TGI4A, 248), INTC_IRQ(MTU2_TGI4B, 249),
+	INTC_IRQ(MTU2_TGI4C, 250), INTC_IRQ(MTU2_TGI4D, 251),
+
+	INTC_IRQ(MTU2_TCI4V, 252), INTC_IRQ(MTU2_TGI5U, 253),
+	INTC_IRQ(MTU2_TGI5V, 254), INTC_IRQ(MTU2_TGI5W, 255),
+};
+
+static struct intc_group groups[] __initdata = {
+	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
+		   PINT4, PINT5, PINT6, PINT7),
+	INTC_GROUP(MTU2_GROUP1, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
+		   MTU2_TCI0V, MTU2_TGI0E),
+	INTC_GROUP(MTU2_GROUP2, MTU2_TGI0F, MTU2_TGI1A, MTU2_TGI1B,
+		   MTU2_TCI1V, MTU2_TCI1U, MTU2_TGI2A),
+	INTC_GROUP(MTU2_GROUP3, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
+		   MTU2_TGI3A),
+	INTC_GROUP(MTU2_GROUP4, MTU2_TGI3D, MTU2_TCI3V, MTU2_TGI4A,
+		   MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
+	INTC_GROUP(MTU2_GROUP5, MTU2_TCI4V, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
+	INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
+	INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+	{ 0xfffd9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
+	{ 0xfffd941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
+	{ 0xfffd941c, 0, 16, 4, /* IPR03 */ { IRQ8, IRQ9, IRQ10, IRQ11 } },
+	{ 0xfffd941e, 0, 16, 4, /* IPR04 */ { IRQ12, IRQ13, IRQ14, IRQ15 } },
+	{ 0xfffd9420, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
+	{ 0xfffd9800, 0, 16, 4, /* IPR06 */ { } },
+	{ 0xfffd9802, 0, 16, 4, /* IPR07 */ { } },
+	{ 0xfffd9804, 0, 16, 4, /* IPR08 */ { } },
+	{ 0xfffd9806, 0, 16, 4, /* IPR09 */ { } },
+	{ 0xfffd9808, 0, 16, 4, /* IPR10 */ { } },
+	{ 0xfffd980a, 0, 16, 4, /* IPR11 */ { } },
+	{ 0xfffd980c, 0, 16, 4, /* IPR12 */ { } },
+	{ 0xfffd980e, 0, 16, 4, /* IPR13 */ { } },
+	{ 0xfffd9810, 0, 16, 4, /* IPR14 */ { 0, 0, 0, SCIF0 } },
+	{ 0xfffd9812, 0, 16, 4, /* IPR15 */
+		{ SCIF1, MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3 } },
+	{ 0xfffd9814, 0, 16, 4, /* IPR16 */
+		{ MTU2_TGI3B, MTU2_TGI3C, MTU2_GROUP4, MTU2_GROUP5 } },
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+	{ 0xfffd9408, 0, 16, /* PINTER */
+	  { 0, 0, 0, 0, 0, 0, 0, 0,
+	    PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
+			 mask_registers, prio_registers, NULL);
+
+static struct plat_sci_port sci_platform_data[] = {
+	{
+		.mapbase	= 0xff804000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 223, 220, 221, 222 },
+	}, {
+		.flags = 0,
+	}
+};
+
+static struct platform_device sci_device = {
+	.name		= "sh-sci",
+	.id		= -1,
+	.dev		= {
+		.platform_data	= sci_platform_data,
+	},
+};
+
+static struct platform_device *mxg_devices[] __initdata = {
+	&sci_device,
+};
+
+static int __init mxg_devices_setup(void)
+{
+	return platform_add_devices(mxg_devices,
+				    ARRAY_SIZE(mxg_devices));
+}
+__initcall(mxg_devices_setup);
+
+void __init plat_irq_setup(void)
+{
+	register_intc_controller(&intc_desc);
+}

arch/sh/kernel/cpu/sh4/probe.c

@@ -53,7 +53,7 @@ int __init detect_cpu_and_cache_system(void)
 	/*
 	 * Setup some generic flags we can probe on SH-4A parts
 	 */
-	if (((pvr >> 16) & 0xff) == 0x10) {
+	if (((pvr >> 24) & 0xff) == 0x10) {
 		if ((cvr & 0x10000000) == 0)
 			boot_cpu_data.flags |= CPU_HAS_DSP;
 
@@ -126,17 +126,22 @@ int __init detect_cpu_and_cache_system(void)
 					  CPU_HAS_LLSC;
 		break;
 	case 0x3008:
-		if (prr == 0xa0 || prr == 0xa1) {
+		boot_cpu_data.icache.ways = 4;
-			boot_cpu_data.type = CPU_SH7722;
+		boot_cpu_data.dcache.ways = 4;
-			boot_cpu_data.icache.ways = 4;
+		boot_cpu_data.flags |= CPU_HAS_LLSC;
-			boot_cpu_data.dcache.ways = 4;
+
-			boot_cpu_data.flags |= CPU_HAS_LLSC;
+		switch (prr) {
-		}
+		case 0x50:
-		else if (prr == 0x70) {
+			boot_cpu_data.type = CPU_SH7723;
+			boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE;
+			break;
+		case 0x70:
 			boot_cpu_data.type = CPU_SH7366;
-			boot_cpu_data.icache.ways = 4;
+			break;
-			boot_cpu_data.dcache.ways = 4;
+		case 0xa0:
-			boot_cpu_data.flags |= CPU_HAS_LLSC;
+		case 0xa1:
+			boot_cpu_data.type = CPU_SH7722;
+			break;
 		}
 		break;
 	case 0x4000:	/* 1st cut */
@@ -215,6 +220,12 @@ int __init detect_cpu_and_cache_system(void)
 	 * SH-4A's have an optional PIPT L2.
 	 */
 	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
+		/* Bug if we can't decode the L2 info */
+		BUG_ON(!(cvr & 0xf));
+
+		/* Silicon and specifications have clearly never met.. */
+		cvr ^= 0xf;
+
 		/*
 		 * Size calculation is much more sensible
 		 * than it is for the L1.

arch/sh/kernel/cpu/sh4a/Makefile

@@ -9,6 +9,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7780)	+= setup-sh7780.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7785)	+= setup-sh7785.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7343)	+= setup-sh7343.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7722)	+= setup-sh7722.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7723)	+= setup-sh7723.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7366)	+= setup-sh7366.o
 obj-$(CONFIG_CPU_SUBTYPE_SHX3)		+= setup-shx3.o
 
@@ -22,6 +23,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7780)	:= clock-sh7780.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7785)	:= clock-sh7785.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7343)	:= clock-sh7343.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7722)	:= clock-sh7722.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7723)	:= clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7366)	:= clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SHX3)	:= clock-shx3.o
 

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

@@ -16,13 +16,12 @@
 
 static struct resource usbf_resources[] = {
 	[0] = {
-		.name	= "m66592_udc",
+		.name	= "USBF",
-		.start	= 0xA4480000,
+		.start	= 0x04480000,
-		.end	= 0xA44800FF,
+		.end	= 0x044800FF,
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.name	= "m66592_udc",
 		.start	= 65,
 		.end	= 65,
 		.flags	= IORESOURCE_IRQ,
@@ -40,6 +39,26 @@ static struct platform_device usbf_device = {
 	.resource	= usbf_resources,
 };
 
+static struct resource iic_resources[] = {
+	[0] = {
+		.name	= "IIC",
+		.start  = 0x04470000,
+		.end    = 0x04470017,
+		.flags  = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start  = 96,
+		.end    = 99,
+		.flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device iic_device = {
+	.name           = "i2c-sh_mobile",
+	.num_resources  = ARRAY_SIZE(iic_resources),
+	.resource       = iic_resources,
+};
+
 static struct plat_sci_port sci_platform_data[] = {
 	{
 		.mapbase	= 0xffe00000,
@@ -74,6 +93,7 @@ static struct platform_device sci_device = {
 
 static struct platform_device *sh7722_devices[] __initdata = {
 	&usbf_device,
+	&iic_device,
 	&sci_device,
 };
 

arch/sh/kernel/cpu/sh4a/setup-sh7723.c

@@ -0,0 +1,300 @@
+/*
+ * SH7723 Setup
+ *
+ *  Copyright (C) 2008  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/mm.h>
+#include <linux/serial_sci.h>
+#include <asm/mmzone.h>
+
+static struct plat_sci_port sci_platform_data[] = {
+	{
+		.mapbase	= 0xa4e30000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCI,
+		.irqs		= { 56, 56, 56, 56 },
+	},{
+		.mapbase	= 0xa4e40000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCI,
+		.irqs		= { 88, 88, 88, 88 },
+	},{
+		.mapbase	= 0xa4e50000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCI,
+		.irqs		= { 109, 109, 109, 109 },
+	}, {
+		.flags = 0,
+	}
+};
+
+static struct platform_device sci_device = {
+	.name		= "sh-sci",
+	.id		= -1,
+	.dev		= {
+		.platform_data	= sci_platform_data,
+	},
+};
+
+static struct resource rtc_resources[] = {
+	[0] = {
+		.start	= 0xa465fec0,
+		.end	= 0xa465fec0 + 0x58 - 1,
+		.flags	= IORESOURCE_IO,
+	},
+	[1] = {
+		/* Period IRQ */
+		.start	= 69,
+		.flags	= IORESOURCE_IRQ,
+	},
+	[2] = {
+		/* Carry IRQ */
+		.start	= 70,
+		.flags	= IORESOURCE_IRQ,
+	},
+	[3] = {
+		/* Alarm IRQ */
+		.start	= 68,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device rtc_device = {
+	.name		= "sh-rtc",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(rtc_resources),
+	.resource	= rtc_resources,
+};
+
+static struct platform_device *sh7723_devices[] __initdata = {
+	&sci_device,
+	&rtc_device,
+};
+
+static int __init sh7723_devices_setup(void)
+{
+	return platform_add_devices(sh7723_devices,
+				    ARRAY_SIZE(sh7723_devices));
+}
+__initcall(sh7723_devices_setup);
+
+enum {
+	UNUSED=0,
+
+	/* interrupt sources */
+	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+	HUDI,
+	DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
+	_2DG_TRI,_2DG_INI,_2DG_CEI,
+	DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
+	VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
+	SCIFA_SCIFA0,
+	VPU_VPUI,
+	TPU_TPUI,
+	ADC_ADI,
+	USB_USI0,
+	RTC_ATI,RTC_PRI,RTC_CUI,
+	DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
+	DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
+	KEYSC_KEYI,
+	SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
+	MSIOF_MSIOFI0,MSIOF_MSIOFI1,
+	SCIFA_SCIFA1,
+	FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
+	I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
+	SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
+	CMT_CMTI,
+	TSIF_TSIFI,
+	SIU_SIUI,
+	SCIFA_SCIFA2,
+	TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
+	IRDA_IRDAI,
+	ATAPI_ATAPII,
+	SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
+	VEU2H1_VEU2HI,
+	LCDC_LCDCI,
+	TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
+
+	/* interrupt groups */
+	DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
+	SDHI1, RTC, DMAC1B, SDHI0,
+};
+
+static struct intc_vect vectors[] __initdata = {
+	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
+	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
+	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
+	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
+
+	INTC_VECT(DMAC1A_DEI0,0x700),
+	INTC_VECT(DMAC1A_DEI1,0x720),
+	INTC_VECT(DMAC1A_DEI2,0x740),
+	INTC_VECT(DMAC1A_DEI3,0x760),
+
+	INTC_VECT(_2DG_TRI, 0x780),
+	INTC_VECT(_2DG_INI, 0x7A0),
+	INTC_VECT(_2DG_CEI, 0x7C0),
+
+	INTC_VECT(DMAC0A_DEI0,0x800),
+	INTC_VECT(DMAC0A_DEI1,0x820),
+	INTC_VECT(DMAC0A_DEI2,0x840),
+	INTC_VECT(DMAC0A_DEI3,0x860),
+
+	INTC_VECT(VIO_CEUI,0x880),
+	INTC_VECT(VIO_BEUI,0x8A0),
+	INTC_VECT(VIO_VEU2HI,0x8C0),
+	INTC_VECT(VIO_VOUI,0x8E0),
+
+	INTC_VECT(SCIFA_SCIFA0,0x900),
+	INTC_VECT(VPU_VPUI,0x920),
+	INTC_VECT(TPU_TPUI,0x9A0),
+	INTC_VECT(ADC_ADI,0x9E0),
+	INTC_VECT(USB_USI0,0xA20),
+
+	INTC_VECT(RTC_ATI,0xA80),
+	INTC_VECT(RTC_PRI,0xAA0),
+	INTC_VECT(RTC_CUI,0xAC0),
+
+	INTC_VECT(DMAC1B_DEI4,0xB00),
+	INTC_VECT(DMAC1B_DEI5,0xB20),
+	INTC_VECT(DMAC1B_DADERR,0xB40),
+
+	INTC_VECT(DMAC0B_DEI4,0xB80),
+	INTC_VECT(DMAC0B_DEI5,0xBA0),
+	INTC_VECT(DMAC0B_DADERR,0xBC0),
+
+	INTC_VECT(KEYSC_KEYI,0xBE0),
+	INTC_VECT(SCIF_SCIF0,0xC00),
+	INTC_VECT(SCIF_SCIF1,0xC20),
+	INTC_VECT(SCIF_SCIF2,0xC40),
+	INTC_VECT(MSIOF_MSIOFI0,0xC80),
+	INTC_VECT(MSIOF_MSIOFI1,0xCA0),
+	INTC_VECT(SCIFA_SCIFA1,0xD00),
+
+	INTC_VECT(FLCTL_FLSTEI,0xD80),
+	INTC_VECT(FLCTL_FLTENDI,0xDA0),
+	INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
+	INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
+
+	INTC_VECT(I2C_ALI,0xE00),
+	INTC_VECT(I2C_TACKI,0xE20),
+	INTC_VECT(I2C_WAITI,0xE40),
+	INTC_VECT(I2C_DTEI,0xE60),
+
+	INTC_VECT(SDHI0_SDHII0,0xE80),
+	INTC_VECT(SDHI0_SDHII1,0xEA0),
+	INTC_VECT(SDHI0_SDHII2,0xEC0),
+
+	INTC_VECT(CMT_CMTI,0xF00),
+	INTC_VECT(TSIF_TSIFI,0xF20),
+	INTC_VECT(SIU_SIUI,0xF80),
+	INTC_VECT(SCIFA_SCIFA2,0xFA0),
+
+	INTC_VECT(TMU0_TUNI0,0x400),
+	INTC_VECT(TMU0_TUNI1,0x420),
+	INTC_VECT(TMU0_TUNI2,0x440),
+
+	INTC_VECT(IRDA_IRDAI,0x480),
+	INTC_VECT(ATAPI_ATAPII,0x4A0),
+
+	INTC_VECT(SDHI1_SDHII0,0x4E0),
+	INTC_VECT(SDHI1_SDHII1,0x500),
+	INTC_VECT(SDHI1_SDHII2,0x520),
+
+	INTC_VECT(VEU2H1_VEU2HI,0x560),
+	INTC_VECT(LCDC_LCDCI,0x580),
+
+	INTC_VECT(TMU1_TUNI0,0x920),
+	INTC_VECT(TMU1_TUNI1,0x940),
+	INTC_VECT(TMU1_TUNI2,0x960),
+
+};
+
+static struct intc_group groups[] __initdata = {
+	INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
+	INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
+	INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
+	INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
+	INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
+	INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
+	INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
+	INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
+	INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
+	INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
+	INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
+	  { 0,  TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
+	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
+	  { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
+	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
+	  { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
+	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
+	  { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
+	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
+	  { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
+	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
+	  { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
+	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
+	  { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
+	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
+	  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
+	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
+	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
+	  { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
+	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
+	  { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
+	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
+	  { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
+	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
+	  { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
+	{ 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
+	  { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
+	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
+	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
+	{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
+	{ 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
+	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
+	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
+	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
+	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
+	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
+	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
+	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
+	{ 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
+	{ 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
+	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
+	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_sense_reg sense_registers[] __initdata = {
+	{ 0xa414001c, 16, 2, /* ICR1 */
+	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh7723", vectors, groups,
+			 mask_registers, prio_registers, sense_registers);
+
+void __init plat_irq_setup(void)
+{
+	register_intc_controller(&intc_desc);
+}
+
+void __init plat_mem_setup(void)
+{
+	/* Register the URAM space as Node 1 */
+	setup_bootmem_node(1, 0x055f0000, 0x05610000);
+}

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

@@ -231,12 +231,6 @@ static struct intc_group groups[] __initdata = {
 	INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3),
 };
 
-static struct intc_prio priorities[] __initdata = {
-	INTC_PRIO(SCIF0, 3),
-	INTC_PRIO(SCIF1, 3),
-	INTC_PRIO(SCIF2, 3),
-};
-
 static struct intc_mask_reg mask_registers[] __initdata = {
 	{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 	  { 0, 0, 0, 0, 0, 0, GPIO, 0,
@@ -270,11 +264,10 @@ static struct intc_prio_reg prio_registers[] __initdata = {
 	{ 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
 };
 
-static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups, priorities,
+static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
 			 mask_registers, prio_registers, NULL);
 
 /* Support for external interrupt pins in IRQ mode */
-
 static struct intc_vect irq_vectors[] __initdata = {
 	INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 	INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
@@ -302,7 +295,6 @@ static DECLARE_INTC_DESC(intc_irq_desc, "sh7763-irq", irq_vectors,
 			 irq_sense_registers);
 
 /* External interrupt pins in IRL mode */
-
 static struct intc_vect irl_vectors[] __initdata = {
 	INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 	INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),

arch/sh/kernel/cpu/sh4a/setup-sh7770.c

@@ -1,7 +1,7 @@
 /*
  * SH7770 Setup
  *
- *  Copyright (C) 2006  Paul Mundt
+ *  Copyright (C) 2006 - 2008  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -28,6 +28,41 @@ static struct plat_sci_port sci_platform_data[] = {
 		.flags		= UPF_BOOT_AUTOCONF,
 		.type		= PORT_SCIF,
 		.irqs		= { 63, 63, 63, 63 },
+	}, {
+		.mapbase	= 0xff926000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 64, 64, 64, 64 },
+	}, {
+		.mapbase	= 0xff927000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 65, 65, 65, 65 },
+	}, {
+		.mapbase	= 0xff928000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 66, 66, 66, 66 },
+	}, {
+		.mapbase	= 0xff929000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 67, 67, 67, 67 },
+	}, {
+		.mapbase	= 0xff92a000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 68, 68, 68, 68 },
+	}, {
+		.mapbase	= 0xff92b000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 69, 69, 69, 69 },
+	}, {
+		.mapbase	= 0xff92c000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 70, 70, 70, 70 },
 	}, {
 		.flags = 0,
 	}

arch/sh/kernel/setup.c

@@ -23,6 +23,8 @@
 #include <linux/kexec.h>
 #include <linux/module.h>
 #include <linux/smp.h>
+#include <linux/err.h>
+#include <linux/debugfs.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/page.h>
@@ -333,6 +335,7 @@ static const char *cpu_name[] = {
 	[CPU_SH7343]	= "SH7343",	[CPU_SH7785]	= "SH7785",
 	[CPU_SH7722]	= "SH7722",	[CPU_SHX3]	= "SH-X3",
 	[CPU_SH5_101]	= "SH5-101",	[CPU_SH5_103]	= "SH5-103",
+	[CPU_MXG]	= "MX-G",	[CPU_SH7723]	= "SH7723",
 	[CPU_SH7366]	= "SH7366",	[CPU_SH_NONE]	= "Unknown"
 };
 
@@ -443,3 +446,15 @@ const struct seq_operations cpuinfo_op = {
 	.show	= show_cpuinfo,
 };
 #endif /* CONFIG_PROC_FS */
+
+struct dentry *sh_debugfs_root;
+
+static int __init sh_debugfs_init(void)
+{
+	sh_debugfs_root = debugfs_create_dir("sh", NULL);
+	if (IS_ERR(sh_debugfs_root))
+		return PTR_ERR(sh_debugfs_root);
+
+	return 0;
+}
+arch_initcall(sh_debugfs_init);

arch/sh/lib/clear_page.S

@@ -27,11 +27,11 @@ ENTRY(clear_page)
 	mov	#0,r0
 	!
 1:
-#if defined(CONFIG_CPU_SH3)
+#if defined(CONFIG_CPU_SH4)
-	mov.l	r0,@r4
-#elif defined(CONFIG_CPU_SH4)
 	movca.l	r0,@r4
 	mov	r4,r1
+#else
+	mov.l	r0,@r4
 #endif
 	add	#32,r4
 	mov.l	r0,@-r4

arch/sh/lib/copy_page.S

@@ -41,11 +41,11 @@ ENTRY(copy_page)
 	mov.l	@r11+,r5
 	mov.l	@r11+,r6
 	mov.l	@r11+,r7
-#if defined(CONFIG_CPU_SH3)
+#if defined(CONFIG_CPU_SH4)
-	mov.l	r0,@r10
-#elif defined(CONFIG_CPU_SH4)
 	movca.l	r0,@r10
 	mov	r10,r0
+#else
+	mov.l	r0,@r10
 #endif
 	add	#32,r10
 	mov.l	r7,@-r10

arch/sh/mm/cache-debugfs.c

@@ -127,13 +127,13 @@ static int __init cache_debugfs_init(void)
 {
 	struct dentry *dcache_dentry, *icache_dentry;
 
-	dcache_dentry = debugfs_create_file("dcache", S_IRUSR, NULL,
+	dcache_dentry = debugfs_create_file("dcache", S_IRUSR, sh_debugfs_root,
 					    (unsigned int *)CACHE_TYPE_DCACHE,
 					    &cache_debugfs_fops);
 	if (IS_ERR(dcache_dentry))
 		return PTR_ERR(dcache_dentry);
 
-	icache_dentry = debugfs_create_file("icache", S_IRUSR, NULL,
+	icache_dentry = debugfs_create_file("icache", S_IRUSR, sh_debugfs_root,
 					    (unsigned int *)CACHE_TYPE_ICACHE,
 					    &cache_debugfs_fops);
 	if (IS_ERR(icache_dentry)) {

arch/sh/mm/pmb.c

@@ -393,7 +393,7 @@ static int __init pmb_debugfs_init(void)
 	struct dentry *dentry;
 
 	dentry = debugfs_create_file("pmb", S_IFREG | S_IRUGO,
-				     NULL, NULL, &pmb_debugfs_fops);
+				     sh_debugfs_root, NULL, &pmb_debugfs_fops);
 	if (IS_ERR(dentry))
 		return PTR_ERR(dentry);
 

arch/sh/tools/mach-types

@@ -21,8 +21,9 @@ HD64465			HD64465
 7206SE			SH_7206_SOLUTION_ENGINE
 7343SE			SH_7343_SOLUTION_ENGINE
 7619SE			SH_7619_SOLUTION_ENGINE
-7722SE			SH_7722_SOLUTION_ENGINE		
+7721SE			SH_7721_SOLUTION_ENGINE
-7751SE			SH_7751_SOLUTION_ENGINE		
+7722SE			SH_7722_SOLUTION_ENGINE
+7751SE			SH_7751_SOLUTION_ENGINE
 7780SE			SH_7780_SOLUTION_ENGINE
 7751SYSTEMH		SH_7751_SYSTEMH
 HP6XX			SH_HP6XX

drivers/input/keyboard/Kconfig

@@ -314,4 +314,13 @@ config KEYBOARD_BFIN
 	  To compile this driver as a module, choose M here: the
 	  module will be called bf54x-keys.
 
+config KEYBOARD_SH_KEYSC
+	tristate "SuperH KEYSC keypad support"
+	depends on SUPERH
+	help
+	  Say Y here if you want to use a keypad attached to the KEYSC block
+	  on SuperH processors such as sh7722 and sh7343.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called sh_keysc.
 endif

drivers/input/keyboard/Makefile

@@ -26,3 +26,4 @@ obj-$(CONFIG_KEYBOARD_HP6XX)		+= jornada680_kbd.o
 obj-$(CONFIG_KEYBOARD_HP7XX)		+= jornada720_kbd.o
 obj-$(CONFIG_KEYBOARD_MAPLE)		+= maple_keyb.o
 obj-$(CONFIG_KEYBOARD_BFIN)		+= bf54x-keys.o
+obj-$(CONFIG_KEYBOARD_SH_KEYSC)		+= sh_keysc.o

drivers/input/keyboard/sh_keysc.c

@@ -0,0 +1,280 @@
+/*
+ * SuperH KEYSC Keypad Driver
+ *
+ * Copyright (C) 2008 Magnus Damm
+ *
+ * Based on gpio_keys.c, Copyright 2005 Phil Blundell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <asm/sh_keysc.h>
+
+#define KYCR1_OFFS   0x00
+#define KYCR2_OFFS   0x04
+#define KYINDR_OFFS  0x08
+#define KYOUTDR_OFFS 0x0c
+
+#define KYCR2_IRQ_LEVEL    0x10
+#define KYCR2_IRQ_DISABLED 0x00
+
+static const struct {
+	unsigned char kymd, keyout, keyin;
+} sh_keysc_mode[] = {
+	[SH_KEYSC_MODE_1] = { 0, 6, 5 },
+	[SH_KEYSC_MODE_2] = { 1, 5, 6 },
+	[SH_KEYSC_MODE_3] = { 2, 4, 7 },
+};
+
+struct sh_keysc_priv {
+	void __iomem *iomem_base;
+	unsigned long last_keys;
+	struct input_dev *input;
+	struct sh_keysc_info pdata;
+};
+
+static irqreturn_t sh_keysc_isr(int irq, void *dev_id)
+{
+	struct platform_device *pdev = dev_id;
+	struct sh_keysc_priv *priv = platform_get_drvdata(pdev);
+	struct sh_keysc_info *pdata = &priv->pdata;
+	unsigned long keys, keys1, keys0, mask;
+	unsigned char keyin_set, tmp;
+	int i, k;
+
+	dev_dbg(&pdev->dev, "isr!\n");
+
+	keys1 = ~0;
+	keys0 = 0;
+
+	do {
+		keys = 0;
+		keyin_set = 0;
+
+		iowrite16(KYCR2_IRQ_DISABLED, priv->iomem_base + KYCR2_OFFS);
+
+		for (i = 0; i < sh_keysc_mode[pdata->mode].keyout; i++) {
+			iowrite16(0xfff ^ (3 << (i * 2)),
+				  priv->iomem_base + KYOUTDR_OFFS);
+			udelay(pdata->delay);
+			tmp = ioread16(priv->iomem_base + KYINDR_OFFS);
+			keys |= tmp << (sh_keysc_mode[pdata->mode].keyin * i);
+			tmp ^= (1 << sh_keysc_mode[pdata->mode].keyin) - 1;
+			keyin_set |= tmp;
+		}
+
+		iowrite16(0, priv->iomem_base + KYOUTDR_OFFS);
+		iowrite16(KYCR2_IRQ_LEVEL | (keyin_set << 8),
+			  priv->iomem_base + KYCR2_OFFS);
+
+		keys ^= ~0;
+		keys &= (1 << (sh_keysc_mode[pdata->mode].keyin *
+			       sh_keysc_mode[pdata->mode].keyout)) - 1;
+		keys1 &= keys;
+		keys0 |= keys;
+
+		dev_dbg(&pdev->dev, "keys 0x%08lx\n", keys);
+
+	} while (ioread16(priv->iomem_base + KYCR2_OFFS) & 0x01);
+
+	dev_dbg(&pdev->dev, "last_keys 0x%08lx keys0 0x%08lx keys1 0x%08lx\n",
+		priv->last_keys, keys0, keys1);
+
+	for (i = 0; i < SH_KEYSC_MAXKEYS; i++) {
+		k = pdata->keycodes[i];
+		if (!k)
+			continue;
+
+		mask = 1 << i;
+
+		if (!((priv->last_keys ^ keys0) & mask))
+			continue;
+
+		if ((keys1 | keys0) & mask) {
+			input_event(priv->input, EV_KEY, k, 1);
+			priv->last_keys |= mask;
+		}
+
+		if (!(keys1 & mask)) {
+			input_event(priv->input, EV_KEY, k, 0);
+			priv->last_keys &= ~mask;
+		}
+
+	}
+	input_sync(priv->input);
+
+	return IRQ_HANDLED;
+}
+
+#define res_size(res) ((res)->end - (res)->start + 1)
+
+static int __devinit sh_keysc_probe(struct platform_device *pdev)
+{
+	struct sh_keysc_priv *priv;
+	struct sh_keysc_info *pdata;
+	struct resource *res;
+	struct input_dev *input;
+	int i, k;
+	int irq, error;
+
+	if (!pdev->dev.platform_data) {
+		dev_err(&pdev->dev, "no platform data defined\n");
+		error = -EINVAL;
+		goto err0;
+	}
+
+	error = -ENXIO;
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "failed to get I/O memory\n");
+		goto err0;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "failed to get irq\n");
+		goto err0;
+	}
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (priv == NULL) {
+		dev_err(&pdev->dev, "failed to allocate driver data\n");
+		error = -ENOMEM;
+		goto err0;
+	}
+
+	platform_set_drvdata(pdev, priv);
+	memcpy(&priv->pdata, pdev->dev.platform_data, sizeof(priv->pdata));
+	pdata = &priv->pdata;
+
+	res = request_mem_region(res->start, res_size(res), pdev->name);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "failed to request I/O memory\n");
+		error = -EBUSY;
+		goto err1;
+	}
+
+	priv->iomem_base = ioremap_nocache(res->start, res_size(res));
+	if (priv->iomem_base == NULL) {
+		dev_err(&pdev->dev, "failed to remap I/O memory\n");
+		error = -ENXIO;
+		goto err2;
+	}
+
+	priv->input = input_allocate_device();
+	if (!priv->input) {
+		dev_err(&pdev->dev, "failed to allocate input device\n");
+		error = -ENOMEM;
+		goto err3;
+	}
+
+	input = priv->input;
+	input->evbit[0] = BIT_MASK(EV_KEY);
+
+	input->name = pdev->name;
+	input->phys = "sh-keysc-keys/input0";
+	input->dev.parent = &pdev->dev;
+
+	input->id.bustype = BUS_HOST;
+	input->id.vendor = 0x0001;
+	input->id.product = 0x0001;
+	input->id.version = 0x0100;
+
+	error = request_irq(irq, sh_keysc_isr, 0, pdev->name, pdev);
+	if (error) {
+		dev_err(&pdev->dev, "failed to request IRQ\n");
+		goto err4;
+	}
+
+	for (i = 0; i < SH_KEYSC_MAXKEYS; i++) {
+		k = pdata->keycodes[i];
+		if (k)
+			input_set_capability(input, EV_KEY, k);
+	}
+
+	error = input_register_device(input);
+	if (error) {
+		dev_err(&pdev->dev, "failed to register input device\n");
+		goto err5;
+	}
+
+	iowrite16((sh_keysc_mode[pdata->mode].kymd << 8) |
+		  pdata->scan_timing, priv->iomem_base + KYCR1_OFFS);
+	iowrite16(0, priv->iomem_base + KYOUTDR_OFFS);
+	iowrite16(KYCR2_IRQ_LEVEL, priv->iomem_base + KYCR2_OFFS);
+	return 0;
+ err5:
+	free_irq(irq, pdev);
+ err4:
+	input_free_device(input);
+ err3:
+	iounmap(priv->iomem_base);
+ err2:
+	release_mem_region(res->start, res_size(res));
+ err1:
+	platform_set_drvdata(pdev, NULL);
+	kfree(priv);
+ err0:
+	return error;
+}
+
+static int __devexit sh_keysc_remove(struct platform_device *pdev)
+{
+	struct sh_keysc_priv *priv = platform_get_drvdata(pdev);
+	struct resource *res;
+
+	iowrite16(KYCR2_IRQ_DISABLED, priv->iomem_base + KYCR2_OFFS);
+
+	input_unregister_device(priv->input);
+	free_irq(platform_get_irq(pdev, 0), pdev);
+	iounmap(priv->iomem_base);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(res->start, res_size(res));
+
+	platform_set_drvdata(pdev, NULL);
+	kfree(priv);
+	return 0;
+}
+
+
+#define sh_keysc_suspend NULL
+#define sh_keysc_resume NULL
+
+struct platform_driver sh_keysc_device_driver = {
+	.probe		= sh_keysc_probe,
+	.remove		= __devexit_p(sh_keysc_remove),
+	.suspend	= sh_keysc_suspend,
+	.resume		= sh_keysc_resume,
+	.driver		= {
+		.name	= "sh_keysc",
+	}
+};
+
+static int __init sh_keysc_init(void)
+{
+	return platform_driver_register(&sh_keysc_device_driver);
+}
+
+static void __exit sh_keysc_exit(void)
+{
+	platform_driver_unregister(&sh_keysc_device_driver);
+}
+
+module_init(sh_keysc_init);
+module_exit(sh_keysc_exit);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("SuperH KEYSC Keypad Driver");
+MODULE_LICENSE("GPL");

drivers/rtc/rtc-sh.c

@@ -1,8 +1,9 @@
 /*
  * SuperH On-Chip RTC Support
  *
- * Copyright (C) 2006, 2007  Paul Mundt
+ * Copyright (C) 2006, 2007, 2008  Paul Mundt
  * Copyright (C) 2006  Jamie Lenehan
+ * Copyright (C) 2008  Angelo Castello
  *
  * Based on the old arch/sh/kernel/cpu/rtc.c by:
  *
@@ -26,7 +27,7 @@
 #include <asm/rtc.h>
 
 #define DRV_NAME	"sh-rtc"
-#define DRV_VERSION	"0.1.6"
+#define DRV_VERSION	"0.2.0"
 
 #define RTC_REG(r)	((r) * rtc_reg_size)
 
@@ -63,6 +64,13 @@
 /* ALARM Bits - or with BCD encoded value */
 #define AR_ENB		0x80	/* Enable for alarm cmp   */
 
+/* Period Bits */
+#define PF_HP		0x100	/* Enable Half Period to support 8,32,128Hz */
+#define PF_COUNT	0x200	/* Half periodic counter */
+#define PF_OXS		0x400	/* Periodic One x Second */
+#define PF_KOU		0x800	/* Kernel or User periodic request 1=kernel */
+#define PF_MASK		0xf00
+
 /* RCR1 Bits */
 #define RCR1_CF		0x80	/* Carry Flag             */
 #define RCR1_CIE	0x10	/* Carry Interrupt Enable */
@@ -84,33 +92,24 @@ struct sh_rtc {
 	unsigned int alarm_irq, periodic_irq, carry_irq;
 	struct rtc_device *rtc_dev;
 	spinlock_t lock;
-	int rearm_aie;
 	unsigned long capabilities;	/* See asm-sh/rtc.h for cap bits */
+	unsigned short periodic_freq;
 };
 
 static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
 {
-	struct platform_device *pdev = to_platform_device(dev_id);
+	struct sh_rtc *rtc = dev_id;
-	struct sh_rtc *rtc = platform_get_drvdata(pdev);
+	unsigned int tmp;
-	unsigned int tmp, events = 0;
 
 	spin_lock(&rtc->lock);
 
 	tmp = readb(rtc->regbase + RCR1);
 	tmp &= ~RCR1_CF;
-
-	if (rtc->rearm_aie) {
-		if (tmp & RCR1_AF)
-			tmp &= ~RCR1_AF;	/* try to clear AF again */
-		else {
-			tmp |= RCR1_AIE;	/* AF has cleared, rearm IRQ */
-			rtc->rearm_aie = 0;
-		}
-	}
-
 	writeb(tmp, rtc->regbase + RCR1);
 
-	rtc_update_irq(rtc->rtc_dev, 1, events);
+	/* Users have requested One x Second IRQ */
+	if (rtc->periodic_freq & PF_OXS)
+		rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
 
 	spin_unlock(&rtc->lock);
 
@@ -119,47 +118,48 @@ static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
 
 static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
 {
-	struct platform_device *pdev = to_platform_device(dev_id);
+	struct sh_rtc *rtc = dev_id;
-	struct sh_rtc *rtc = platform_get_drvdata(pdev);
+	unsigned int tmp;
-	unsigned int tmp, events = 0;
 
 	spin_lock(&rtc->lock);
 
 	tmp = readb(rtc->regbase + RCR1);
-
+	tmp &= ~(RCR1_AF | RCR1_AIE);
-	/*
-	 * If AF is set then the alarm has triggered. If we clear AF while
-	 * the alarm time still matches the RTC time then AF will
-	 * immediately be set again, and if AIE is enabled then the alarm
-	 * interrupt will immediately be retrigger. So we clear AIE here
-	 * and use rtc->rearm_aie so that the carry interrupt will keep
-	 * trying to clear AF and once it stays cleared it'll re-enable
-	 * AIE.
-	 */
-	if (tmp & RCR1_AF) {
-		events |= RTC_AF | RTC_IRQF;
-
-		tmp &= ~(RCR1_AF|RCR1_AIE);
-
 		writeb(tmp, rtc->regbase + RCR1);
 
-		rtc->rearm_aie = 1;
+	rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
-
-		rtc_update_irq(rtc->rtc_dev, 1, events);
-	}
 
 	spin_unlock(&rtc->lock);
+
 	return IRQ_HANDLED;
 }
 
 static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
 {
-	struct platform_device *pdev = to_platform_device(dev_id);
+	struct sh_rtc *rtc = dev_id;
-	struct sh_rtc *rtc = platform_get_drvdata(pdev);
+	struct rtc_device *rtc_dev = rtc->rtc_dev;
+	unsigned int tmp;
 
 	spin_lock(&rtc->lock);
 
-	rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
+	tmp = readb(rtc->regbase + RCR2);
+	tmp &= ~RCR2_PEF;
+	writeb(tmp, rtc->regbase + RCR2);
+
+	/* Half period enabled than one skipped and the next notified */
+	if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
+		rtc->periodic_freq &= ~PF_COUNT;
+	else {
+		if (rtc->periodic_freq & PF_HP)
+			rtc->periodic_freq |= PF_COUNT;
+		if (rtc->periodic_freq & PF_KOU) {
+			spin_lock(&rtc_dev->irq_task_lock);
+			if (rtc_dev->irq_task)
+				rtc_dev->irq_task->func(rtc_dev->irq_task->private_data);
+			spin_unlock(&rtc_dev->irq_task_lock);
+		} else
+			rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
+	}
 
 	spin_unlock(&rtc->lock);
 
@@ -176,8 +176,8 @@ static inline void sh_rtc_setpie(struct device *dev, unsigned int enable)
 	tmp = readb(rtc->regbase + RCR2);
 
 	if (enable) {
-		tmp &= ~RCR2_PESMASK;
+		tmp &= ~RCR2_PEF;	/* Clear PES bit */
-		tmp |= RCR2_PEF | (2 << 4);
+		tmp |= (rtc->periodic_freq & ~PF_HP);	/* Set PES2-0 */
 	} else
 		tmp &= ~(RCR2_PESMASK | RCR2_PEF);
 
@@ -186,6 +186,58 @@ static inline void sh_rtc_setpie(struct device *dev, unsigned int enable)
 	spin_unlock_irq(&rtc->lock);
 }
 
+static inline int sh_rtc_setfreq(struct device *dev, unsigned int freq)
+{
+	struct sh_rtc *rtc = dev_get_drvdata(dev);
+	int tmp, ret = 0;
+
+	spin_lock_irq(&rtc->lock);
+	tmp = rtc->periodic_freq & PF_MASK;
+
+	switch (freq) {
+	case 0:
+		rtc->periodic_freq = 0x00;
+		break;
+	case 1:
+		rtc->periodic_freq = 0x60;
+		break;
+	case 2:
+		rtc->periodic_freq = 0x50;
+		break;
+	case 4:
+		rtc->periodic_freq = 0x40;
+		break;
+	case 8:
+		rtc->periodic_freq = 0x30 | PF_HP;
+		break;
+	case 16:
+		rtc->periodic_freq = 0x30;
+		break;
+	case 32:
+		rtc->periodic_freq = 0x20 | PF_HP;
+		break;
+	case 64:
+		rtc->periodic_freq = 0x20;
+		break;
+	case 128:
+		rtc->periodic_freq = 0x10 | PF_HP;
+		break;
+	case 256:
+		rtc->periodic_freq = 0x10;
+		break;
+	default:
+		ret = -ENOTSUPP;
+	}
+
+	if (ret == 0) {
+		rtc->periodic_freq |= tmp;
+		rtc->rtc_dev->irq_freq = freq;
+	}
+
+	spin_unlock_irq(&rtc->lock);
+	return ret;
+}
+
 static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
 {
 	struct sh_rtc *rtc = dev_get_drvdata(dev);
@@ -195,10 +247,9 @@ static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
 
 	tmp = readb(rtc->regbase + RCR1);
 
-	if (!enable) {
+	if (!enable)
 		tmp &= ~RCR1_AIE;
-		rtc->rearm_aie = 0;
+	else
-	} else if (rtc->rearm_aie == 0)
 		tmp |= RCR1_AIE;
 
 	writeb(tmp, rtc->regbase + RCR1);
@@ -206,62 +257,10 @@ static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
 	spin_unlock_irq(&rtc->lock);
 }
 
-static int sh_rtc_open(struct device *dev)
-{
-	struct sh_rtc *rtc = dev_get_drvdata(dev);
-	unsigned int tmp;
-	int ret;
-
-	tmp = readb(rtc->regbase + RCR1);
-	tmp &= ~RCR1_CF;
-	tmp |= RCR1_CIE;
-	writeb(tmp, rtc->regbase + RCR1);
-
-	ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, IRQF_DISABLED,
-			  "sh-rtc period", dev);
-	if (unlikely(ret)) {
-		dev_err(dev, "request period IRQ failed with %d, IRQ %d\n",
-			ret, rtc->periodic_irq);
-		return ret;
-	}
-
-	ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, IRQF_DISABLED,
-			  "sh-rtc carry", dev);
-	if (unlikely(ret)) {
-		dev_err(dev, "request carry IRQ failed with %d, IRQ %d\n",
-			ret, rtc->carry_irq);
-		free_irq(rtc->periodic_irq, dev);
-		goto err_bad_carry;
-	}
-
-	ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, IRQF_DISABLED,
-			  "sh-rtc alarm", dev);
-	if (unlikely(ret)) {
-		dev_err(dev, "request alarm IRQ failed with %d, IRQ %d\n",
-			ret, rtc->alarm_irq);
-		goto err_bad_alarm;
-	}
-
-	return 0;
-
-err_bad_alarm:
-	free_irq(rtc->carry_irq, dev);
-err_bad_carry:
-	free_irq(rtc->periodic_irq, dev);
-
-	return ret;
-}
-
 static void sh_rtc_release(struct device *dev)
 {
-	struct sh_rtc *rtc = dev_get_drvdata(dev);
-
 	sh_rtc_setpie(dev, 0);
 	sh_rtc_setaie(dev, 0);
-
-	free_irq(rtc->periodic_irq, dev);
-	free_irq(rtc->carry_irq, dev);
-	free_irq(rtc->alarm_irq, dev);
 }
 
 static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
@@ -270,31 +269,44 @@ static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
 	unsigned int tmp;
 
 	tmp = readb(rtc->regbase + RCR1);
-	seq_printf(seq, "carry_IRQ\t: %s\n",
+	seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
-		   (tmp & RCR1_CIE) ? "yes" : "no");
 
 	tmp = readb(rtc->regbase + RCR2);
 	seq_printf(seq, "periodic_IRQ\t: %s\n",
-		   (tmp & RCR2_PEF) ? "yes" : "no");
+		   (tmp & RCR2_PESMASK) ? "yes" : "no");
 
 	return 0;
 }
 
 static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
 {
-	unsigned int ret = -ENOIOCTLCMD;
+	struct sh_rtc *rtc = dev_get_drvdata(dev);
+	unsigned int ret = 0;
 
 	switch (cmd) {
 	case RTC_PIE_OFF:
 	case RTC_PIE_ON:
 		sh_rtc_setpie(dev, cmd == RTC_PIE_ON);
-		ret = 0;
 		break;
 	case RTC_AIE_OFF:
 	case RTC_AIE_ON:
 		sh_rtc_setaie(dev, cmd == RTC_AIE_ON);
-		ret = 0;
 		break;
+	case RTC_UIE_OFF:
+		rtc->periodic_freq &= ~PF_OXS;
+		break;
+	case RTC_UIE_ON:
+		rtc->periodic_freq |= PF_OXS;
+		break;
+	case RTC_IRQP_READ:
+		ret = put_user(rtc->rtc_dev->irq_freq,
+			       (unsigned long __user *)arg);
+		break;
+	case RTC_IRQP_SET:
+		ret = sh_rtc_setfreq(dev, arg);
+		break;
+	default:
+		ret = -ENOIOCTLCMD;
 	}
 
 	return ret;
@@ -421,7 +433,7 @@ static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
 {
 	struct platform_device *pdev = to_platform_device(dev);
 	struct sh_rtc *rtc = platform_get_drvdata(pdev);
-	struct rtc_time* tm = &wkalrm->time;
+	struct rtc_time *tm = &wkalrm->time;
 
 	spin_lock_irq(&rtc->lock);
 
@@ -452,7 +464,7 @@ static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
 		writeb(BIN2BCD(value) | AR_ENB,  rtc->regbase + reg_off);
 }
 
-static int sh_rtc_check_alarm(struct rtc_time* tm)
+static int sh_rtc_check_alarm(struct rtc_time *tm)
 {
 	/*
 	 * The original rtc says anything > 0xc0 is "don't care" or "match
@@ -503,11 +515,9 @@ static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
 
 	/* disable alarm interrupt and clear the alarm flag */
 	rcr1 = readb(rtc->regbase + RCR1);
-	rcr1 &= ~(RCR1_AF|RCR1_AIE);
+	rcr1 &= ~(RCR1_AF | RCR1_AIE);
 	writeb(rcr1, rtc->regbase + RCR1);
 
-	rtc->rearm_aie = 0;
-
 	/* set alarm time */
 	sh_rtc_write_alarm_value(rtc, tm->tm_sec,  RSECAR);
 	sh_rtc_write_alarm_value(rtc, tm->tm_min,  RMINAR);
@@ -529,14 +539,34 @@ static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
 	return 0;
 }
 
+static int sh_rtc_irq_set_state(struct device *dev, int enabled)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct sh_rtc *rtc = platform_get_drvdata(pdev);
+
+	if (enabled) {
+		rtc->periodic_freq |= PF_KOU;
+		return sh_rtc_ioctl(dev, RTC_PIE_ON, 0);
+	} else {
+		rtc->periodic_freq &= ~PF_KOU;
+		return sh_rtc_ioctl(dev, RTC_PIE_OFF, 0);
+	}
+}
+
+static int sh_rtc_irq_set_freq(struct device *dev, int freq)
+{
+	return sh_rtc_ioctl(dev, RTC_IRQP_SET, freq);
+}
+
 static struct rtc_class_ops sh_rtc_ops = {
-	.open		= sh_rtc_open,
 	.release	= sh_rtc_release,
 	.ioctl		= sh_rtc_ioctl,
 	.read_time	= sh_rtc_read_time,
 	.set_time	= sh_rtc_set_time,
 	.read_alarm	= sh_rtc_read_alarm,
 	.set_alarm	= sh_rtc_set_alarm,
+	.irq_set_state	= sh_rtc_irq_set_state,
+	.irq_set_freq	= sh_rtc_irq_set_freq,
 	.proc		= sh_rtc_proc,
 };
 
@@ -544,6 +574,7 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
 {
 	struct sh_rtc *rtc;
 	struct resource *res;
+	unsigned int tmp;
 	int ret = -ENOENT;
 
 	rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL);
@@ -552,6 +583,7 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
 
 	spin_lock_init(&rtc->lock);
 
+	/* get periodic/carry/alarm irqs */
 	rtc->periodic_irq = platform_get_irq(pdev, 0);
 	if (unlikely(rtc->periodic_irq < 0)) {
 		dev_err(&pdev->dev, "No IRQ for period\n");
@@ -608,8 +640,48 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
 		rtc->capabilities |= pinfo->capabilities;
 	}
 
+	rtc->rtc_dev->max_user_freq = 256;
+	rtc->rtc_dev->irq_freq = 1;
+	rtc->periodic_freq = 0x60;
+
 	platform_set_drvdata(pdev, rtc);
 
+	/* register periodic/carry/alarm irqs */
+	ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, IRQF_DISABLED,
+			  "sh-rtc period", rtc);
+	if (unlikely(ret)) {
+		dev_err(&pdev->dev,
+			"request period IRQ failed with %d, IRQ %d\n", ret,
+			rtc->periodic_irq);
+		goto err_badmap;
+	}
+
+	ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, IRQF_DISABLED,
+			  "sh-rtc carry", rtc);
+	if (unlikely(ret)) {
+		dev_err(&pdev->dev,
+			"request carry IRQ failed with %d, IRQ %d\n", ret,
+			rtc->carry_irq);
+		free_irq(rtc->periodic_irq, rtc);
+		goto err_badmap;
+	}
+
+	ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, IRQF_DISABLED,
+			  "sh-rtc alarm", rtc);
+	if (unlikely(ret)) {
+		dev_err(&pdev->dev,
+			"request alarm IRQ failed with %d, IRQ %d\n", ret,
+			rtc->alarm_irq);
+		free_irq(rtc->carry_irq, rtc);
+		free_irq(rtc->periodic_irq, rtc);
+		goto err_badmap;
+	}
+
+	tmp = readb(rtc->regbase + RCR1);
+	tmp &= ~RCR1_CF;
+	tmp |= RCR1_CIE;
+	writeb(tmp, rtc->regbase + RCR1);
+
 	return 0;
 
 err_badmap:
@@ -630,6 +702,10 @@ static int __devexit sh_rtc_remove(struct platform_device *pdev)
 	sh_rtc_setpie(&pdev->dev, 0);
 	sh_rtc_setaie(&pdev->dev, 0);
 
+	free_irq(rtc->carry_irq, rtc);
+	free_irq(rtc->periodic_irq, rtc);
+	free_irq(rtc->alarm_irq, rtc);
+
 	release_resource(rtc->res);
 
 	platform_set_drvdata(pdev, NULL);
@@ -662,6 +738,8 @@ module_exit(sh_rtc_exit);
 
 MODULE_DESCRIPTION("SuperH on-chip RTC driver");
 MODULE_VERSION(DRV_VERSION);
-MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, Jamie Lenehan <lenehan@twibble.org>");
+MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
+	      "Jamie Lenehan <lenehan@twibble.org>, "
+	      "Angelo Castello <angelo.castello@st.com>");
 MODULE_LICENSE("GPL");
 MODULE_ALIAS("platform:" DRV_NAME);

drivers/serial/sh-sci.c

@@ -333,7 +333,6 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
 	}
 	sci_out(port, SCFCR, fcr_val);
 }
-
 #elif defined(CONFIG_CPU_SH3)
 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
@@ -384,6 +383,12 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
 
 	sci_out(port, SCFCR, fcr_val);
 }
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
+{
+	/* Nothing to do here.. */
+	sci_out(port, SCFCR, 0);
+}
 #else
 /* For SH7750 */
 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)

drivers/serial/sh-sci.h

@@ -1,20 +1,5 @@
-/* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
- *
- *  linux/drivers/serial/sh-sci.h
- *
- *  SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
- *  Copyright (C) 1999, 2000  Niibe Yutaka
- *  Copyright (C) 2000  Greg Banks
- *  Copyright (C) 2002, 2003  Paul Mundt
- *  Modified to support multiple serial ports. Stuart Menefy (May 2000).
- *  Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
- *  Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
- *  Removed SH7300 support (Jul 2007).
- *  Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007).
- */
 #include <linux/serial_core.h>
 #include <asm/io.h>
-
 #include <asm/gpio.h>
 
 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
@@ -102,6 +87,15 @@
 # define SCSPTR0		SCPDR0
 # define SCIF_ORER		0x0001  /* overrun error bit */
 # define SCSCR_INIT(port)	0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+# define SCSPTR0                0xa4050160
+# define SCSPTR1                0xa405013e
+# define SCSPTR2                0xa4050160
+# define SCSPTR3                0xa405013e
+# define SCSPTR4                0xa4050128
+# define SCSPTR5                0xa4050128
+# define SCIF_ORER              0x0001  /* overrun error bit */
+# define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 # define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
@@ -395,6 +389,11 @@
                  h8_sci_offset, h8_sci_size) \
   CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+        #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
+                CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
+        #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
+                CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 #else
 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 		 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
@@ -419,6 +418,18 @@ SCIF_FNS(SCFDR,  0x1c, 16)
 SCIF_FNS(SCxTDR, 0x20,  8)
 SCIF_FNS(SCxRDR, 0x24,  8)
 SCIF_FNS(SCLSR,  0x24, 16)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+SCIx_FNS(SCSMR,  0x00, 16, 0x00, 16)
+SCIx_FNS(SCBRR,  0x04,  8, 0x04,  8)
+SCIx_FNS(SCSCR,  0x08, 16, 0x08, 16)
+SCIx_FNS(SCxTDR, 0x20,  8, 0x0c,  8)
+SCIx_FNS(SCxSR,  0x14, 16, 0x10, 16)
+SCIx_FNS(SCxRDR, 0x24,  8, 0x14,  8)
+SCIF_FNS(SCTDSR, 0x0c,  8)
+SCIF_FNS(SCFER,  0x10, 16)
+SCIF_FNS(SCFCR,  0x18, 16)
+SCIF_FNS(SCFDR,  0x1c, 16)
+SCIF_FNS(SCLSR,  0x24, 16)
 #else
 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
@@ -589,6 +600,23 @@ static inline int sci_rxd_in(struct uart_port *port)
 		return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
 	return 1;
 }
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+static inline int sci_rxd_in(struct uart_port *port)
+{
+        if (port->mapbase == 0xffe00000)
+                return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
+        if (port->mapbase == 0xffe10000)
+                return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
+        if (port->mapbase == 0xffe20000)
+                return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
+        if (port->mapbase == 0xa4e30000)
+                return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
+        if (port->mapbase == 0xa4e40000)
+                return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
+        if (port->mapbase == 0xa4e50000)
+                return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
+        return 1;
+}
 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 static inline int sci_rxd_in(struct uart_port *port)
 {
@@ -727,6 +755,8 @@ static inline int sci_rxd_in(struct uart_port *port)
       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
       defined(CONFIG_CPU_SUBTYPE_SH7721)
 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(16*bps)-1)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
 #elif defined(CONFIG_SUPERH64)

include/asm-sh/bugs.h

@@ -25,7 +25,7 @@ static void __init check_bugs(void)
 	case CPU_SH7619:
 		*p++ = '2';
 		break;
-	case CPU_SH7203 ... CPU_SH7263:
+	case CPU_SH7203 ... CPU_MXG:
 		*p++ = '2';
 		*p++ = 'a';
 		break;

include/asm-sh/cpu-sh4/freq.h

@@ -10,14 +10,14 @@
 #ifndef __ASM_CPU_SH4_FREQ_H
 #define __ASM_CPU_SH4_FREQ_H
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7366)
+#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7723) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7366)
 #define FRQCR		        0xa4150000
 #define VCLKCR			0xa4150004
 #define SCLKACR			0xa4150008
 #define SCLKBCR			0xa415000c
-#if defined(CONFIG_CPU_SUBTYPE_SH7722)
 #define IrDACLKCR		0xa4150010
-#endif
 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
       defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define	FRQCR			0xffc80000

include/asm-sh/cpu-sh4/rtc.h

@@ -1,7 +1,12 @@
 #ifndef __ASM_SH_CPU_SH4_RTC_H
 #define __ASM_SH_CPU_SH4_RTC_H
 
+#ifdef CONFIG_CPU_SUBTYPE_SH7723
+#define rtc_reg_size		sizeof(u16)
+#else
 #define rtc_reg_size		sizeof(u32)
+#endif
+
 #define RTC_BIT_INVERTED	0x40	/* bug on SH7750, SH7750S */
 #define RTC_DEF_CAPABILITIES	RTC_CAP_4_DIGIT_YEAR
 

include/asm-sh/migor.h

@@ -0,0 +1,58 @@
+#ifndef __ASM_SH_MIGOR_H
+#define __ASM_SH_MIGOR_H
+
+/*
+ * linux/include/asm-sh/migor.h
+ *
+ * Copyright (C) 2008 Renesas Solutions
+ *
+ * Portions Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+/* GPIO */
+#define MSTPCR0 0xa4150030
+#define MSTPCR1 0xa4150034
+#define MSTPCR2 0xa4150038
+
+#define PORT_PACR 0xa4050100
+#define PORT_PDCR 0xa4050106
+#define PORT_PECR 0xa4050108
+#define PORT_PHCR 0xa405010e
+#define PORT_PJCR 0xa4050110
+#define PORT_PKCR 0xa4050112
+#define PORT_PLCR 0xa4050114
+#define PORT_PMCR 0xa4050116
+#define PORT_PRCR 0xa405011c
+#define PORT_PWCR 0xa4050146
+#define PORT_PXCR 0xa4050148
+#define PORT_PYCR 0xa405014a
+#define PORT_PZCR 0xa405014c
+#define PORT_PADR 0xa4050120
+#define PORT_PWDR 0xa4050166
+
+#define PORT_HIZCRA 0xa4050158
+#define PORT_HIZCRC 0xa405015c
+
+#define PORT_MSELCRB 0xa4050182
+
+#define MSTPCR1 0xa4150034
+#define MSTPCR2 0xa4150038
+
+#define PORT_PSELA 0xa405014e
+#define PORT_PSELB 0xa4050150
+#define PORT_PSELC 0xa4050152
+#define PORT_PSELD 0xa4050154
+
+#define PORT_HIZCRA 0xa4050158
+#define PORT_HIZCRB 0xa405015a
+#define PORT_HIZCRC 0xa405015c
+
+#define BSC_CS6ABCR 0xfec1001c
+
+#endif /* __ASM_SH_MIGOR_H */

include/asm-sh/processor.h

@@ -16,7 +16,7 @@ enum cpu_type {
 	CPU_SH7619,
 
 	/* SH-2A types */
-	CPU_SH7203, CPU_SH7206, CPU_SH7263,
+	CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
 
 	/* SH-3 types */
 	CPU_SH7705, CPU_SH7706, CPU_SH7707,
@@ -29,7 +29,8 @@ enum cpu_type {
 	CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
 
 	/* SH-4A types */
-	CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
+	CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
+	CPU_SH7723, CPU_SHX3,
 
 	/* SH4AL-DSP types */
 	CPU_SH7343, CPU_SH7722, CPU_SH7366,

include/asm-sh/r7780rp.h

@@ -55,11 +55,11 @@
 #define PA_SCSPTR1      (PA_BCR+0x0524) /* SCIF1 Serial Port control */
 #define PA_SCLSR1       (PA_BCR+0x0528) /* SCIF1 Line Status control */
 #define PA_SCRER1       (PA_BCR+0x052c) /* SCIF1 Serial Error control */
-#define PA_ICCR         (PA_BCR+0x0600) /* Serial control */
+#define PA_SMCR         (PA_BCR+0x0600) /* 2-wire Serial control */
-#define PA_SAR          (PA_BCR+0x0602) /* Serial Slave control */
+#define PA_SMSMADR      (PA_BCR+0x0602) /* 2-wire Serial Slave control */
-#define PA_MDR          (PA_BCR+0x0604) /* Serial Mode control */
+#define PA_SMMR         (PA_BCR+0x0604) /* 2-wire Serial Mode control */
-#define PA_ADR1         (PA_BCR+0x0606) /* Serial Address1 control */
+#define PA_SMSADR1      (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
-#define PA_DAR1         (PA_BCR+0x0646) /* Serial Data1 control */
+#define PA_SMTRDR1      (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
 #define PA_VERREG       (PA_BCR+0x0700) /* FPGA Version Register */
 #define PA_POFF         (PA_BCR+0x0800) /* System Power Off control */
 #define PA_PMR          (PA_BCR+0x0900) /*  */
@@ -107,11 +107,11 @@
 #define PA_SCFCR	(PA_BCR+0x040c)	/* SCIF FIFO control */
 #define PA_SCFDR	(PA_BCR+0x040e)	/* SCIF FIFO data control */
 #define PA_SCLSR	(PA_BCR+0x0412)	/* SCIF Line Status control */
-#define PA_ICCR		(PA_BCR+0x0500)	/* Serial control */
+#define PA_SMCR		(PA_BCR+0x0500)	/* 2-wire Serial control */
-#define PA_SAR		(PA_BCR+0x0502)	/* Serial Slave control */
+#define PA_SMSMADR	(PA_BCR+0x0502)	/* 2-wire Serial Slave control */
-#define PA_MDR		(PA_BCR+0x0504)	/* Serial Mode control */
+#define PA_SMMR		(PA_BCR+0x0504)	/* 2-wire Serial Mode control */
-#define PA_ADR1		(PA_BCR+0x0506)	/* Serial Address1 control */
+#define PA_SMSADR1	(PA_BCR+0x0506)	/* 2-wire Serial Address1 control */
-#define PA_DAR1		(PA_BCR+0x0546)	/* Serial Data1 control */
+#define PA_SMTRDR1	(PA_BCR+0x0546)	/* 2-wire Serial Data1 control */
 #define PA_VERREG	(PA_BCR+0x0600)	/* FPGA Version Register */
 
 #define PA_AX88796L	0xa5800400	/* AX88796L Area */
@@ -190,6 +190,8 @@
 #define IRQ_TP			(HL_FPGA_IRQ_BASE + 12)
 #define IRQ_RTC			(HL_FPGA_IRQ_BASE + 13)
 #define IRQ_TH_ALERT		(HL_FPGA_IRQ_BASE + 14)
+#define IRQ_SCIF0		(HL_FPGA_IRQ_BASE + 15)
+#define IRQ_SCIF1		(HL_FPGA_IRQ_BASE + 16)
 
 unsigned char *highlander_init_irq_r7780mp(void);
 unsigned char *highlander_init_irq_r7780rp(void);

include/asm-sh/se7721.h

@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * Hitachi UL SolutionEngine 7721 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#ifndef __ASM_SH_SE7721_H
+#define __ASM_SH_SE7721_H
+#include <asm/addrspace.h>
+
+/* Box specific addresses. */
+#define SE_AREA0_WIDTH	2		/* Area0: 32bit */
+#define PA_ROM		0xa0000000	/* EPROM */
+#define PA_ROM_SIZE	0x00200000	/* EPROM size 2M byte */
+#define PA_FROM		0xa1000000	/* Flash-ROM */
+#define PA_FROM_SIZE	0x01000000	/* Flash-ROM size 16M byte */
+#define PA_EXT1		0xa4000000
+#define PA_EXT1_SIZE	0x04000000
+#define PA_SDRAM	0xaC000000	/* SDRAM(Area3) 64MB */
+#define PA_SDRAM_SIZE	0x04000000
+
+#define PA_EXT4		0xb0000000
+#define PA_EXT4_SIZE	0x04000000
+
+#define PA_PERIPHERAL	0xB8000000
+
+#define PA_PCIC		PA_PERIPHERAL
+#define PA_MRSHPC	(PA_PERIPHERAL + 0x003fffe0)
+#define PA_MRSHPC_MW1	(PA_PERIPHERAL + 0x00400000)
+#define PA_MRSHPC_MW2	(PA_PERIPHERAL + 0x00500000)
+#define PA_MRSHPC_IO	(PA_PERIPHERAL + 0x00600000)
+#define MRSHPC_OPTION	(PA_MRSHPC + 6)
+#define MRSHPC_CSR	(PA_MRSHPC + 8)
+#define MRSHPC_ISR	(PA_MRSHPC + 10)
+#define MRSHPC_ICR	(PA_MRSHPC + 12)
+#define MRSHPC_CPWCR	(PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1	(PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1	(PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1	(PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2	(PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2	(PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2	(PA_MRSHPC + 26)
+#define MRSHPC_CDCR	(PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO	(PA_MRSHPC + 30)
+
+#define PA_LED		0xB6800000	/* 8bit LED */
+#define PA_FPGA		0xB7000000 	/* FPGA base address */
+
+#define MRSHPC_IRQ0	10
+
+#define FPGA_ILSR1	(PA_FPGA + 0x02)
+#define FPGA_ILSR2	(PA_FPGA + 0x03)
+#define FPGA_ILSR3	(PA_FPGA + 0x04)
+#define FPGA_ILSR4	(PA_FPGA + 0x05)
+#define FPGA_ILSR5	(PA_FPGA + 0x06)
+#define FPGA_ILSR6	(PA_FPGA + 0x07)
+#define FPGA_ILSR7	(PA_FPGA + 0x08)
+#define FPGA_ILSR8	(PA_FPGA + 0x09)
+
+void init_se7721_IRQ(void);
+
+#define __IO_PREFIX		se7721
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SE7721_H */

include/asm-sh/se7722.h

@@ -77,6 +77,8 @@
 #define PORT_PSELA      0xA405014EUL
 #define PORT_PYCR       0xA405014AUL
 #define PORT_PZCR       0xA405014CUL
+#define PORT_HIZCRA     0xA4050158UL
+#define PORT_HIZCRC     0xA405015CUL
 
 /* IRQ */
 #define IRQ0_IRQ        32

include/asm-sh/sh_keysc.h

@@ -0,0 +1,13 @@
+#ifndef __ASM_KEYSC_H__
+#define __ASM_KEYSC_H__
+
+#define SH_KEYSC_MAXKEYS 30
+
+struct sh_keysc_info {
+	enum { SH_KEYSC_MODE_1, SH_KEYSC_MODE_2, SH_KEYSC_MODE_3 } mode;
+	int scan_timing; /* 0 -> 7, see KYCR1, SCN[2:0] */
+	int delay;
+	int keycodes[SH_KEYSC_MAXKEYS];
+};
+
+#endif /* __ASM_KEYSC_H__ */

include/asm-sh/system.h

@@ -146,6 +146,8 @@ extern unsigned int instruction_size(unsigned int insn);
 
 extern unsigned long cached_to_uncached;
 
+extern struct dentry *sh_debugfs_root;
+
 /* XXX
  * disable hlt during certain critical i/o operations
  */

include/asm-sh/uaccess_32.h

@@ -55,13 +55,10 @@ static inline void set_fs(mm_segment_t s)
  * If we don't have an MMU (or if its disabled) the only thing we really have
  * to look out for is if the address resides somewhere outside of what
  * available RAM we have.
- *
- * TODO: This check could probably also stand to be restricted somewhat more..
- * though it still does the Right Thing(tm) for the time being.
  */
 static inline int __access_ok(unsigned long addr, unsigned long size)
 {
-	return ((addr >= memory_start) && ((addr + size) < memory_end));
+	return 1;
 }
 #else /* CONFIG_MMU */
 #define __addr_ok(addr) \