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https://github.com/edk2-porting/linux-next.git
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qla4xxx: Added new opcodes for 84XX Minidump template
Updated driver with new opcode (RDDFE, RDMDIO and POLLWR) which are added with latest firmware minidump template Signed-off-by: Tej Parkash <tej.parkash@qlogic.com> Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com> Reviewed-by: Mike Christie <michaelc@cs.wisc.edu> Signed-off-by: Christoph Hellwig <hch@lst.de>
This commit is contained in:
Tej Parkash
Christoph Hellwig
parent
b410982c98
commit
b182978945
@ -254,6 +254,50 @@ struct qla83xx_minidump_entry_pollrd {
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uint32_t rsvd_1;
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};
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struct qla8044_minidump_entry_rddfe {
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struct qla8xxx_minidump_entry_hdr h;
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uint32_t addr_1;
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uint32_t value;
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uint8_t stride;
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uint8_t stride2;
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uint16_t count;
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uint32_t poll;
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uint32_t mask;
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uint32_t modify_mask;
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uint32_t data_size;
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uint32_t rsvd;
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} __packed;
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struct qla8044_minidump_entry_rdmdio {
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struct qla8xxx_minidump_entry_hdr h;
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uint32_t addr_1;
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uint32_t addr_2;
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uint32_t value_1;
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uint8_t stride_1;
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uint8_t stride_2;
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uint16_t count;
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uint32_t poll;
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uint32_t mask;
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uint32_t value_2;
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uint32_t data_size;
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} __packed;
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struct qla8044_minidump_entry_pollwr {
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struct qla8xxx_minidump_entry_hdr h;
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uint32_t addr_1;
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uint32_t addr_2;
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uint32_t value_1;
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uint32_t value_2;
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uint32_t poll;
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uint32_t mask;
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uint32_t data_size;
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uint32_t rsvd;
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} __packed;
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/* RDMUX2 Entry */
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struct qla83xx_minidump_entry_rdmux2 {
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struct qla8xxx_minidump_entry_hdr h;
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@ -14,6 +14,7 @@
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#include <asm-generic/io-64-nonatomic-lo-hi.h>
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#define TIMEOUT_100_MS 100
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#define MASK(n) DMA_BIT_MASK(n)
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#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
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#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
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@ -1714,6 +1715,101 @@ void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
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qla4_82xx_rom_unlock(ha);
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}
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static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha,
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uint32_t addr1, uint32_t mask)
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{
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unsigned long timeout;
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uint32_t rval = QLA_SUCCESS;
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uint32_t temp;
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timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
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do {
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ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
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if ((temp & mask) != 0)
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break;
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if (time_after_eq(jiffies, timeout)) {
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ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n");
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return QLA_ERROR;
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}
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} while (1);
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return rval;
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}
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uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1,
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uint32_t addr3, uint32_t mask, uint32_t addr,
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uint32_t *data_ptr)
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{
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int rval = QLA_SUCCESS;
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uint32_t temp;
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uint32_t data;
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rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
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if (rval)
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goto exit_ipmdio_rd_reg;
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temp = (0x40000000 | addr);
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ha->isp_ops->wr_reg_indirect(ha, addr1, temp);
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rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
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if (rval)
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goto exit_ipmdio_rd_reg;
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ha->isp_ops->rd_reg_indirect(ha, addr3, &data);
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*data_ptr = data;
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exit_ipmdio_rd_reg:
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return rval;
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}
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static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha,
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uint32_t addr1,
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uint32_t addr2,
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uint32_t addr3,
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uint32_t mask)
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{
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unsigned long timeout;
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uint32_t temp;
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uint32_t rval = QLA_SUCCESS;
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timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
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do {
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ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp);
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if ((temp & 0x1) != 1)
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break;
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if (time_after_eq(jiffies, timeout)) {
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ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n");
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return QLA_ERROR;
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}
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} while (1);
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return rval;
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}
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static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha,
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uint32_t addr1, uint32_t addr3,
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uint32_t mask, uint32_t addr,
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uint32_t value)
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{
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int rval = QLA_SUCCESS;
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rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
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if (rval)
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goto exit_ipmdio_wr_reg;
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ha->isp_ops->wr_reg_indirect(ha, addr3, value);
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ha->isp_ops->wr_reg_indirect(ha, addr1, addr);
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rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
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if (rval)
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goto exit_ipmdio_wr_reg;
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exit_ipmdio_wr_reg:
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return rval;
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}
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static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
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struct qla8xxx_minidump_entry_hdr *entry_hdr,
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uint32_t **d_ptr)
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@ -2440,6 +2536,227 @@ exit_process_pollrd:
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return rval;
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}
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static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha,
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struct qla8xxx_minidump_entry_hdr *entry_hdr,
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uint32_t **d_ptr)
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{
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int loop_cnt;
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uint32_t addr1, addr2, value, data, temp, wrval;
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uint8_t stride, stride2;
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uint16_t count;
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uint32_t poll, mask, data_size, modify_mask;
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uint32_t wait_count = 0;
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uint32_t *data_ptr = *d_ptr;
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struct qla8044_minidump_entry_rddfe *rddfe;
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uint32_t rval = QLA_SUCCESS;
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rddfe = (struct qla8044_minidump_entry_rddfe *)entry_hdr;
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addr1 = le32_to_cpu(rddfe->addr_1);
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value = le32_to_cpu(rddfe->value);
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stride = le32_to_cpu(rddfe->stride);
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stride2 = le32_to_cpu(rddfe->stride2);
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count = le32_to_cpu(rddfe->count);
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poll = le32_to_cpu(rddfe->poll);
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mask = le32_to_cpu(rddfe->mask);
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modify_mask = le32_to_cpu(rddfe->modify_mask);
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data_size = le32_to_cpu(rddfe->data_size);
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addr2 = addr1 + stride;
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for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
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ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value));
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wait_count = 0;
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while (wait_count < poll) {
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ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
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if ((temp & mask) != 0)
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break;
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wait_count++;
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}
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if (wait_count == poll) {
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ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
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rval = QLA_ERROR;
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goto exit_process_rddfe;
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} else {
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ha->isp_ops->rd_reg_indirect(ha, addr2, &temp);
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temp = temp & modify_mask;
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temp = (temp | ((loop_cnt << 16) | loop_cnt));
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wrval = ((temp << 16) | temp);
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ha->isp_ops->wr_reg_indirect(ha, addr2, wrval);
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ha->isp_ops->wr_reg_indirect(ha, addr1, value);
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wait_count = 0;
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while (wait_count < poll) {
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ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
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if ((temp & mask) != 0)
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break;
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wait_count++;
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}
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if (wait_count == poll) {
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ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
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__func__);
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rval = QLA_ERROR;
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goto exit_process_rddfe;
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}
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ha->isp_ops->wr_reg_indirect(ha, addr1,
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((0x40000000 | value) +
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stride2));
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wait_count = 0;
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while (wait_count < poll) {
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ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
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if ((temp & mask) != 0)
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break;
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wait_count++;
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}
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if (wait_count == poll) {
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ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
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__func__);
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rval = QLA_ERROR;
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goto exit_process_rddfe;
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}
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ha->isp_ops->rd_reg_indirect(ha, addr2, &data);
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*data_ptr++ = cpu_to_le32(wrval);
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*data_ptr++ = cpu_to_le32(data);
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}
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}
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*d_ptr = data_ptr;
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exit_process_rddfe:
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return rval;
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}
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static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha,
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struct qla8xxx_minidump_entry_hdr *entry_hdr,
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uint32_t **d_ptr)
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{
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int rval = QLA_SUCCESS;
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uint32_t addr1, addr2, value1, value2, data, selval;
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uint8_t stride1, stride2;
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uint32_t addr3, addr4, addr5, addr6, addr7;
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uint16_t count, loop_cnt;
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uint32_t poll, mask;
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uint32_t *data_ptr = *d_ptr;
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struct qla8044_minidump_entry_rdmdio *rdmdio;
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rdmdio = (struct qla8044_minidump_entry_rdmdio *)entry_hdr;
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addr1 = le32_to_cpu(rdmdio->addr_1);
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addr2 = le32_to_cpu(rdmdio->addr_2);
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value1 = le32_to_cpu(rdmdio->value_1);
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stride1 = le32_to_cpu(rdmdio->stride_1);
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stride2 = le32_to_cpu(rdmdio->stride_2);
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count = le32_to_cpu(rdmdio->count);
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poll = le32_to_cpu(rdmdio->poll);
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mask = le32_to_cpu(rdmdio->mask);
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value2 = le32_to_cpu(rdmdio->value_2);
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addr3 = addr1 + stride1;
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for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
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rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
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addr3, mask);
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if (rval)
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goto exit_process_rdmdio;
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addr4 = addr2 - stride1;
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rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4,
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value2);
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if (rval)
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goto exit_process_rdmdio;
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addr5 = addr2 - (2 * stride1);
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rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5,
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value1);
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if (rval)
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goto exit_process_rdmdio;
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addr6 = addr2 - (3 * stride1);
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rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask,
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addr6, 0x2);
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if (rval)
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goto exit_process_rdmdio;
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rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
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addr3, mask);
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if (rval)
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goto exit_process_rdmdio;
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addr7 = addr2 - (4 * stride1);
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rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3,
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mask, addr7, &data);
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if (rval)
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goto exit_process_rdmdio;
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selval = (value2 << 18) | (value1 << 2) | 2;
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stride2 = le32_to_cpu(rdmdio->stride_2);
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*data_ptr++ = cpu_to_le32(selval);
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*data_ptr++ = cpu_to_le32(data);
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value1 = value1 + stride2;
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*d_ptr = data_ptr;
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}
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exit_process_rdmdio:
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return rval;
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}
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static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha,
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struct qla8xxx_minidump_entry_hdr *entry_hdr,
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uint32_t **d_ptr)
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{
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uint32_t addr1, addr2, value1, value2, poll, mask, r_value;
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struct qla8044_minidump_entry_pollwr *pollwr_hdr;
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uint32_t wait_count = 0;
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uint32_t rval = QLA_SUCCESS;
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pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
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addr1 = le32_to_cpu(pollwr_hdr->addr_1);
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addr2 = le32_to_cpu(pollwr_hdr->addr_2);
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value1 = le32_to_cpu(pollwr_hdr->value_1);
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value2 = le32_to_cpu(pollwr_hdr->value_2);
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poll = le32_to_cpu(pollwr_hdr->poll);
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mask = le32_to_cpu(pollwr_hdr->mask);
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while (wait_count < poll) {
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ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
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if ((r_value & poll) != 0)
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break;
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wait_count++;
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}
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if (wait_count == poll) {
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ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
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rval = QLA_ERROR;
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goto exit_process_pollwr;
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}
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ha->isp_ops->wr_reg_indirect(ha, addr2, value2);
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ha->isp_ops->wr_reg_indirect(ha, addr1, value1);
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wait_count = 0;
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while (wait_count < poll) {
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ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
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if ((r_value & poll) != 0)
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break;
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wait_count++;
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}
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exit_process_pollwr:
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return rval;
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}
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static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
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struct qla8xxx_minidump_entry_hdr *entry_hdr,
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uint32_t **d_ptr)
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@ -2753,6 +3070,24 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
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if (rval != QLA_SUCCESS)
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qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
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break;
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case QLA8044_RDDFE:
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rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr,
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&data_ptr);
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if (rval != QLA_SUCCESS)
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qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
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break;
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case QLA8044_RDMDIO:
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rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr,
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&data_ptr);
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if (rval != QLA_SUCCESS)
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qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
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break;
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case QLA8044_POLLWR:
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rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr,
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&data_ptr);
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if (rval != QLA_SUCCESS)
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qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
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break;
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case QLA8XXX_RDNOP:
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default:
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qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
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@ -858,6 +858,9 @@ struct crb_addr_pair {
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#define QLA83XX_POLLRD 35
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#define QLA83XX_RDMUX2 36
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#define QLA83XX_POLLRDMWR 37
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#define QLA8044_RDDFE 38
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#define QLA8044_RDMDIO 39
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#define QLA8044_POLLWR 40
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#define QLA8XXX_RDROM 71
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#define QLA8XXX_RDMEM 72
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#define QLA8XXX_CNTRL 98
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