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ARM: dts: rockchip: add cru nodes and update device clocks to use it
This adds a node for the clock and reset unit on rk3188 and rk3066 SoCs and also updates the device nodes retrieve their clocks from there, instead of the previous gate clock nodes. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de>
This commit is contained in:
Heiko Stuebner
parent
1fe69496cf
commit
b13d2a7b43
@ -15,6 +15,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3066a-cru.h>
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#include "rk3xxx.dtsi"
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#include "rk3066a-clocks.dtsi"
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@ -45,7 +46,7 @@
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x20038000 0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates1 0>, <&clk_gates7 7>;
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clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
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clock-names = "timer", "pclk";
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};
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@ -53,7 +54,7 @@
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x2003a000 0x100>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates1 1>, <&clk_gates7 8>;
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clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
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clock-names = "timer", "pclk";
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};
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@ -61,7 +62,7 @@
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x2000e000 0x100>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates1 2>, <&clk_gates7 9>;
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clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
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clock-names = "timer", "pclk";
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};
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@ -78,6 +79,15 @@
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};
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};
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3066a-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pinctrl@20008000 {
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compatible = "rockchip,rk3066a-pinctrl";
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rockchip,grf = <&grf>;
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@ -89,7 +99,7 @@
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compatible = "rockchip,gpio-bank";
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reg = <0x20034000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 9>;
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clocks = <&cru PCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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@ -102,7 +112,7 @@
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compatible = "rockchip,gpio-bank";
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reg = <0x2003c000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 10>;
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clocks = <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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@ -115,7 +125,7 @@
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compatible = "rockchip,gpio-bank";
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reg = <0x2003e000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 11>;
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clocks = <&cru PCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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@ -128,7 +138,7 @@
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 12>;
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clocks = <&cru PCLK_GPIO3>;
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gpio-controller;
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#gpio-cells = <2>;
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@ -141,7 +151,7 @@
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compatible = "rockchip,gpio-bank";
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reg = <0x20084000 0x100>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 13>;
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clocks = <&cru PCLK_GPIO4>;
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gpio-controller;
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#gpio-cells = <2>;
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@ -154,7 +164,7 @@
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compatible = "rockchip,gpio-bank";
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reg = <0x2000a000 0x100>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 15>;
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clocks = <&cru PCLK_GPIO6>;
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gpio-controller;
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#gpio-cells = <2>;
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@ -15,6 +15,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3188-cru.h>
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#include "rk3xxx.dtsi"
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#include "rk3188-clocks.dtsi"
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@ -74,6 +75,15 @@
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};
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};
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3188-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pinctrl@20008000 {
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compatible = "rockchip,rk3188-pinctrl";
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rockchip,grf = <&grf>;
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@ -87,7 +97,7 @@
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compatible = "rockchip,rk3188-gpio-bank0";
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reg = <0x2000a000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 9>;
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clocks = <&cru PCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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@ -100,7 +110,7 @@
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compatible = "rockchip,gpio-bank";
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reg = <0x2003c000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 10>;
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clocks = <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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@ -113,7 +123,7 @@
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compatible = "rockchip,gpio-bank";
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reg = <0x2003e000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 11>;
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clocks = <&cru PCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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@ -126,7 +136,7 @@
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 12>;
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clocks = <&cru PCLK_GPIO3>;
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gpio-controller;
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#gpio-cells = <2>;
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@ -60,14 +60,14 @@
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x1013c200 0x20>;
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interrupts = <GIC_PPI 11 0x304>;
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clocks = <&dummy150m>;
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clocks = <&cru CORE_PERI>;
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};
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local-timer@1013c600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x1013c600 0x20>;
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interrupts = <GIC_PPI 13 0x304>;
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clocks = <&dummy150m>;
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clocks = <&cru CORE_PERI>;
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};
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uart0: serial@10124000 {
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@ -76,7 +76,7 @@
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&clk_gates1 8>;
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clocks = <&cru SCLK_UART0>;
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status = "disabled";
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};
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@ -86,7 +86,7 @@
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&clk_gates1 10>;
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clocks = <&cru SCLK_UART1>;
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status = "disabled";
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};
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@ -96,7 +96,7 @@
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&clk_gates1 12>;
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clocks = <&cru SCLK_UART2>;
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status = "disabled";
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};
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@ -106,7 +106,7 @@
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&clk_gates1 14>;
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clocks = <&cru SCLK_UART3>;
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status = "disabled";
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};
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@ -117,7 +117,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk_gates5 10>, <&clk_gates2 11>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
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clock-names = "biu", "ciu";
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status = "disabled";
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@ -130,7 +130,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk_gates5 11>, <&clk_gates2 13>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
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clock-names = "biu", "ciu";
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status = "disabled";
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