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Renesas ARM DT updates for v5.18 (take two)

Browse Source 
- Document the use of the renesas-soc IRC channel,
   - Watchdog support for the R-Car S4-8, RZ/N1D, and RZ/G2LC SoCs on the
     Spider, RZN1D-DB, and RZ/G2LC SMARC EVK development boards,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.18 (take two)

  - Document the use of the renesas-soc IRC channel,
  - Watchdog support for the R-Car S4-8, RZ/N1D, and RZ/G2LC SoCs on the
    Spider, RZN1D-DB, and RZ/G2LC SMARC EVK development boards,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  ARM: dts: renesas: Align GPIO hog names with dtschema
  arm64: dts: renesas: Align GPIO hog names with dtschema
  arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdog
  ARM: dts: r9a06g032-rzn1d400-db: Enable watchdog0 with a 60s timeout
  ARM: dts: r9a06g032: Add the watchdog nodes
  dt-bindings: clock: r9a06g032: Add the definition of the watchdog clock
  arm64: dts: renesas: spider-cpu: Enable watchdog timer
  arm64: dts: renesas: r8a779f0: Add RWDT node
  MAINTAINERS: Specify IRC channel for Renesas ARM64 port
  MAINTAINERS: Specify IRC channel for Renesas ARM32 port
  arm64: dts: renesas: ulcb-kf: fix wrong comment

Link: https://lore.kernel.org/r/cover.1645784466.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-02-25 16:14:30 +01:00
commit b10e270dc9
21 changed files with 71 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -2530,6 +2530,7 @@ M: Magnus Damm <magnus.damm@gmail.com>
L: linux-renesas-soc@vger.kernel.org
S: Supported
Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/
C: irc://irc.libera.chat/renesas-soc
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
F: Documentation/devicetree/bindings/arm/renesas.yaml
F: arch/arm64/boot/dts/renesas/
@ -2643,6 +2644,7 @@ M: Magnus Damm <magnus.damm@gmail.com>
L: linux-renesas-soc@vger.kernel.org
S: Supported
Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/
C: irc://irc.libera.chat/renesas-soc
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
F: Documentation/devicetree/bindings/arm/renesas.yaml
F: arch/arm/boot/dts/emev2*

2
arch/arm/boot/dts/iwg20d-q7-common.dtsi
View File

@ -181,7 +181,7 @@
};
&gpio2 {
touch-interrupt {
touch-interrupt-hog {
gpio-hog;
gpios = <12 GPIO_ACTIVE_LOW>;
input;

2
arch/arm/boot/dts/r8a7740-armadillo800eva.dts
View File

@ -266,7 +266,7 @@
function = "lcd0";
};
lcd0_mux {
lcd0-mux-hog {
/* DBGMD/LCDC0/FSIA MUX */
gpio-hog;
gpios = <176 0>;

4
arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
View File

@ -91,10 +91,10 @@
&gpio0 {
/* Disable hogging GP0_18 to output LOW */
/delete-node/ qspi_en;
/delete-node/ qspi-en-hog;
/* Hog GP0_18 to output HIGH to enable VIN2 */
vin2_en {
vin2-en-hog {
gpio-hog;
gpios = <18 GPIO_ACTIVE_HIGH>;
output-high;

4
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
View File

@ -226,7 +226,7 @@
};
&gpio0 {
touch-interrupt {
touch-interrupt-hog {
gpio-hog;
gpios = <24 GPIO_ACTIVE_LOW>;
input;
@ -234,7 +234,7 @@
};
&gpio1 {
can-trx-en-gpio{
can-trx-en-hog {
gpio-hog;
gpios = <28 GPIO_ACTIVE_HIGH>;
output-low;

2
arch/arm/boot/dts/r8a7742-iwg21m.dtsi
View File

@ -37,7 +37,7 @@
&gpio0 {
/* GP0_18 set low to select QSPI. Doing so will disable VIN2 */
qspi_en {
qspi-en-hog {
gpio-hog;
gpios = <18 GPIO_ACTIVE_HIGH>;
output-low;

2
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
View File

@ -116,7 +116,7 @@
};
&gpio2 {
interrupt-fixup {
interrupt-fixup-hog {
gpio-hog;
gpios = <29 GPIO_ACTIVE_HIGH>;
line-name = "hdmi-hpd-int";

5
arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
View File

@ -26,3 +26,8 @@
&uart0 {
status = "okay";
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};

16
arch/arm/boot/dts/r9a06g032.dtsi
View File

@ -66,6 +66,22 @@
interrupt-parent = <&gic>;
ranges;
wdt0: watchdog@40008000 {
compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
reg = <0x40008000 0x1000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
status = "disabled";
};
wdt1: watchdog@40009000 {
compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
reg = <0x40009000 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
status = "disabled";
};
sysctrl: system-controller@4000c000 {
compatible = "renesas,r9a06g032-sysctrl";
reg = <0x4000c000 0x1000>;

2
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
View File

@ -77,7 +77,7 @@
};
&gpio6 {
usb_hub_reset {
usb-hub-reset-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;

2
arch/arm64/boot/dts/renesas/hihope-common.dtsi
View File

@ -140,7 +140,7 @@
};
&gpio6 {
usb1-reset {
usb1-reset-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_LOW>;
output-low;

2
arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi
View File

@ -20,7 +20,7 @@
* When GP1_20 is LOW LVDS0 is connected to the LVDS connector
* When GP1_20 is HIGH LVDS0 is connected to the LT8918L
*/
lvds-connector-en-gpio {
lvds-connector-en-hog {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
output-low;

2
arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts
View File

@ -68,7 +68,7 @@
* When GP0_17 is low LVDS[01] are connected to the LVDS connector
* When GP0_17 is high LVDS[01] are connected to the LT8918L
*/
lvds-connector-en-gpio{
lvds-connector-en-hog {
gpio-hog;
gpios = <17 GPIO_ACTIVE_HIGH>;
output-low;

5
arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
View File

@ -31,6 +31,11 @@
clock-frequency = <32768>;
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif3 {
status = "okay";
};

10
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
View File

@ -59,6 +59,16 @@
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a779f0-wdt",
"renesas,rcar-gen4-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 907>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779f0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;

4
arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
View File

@ -18,8 +18,8 @@
};
&pinctrl {
/delete-node/ can0-stb;
/delete-node/ can1-stb;
/delete-node/ can0-stb-hog;
/delete-node/ can1-stb-hog;
/delete-node/ gpio-sd0-pwr-en-hog;
/delete-node/ sd0-dev-sel-hog;
/delete-node/ sd1-pwr-en-hog;

4
arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
View File

@ -18,7 +18,7 @@
};
/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
can0-stb {
can0-stb-hog {
gpio-hog;
gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
output-low;
@ -31,7 +31,7 @@
};
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
can1-stb {
can1-stb-hog {
gpio-hog;
gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
output-low;

2
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
View File

@ -34,7 +34,7 @@
#if SW_RSPI_CAN
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
can1-stb {
can1-stb-hog {
gpio-hog;
gpios = <RZG2L_GPIO(44, 3) GPIO_ACTIVE_HIGH>;
output-low;

14
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
View File

@ -206,3 +206,17 @@
};
#endif
&wdt0 {
status = "okay";
timeout-sec = <60>;
};
&wdt1 {
status = "okay";
timeout-sec = <60>;
};
&wdt2 {
status = "okay";
timeout-sec = <60>;
};

2
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
View File

@ -414,7 +414,7 @@
&sound_pcm_pins>;
ports {
/* rsnd_port0/1 are on salvator-common */
/* rsnd_port0/1 are defined in ulcb.dtsi */
rsnd_port2: port@2 {
reg = <2>;
rsnd_for_pcm3168a_play: endpoint {

1
include/dt-bindings/clock/r9a06g032-sysctrl.h
View File

@ -74,6 +74,7 @@
#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */
#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */
#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */
#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */
#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */
#define R9A06G032_HCLK_CAN0 85
#define R9A06G032_HCLK_CAN1 86