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x86/pmc_atom: Eisable a few S0ix wake up events for S0ix residency
Disable PMC S0IX_WAKE_EN events coming from LPC block(unused) and also from GPIO_SUS ored dedicated IRQs (must be disabled as per PMC programming rule), GPIOSCORE ored dedicated IRQs (must be disabled as per PMC programming rule), GPIO_SUS shared IRQ (not necessary since the IOAPIC_DS wake event will still work), GPIO_SCORE shared IRQ (not necessary since the IOAPIC_DS wake event will still work). Signed-off-by: Aubrey Li <aubrey.li@linux.intel.com> Link: http://lkml.kernel.org/r/53B0FF22.5080403@linux.intel.com Signed-off-by: Olivier Leveque <olivier.leveque@intel.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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@ -19,6 +19,27 @@
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/* ValleyView Power Control Unit PCI Device ID */
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#define PCI_DEVICE_ID_VLV_PMC 0x0F1C
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/* PMC Memory mapped IO registers */
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#define PMC_BASE_ADDR_OFFSET 0x44
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#define PMC_BASE_ADDR_MASK 0xFFFFFE00
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#define PMC_MMIO_REG_LEN 0x100
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#define PMC_REG_BIT_WIDTH 32
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/* S0ix wake event control */
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#define PMC_S0IX_WAKE_EN 0x3C
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#define BIT_LPC_CLOCK_RUN BIT(4)
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#define BIT_SHARED_IRQ_GPSC BIT(5)
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#define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18)
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#define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19)
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#define BIT_SHARED_IRQ_GPSS BIT(20)
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#define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \
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BIT_SHARED_IRQ_GPSC | \
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BIT_ORED_DEDICATED_IRQ_GPSS | \
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BIT_ORED_DEDICATED_IRQ_GPSC | \
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BIT_SHARED_IRQ_GPSS)
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/* PMC I/O Registers */
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#define ACPI_BASE_ADDR_OFFSET 0x40
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#define ACPI_BASE_ADDR_MASK 0xFFFFFE00
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@ -23,8 +23,24 @@
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#include <asm/pmc_atom.h>
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struct pmc_dev {
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u32 base_addr;
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void __iomem *regmap;
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};
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static struct pmc_dev pmc_device;
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static u32 acpi_base_addr;
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static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
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{
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return readl(pmc->regmap + reg_offset);
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}
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static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
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{
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writel(val, pmc->regmap + reg_offset);
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}
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static void pmc_power_off(void)
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{
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u16 pm1_cnt_port;
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@ -42,8 +58,23 @@ static void pmc_power_off(void)
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outl(pm1_cnt_value, pm1_cnt_port);
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}
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static void pmc_hw_reg_setup(struct pmc_dev *pmc)
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{
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/*
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* Disable PMC S0IX_WAKE_EN events coming from:
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* - LPC clock run
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* - GPIO_SUS ored dedicated IRQs
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* - GPIO_SCORE ored dedicated IRQs
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* - GPIO_SUS shared IRQ
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* - GPIO_SCORE shared IRQ
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*/
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pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
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}
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static int pmc_setup_dev(struct pci_dev *pdev)
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{
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struct pmc_dev *pmc = &pmc_device;
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/* Obtain ACPI base address */
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pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
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acpi_base_addr &= ACPI_BASE_ADDR_MASK;
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@ -52,6 +83,17 @@ static int pmc_setup_dev(struct pci_dev *pdev)
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if (acpi_base_addr != 0 && pm_power_off == NULL)
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pm_power_off = pmc_power_off;
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pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
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pmc->base_addr &= PMC_BASE_ADDR_MASK;
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pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
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if (!pmc->regmap) {
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dev_err(&pdev->dev, "error: ioremap failed\n");
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return -ENOMEM;
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}
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/* PMC hardware registers setup */
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pmc_hw_reg_setup(pmc);
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return 0;
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}
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