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dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740

The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
compared to 3 in FU540. Update the DT documentation accordingly with
"compatible" and "interrupt" property changes.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Yash Shah 2020-12-10 15:58:02 +05:30 committed by Palmer Dabbelt
parent 21855cac82
commit af951c3a11
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@ -27,6 +27,7 @@ select:
items:
- enum:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
required:
- compatible
@ -34,7 +35,9 @@ select:
properties:
compatible:
items:
- const: sifive,fu540-c000-ccache
- enum:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- const: cache
cache-block-size:
@ -52,10 +55,13 @@ properties:
cache-unified: true
interrupts:
description: |
Must contain entries for DirError, DataError and DataFail signals.
minItems: 3
maxItems: 3
maxItems: 4
items:
- description: DirError interrupt
- description: DataError interrupt
- description: DataFail interrupt
- description: DirFail interrupt
reg:
maxItems: 1
@ -67,6 +73,26 @@ properties:
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
The reserved memory node should be defined as per the bindings in reserved-memory.txt.
if:
properties:
compatible:
contains:
const: sifive,fu540-c000-ccache
then:
properties:
interrupts:
description: |
Must contain entries for DirError, DataError and DataFail signals.
maxItems: 3
else:
properties:
interrupts:
description: |
Must contain entries for DirError, DataError, DataFail, DirFail signals.
minItems: 4
additionalProperties: false
required: