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ARM: dts: vf610-zii-dev: Add QSPI node
Both rev C and rev B of the board come with two QSPI-NOR chips attached to the SoC. Add DT code describing all of this. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Fabio Estevam <festevam@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -177,6 +177,36 @@
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status = "okay";
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};
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&qspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi0>;
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status = "okay";
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/*
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* Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR
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* modes, so, spi-max-frequency is limited to 90MHz
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*/
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flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <90000000>;
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spi-rx-bus-width = <4>;
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reg = <0>;
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m25p,fast-read;
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};
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flash@2 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <90000000>;
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spi-rx-bus-width = <4>;
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reg = <2>;
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m25p,fast-read;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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@ -360,12 +390,18 @@
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pinctrl_qspi0: qspi0grp {
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fsl,pins = <
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VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3
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VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff
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VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3
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VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3
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VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3
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VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3
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VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2
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VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2
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VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3
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VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3
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VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3
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VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3
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VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2
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VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2
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VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3
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VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3
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VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3
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VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3
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>;
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};
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