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mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as well as the hardware BCH controller. DMA is not currently implemented. While older 47xx SoCs also have a BCH controller, they are incompatible with the one in the 4780 due to differing register/bit positions, which would make implementing a common driver for them quite messy. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: linux-mtd@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Brian: fixed a few small mistakes] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Alex Smith
Brian Norris
parent
48bf35de31
commit
ae02ab00aa
@ -519,6 +519,13 @@ config MTD_NAND_JZ4740
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help
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Enables support for NAND Flash on JZ4740 SoC based boards.
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config MTD_NAND_JZ4780
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tristate "Support for NAND on JZ4780 SoC"
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depends on MACH_JZ4780 && JZ4780_NEMC
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help
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Enables support for NAND Flash connected to the NEMC on JZ4780 SoC
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based boards, using the BCH controller for hardware error correction.
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config MTD_NAND_FSMC
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tristate "Support for NAND on ST Micros FSMC"
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depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300
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@ -49,6 +49,7 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
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obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o
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obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
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obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
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obj-$(CONFIG_MTD_NAND_JZ4780) += jz4780_nand.o jz4780_bch.o
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obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
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obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
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obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
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381
drivers/mtd/nand/jz4780_bch.c
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381
drivers/mtd/nand/jz4780_bch.c
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@ -0,0 +1,381 @@
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/*
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* JZ4780 BCH controller
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*
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* Copyright (c) 2015 Imagination Technologies
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* Author: Alex Smith <alex.smith@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include "jz4780_bch.h"
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#define BCH_BHCR 0x0
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#define BCH_BHCCR 0x8
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#define BCH_BHCNT 0xc
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#define BCH_BHDR 0x10
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#define BCH_BHPAR0 0x14
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#define BCH_BHERR0 0x84
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#define BCH_BHINT 0x184
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#define BCH_BHINTES 0x188
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#define BCH_BHINTEC 0x18c
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#define BCH_BHINTE 0x190
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#define BCH_BHCR_BSEL_SHIFT 4
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#define BCH_BHCR_BSEL_MASK (0x7f << BCH_BHCR_BSEL_SHIFT)
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#define BCH_BHCR_ENCE BIT(2)
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#define BCH_BHCR_INIT BIT(1)
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#define BCH_BHCR_BCHE BIT(0)
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#define BCH_BHCNT_PARITYSIZE_SHIFT 16
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#define BCH_BHCNT_PARITYSIZE_MASK (0x7f << BCH_BHCNT_PARITYSIZE_SHIFT)
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#define BCH_BHCNT_BLOCKSIZE_SHIFT 0
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#define BCH_BHCNT_BLOCKSIZE_MASK (0x7ff << BCH_BHCNT_BLOCKSIZE_SHIFT)
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#define BCH_BHERR_MASK_SHIFT 16
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#define BCH_BHERR_MASK_MASK (0xffff << BCH_BHERR_MASK_SHIFT)
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#define BCH_BHERR_INDEX_SHIFT 0
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#define BCH_BHERR_INDEX_MASK (0x7ff << BCH_BHERR_INDEX_SHIFT)
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#define BCH_BHINT_ERRC_SHIFT 24
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#define BCH_BHINT_ERRC_MASK (0x7f << BCH_BHINT_ERRC_SHIFT)
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#define BCH_BHINT_TERRC_SHIFT 16
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#define BCH_BHINT_TERRC_MASK (0x7f << BCH_BHINT_TERRC_SHIFT)
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#define BCH_BHINT_DECF BIT(3)
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#define BCH_BHINT_ENCF BIT(2)
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#define BCH_BHINT_UNCOR BIT(1)
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#define BCH_BHINT_ERR BIT(0)
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#define BCH_CLK_RATE (200 * 1000 * 1000)
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/* Timeout for BCH calculation/correction. */
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#define BCH_TIMEOUT_US 100000
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struct jz4780_bch {
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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struct mutex lock;
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};
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static void jz4780_bch_init(struct jz4780_bch *bch,
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struct jz4780_bch_params *params, bool encode)
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{
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u32 reg;
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/* Clear interrupt status. */
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writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
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/* Set up BCH count register. */
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reg = params->size << BCH_BHCNT_BLOCKSIZE_SHIFT;
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reg |= params->bytes << BCH_BHCNT_PARITYSIZE_SHIFT;
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writel(reg, bch->base + BCH_BHCNT);
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/* Initialise and enable BCH. */
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reg = BCH_BHCR_BCHE | BCH_BHCR_INIT;
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reg |= params->strength << BCH_BHCR_BSEL_SHIFT;
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if (encode)
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reg |= BCH_BHCR_ENCE;
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writel(reg, bch->base + BCH_BHCR);
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}
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static void jz4780_bch_disable(struct jz4780_bch *bch)
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{
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writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
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writel(BCH_BHCR_BCHE, bch->base + BCH_BHCCR);
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}
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static void jz4780_bch_write_data(struct jz4780_bch *bch, const void *buf,
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size_t size)
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{
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size_t size32 = size / sizeof(u32);
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size_t size8 = size % sizeof(u32);
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const u32 *src32;
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const u8 *src8;
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src32 = (const u32 *)buf;
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while (size32--)
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writel(*src32++, bch->base + BCH_BHDR);
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src8 = (const u8 *)src32;
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while (size8--)
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writeb(*src8++, bch->base + BCH_BHDR);
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}
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static void jz4780_bch_read_parity(struct jz4780_bch *bch, void *buf,
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size_t size)
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{
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size_t size32 = size / sizeof(u32);
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size_t size8 = size % sizeof(u32);
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u32 *dest32;
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u8 *dest8;
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u32 val, offset = 0;
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dest32 = (u32 *)buf;
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while (size32--) {
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*dest32++ = readl(bch->base + BCH_BHPAR0 + offset);
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offset += sizeof(u32);
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}
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dest8 = (u8 *)dest32;
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val = readl(bch->base + BCH_BHPAR0 + offset);
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switch (size8) {
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case 3:
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dest8[2] = (val >> 16) & 0xff;
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case 2:
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dest8[1] = (val >> 8) & 0xff;
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case 1:
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dest8[0] = val & 0xff;
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break;
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}
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}
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static bool jz4780_bch_wait_complete(struct jz4780_bch *bch, unsigned int irq,
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u32 *status)
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{
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u32 reg;
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int ret;
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/*
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* While we could use interrupts here and sleep until the operation
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* completes, the controller works fairly quickly (usually a few
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* microseconds) and so the overhead of sleeping until we get an
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* interrupt quite noticeably decreases performance.
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*/
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ret = readl_poll_timeout(bch->base + BCH_BHINT, reg,
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(reg & irq) == irq, 0, BCH_TIMEOUT_US);
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if (ret)
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return false;
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if (status)
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*status = reg;
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writel(reg, bch->base + BCH_BHINT);
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return true;
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}
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/**
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* jz4780_bch_calculate() - calculate ECC for a data buffer
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* @bch: BCH device.
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* @params: BCH parameters.
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* @buf: input buffer with raw data.
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* @ecc_code: output buffer with ECC.
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*
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* Return: 0 on success, -ETIMEDOUT if timed out while waiting for BCH
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* controller.
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*/
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int jz4780_bch_calculate(struct jz4780_bch *bch, struct jz4780_bch_params *params,
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const u8 *buf, u8 *ecc_code)
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{
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int ret = 0;
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mutex_lock(&bch->lock);
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jz4780_bch_init(bch, params, true);
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jz4780_bch_write_data(bch, buf, params->size);
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if (jz4780_bch_wait_complete(bch, BCH_BHINT_ENCF, NULL)) {
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jz4780_bch_read_parity(bch, ecc_code, params->bytes);
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} else {
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dev_err(bch->dev, "timed out while calculating ECC\n");
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ret = -ETIMEDOUT;
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}
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jz4780_bch_disable(bch);
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mutex_unlock(&bch->lock);
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return ret;
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}
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EXPORT_SYMBOL(jz4780_bch_calculate);
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/**
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* jz4780_bch_correct() - detect and correct bit errors
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* @bch: BCH device.
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* @params: BCH parameters.
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* @buf: raw data read from the chip.
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* @ecc_code: ECC read from the chip.
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*
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* Given the raw data and the ECC read from the NAND device, detects and
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* corrects errors in the data.
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*
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* Return: the number of bit errors corrected, or -1 if there are too many
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* errors to correct or we timed out waiting for the controller.
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*/
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int jz4780_bch_correct(struct jz4780_bch *bch, struct jz4780_bch_params *params,
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u8 *buf, u8 *ecc_code)
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{
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u32 reg, mask, index;
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int i, ret, count;
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mutex_lock(&bch->lock);
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jz4780_bch_init(bch, params, false);
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jz4780_bch_write_data(bch, buf, params->size);
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jz4780_bch_write_data(bch, ecc_code, params->bytes);
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if (!jz4780_bch_wait_complete(bch, BCH_BHINT_DECF, ®)) {
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dev_err(bch->dev, "timed out while correcting data\n");
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ret = -1;
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goto out;
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}
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if (reg & BCH_BHINT_UNCOR) {
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dev_warn(bch->dev, "uncorrectable ECC error\n");
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ret = -1;
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goto out;
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}
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/* Correct any detected errors. */
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if (reg & BCH_BHINT_ERR) {
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count = (reg & BCH_BHINT_ERRC_MASK) >> BCH_BHINT_ERRC_SHIFT;
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ret = (reg & BCH_BHINT_TERRC_MASK) >> BCH_BHINT_TERRC_SHIFT;
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for (i = 0; i < count; i++) {
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reg = readl(bch->base + BCH_BHERR0 + (i * 4));
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mask = (reg & BCH_BHERR_MASK_MASK) >>
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BCH_BHERR_MASK_SHIFT;
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index = (reg & BCH_BHERR_INDEX_MASK) >>
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BCH_BHERR_INDEX_SHIFT;
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buf[(index * 2) + 0] ^= mask;
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buf[(index * 2) + 1] ^= mask >> 8;
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}
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} else {
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ret = 0;
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}
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out:
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jz4780_bch_disable(bch);
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mutex_unlock(&bch->lock);
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return ret;
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}
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EXPORT_SYMBOL(jz4780_bch_correct);
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/**
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* jz4780_bch_get() - get the BCH controller device
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* @np: BCH device tree node.
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*
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* Gets the BCH controller device from the specified device tree node. The
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* device must be released with jz4780_bch_release() when it is no longer being
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* used.
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*
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* Return: a pointer to jz4780_bch, errors are encoded into the pointer.
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* PTR_ERR(-EPROBE_DEFER) if the device hasn't been initialised yet.
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*/
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static struct jz4780_bch *jz4780_bch_get(struct device_node *np)
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{
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struct platform_device *pdev;
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struct jz4780_bch *bch;
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pdev = of_find_device_by_node(np);
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if (!pdev || !platform_get_drvdata(pdev))
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return ERR_PTR(-EPROBE_DEFER);
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get_device(&pdev->dev);
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bch = platform_get_drvdata(pdev);
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clk_prepare_enable(bch->clk);
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bch->dev = &pdev->dev;
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return bch;
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}
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/**
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* of_jz4780_bch_get() - get the BCH controller from a DT node
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* @of_node: the node that contains a bch-controller property.
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*
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* Get the bch-controller property from the given device tree
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* node and pass it to jz4780_bch_get to do the work.
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*
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* Return: a pointer to jz4780_bch, errors are encoded into the pointer.
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* PTR_ERR(-EPROBE_DEFER) if the device hasn't been initialised yet.
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*/
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struct jz4780_bch *of_jz4780_bch_get(struct device_node *of_node)
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{
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struct jz4780_bch *bch = NULL;
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struct device_node *np;
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np = of_parse_phandle(of_node, "ingenic,bch-controller", 0);
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if (np) {
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bch = jz4780_bch_get(np);
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of_node_put(np);
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}
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return bch;
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}
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EXPORT_SYMBOL(of_jz4780_bch_get);
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/**
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* jz4780_bch_release() - release the BCH controller device
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* @bch: BCH device.
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*/
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void jz4780_bch_release(struct jz4780_bch *bch)
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{
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clk_disable_unprepare(bch->clk);
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put_device(bch->dev);
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}
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EXPORT_SYMBOL(jz4780_bch_release);
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static int jz4780_bch_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct jz4780_bch *bch;
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struct resource *res;
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bch = devm_kzalloc(dev, sizeof(*bch), GFP_KERNEL);
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if (!bch)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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bch->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(bch->base))
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return PTR_ERR(bch->base);
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jz4780_bch_disable(bch);
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bch->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(bch->clk)) {
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dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(bch->clk));
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return PTR_ERR(bch->clk);
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}
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clk_set_rate(bch->clk, BCH_CLK_RATE);
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mutex_init(&bch->lock);
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bch->dev = dev;
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platform_set_drvdata(pdev, bch);
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return 0;
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}
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static const struct of_device_id jz4780_bch_dt_match[] = {
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{ .compatible = "ingenic,jz4780-bch" },
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{},
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};
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MODULE_DEVICE_TABLE(of, jz4780_bch_dt_match);
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static struct platform_driver jz4780_bch_driver = {
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.probe = jz4780_bch_probe,
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.driver = {
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.name = "jz4780-bch",
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.of_match_table = of_match_ptr(jz4780_bch_dt_match),
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},
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};
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module_platform_driver(jz4780_bch_driver);
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MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
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MODULE_AUTHOR("Harvey Hunt <harvey.hunt@imgtec.com>");
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MODULE_DESCRIPTION("Ingenic JZ4780 BCH error correction driver");
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MODULE_LICENSE("GPL v2");
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43
drivers/mtd/nand/jz4780_bch.h
Normal file
43
drivers/mtd/nand/jz4780_bch.h
Normal file
@ -0,0 +1,43 @@
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/*
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* JZ4780 BCH controller
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*
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* Copyright (c) 2015 Imagination Technologies
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* Author: Alex Smith <alex.smith@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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||||
#ifndef __DRIVERS_MTD_NAND_JZ4780_BCH_H__
|
||||
#define __DRIVERS_MTD_NAND_JZ4780_BCH_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct device;
|
||||
struct device_node;
|
||||
struct jz4780_bch;
|
||||
|
||||
/**
|
||||
* struct jz4780_bch_params - BCH parameters
|
||||
* @size: data bytes per ECC step.
|
||||
* @bytes: ECC bytes per step.
|
||||
* @strength: number of correctable bits per ECC step.
|
||||
*/
|
||||
struct jz4780_bch_params {
|
||||
int size;
|
||||
int bytes;
|
||||
int strength;
|
||||
};
|
||||
|
||||
int jz4780_bch_calculate(struct jz4780_bch *bch,
|
||||
struct jz4780_bch_params *params,
|
||||
const u8 *buf, u8 *ecc_code);
|
||||
int jz4780_bch_correct(struct jz4780_bch *bch,
|
||||
struct jz4780_bch_params *params, u8 *buf,
|
||||
u8 *ecc_code);
|
||||
|
||||
void jz4780_bch_release(struct jz4780_bch *bch);
|
||||
struct jz4780_bch *of_jz4780_bch_get(struct device_node *np);
|
||||
|
||||
#endif /* __DRIVERS_MTD_NAND_JZ4780_BCH_H__ */
|
||||
425
drivers/mtd/nand/jz4780_nand.c
Normal file
425
drivers/mtd/nand/jz4780_nand.c
Normal file
@ -0,0 +1,425 @@
|
||||
/*
|
||||
* JZ4780 NAND driver
|
||||
*
|
||||
* Copyright (c) 2015 Imagination Technologies
|
||||
* Author: Alex Smith <alex.smith@imgtec.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/of_mtd.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
||||
#include <linux/jz4780-nemc.h>
|
||||
|
||||
#include "jz4780_bch.h"
|
||||
|
||||
#define DRV_NAME "jz4780-nand"
|
||||
|
||||
#define OFFSET_DATA 0x00000000
|
||||
#define OFFSET_CMD 0x00400000
|
||||
#define OFFSET_ADDR 0x00800000
|
||||
|
||||
/* Command delay when there is no R/B pin. */
|
||||
#define RB_DELAY_US 100
|
||||
|
||||
struct jz4780_nand_cs {
|
||||
unsigned int bank;
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
struct jz4780_nand_controller {
|
||||
struct device *dev;
|
||||
struct jz4780_bch *bch;
|
||||
struct nand_hw_control controller;
|
||||
unsigned int num_banks;
|
||||
struct list_head chips;
|
||||
int selected;
|
||||
struct jz4780_nand_cs cs[];
|
||||
};
|
||||
|
||||
struct jz4780_nand_chip {
|
||||
struct nand_chip chip;
|
||||
struct list_head chip_list;
|
||||
|
||||
struct nand_ecclayout ecclayout;
|
||||
|
||||
struct gpio_desc *busy_gpio;
|
||||
struct gpio_desc *wp_gpio;
|
||||
unsigned int reading: 1;
|
||||
};
|
||||
|
||||
static inline struct jz4780_nand_chip *to_jz4780_nand_chip(struct mtd_info *mtd)
|
||||
{
|
||||
return container_of(mtd_to_nand(mtd), struct jz4780_nand_chip, chip);
|
||||
}
|
||||
|
||||
static inline struct jz4780_nand_controller *to_jz4780_nand_controller(struct nand_hw_control *ctrl)
|
||||
{
|
||||
return container_of(ctrl, struct jz4780_nand_controller, controller);
|
||||
}
|
||||
|
||||
static void jz4780_nand_select_chip(struct mtd_info *mtd, int chipnr)
|
||||
{
|
||||
struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
|
||||
struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
|
||||
struct jz4780_nand_cs *cs;
|
||||
|
||||
/* Ensure the currently selected chip is deasserted. */
|
||||
if (chipnr == -1 && nfc->selected >= 0) {
|
||||
cs = &nfc->cs[nfc->selected];
|
||||
jz4780_nemc_assert(nfc->dev, cs->bank, false);
|
||||
}
|
||||
|
||||
nfc->selected = chipnr;
|
||||
}
|
||||
|
||||
static void jz4780_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
|
||||
unsigned int ctrl)
|
||||
{
|
||||
struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
|
||||
struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
|
||||
struct jz4780_nand_cs *cs;
|
||||
|
||||
if (WARN_ON(nfc->selected < 0))
|
||||
return;
|
||||
|
||||
cs = &nfc->cs[nfc->selected];
|
||||
|
||||
jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE);
|
||||
|
||||
if (cmd == NAND_CMD_NONE)
|
||||
return;
|
||||
|
||||
if (ctrl & NAND_ALE)
|
||||
writeb(cmd, cs->base + OFFSET_ADDR);
|
||||
else if (ctrl & NAND_CLE)
|
||||
writeb(cmd, cs->base + OFFSET_CMD);
|
||||
}
|
||||
|
||||
static int jz4780_nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
|
||||
|
||||
return !gpiod_get_value_cansleep(nand->busy_gpio);
|
||||
}
|
||||
|
||||
static void jz4780_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
|
||||
{
|
||||
struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
|
||||
|
||||
nand->reading = (mode == NAND_ECC_READ);
|
||||
}
|
||||
|
||||
static int jz4780_nand_ecc_calculate(struct mtd_info *mtd, const u8 *dat,
|
||||
u8 *ecc_code)
|
||||
{
|
||||
struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
|
||||
struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
|
||||
struct jz4780_bch_params params;
|
||||
|
||||
/*
|
||||
* Don't need to generate the ECC when reading, BCH does it for us as
|
||||
* part of decoding/correction.
|
||||
*/
|
||||
if (nand->reading)
|
||||
return 0;
|
||||
|
||||
params.size = nand->chip.ecc.size;
|
||||
params.bytes = nand->chip.ecc.bytes;
|
||||
params.strength = nand->chip.ecc.strength;
|
||||
|
||||
return jz4780_bch_calculate(nfc->bch, ¶ms, dat, ecc_code);
|
||||
}
|
||||
|
||||
static int jz4780_nand_ecc_correct(struct mtd_info *mtd, u8 *dat,
|
||||
u8 *read_ecc, u8 *calc_ecc)
|
||||
{
|
||||
struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
|
||||
struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
|
||||
struct jz4780_bch_params params;
|
||||
|
||||
params.size = nand->chip.ecc.size;
|
||||
params.bytes = nand->chip.ecc.bytes;
|
||||
params.strength = nand->chip.ecc.strength;
|
||||
|
||||
return jz4780_bch_correct(nfc->bch, ¶ms, dat, read_ecc);
|
||||
}
|
||||
|
||||
static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *dev)
|
||||
{
|
||||
struct nand_chip *chip = &nand->chip;
|
||||
struct mtd_info *mtd = nand_to_mtd(chip);
|
||||
struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(chip->controller);
|
||||
struct nand_ecclayout *layout = &nand->ecclayout;
|
||||
u32 start, i;
|
||||
|
||||
chip->ecc.bytes = fls((1 + 8) * chip->ecc.size) *
|
||||
(chip->ecc.strength / 8);
|
||||
|
||||
if (nfc->bch && chip->ecc.mode == NAND_ECC_HW) {
|
||||
chip->ecc.hwctl = jz4780_nand_ecc_hwctl;
|
||||
chip->ecc.calculate = jz4780_nand_ecc_calculate;
|
||||
chip->ecc.correct = jz4780_nand_ecc_correct;
|
||||
} else if (!nfc->bch && chip->ecc.mode == NAND_ECC_HW) {
|
||||
dev_err(dev, "HW BCH selected, but BCH controller not found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (chip->ecc.mode == NAND_ECC_HW_SYNDROME) {
|
||||
dev_err(dev, "ECC HW syndrome not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (chip->ecc.mode != NAND_ECC_NONE)
|
||||
dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n",
|
||||
(nfc->bch) ? "hardware BCH" : "software ECC",
|
||||
chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
|
||||
else
|
||||
dev_info(dev, "not using ECC\n");
|
||||
|
||||
/* The NAND core will generate the ECC layout. */
|
||||
if (chip->ecc.mode == NAND_ECC_SOFT || chip->ecc.mode == NAND_ECC_SOFT_BCH)
|
||||
return 0;
|
||||
|
||||
/* Generate ECC layout. ECC codes are right aligned in the OOB area. */
|
||||
layout->eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
|
||||
|
||||
if (layout->eccbytes > mtd->oobsize - 2) {
|
||||
dev_err(dev,
|
||||
"invalid ECC config: required %d ECC bytes, but only %d are available",
|
||||
layout->eccbytes, mtd->oobsize - 2);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
start = mtd->oobsize - layout->eccbytes;
|
||||
for (i = 0; i < layout->eccbytes; i++)
|
||||
layout->eccpos[i] = start + i;
|
||||
|
||||
layout->oobfree[0].offset = 2;
|
||||
layout->oobfree[0].length = mtd->oobsize - layout->eccbytes - 2;
|
||||
|
||||
chip->ecc.layout = layout;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4780_nand_init_chip(struct platform_device *pdev,
|
||||
struct jz4780_nand_controller *nfc,
|
||||
struct device_node *np,
|
||||
unsigned int chipnr)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct jz4780_nand_chip *nand;
|
||||
struct jz4780_nand_cs *cs;
|
||||
struct resource *res;
|
||||
struct nand_chip *chip;
|
||||
struct mtd_info *mtd;
|
||||
const __be32 *reg;
|
||||
int ret = 0;
|
||||
|
||||
cs = &nfc->cs[chipnr];
|
||||
|
||||
reg = of_get_property(np, "reg", NULL);
|
||||
if (!reg)
|
||||
return -EINVAL;
|
||||
|
||||
cs->bank = be32_to_cpu(*reg);
|
||||
|
||||
jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, chipnr);
|
||||
cs->base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(cs->base))
|
||||
return PTR_ERR(cs->base);
|
||||
|
||||
nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
|
||||
if (!nand)
|
||||
return -ENOMEM;
|
||||
|
||||
nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
|
||||
|
||||
if (IS_ERR(nand->busy_gpio)) {
|
||||
ret = PTR_ERR(nand->busy_gpio);
|
||||
dev_err(dev, "failed to request busy GPIO: %d\n", ret);
|
||||
return ret;
|
||||
} else if (nand->busy_gpio) {
|
||||
nand->chip.dev_ready = jz4780_nand_dev_ready;
|
||||
}
|
||||
|
||||
nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
|
||||
|
||||
if (IS_ERR(nand->wp_gpio)) {
|
||||
ret = PTR_ERR(nand->wp_gpio);
|
||||
dev_err(dev, "failed to request WP GPIO: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
chip = &nand->chip;
|
||||
mtd = nand_to_mtd(chip);
|
||||
mtd->priv = chip;
|
||||
mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
|
||||
cs->bank);
|
||||
if (!mtd->name)
|
||||
return -ENOMEM;
|
||||
mtd->dev.parent = dev;
|
||||
|
||||
chip->IO_ADDR_R = cs->base + OFFSET_DATA;
|
||||
chip->IO_ADDR_W = cs->base + OFFSET_DATA;
|
||||
chip->chip_delay = RB_DELAY_US;
|
||||
chip->options = NAND_NO_SUBPAGE_WRITE;
|
||||
chip->select_chip = jz4780_nand_select_chip;
|
||||
chip->cmd_ctrl = jz4780_nand_cmd_ctrl;
|
||||
chip->ecc.mode = NAND_ECC_HW;
|
||||
chip->controller = &nfc->controller;
|
||||
nand_set_flash_node(chip, np);
|
||||
|
||||
ret = nand_scan_ident(mtd, 1, NULL);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = jz4780_nand_init_ecc(nand, dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nand_scan_tail(mtd);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = mtd_device_register(mtd, NULL, 0);
|
||||
if (ret) {
|
||||
nand_release(mtd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
list_add_tail(&nand->chip_list, &nfc->chips);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz4780_nand_cleanup_chips(struct jz4780_nand_controller *nfc)
|
||||
{
|
||||
struct jz4780_nand_chip *chip;
|
||||
|
||||
while (!list_empty(&nfc->chips)) {
|
||||
chip = list_first_entry(&nfc->chips, struct jz4780_nand_chip, chip_list);
|
||||
nand_release(nand_to_mtd(&chip->chip));
|
||||
list_del(&chip->chip_list);
|
||||
}
|
||||
}
|
||||
|
||||
static int jz4780_nand_init_chips(struct jz4780_nand_controller *nfc,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np;
|
||||
int i = 0;
|
||||
int ret;
|
||||
int num_chips = of_get_child_count(dev->of_node);
|
||||
|
||||
if (num_chips > nfc->num_banks) {
|
||||
dev_err(dev, "found %d chips but only %d banks\n", num_chips, nfc->num_banks);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for_each_child_of_node(dev->of_node, np) {
|
||||
ret = jz4780_nand_init_chip(pdev, nfc, np, i);
|
||||
if (ret) {
|
||||
jz4780_nand_cleanup_chips(nfc);
|
||||
return ret;
|
||||
}
|
||||
|
||||
i++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4780_nand_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
unsigned int num_banks;
|
||||
struct jz4780_nand_controller *nfc;
|
||||
int ret;
|
||||
|
||||
num_banks = jz4780_nemc_num_banks(dev);
|
||||
if (num_banks == 0) {
|
||||
dev_err(dev, "no banks found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
nfc = devm_kzalloc(dev, sizeof(*nfc) + (sizeof(nfc->cs[0]) * num_banks), GFP_KERNEL);
|
||||
if (!nfc)
|
||||
return -ENOMEM;
|
||||
|
||||
/*
|
||||
* Check for BCH HW before we call nand_scan_ident, to prevent us from
|
||||
* having to call it again if the BCH driver returns -EPROBE_DEFER.
|
||||
*/
|
||||
nfc->bch = of_jz4780_bch_get(dev->of_node);
|
||||
if (IS_ERR(nfc->bch))
|
||||
return PTR_ERR(nfc->bch);
|
||||
|
||||
nfc->dev = dev;
|
||||
nfc->num_banks = num_banks;
|
||||
|
||||
spin_lock_init(&nfc->controller.lock);
|
||||
INIT_LIST_HEAD(&nfc->chips);
|
||||
init_waitqueue_head(&nfc->controller.wq);
|
||||
|
||||
ret = jz4780_nand_init_chips(nfc, pdev);
|
||||
if (ret) {
|
||||
if (nfc->bch)
|
||||
jz4780_bch_release(nfc->bch);
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, nfc);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4780_nand_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct jz4780_nand_controller *nfc = platform_get_drvdata(pdev);
|
||||
|
||||
if (nfc->bch)
|
||||
jz4780_bch_release(nfc->bch);
|
||||
|
||||
jz4780_nand_cleanup_chips(nfc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id jz4780_nand_dt_match[] = {
|
||||
{ .compatible = "ingenic,jz4780-nand" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, jz4780_nand_dt_match);
|
||||
|
||||
static struct platform_driver jz4780_nand_driver = {
|
||||
.probe = jz4780_nand_probe,
|
||||
.remove = jz4780_nand_remove,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.of_match_table = of_match_ptr(jz4780_nand_dt_match),
|
||||
},
|
||||
};
|
||||
module_platform_driver(jz4780_nand_driver);
|
||||
|
||||
MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
|
||||
MODULE_AUTHOR("Harvey Hunt <harvey.hunt@imgtec.com>");
|
||||
MODULE_DESCRIPTION("Ingenic JZ4780 NAND driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user