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ARM: EXYNOS: Use MCPM call-backs to support S2R on exynos5420
Use the MCPM layer to handle core suspend/resume on Exynos5420. Also, restore the entry address setup code post-resume. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -15,6 +15,7 @@
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include <asm/cputype.h>
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#include <asm/cp15.h>
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@ -30,6 +31,8 @@
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#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
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#define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
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static void __iomem *ns_sram_base_addr;
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/*
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* The common v7_exit_coherency_flush API could not be used because of the
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* Erratum 799270 workaround. This macro is the same as the common one (in
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@ -318,10 +321,26 @@ static const struct of_device_id exynos_dt_mcpm_match[] = {
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{},
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};
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static void exynos_mcpm_setup_entry_point(void)
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{
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/*
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* U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
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* as part of secondary_cpu_start(). Let's redirect it to the
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* mcpm_entry_point(). This is done during both secondary boot-up as
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* well as system resume.
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*/
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__raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
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__raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
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__raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
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}
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static struct syscore_ops exynos_mcpm_syscore_ops = {
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.resume = exynos_mcpm_setup_entry_point,
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};
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static int __init exynos_mcpm_init(void)
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{
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struct device_node *node;
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void __iomem *ns_sram_base_addr;
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unsigned int value, i;
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int ret;
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@ -387,16 +406,9 @@ static int __init exynos_mcpm_init(void)
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pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
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}
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/*
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* U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
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* as part of secondary_cpu_start(). Let's redirect it to the
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* mcpm_entry_point().
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*/
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__raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
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__raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
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__raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
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exynos_mcpm_setup_entry_point();
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iounmap(ns_sram_base_addr);
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register_syscore_ops(&exynos_mcpm_syscore_ops);
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return ret;
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}
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@ -126,6 +126,18 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
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*/
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void exynos_cpu_power_down(int cpu)
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{
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if (cpu == 0 && (of_machine_is_compatible("samsung,exynos5420") ||
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of_machine_is_compatible("samsung,exynos5800"))) {
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/*
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* Bypass power down for CPU0 during suspend. Check for
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* the SYS_PWR_REG value to decide if we are suspending
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* the system.
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*/
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int val = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
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if (!(val & S5P_CORE_LOCAL_PWR_EN))
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return;
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}
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pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
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}
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@ -24,6 +24,7 @@
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/firmware.h>
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#include <asm/mcpm.h>
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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@ -72,6 +73,7 @@ struct exynos_pm_data {
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unsigned int *release_ret_regs;
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void (*pm_prepare)(void);
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void (*pm_resume_prepare)(void);
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void (*pm_resume)(void);
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int (*pm_suspend)(void);
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int (*cpu_suspend)(unsigned long);
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@ -172,9 +174,28 @@ static int exynos_cpu_suspend(unsigned long arg)
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static int exynos5420_cpu_suspend(unsigned long arg)
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{
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exynos_flush_cache_all();
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/* MCPM works with HW CPU identifiers */
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unsigned int mpidr = read_cpuid_mpidr();
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unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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__raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
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return exynos_cpu_do_idle();
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
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mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
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/*
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* Residency value passed to mcpm_cpu_suspend back-end
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* has to be given clear semantics. Set to 0 as a
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* temporary value.
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*/
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mcpm_cpu_suspend(0);
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}
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pr_info("Failed to suspend the system\n");
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/* return value != 0 means failure */
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return 1;
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}
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static void exynos_pm_set_wakeup_mask(void)
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@ -189,9 +210,6 @@ static void exynos_pm_enter_sleep_mode(void)
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/* Set value of power down register for sleep mode */
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exynos_sys_powerdown_conf(SYS_SLEEP);
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pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
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/* ensure at least INFORM0 has the resume address */
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pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
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}
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static void exynos_pm_prepare(void)
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@ -206,6 +224,9 @@ static void exynos_pm_prepare(void)
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pm_data->num_extra_save);
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exynos_pm_enter_sleep_mode();
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/* ensure at least INFORM0 has the resume address */
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pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
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}
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static void exynos5420_pm_prepare(void)
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@ -230,6 +251,10 @@ static void exynos5420_pm_prepare(void)
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exynos_pm_enter_sleep_mode();
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/* ensure at least INFORM0 has the resume address */
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
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pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
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tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
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tmp &= ~EXYNOS5_USE_RETENTION;
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pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
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@ -318,10 +343,21 @@ early_wakeup:
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pmu_raw_writel(0x0, S5P_INFORM1);
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}
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static void exynos5420_prepare_pm_resume(void)
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{
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
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WARN_ON(mcpm_cpu_powered_up());
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}
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static void exynos5420_pm_resume(void)
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{
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unsigned long tmp;
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/* Restore the CPU0 low power state register */
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tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
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pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
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EXYNOS5_ARM_CORE0_SYS_PWR_REG);
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/* Restore the sysram cpu state register */
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__raw_writel(exynos5420_cpu_state,
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sysram_base_addr + EXYNOS5420_CPU_STATE);
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@ -391,6 +427,8 @@ static int exynos_suspend_enter(suspend_state_t state)
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if (ret)
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return ret;
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if (pm_data->pm_resume_prepare)
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pm_data->pm_resume_prepare();
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s3c_pm_restore_uarts();
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S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
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@ -448,6 +486,7 @@ static struct exynos_pm_data exynos5420_pm_data = {
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.wkup_irq = exynos5250_wkup_irq,
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.wake_disable_mask = (0x7F << 7) | (0x1F << 1),
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.release_ret_regs = exynos5420_release_ret_regs,
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.pm_resume_prepare = exynos5420_prepare_pm_resume,
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.pm_resume = exynos5420_pm_resume,
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.pm_suspend = exynos5420_pm_suspend,
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.pm_prepare = exynos5420_pm_prepare,
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