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soc: mediatek: pwrap: add pwrap driver for MT6779 SoCs
MT6779 is a highly integrated SoCs, it uses PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -497,6 +497,45 @@ static int mt6765_regs[] = {
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[PWRAP_DCM_DBC_PRD] = 0x1E0,
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};
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static int mt6779_regs[] = {
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[PWRAP_MUX_SEL] = 0x0,
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[PWRAP_WRAP_EN] = 0x4,
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[PWRAP_DIO_EN] = 0x8,
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[PWRAP_RDDMY] = 0x20,
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[PWRAP_CSHEXT_WRITE] = 0x24,
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[PWRAP_CSHEXT_READ] = 0x28,
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[PWRAP_CSLEXT_WRITE] = 0x2C,
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[PWRAP_CSLEXT_READ] = 0x30,
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[PWRAP_EXT_CK_WRITE] = 0x34,
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[PWRAP_STAUPD_CTRL] = 0x3C,
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[PWRAP_STAUPD_GRPEN] = 0x40,
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[PWRAP_EINT_STA0_ADR] = 0x44,
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[PWRAP_HARB_HPRIO] = 0x68,
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[PWRAP_HIPRIO_ARB_EN] = 0x6C,
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[PWRAP_MAN_EN] = 0x7C,
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[PWRAP_MAN_CMD] = 0x80,
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[PWRAP_WACS0_EN] = 0x8C,
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[PWRAP_INIT_DONE0] = 0x90,
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[PWRAP_WACS1_EN] = 0x94,
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[PWRAP_WACS2_EN] = 0x9C,
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[PWRAP_INIT_DONE1] = 0x98,
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[PWRAP_INIT_DONE2] = 0xA0,
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[PWRAP_INT_EN] = 0xBC,
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[PWRAP_INT_FLG_RAW] = 0xC0,
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[PWRAP_INT_FLG] = 0xC4,
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[PWRAP_INT_CLR] = 0xC8,
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[PWRAP_INT1_EN] = 0xCC,
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[PWRAP_INT1_FLG] = 0xD4,
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[PWRAP_INT1_CLR] = 0xD8,
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[PWRAP_TIMER_EN] = 0xF0,
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[PWRAP_WDT_UNIT] = 0xF8,
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[PWRAP_WDT_SRC_EN] = 0xFC,
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[PWRAP_WDT_SRC_EN_1] = 0x100,
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[PWRAP_WACS2_CMD] = 0xC20,
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[PWRAP_WACS2_RDATA] = 0xC24,
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[PWRAP_WACS2_VLDCLR] = 0xC28,
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};
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static int mt6797_regs[] = {
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[PWRAP_MUX_SEL] = 0x0,
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[PWRAP_WRAP_EN] = 0x4,
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@ -945,6 +984,7 @@ enum pmic_type {
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enum pwrap_type {
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PWRAP_MT2701,
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PWRAP_MT6765,
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PWRAP_MT6779,
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PWRAP_MT6797,
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PWRAP_MT7622,
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PWRAP_MT8135,
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@ -1377,6 +1417,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
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break;
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case PWRAP_MT2701:
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case PWRAP_MT6765:
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case PWRAP_MT6779:
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case PWRAP_MT6797:
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case PWRAP_MT8173:
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case PWRAP_MT8516:
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@ -1783,6 +1824,19 @@ static const struct pmic_wrapper_type pwrap_mt6765 = {
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.init_soc_specific = NULL,
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};
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static const struct pmic_wrapper_type pwrap_mt6779 = {
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.regs = mt6779_regs,
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.type = PWRAP_MT6779,
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.arb_en_all = 0xfbb7f,
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.int_en_all = 0xfffffffe,
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.int1_en_all = 0,
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.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
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.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
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.caps = 0,
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.init_reg_clock = pwrap_common_init_reg_clock,
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.init_soc_specific = NULL,
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};
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static const struct pmic_wrapper_type pwrap_mt6797 = {
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.regs = mt6797_regs,
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.type = PWRAP_MT6797,
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@ -1867,6 +1921,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
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}, {
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.compatible = "mediatek,mt6765-pwrap",
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.data = &pwrap_mt6765,
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}, {
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.compatible = "mediatek,mt6779-pwrap",
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.data = &pwrap_mt6779,
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}, {
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.compatible = "mediatek,mt6797-pwrap",
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.data = &pwrap_mt6797,
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