From d900a1cd310de097fb94796ca575c118b2637b3b Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Sat, 16 Oct 2021 12:20:22 +0200 Subject: [PATCH 001/574] arm64: dts: allwinner: add 'chassis-type' property A new 'chassis-type' root node property has recently been approved for the device-tree specification, in order to provide a simple way for userspace to detect the device form factor and adjust their behavior accordingly. This patch fills in this property for end-user devices (such as laptops, smartphones and tablets) based on Allwinner ARM64 processors. Signed-off-by: Arnaud Ferraris Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211016102025.23346-2-arnaud.ferraris@collabora.com --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 1 + arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 ++ arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 1 + arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 1 + 4 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 34e67f5f8297..63571df24da4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -15,6 +15,7 @@ / { model = "Pinebook"; compatible = "pine64,pinebook", "allwinner,sun50i-a64"; + chassis-type = "laptop"; aliases { serial0 = &uart0; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 5b44a979f250..87847116ab6d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -12,6 +12,8 @@ #include / { + chassis-type = "handset"; + aliases { ethernet0 = &rtl8723cs; serial0 = &uart0; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts index adb0b28b06d8..0a5607f73049 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts @@ -16,6 +16,7 @@ / { model = "PineTab, Development Sample"; compatible = "pine64,pinetab", "allwinner,sun50i-a64"; + chassis-type = "tablet"; aliases { serial0 = &uart0; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index aef571acd67f..aff0660b899c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -14,6 +14,7 @@ / { model = "Olimex A64 Teres-I"; compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64"; + chassis-type = "laptop"; aliases { serial0 = &uart0; From 1ab0a62f28c9347a5abb9ff9ba544271deb45f87 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 14 Oct 2021 16:44:12 +0200 Subject: [PATCH 002/574] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add missing camera regulators make dtbs_check: arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dt.yaml: ov5640@3c: 'AVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dt.yaml: ov5640@3c: 'DVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dt.yaml: ov5640@3c: 'DOVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml Fix this by describing the missing regulators. Signed-off-by: Geert Uytterhoeven Reviewed-by: Kieran Bingham Link: https://lore.kernel.org/r/300149c730931914b77e17df6bcce89b67c3005f.1634222546.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts | 16 ++++++++++++++++ .../r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi | 3 +++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts index 33db5938f2d4..3c8a7c8b1fdd 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -44,6 +44,22 @@ #clock-cells = <0>; clock-frequency = <26000000>; }; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p8v: 2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; }; &avb { diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi index 70c72ba4fe72..40cef0b1d1e6 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi @@ -17,6 +17,9 @@ reg = <0x3c>; clocks = <&MCLK_CAM>; clock-names = "xclk"; + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_2p8v>; + DVDD-supply = <®_1p8v>; status = "okay"; port { From 68f8eb19c18a377181622e58c1fd2ca0f5c0d15d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 3 Nov 2021 19:55:58 +0000 Subject: [PATCH 003/574] arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes Add SCIF[1-4] nodes to r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211103195600.23964-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 485ef5f0fea1..09bfdedfac2a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -194,6 +194,78 @@ status = "disabled"; }; + scif1: serial@1004bc00 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004bc00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + canfd: can@10050000 { compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; From 5a8aa63c9bca800e6049d90422abe5404227a703 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 3 Nov 2021 19:56:00 +0000 Subject: [PATCH 004/574] arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board SCIF2 interface is available on PMOD1 connector (CN7) on carrier board, This patch adds pinmux and scif2 node to carrier board dtsi file. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211103195600.23964-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 28 ++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 2863e487a640..4c32f068a1f0 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -21,9 +21,13 @@ * */ +/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + / { aliases { serial0 = &scif0; + serial1 = &scif2; i2c0 = &i2c0; i2c1 = &i2c1; i2c3 = &i2c3; @@ -208,6 +212,13 @@ ; /* RxD */ }; + scif2_pins: scif2 { + pinmux = , /* TxD */ + , /* RxD */ + , /* CTS# */ + ; /* RTS# */ + }; + sd1-pwr-en-hog { gpio-hog; gpios = ; @@ -277,6 +288,23 @@ status = "okay"; }; +/* + * To enable SCIF2 (SER0) on PMOD1 (CN7) + * SW1 should be at position 2->3 so that SER0_CTS# line is activated + * SW2 should be at position 2->3 so that SER0_TX line is activated + * SW3 should be at position 2->3 so that SER0_RX line is activated + * SW4 should be at position 2->3 so that SER0_RTS# line is activated + */ +#if PMOD1_SER0 +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; +#endif + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-1 = <&sdhi1_pins_uhs>; From f9a2adcc9e908907129c18518d4ea6195c44bf00 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 9 Nov 2021 12:31:10 +0000 Subject: [PATCH 005/574] arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes Add SCI[0-1] nodes to r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211109123110.8543-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 09bfdedfac2a..358db254c4ea 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -266,6 +266,36 @@ status = "disabled"; }; + sci0: serial@1004d000 { + compatible = "renesas,r9a07g044-sci", "renesas,sci"; + reg = <0 0x1004d000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCI0_RST>; + status = "disabled"; + }; + + sci1: serial@1004d400 { + compatible = "renesas,r9a07g044-sci", "renesas,sci"; + reg = <0 0x1004d400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCI1_RST>; + status = "disabled"; + }; + canfd: can@10050000 { compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; From 83c9eee72603adbaaf0420eb2c4d537a9d65d5fe Mon Sep 17 00:00:00 2001 From: Dmitry Shmidt Date: Thu, 7 Oct 2021 11:01:30 -0700 Subject: [PATCH 006/574] arm64: dts: meson-sm1-odroid: add cec nodes Enable CEC in same way it is done for other meson odroid devices Signed-off-by: Dmitry Shmidt Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211007180130.805401-1-dimitrysh@google.com --- arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index 5779e70caccd..0bd1e98a0eef 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -225,6 +225,20 @@ status = "okay"; }; +&cec_AO { + pinctrl-0 = <&cec_ao_a_h_pins>; + pinctrl-names = "default"; + status = "disabled"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + &clkc_audio { status = "okay"; }; From cdc5091694595606f0e38d651135d5d67fd397d0 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 26 Oct 2021 20:28:11 +0200 Subject: [PATCH 007/574] arm64: dts: amlogic: meson-g12: Fix thermal-zones indent This node is currently at /soc/thermal-zones, but the later introduced bindings in commit 1202a442a31f ("dt-bindings: thermal: Add yaml bindings for thermal zones") put this at /thermal-zones. Fix dtb_check warning by moving the thermal-zones node to / Signed-off-by: Alexander Stein Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211026182813.900775-1-alexander.stein@mailbox.org --- .../boot/dts/amlogic/meson-g12-common.dtsi | 110 +++++++++--------- 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 00c6f53290d4..ff987e7ccff2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -159,61 +159,6 @@ status = "disabled"; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&cpu_temp>; - - trips { - cpu_passive: cpu-passive { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - cpu_hot: cpu-hot { - temperature = <95000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - cpu_critical: cpu-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - }; - - ddr_thermal: ddr-thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&ddr_temp>; - - trips { - ddr_passive: ddr-passive { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ddr_critical: ddr-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map { - trip = <&ddr_passive>; - cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - ethmac: ethernet@ff3f0000 { compatible = "amlogic,meson-g12a-dwmac", "snps,dwmac-3.70a", @@ -2415,6 +2360,61 @@ }; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&cpu_temp>; + + trips { + cpu_passive: cpu-passive { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + cpu_hot: cpu-hot { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "hot"; + }; + + cpu_critical: cpu-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + ddr_thermal: ddr-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&ddr_temp>; + + trips { + ddr_passive: ddr-passive { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ddr_critical: ddr-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map { + trip = <&ddr_passive>; + cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = Date: Tue, 26 Oct 2021 20:28:12 +0200 Subject: [PATCH 008/574] arm64: dts: amlogic: meson-g12: Fix GPU operating point table node name Starting with commit 94274f20f6bf ("dt-bindings: opp: Convert to DT schema") the opp node name has a mandatory pattern. This change fixes the dtbs_check warning: gpu-opp-table: $nodename:0: 'gpu-opp-table' does not match '^opp-table(-[a-z0-9]+)?$' Put the 'gpu' part at the end to match the pattern. Fixes: 916a0edc43f0 ("arm64: dts: amlogic: meson-g12: add the Mali OPP table and use DVFS") Reviewed-by: Neil Armstrong Signed-off-by: Alexander Stein Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211026182813.900775-2-alexander.stein@mailbox.org --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index ff987e7ccff2..517519e6e87f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -58,7 +58,7 @@ secure-monitor = <&sm>; }; - gpu_opp_table: gpu-opp-table { + gpu_opp_table: opp-table-gpu { compatible = "operating-points-v2"; opp-124999998 { From 95d35256b564aca33fb661eac77dc94bfcffc8df Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 26 Oct 2021 20:28:13 +0200 Subject: [PATCH 009/574] arm64: dts: amlogic: Fix SPI NOR flash node name for ODROID N2/N2+ Fix the schema warning: "spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$'" from jedec,spi-nor.yaml Fixes: a084eaf3096c ("arm64: dts: meson-g12b-odroid-n2: add SPIFC controller node") Reviewed-by: Neil Armstrong Signed-off-by: Alexander Stein Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211026182813.900775-3-alexander.stein@mailbox.org --- arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi index e8a00a2f8812..3e968b244191 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi @@ -609,7 +609,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - mx25u64: spi-flash@0 { + mx25u64: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "mxicy,mx25u6435f", "jedec,spi-nor"; From 8182a35868db5f053111d5d9d4da8fcb3f99259d Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 12 Oct 2021 05:25:20 +0000 Subject: [PATCH 010/574] arm64: dts: meson-gxbb-wetek: fix HDMI in early boot Mark the VDDIO_AO18 regulator always-on and set hdmi-supply for the hdmi_tx node to ensure HDMI is powered in the early stages of boot. Fixes: fb72c03e0e32 ("ARM64: dts: meson-gxbb-wetek: add a wetek specific dtsi to cleanup hub and play2") Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211012052522.30873-2-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index a350fee1264d..8e2af986ceba 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -64,6 +64,7 @@ regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; }; vcc_3v3: regulator-vcc_3v3 { @@ -161,6 +162,7 @@ status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; pinctrl-names = "default"; + hdmi-supply = <&vddio_ao18>; }; &hdmi_tx_tmds_port { From c019abb2feba3cbbd7cf7178f8e6499c4fa6fced Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 12 Oct 2021 05:25:21 +0000 Subject: [PATCH 011/574] arm64: dts: meson-gxbb-wetek: fix missing GPIO binding The absence of this binding appears to be harmless in Linux but it breaks Ethernet support in mainline u-boot. So add the binding (which is present in all other u-boot supported GXBB device-trees). Fixes: fb72c03e0e32 ("ARM64: dts: meson-gxbb-wetek: add a wetek specific dtsi to cleanup hub and play2") Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211012052522.30873-3-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index 8e2af986ceba..a4d34398da35 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -6,6 +6,7 @@ */ #include "meson-gxbb.dtsi" +#include / { aliases { From 1e9fc71213d784dfbd153289daf08fdfc87f32ba Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 12 Oct 2021 05:25:22 +0000 Subject: [PATCH 012/574] arm64: dts: meson-gxbb-wetek: use updated LED bindings Update the dts to use the newer style of LED bindings. Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211012052522.30873-4-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index a4d34398da35..94dafb955301 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -7,6 +7,7 @@ #include "meson-gxbb.dtsi" #include +#include / { aliases { @@ -26,8 +27,10 @@ leds { compatible = "gpio-leds"; - led-system { - label = "wetek-play:system-status"; + led-power { + /* red in suspend or power-off */ + color = ; + function = LED_FUNCTION_POWER; gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; default-state = "on"; panic-indicator; From 5d978f8ad2ae14b6aaae00dc5520b9657675aeef Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Fri, 24 Sep 2021 11:39:35 +0800 Subject: [PATCH 013/574] arm64: dts: mt8183: change rpmsg property name The the rpmsg property name is changed to "mediatek," to sync with the vendor name defined in vendor-prefixes.yaml. Signed-off-by: Tinghan Shen Reviewed-By: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20210924033935.2127-7-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index b42d81d26d72..a1a8fc7ba007 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -813,7 +813,7 @@ cros_ec { compatible = "google,cros-ec-rpmsg"; - mtk,rpmsg-name = "cros-ec-rpmsg"; + mediatek,rpmsg-name = "cros-ec-rpmsg"; }; }; From 9cb6de45a006a9799ec399bce60d64b6d4fcc4af Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 31 Oct 2021 23:41:36 +0000 Subject: [PATCH 014/574] ARM: dts: exynos: Fix BCM4330 Bluetooth reset polarity in I9100 The reset GPIO was marked active-high, which is against what's specified in the documentation. Mark the reset GPIO as active-low. With this change, Bluetooth can now be used on the i9100. Fixes: 8620cc2f99b7 ("ARM: dts: exynos: Add devicetree file for the Galaxy S2") Cc: stable@vger.kernel.org Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20211031234137.87070-1-paul@crapouillou.net Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-i9100.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 19bb7dc98b33..21b791150697 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -828,7 +828,7 @@ compatible = "brcm,bcm4330-bt"; shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpl1 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpl1 0 GPIO_ACTIVE_LOW>; device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; }; From 8e14b530f8c90346eab43c7b59b03ff9fec7d171 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 31 Oct 2021 23:41:37 +0000 Subject: [PATCH 015/574] ARM: dts: exynos: Use interrupt for BCM4330 host wakeup in I9100 Switch away from using the deprecated 'host-wakeup-gpios' property, and use a 'host-wakeup' interrupt instead, as suggested by the binding documentation. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20211031234137.87070-2-paul@crapouillou.net Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-i9100.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 21b791150697..33894054b8b0 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -830,7 +830,10 @@ shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpl1 0 GPIO_ACTIVE_LOW>; device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + + interrupt-parent = <&gpx2>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wakeup"; }; }; From aa67bacb482ae66bdb18b78ddccf7b9180441588 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 24 Oct 2021 10:45:35 +0200 Subject: [PATCH 016/574] arm: dts: mt6589: Add device tree for Fairphone 1 Add rudimentary support for the Fairphone 1, based on MT6589 to boot to UART console. The recently added SMP support needs to be disabled for this board as the kernel panics executing /init with it, even though the CPUs seem to start up fine - maybe a stability issue. [ 0.072010] smp: Bringing up secondary CPUs ... [ 0.131888] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [ 0.191889] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002 [ 0.251890] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003 [ 0.251982] smp: Brought up 1 node, 4 CPUs [ 0.254745] SMP: Total of 4 processors activated (7982.28 BogoMIPS). [ 0.255582] CPU: All CPU(s) started in SVC mode. [ 0.472039] Run /init as init process [ 0.473317] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004 Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20211024084535.30959-1-luca@z3ntu.xyz Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/mt6589-fairphone-fp1.dts | 30 ++++++++++++++++++++++ arch/arm/boot/dts/mt6589.dtsi | 2 +- 3 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/mt6589-fairphone-fp1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..8a2dfdf01ce3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1457,6 +1457,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt2701-evb.dtb \ mt6580-evbp1.dtb \ mt6589-aquaris5.dtb \ + mt6589-fairphone-fp1.dtb \ mt6592-evb.dtb \ mt7623a-rfb-emmc.dtb \ mt7623a-rfb-nand.dtb \ diff --git a/arch/arm/boot/dts/mt6589-fairphone-fp1.dts b/arch/arm/boot/dts/mt6589-fairphone-fp1.dts new file mode 100644 index 000000000000..c952347981de --- /dev/null +++ b/arch/arm/boot/dts/mt6589-fairphone-fp1.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Luca Weiss + */ + +/dts-v1/; +#include "mt6589.dtsi" + +/ { + model = "Fairphone 1"; + compatible = "fairphone,fp1", "mediatek,mt6589"; + + chosen { + stdout-path = &uart3; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&cpus { + /* SMP is not stable on this board, makes the kernel panic */ + /delete-property/ enable-method; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index 70df00a7bb26..c6babc8ad2ba 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -14,7 +14,7 @@ compatible = "mediatek,mt6589"; interrupt-parent = <&sysirq>; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; enable-method = "mediatek,mt6589-smp"; From 5f9cfe9e94a6eef576f89bbf5a946f8ae63c0f71 Mon Sep 17 00:00:00 2001 From: Matthew Hagan Date: Fri, 15 Oct 2021 23:50:22 +0100 Subject: [PATCH 017/574] ARM: dts: NSP: MX65: add qca8k falling-edge, PLL properties This patch enables two properties for the QCA8337 switches on the MX65. Set the SGMII transmit clock to falling edge "qca,sgmii-txclk-falling-edge" to conform to the OEM configuration [1]. The new explicit PLL enable option "qca,sgmii-enable-pll" is required [2]. [1] https://git.kernel.org/netdev/net-next/c/6c43809bf1be [2] https://git.kernel.org/netdev/net-next/c/bbc4799e8bb6 Signed-off-by: Matthew Hagan Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi index 102acd85fab2..ba01054a76cf 100644 --- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi +++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi @@ -118,6 +118,8 @@ reg = <0>; ethernet = <&sgmii1>; phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-txclk-falling-edge; fixed-link { speed = <1000>; full-duplex; @@ -194,6 +196,8 @@ reg = <0>; ethernet = <&sgmii0>; phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-txclk-falling-edge; fixed-link { speed = <1000>; full-duplex; From 8c9f00d4b05134164e462f27b21c8295255ffa64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Wed, 27 Oct 2021 00:57:03 +0800 Subject: [PATCH 018/574] ARM: dts: BCM5301X: remove unnecessary address & size cells from Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the unnecessary #address-cells & #size-cells in the gpio-keys node from the device tree of Asus RT-AC88U. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 448060561cd0..b0cee1d87600 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -68,8 +68,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; wps { label = "WPS"; From 3d2d52a0d1835b56f6bd67d268f6c39df0e41692 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Wed, 27 Oct 2021 00:57:06 +0800 Subject: [PATCH 019/574] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the Realtek RTL8365MB switch without interrupt support on the device tree of Asus RT-AC88U. Signed-off-by: Arınç ÜNAL Acked-by: Alvin Šipraga Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index b0cee1d87600..16dea851719f 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -93,6 +93,83 @@ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; }; + + switch { + compatible = "realtek,rtl8365mb"; + /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ + mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + realtek,disable-leds; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + phy-handle = <ðphy0>; + }; + + port@1 { + reg = <1>; + label = "lan6"; + phy-handle = <ðphy1>; + }; + + port@2 { + reg = <2>; + label = "lan7"; + phy-handle = <ðphy2>; + }; + + port@3 { + reg = <3>; + label = "lan8"; + phy-handle = <ðphy3>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&sw0_p5>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + compatible = "realtek,smi-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + }; + }; }; &srab { From de7880016665afe7fa7d40e1fafa859260d53ba1 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Thu, 28 Oct 2021 09:03:44 +0200 Subject: [PATCH 020/574] ARM: BCM53016: MR32: convert to Broadcom iProc I2C Driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit replaces the bit-banged i2c-gpio provided i2c functionality with the hardware in the SoC. During review of the MR32, Florian Fainelli pointed out that the SoC has a real I2C-controller. Furthermore, the connected pins (SDA and SCL) would line up perfectly for use. Back then I couldn't get it working though and I left it with i2c-gpio (which worked). Now we know the reason: the interrupt was incorrectly specified. (Hence, this patch depends on Florian Fainelli's "ARM: dts: BCM5301X: Fix I2C controller interrupt" patch). Cc: Florian Fainelli Cc: Rafał Miłecki Cc: Matthew Hagan Signed-off-by: Christian Lamparter Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 62 ++++++++++------------ 1 file changed, 28 insertions(+), 34 deletions(-) diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index 64f973e1ef12..66c64a6ec414 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -84,40 +84,6 @@ max-brightness = <255>; }; }; - - i2c { - /* - * The platform provided I2C does not budge. - * This is a replacement until I can figure - * out what are the missing bits... - */ - - compatible = "i2c-gpio"; - sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <10>; /* close to 100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - current_sense: ina219@45 { - compatible = "ti,ina219"; - reg = <0x45>; - shunt-resistor = <60000>; /* = 60 mOhms */ - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - mac_address: mac-address@66 { - reg = <0x66 0x6>; - }; - }; - }; }; &uart0 { @@ -228,3 +194,31 @@ }; }; }; + +&i2c0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_i2c>; + + clock-frequency = <100000>; + + current_sense: ina219@45 { + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <60000>; /* = 60 mOhms */ + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; + }; +}; From 31fd9b79dc580301c53a001482755ba7e88c2809 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 29 Oct 2021 18:05:23 +0200 Subject: [PATCH 021/574] ARM: dts: BCM5301X: update CRU block description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This describes CRU in a way matching documentation and fixes: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: cru@100: $nodename:0: 'cru@100' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /lib/python3.6/site-packages/dtschema/schemas/simple-bus.yaml Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index d4f355015e3c..e1cffef4935a 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -421,14 +421,14 @@ #address-cells = <1>; #size-cells = <1>; - cru@100 { - compatible = "simple-bus"; + cru-bus@100 { + compatible = "brcm,ns-cru", "simple-mfd"; reg = <0x100 0x1a4>; ranges; #address-cells = <1>; #size-cells = <1>; - lcpll0: lcpll0@100 { + lcpll0: clock-controller@100 { #clock-cells = <1>; compatible = "brcm,nsp-lcpll0"; reg = <0x100 0x14>; @@ -437,7 +437,7 @@ "sdio", "ddr_phy"; }; - genpll: genpll@140 { + genpll: clock-controller@140 { #clock-cells = <1>; compatible = "brcm,nsp-genpll"; reg = <0x140 0x24>; @@ -448,6 +448,11 @@ "sata1", "sata2"; }; + syscon@180 { + compatible = "brcm,cru-clkset", "syscon"; + reg = <0x180 0x4>; + }; + pinctrl: pin-controller@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; From 7b0c9ca7f18e8d2e2cf3c342d91f037d436777bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 5 Nov 2021 11:14:12 +0100 Subject: [PATCH 022/574] dt-bindings: arm: bcm: document Netgear RAXE500 binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit One more BCM4908 based device. Signed-off-by: Rafał Miłecki Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml index 2cd4e4a32278..9b745531ff04 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml @@ -29,6 +29,7 @@ properties: items: - enum: - asus,gt-ac5300 + - netgear,raxe500 - const: brcm,bcm4908 - description: BCM49408 based boards From d0e68d354f345873e15876a7b35be1baaf5e3ec9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 5 Nov 2021 11:14:13 +0100 Subject: [PATCH 023/574] arm64: dts: broadcom: bcm4908: add DT for Netgear RAXE500 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's a home router based on BCM4908 SoC. It has: 1 GiB of RAM, 512 MiB NAND flash, 6 Ethernet ports and 3 x BCM43684 (WiFi). One of Ethernet ports is "2.5 G Multi-Gig port" that isn't described yet (it isn't known how it's wired up). Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 1 + .../bcm4908/bcm4908-netgear-raxe500.dts | 50 +++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile index cc75854519ac..6e364e304d4f 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile +++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile @@ -2,3 +2,4 @@ dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-tplink-archer-c2300-v1.dtb dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb +dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-netgear-raxe500.dtb diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts new file mode 100644 index 000000000000..3c2cf2d238b6 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "bcm4908.dtsi" + +/ { + compatible = "netgear,raxe500", "brcm,bcm4908"; + model = "Netgear RAXE500"; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00 0x00 0x40000000>; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@7 { + reg = <7>; + phy-mode = "internal"; + phy-handle = <&phy12>; + label = "wan"; + }; +}; From f5029f62d9ba9b99fd712514784f91f920a63d21 Mon Sep 17 00:00:00 2001 From: Wan Jiabing Date: Fri, 15 Oct 2021 02:49:23 -0400 Subject: [PATCH 024/574] soc: bcm: brcmstb: Add of_node_put() in pm-mips Fix following coccicheck warning: ./drivers/soc/bcm/brcmstb/pm/pm-mips.c:404:1-23: WARNING: Function for_each_matching_node should have of_node_put() before goto or break Early exits from for_each_matching_node should decrement the node reference counter. Signed-off-by: Wan Jiabing Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/pm/pm-mips.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/soc/bcm/brcmstb/pm/pm-mips.c b/drivers/soc/bcm/brcmstb/pm/pm-mips.c index cdc3e387f049..4dfb5a85032b 100644 --- a/drivers/soc/bcm/brcmstb/pm/pm-mips.c +++ b/drivers/soc/bcm/brcmstb/pm/pm-mips.c @@ -405,11 +405,14 @@ static int brcmstb_pm_init(void) i = ctrl.num_memc; if (i >= MAX_NUM_MEMC) { pr_warn("Too many MEMCs (max %d)\n", MAX_NUM_MEMC); + of_node_put(dn); break; } base = brcmstb_ioremap_node(dn, 0); - if (IS_ERR(base)) + if (IS_ERR(base)) { + of_node_put(dn); goto ddr_err; + } ctrl.memcs[i].ddr_phy_base = base; ctrl.num_memc++; From 82099d76cb6ff6738306e90e816754a5d6b046ce Mon Sep 17 00:00:00 2001 From: Oskar Senft Date: Thu, 4 Nov 2021 23:29:10 -0400 Subject: [PATCH 025/574] ARM: dts: aspeed: tyan-s7106: Update nct7802 config This change updates the configuration for the nct7802 hardware monitor to correctly configure its temperature sensors. Signed-off-by: Oskar Senft Link: https://lore.kernel.org/r/20211105032910.446492-1-osk@google.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts | 24 +++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts index 68f332ee1886..60ac6d3f03b5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts +++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts @@ -213,6 +213,30 @@ nct7802@28 { compatible = "nuvoton,nct7802"; reg = <0x28>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* LTD */ + reg = <0>; + }; + + channel@1 { /* RTD1 */ + reg = <1>; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@2 { /* RTD2 */ + reg = <2>; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@3 { /* RTD3 */ + reg = <3>; + sensor-type = "temperature"; + }; }; /* Also connected to: From 8189162c66b7bc2d91224269b472aae57fc699e1 Mon Sep 17 00:00:00 2001 From: Quan Nguyen Date: Tue, 19 Oct 2021 13:01:54 +0700 Subject: [PATCH 026/574] ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices This commit adds configuration i2c busses for 24 NVMe slots and 2 M2 NVMe slots found on Mt.Jade hardware reference platform with Ampere's Altra processor family. Signed-off-by: Quan Nguyen Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20211019060155.945-3-quan@os.amperecomputing.com Signed-off-by: Joel Stanley --- .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 258 ++++++++++++++++++ 1 file changed, 258 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 3515d55bd312..723c7063c223 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -7,6 +7,50 @@ model = "Ampere Mt. Jade BMC"; compatible = "ampere,mtjade-bmc", "aspeed,ast2500"; + aliases { + /* + * i2c bus 50-57 assigned to NVMe slot 0-7 + */ + i2c50 = &nvmeslot_0; + i2c51 = &nvmeslot_1; + i2c52 = &nvmeslot_2; + i2c53 = &nvmeslot_3; + i2c54 = &nvmeslot_4; + i2c55 = &nvmeslot_5; + i2c56 = &nvmeslot_6; + i2c57 = &nvmeslot_7; + + /* + * i2c bus 60-67 assigned to NVMe slot 8-15 + */ + i2c60 = &nvmeslot_8; + i2c61 = &nvmeslot_9; + i2c62 = &nvmeslot_10; + i2c63 = &nvmeslot_11; + i2c64 = &nvmeslot_12; + i2c65 = &nvmeslot_13; + i2c66 = &nvmeslot_14; + i2c67 = &nvmeslot_15; + + /* + * i2c bus 70-77 assigned to NVMe slot 16-23 + */ + i2c70 = &nvmeslot_16; + i2c71 = &nvmeslot_17; + i2c72 = &nvmeslot_18; + i2c73 = &nvmeslot_19; + i2c74 = &nvmeslot_20; + i2c75 = &nvmeslot_21; + i2c76 = &nvmeslot_22; + i2c77 = &nvmeslot_23; + + /* + * i2c bus 80-81 assigned to NVMe M2 slot 0-1 + */ + i2c80 = &nvme_m2_0; + i2c81 = &nvme_m2_1; + }; + chosen { stdout-path = &uart5; bootargs = "console=ttyS4,115200 earlycon"; @@ -445,6 +489,220 @@ &i2c5 { status = "okay"; + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + nvmeslot_0_7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + }; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + nvmeslot_8_15: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + nvmeslot_16_23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + }; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72>; + i2c-mux-idle-disconnect; + + nvme_m2_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + nvme_m2_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + }; +}; + +&nvmeslot_0_7 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + + }; +}; + +&nvmeslot_8_15 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_8: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_9: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_10: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_11: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_12: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_13: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_14: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_15: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; +}; + +&nvmeslot_16_23 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; }; &i2c6 { From 16d6dc8d8030dfe88104616cd3dea4e055af506d Mon Sep 17 00:00:00 2001 From: Quan Nguyen Date: Tue, 19 Oct 2021 13:01:55 +0700 Subject: [PATCH 027/574] ARM: dts: aspeed: mtjade: Add uefi partition Add SPI NOR partition for uefi. Signed-off-by: Thang Q. Nguyen Signed-off-by: Quan Nguyen Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20211019060155.945-4-quan@os.amperecomputing.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 723c7063c223..4c3c3f1a12ea 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -374,6 +374,15 @@ m25p,fast-read; label = "pnor"; /* spi-max-frequency = <100000000>; */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + uefi@400000 { + reg = <0x400000 0x1C00000>; + label = "pnor-uefi"; + }; + }; }; }; From e927f53f7dd9b3cd389696161b72c8c079770941 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 15 Nov 2021 21:11:12 +0100 Subject: [PATCH 028/574] arm64: dts: allwinner: h6: tanix-tx6: Add SPDIF Tanix TX6 board has SPDIF connector in form of 3.5 mm jack. Add support for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211115201112.452696-1-jernej.skrabec@gmail.com --- .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts index 8f2a80f128de..6c10ff7f4b1c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts @@ -52,6 +52,24 @@ regulator-min-microvolt = <1135000>; regulator-max-microvolt = <1135000>; }; + + sound-spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "sun50i-h6-spdif"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; }; &cpu0 { @@ -127,6 +145,10 @@ status = "okay"; }; +&spdif { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; From 7f1a9f47df618f19c943e5673b3b42b849de7e8d Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 10 Nov 2021 20:49:59 +0100 Subject: [PATCH 029/574] arm64: dts: mediatek: mt8192: fix i2c node names Fix the i2c node names to be compliant to the YAML schema. The I2C node name should match the following pattern: "^i2c@[0-9a-f]+$". Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20211110194959.20611-4-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c7c7d4e017ae..53d790c335f9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -479,7 +479,7 @@ #clock-cells = <1>; }; - i2c3: i2c3@11cb0000 { + i2c3: i2c@11cb0000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11cb0000 0 0x1000>, <0 0x10217300 0 0x80>; @@ -498,7 +498,7 @@ #clock-cells = <1>; }; - i2c7: i2c7@11d00000 { + i2c7: i2c@11d00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d00000 0 0x1000>, <0 0x10217600 0 0x180>; @@ -511,7 +511,7 @@ status = "disabled"; }; - i2c8: i2c8@11d01000 { + i2c8: i2c@11d01000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d01000 0 0x1000>, <0 0x10217780 0 0x180>; @@ -524,7 +524,7 @@ status = "disabled"; }; - i2c9: i2c9@11d02000 { + i2c9: i2c@11d02000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d02000 0 0x1000>, <0 0x10217900 0 0x180>; @@ -543,7 +543,7 @@ #clock-cells = <1>; }; - i2c1: i2c1@11d20000 { + i2c1: i2c@11d20000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d20000 0 0x1000>, <0 0x10217100 0 0x80>; @@ -556,7 +556,7 @@ status = "disabled"; }; - i2c2: i2c2@11d21000 { + i2c2: i2c@11d21000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d21000 0 0x1000>, <0 0x10217180 0 0x180>; @@ -569,7 +569,7 @@ status = "disabled"; }; - i2c4: i2c4@11d22000 { + i2c4: i2c@11d22000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d22000 0 0x1000>, <0 0x10217380 0 0x180>; @@ -588,7 +588,7 @@ #clock-cells = <1>; }; - i2c5: i2c5@11e00000 { + i2c5: i2c@11e00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11e00000 0 0x1000>, <0 0x10217500 0 0x80>; @@ -607,7 +607,7 @@ #clock-cells = <1>; }; - i2c0: i2c0@11f00000 { + i2c0: i2c@11f00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f00000 0 0x1000>, <0 0x10217080 0 0x80>; @@ -620,7 +620,7 @@ status = "disabled"; }; - i2c6: i2c6@11f01000 { + i2c6: i2c@11f01000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f01000 0 0x1000>, <0 0x10217580 0 0x80>; From 9cf6a26ae352a6a150662c0c4ddff87664cc6e3c Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 10 Nov 2021 20:35:20 +0100 Subject: [PATCH 030/574] arm64: dts: mediatek: mt8516: remove 2 invalid i2c clocks The two clocks "main-source" and "main-sel" are not present in the driver and not defined in the binding documentation. Remove them as they are not used and not described in the documentation. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20211110193520.488-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 27 ++++++------------------ 1 file changed, 6 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index bbe5a1419eff..d1b67c82d761 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -345,14 +345,9 @@ reg = <0 0x11009000 0 0x90>, <0 0x11000180 0 0x80>; interrupts = ; - clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, - <&infracfg CLK_IFR_I2C0_SEL>, - <&topckgen CLK_TOP_I2C0>, + clocks = <&topckgen CLK_TOP_I2C0>, <&topckgen CLK_TOP_APDMA>; - clock-names = "main-source", - "main-sel", - "main", - "dma"; + clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -364,14 +359,9 @@ reg = <0 0x1100a000 0 0x90>, <0 0x11000200 0 0x80>; interrupts = ; - clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, - <&infracfg CLK_IFR_I2C1_SEL>, - <&topckgen CLK_TOP_I2C1>, + clocks = <&topckgen CLK_TOP_I2C1>, <&topckgen CLK_TOP_APDMA>; - clock-names = "main-source", - "main-sel", - "main", - "dma"; + clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -383,14 +373,9 @@ reg = <0 0x1100b000 0 0x90>, <0 0x11000280 0 0x80>; interrupts = ; - clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, - <&infracfg CLK_IFR_I2C2_SEL>, - <&topckgen CLK_TOP_I2C2>, + clocks = <&topckgen CLK_TOP_I2C2>, <&topckgen CLK_TOP_APDMA>; - clock-names = "main-source", - "main-sel", - "main", - "dma"; + clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From ff9ea5c62279790eea8c0cd7295836db06da174d Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 10 Nov 2021 20:26:31 +0100 Subject: [PATCH 031/574] arm64: dts: mediatek: mt8183-evb: Add node for thermistor Add node to be able to read the temperature for the thermistor connected to AUXIN0. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20211110192631.4182485-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 7bc0a6a7fadf..f3fd3cca23e9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -36,6 +36,14 @@ no-map; }; }; + + ntc@0 { + compatible = "murata,ncp03wf104"; + pullup-uv = <1800000>; + pullup-ohm = <390000>; + pulldown-ohm = <0>; + io-channels = <&auxadc 0>; + }; }; &auxadc { From 2706707b225d29aae6f79a21eff277b53b7b05e9 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:12 +0800 Subject: [PATCH 032/574] arm64: dts: mt8183: jacuzzi: remove unused ddc-i2c-bus EDID is read from bridge, so the ddc-i2c-bus is unused. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index d8826c82bcda..8f7bf33f607d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -9,7 +9,6 @@ panel: panel { compatible = "auo,b116xw03"; power-supply = <&pp3300_panel>; - ddc-i2c-bus = <&i2c4>; backlight = <&backlight_lcd0>; port { From 52e84f23345904e91ea35199033fe8b0772f2f39 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:13 +0800 Subject: [PATCH 033/574] arm64: dts: mt8183: Add kukui-jacuzzi-cozmo board Cozmo is known as Acer Chromebook 314 (CB314-2H/CB314-2HT) Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-2-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../mediatek/mt8183-kukui-jacuzzi-cozmo.dts | 36 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 4f68ebed2e31..045927402269 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts new file mode 100644 index 000000000000..072133fb0f01 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" + +/ { + model = "Google cozmo board"; + compatible = "google,cozmo", "mediatek,mt8183"; +}; + +&i2c_tunnel { + google,remote-bus = <0>; +}; + +&i2c2 { + trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + + interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_COZMO"; +}; From 1c1f350be884fcd8280913d10f18231b5faff4da Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:14 +0800 Subject: [PATCH 034/574] arm64: dts: mt8183: Add more fennel SKUs Add fennel sku7 and fennel14 sku2, which use different audio codec than previous fennel/fennel14 boards. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-3-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 2 ++ .../mt8183-kukui-jacuzzi-fennel-sku1.dts | 1 + .../mt8183-kukui-jacuzzi-fennel-sku6.dts | 1 + .../mt8183-kukui-jacuzzi-fennel-sku7.dts | 33 +++++++++++++++++++ .../mediatek/mt8183-kukui-jacuzzi-fennel.dtsi | 1 - .../mt8183-kukui-jacuzzi-fennel14-sku2.dts | 17 ++++++++++ .../mt8183-kukui-jacuzzi-fennel14.dts | 1 + 7 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 045927402269..9834bd659d15 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -18,7 +18,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index ef6257c9a2d2..dec11a4eb59e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" / { model = "Google fennel sku1 board"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts index 899c2e42385c..37e6e58f63b7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" / { model = "Google fennel sku6 board"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts new file mode 100644 index 000000000000..0e09604004d5 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi" + +/ { + model = "Google fennel sku7 board"; + compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183"; +}; + +&touchscreen { + status = "okay"; + + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; +}; + + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi index 577519a775c0..bbe6c338f465 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi @@ -5,7 +5,6 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi.dtsi" -#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" &mt6358codec { mediatek,dmic-mode = <1>; /* one-wire */ diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts new file mode 100644 index 000000000000..3fc5a6181d7e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi" + +/ { + model = "Google fennel14 sku2 board"; + compatible = "google,fennel-sku2", "google,fennel", "mediatek,mt8183"; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL14"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts index e8c41f6b4b0d..23ad0b91e977 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" / { model = "Google fennel14 sku0 board"; From 3831b385147f9c1bc23f46ef156ffa165b8307f9 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:15 +0800 Subject: [PATCH 035/574] arm64: dts: mt8183: Add kakadu sku22 Kakadu sku22 is using mediatek,mt8183_mt6358_ts3a227_rt1015p audio codec Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-4-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../mediatek/mt8183-kukui-kakadu-sku22.dts | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 9834bd659d15..1613259b6865 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts new file mode 100644 index 000000000000..3a724e6f915c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-kakadu.dtsi" +#include "mt8183-kukui-audio-rt1015p.dtsi" + +/ { + model = "MediaTek kakadu board sku22"; + compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22", + "google,kakadu", "mediatek,mt8183"; +}; + +&sound { + compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p"; +}; + From 7358101393123aae68878fc05835f5add649ea6b Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:16 +0800 Subject: [PATCH 036/574] dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-cozmo Cozmo is known as Acer Chromebook 314 (CB314-2H/CB314-2HT) Chromebook. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-5-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 0fa55497b96f..7cf0c76cd310 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -134,6 +134,10 @@ properties: - google,krane-sku176 - const: google,krane - const: mediatek,mt8183 + - description: Google Cozmo (Acer Chromebook 314) + items: + - const: google,cozmo + - const: mediatek,mt8183 - description: Google Damu (ASUS Chromebook Flip CM3) items: - const: google,damu From bf08726b34c18dc917d9155ee52ee9cba94fb9e1 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:17 +0800 Subject: [PATCH 037/574] dt-bindings: arm64: dts: mediatek: Add more SKUs for mt8183 fennel board Add sku2 and sku7 which uses different audio codec than other fennel boards. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-6-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 7cf0c76cd310..99e7f8e294cd 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -147,7 +147,9 @@ properties: - enum: - google,fennel-sku0 - google,fennel-sku1 + - google,fennel-sku2 - google,fennel-sku6 + - google,fennel-sku7 - const: google,fennel - const: mediatek,mt8183 - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311) From 861a08874fdbf625fea5ac265ff6aabbf6b68c56 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:18 +0800 Subject: [PATCH 038/574] dt-bindings: arm64: dts: mediatek: Add sku22 for mt8183 kakadu board Add sku22 which uses different audio codec than previous kakadu board. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-7-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 99e7f8e294cd..723810cffce2 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -165,6 +165,12 @@ properties: - const: google,kakadu-rev2 - const: google,kakadu - const: mediatek,mt8183 + - description: Google Kakadu (ASUS Chromebook Detachable CM3) + items: + - const: google,kakadu-rev3-sku22 + - const: google,kakadu-rev2-sku22 + - const: google,kakadu + - const: mediatek,mt8183 - description: Google Kappa (HP Chromebook 11a) items: - const: google,kappa From ab0c1e34536c8077bf92ed9ec92941339acf9045 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 4 Nov 2021 14:52:54 +0100 Subject: [PATCH 039/574] arm64: dts: mediatek: mt8173: Add gce-client-reg to display od/ufo In order to use CMDQ commands on these two IPs, we need to declare the appropriate mediatek,gce-client-reg for them. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20211104135254.580257-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index dee66e5f054c..2b7d331a4588 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1212,6 +1212,7 @@ interrupts = ; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_UFOE>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; }; dsi0: dsi@1401b000 { @@ -1316,6 +1317,7 @@ compatible = "mediatek,mt8173-disp-od"; reg = <0 0x14023000 0 0x1000>; clocks = <&mmsys CLK_MM_DISP_OD>; + mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; }; hdmi0: hdmi@14025000 { From 98c3384fa770da1e782c6e07e0077825ec46c23f Mon Sep 17 00:00:00 2001 From: Ben Tseng Date: Wed, 3 Nov 2021 11:30:44 +0800 Subject: [PATCH 040/574] arm64: dts: mt8183-kukui: Update Tboard sensor mapping table According to auxadc change the readback value from raw data to Vsense. Update the tboard table that temperature map to Vsense. pull-up voltage: 1800 mv pull-up resistor: 75K Vsense = pull-up voltage * Rntc / ( pull-up resistor + Rntc ) Signed-off-by: Ben Tseng Tested-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211103033044.2777-1-ben.tseng@mediatek.com Signed-off-by: Matthias Brugger --- .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 108 +++++++++--------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index a1a8fc7ba007..94c13c459194 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -157,33 +157,33 @@ #thermal-sensor-cells = <0>; io-channels = <&auxadc 0>; io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-5000) 4241 - 0 4063 - 5000 3856 - 10000 3621 - 15000 3364 - 20000 3091 - 25000 2810 - 30000 2526 - 35000 2247 - 40000 1982 - 45000 1734 - 50000 1507 - 55000 1305 - 60000 1122 - 65000 964 - 70000 827 - 75000 710 - 80000 606 - 85000 519 - 90000 445 - 95000 382 - 100000 330 - 105000 284 - 110000 245 - 115000 213 - 120000 183 - 125000 161>; + temperature-lookup-table = < (-5000) 1553 + 0 1488 + 5000 1412 + 10000 1326 + 15000 1232 + 20000 1132 + 25000 1029 + 30000 925 + 35000 823 + 40000 726 + 45000 635 + 50000 552 + 55000 478 + 60000 411 + 65000 353 + 70000 303 + 75000 260 + 80000 222 + 85000 190 + 90000 163 + 95000 140 + 100000 121 + 105000 104 + 110000 90 + 115000 78 + 120000 67 + 125000 59>; }; tboard_thermistor2: thermal-sensor2 { @@ -191,33 +191,33 @@ #thermal-sensor-cells = <0>; io-channels = <&auxadc 1>; io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-5000) 4241 - 0 4063 - 5000 3856 - 10000 3621 - 15000 3364 - 20000 3091 - 25000 2810 - 30000 2526 - 35000 2247 - 40000 1982 - 45000 1734 - 50000 1507 - 55000 1305 - 60000 1122 - 65000 964 - 70000 827 - 75000 710 - 80000 606 - 85000 519 - 90000 445 - 95000 382 - 100000 330 - 105000 284 - 110000 245 - 115000 213 - 120000 183 - 125000 161>; + temperature-lookup-table = < (-5000) 1553 + 0 1488 + 5000 1412 + 10000 1326 + 15000 1232 + 20000 1132 + 25000 1029 + 30000 925 + 35000 823 + 40000 726 + 45000 635 + 50000 552 + 55000 478 + 60000 411 + 65000 353 + 70000 303 + 75000 260 + 80000 222 + 85000 190 + 90000 163 + 95000 140 + 100000 121 + 105000 104 + 110000 90 + 115000 78 + 120000 67 + 125000 59>; }; }; From 24f52ef0c4bfee3b18ca42bef47efa76abab56ab Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 6 Oct 2021 17:47:09 +0100 Subject: [PATCH 041/574] arm64: dts: qcom: sm8250: Add nodes for tx and rx macros with soundwire masters SM8250 has TX and RX macros with SoundWire Controllers to attach with codecs like WCD938x. Add these nodes for sm8250 mtp audio use case. Signed-off-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211006164712.16078-2-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 157 +++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 6f6129b39c9c..c46c35a74601 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1831,6 +1831,101 @@ #sound-dai-cells = <1>; }; + rxmacro: rxmacro@3200000 { + pinctrl-names = "default"; + pinctrl-0 = <&rx_swr_active>; + compatible = "qcom,sm8250-lpass-rx-macro"; + reg = <0 0x3200000 0 0x1000>; + + clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + + #clock-cells = <0>; + clock-frequency = <9600000>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + swr1: soundwire-controller@3210000 { + reg = <0 0x3210000 0 0x2000>; + compatible = "qcom,soundwire-v1.5.1"; + interrupts = ; + clocks = <&rxmacro>; + clock-names = "iface"; + label = "RX"; + qcom,din-ports = <0>; + qcom,dout-ports = <5>; + + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; + qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + txmacro: txmacro@3220000 { + pinctrl-names = "default"; + pinctrl-0 = <&tx_swr_active>; + compatible = "qcom,sm8250-lpass-tx-macro"; + reg = <0 0x3220000 0 0x1000>; + + clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + + #clock-cells = <0>; + clock-frequency = <9600000>; + clock-output-names = "mclk"; + #address-cells = <2>; + #size-cells = <2>; + #sound-dai-cells = <1>; + }; + + /* tx macro */ + swr2: soundwire-controller@3230000 { + reg = <0 0x3230000 0 0x2000>; + compatible = "qcom,soundwire-v1.5.1"; + interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "core"; + + clocks = <&txmacro>; + clock-names = "iface"; + label = "TX"; + + qcom,din-ports = <5>; + qcom,dout-ports = <0>; + qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; + qcom,port-offset = <1>; + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + aoncc: clock-controller@3380000 { compatible = "qcom,sm8250-lpass-aoncc"; reg = <0 0x03380000 0 0x40000>; @@ -1923,6 +2018,68 @@ input-enable; }; }; + + rx_swr_active: rx_swr-active-pins { + clk { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + tx_swr_active: tx_swr-active-pins { + clk { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data { + pins = "gpio1", "gpio2"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + tx_swr_sleep: tx_swr-sleep-pins { + clk { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + input-enable; + bias-pull-down; + }; + + data1 { + pins = "gpio1"; + function = "swr_tx_data"; + drive-strength = <2>; + input-enable; + bias-bus-hold; + }; + + data2 { + pins = "gpio2"; + function = "swr_tx_data"; + drive-strength = <2>; + input-enable; + bias-pull-down; + }; + }; }; gpu: gpu@3d00000 { From 5a263cf629a85aa831081de4b9f85926bb067c08 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 6 Oct 2021 17:47:10 +0100 Subject: [PATCH 042/574] arm64: dts: qcom: sm8250-mtp: Add wcd9380 audio codec node SM8250-MTP has WCD9380 codec for headset playback and capture via rx and tx macro respectively. Add node for this device to be able to use it for sound card device. Signed-off-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211006164712.16078-3-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 67 +++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 5ffbcdd387ba..7cf4fc97e825 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -6,6 +6,9 @@ /dts-v1/; #include +#include +#include +#include #include "sm8250.dtsi" #include "pm8150.dtsi" #include "pm8150b.dtsi" @@ -624,8 +627,72 @@ firmware-name = "qcom/sm8250/slpi.mbn"; }; +&soc { + wcd938x: codec { + compatible = "qcom,wcd9380-codec"; + #sound-dai-cells = <1>; + reset-gpios = <&tlmm 32 0>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-rxtx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + vdd-mic-bias-supply = <&vreg_bob>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + }; +}; + +&swr1 { + wcd_rx: wcd9380-rx@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + wcd_tx: wcd9380-tx@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 3 4 5>; + }; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <40 4>; + + wcd938x_reset_default: wcd938x_reset_default { + mux { + pins = "gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio32"; + drive-strength = <16>; + output-high; + }; + }; + + wcd938x_reset_sleep: wcd938x_reset_sleep { + mux { + pins = "gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio32"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; }; &uart12 { From 6fcda0b556cce2afee8322e3e01eeb9e3993eb6a Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 6 Oct 2021 17:47:11 +0100 Subject: [PATCH 043/574] arm64: dts: qcom: sm8250-mtp: Add wsa8810 audio codec node SM8250-MTP has WSA8810 via wsa macro for Speaker playback use case. Add node for this device to be able to use it for sound card device. Signed-off-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211006164712.16078-4-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 7cf4fc97e825..ee8a6c36d06f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -648,6 +648,26 @@ }; }; +&swr0 { + left_spkr: wsa8810-right@0,3{ + compatible = "sdw10217211000"; + reg = <0 3>; + powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + }; + + right_spkr: wsa8810-left@0,4{ + compatible = "sdw10217211000"; + reg = <0 4>; + powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + }; +}; + &swr1 { wcd_rx: wcd9380-rx@0,4 { compatible = "sdw20217010d00"; From fa244dca404c8b02999348098be7f2ae62670af0 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 6 Oct 2021 17:47:12 +0100 Subject: [PATCH 044/574] arm64: dts: qcom: sm8250-mtp: add sound card support This patch adds sound card support for MTP using WCD938x headset playback, capture, WSA8810 Speaker Playback and DMICs via VA macro. Signed-off-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211006164712.16078-5-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 104 ++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index ee8a6c36d06f..fb99cc2827c7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -648,6 +648,110 @@ }; }; +&sound { + compatible = "qcom,sm8250-sndcard"; + model = "SM8250-MTP-WCD9380-WSA8810-VA-DMIC"; + audio-routing = + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS3", + "AMIC5", "MIC BIAS4", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_ADC3", "ADC4_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + cpu { + sound-dai = <&q6afedai RX_CODEC_DMA_RX_0>; + }; + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; + }; + platform { + sound-dai = <&q6routing>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + cpu { + sound-dai = <&q6afedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>; + }; + platform { + sound-dai = <&q6routing>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + cpu { + sound-dai = <&q6afedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>; + }; + platform { + sound-dai = <&q6routing>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + cpu { + sound-dai = <&q6afedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&vamacro 0>; + }; + }; +}; + &swr0 { left_spkr: wsa8810-right@0,3{ compatible = "sdw10217211000"; From 0112b06fde557d407c0d477ee7ed973e44e65c75 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 25 Oct 2021 12:22:24 +0200 Subject: [PATCH 045/574] arm64: dts: qcom: Add missing 'chassis-type's Add the "chassis-type" to msm8916-samsung-serranove and sm7225-fairphone-fp4 that were posted before the patch that added the chassis-type to existing device trees, but merged after it. Also, looks like sdm636-sony-xperia-ganges-mermaid was missing in commit eaa744b1c101 ("arm64: dts: qcom: add 'chassis-type' property") so add it there as well. Cc: Luca Weiss Cc: Arnaud Ferraris Signed-off-by: Stephan Gerhold Reviewed-by: Arnaud Ferraris Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211025102224.23746-1-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts | 1 + arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts | 1 + arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index a78f87a5bf4f..58dfbfff4c7d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -23,6 +23,7 @@ / { model = "Samsung Galaxy S4 Mini Value Edition"; compatible = "samsung,serranove", "qcom,msm8916"; + chassis-type = "handset"; aliases { serial0 = &blsp1_uart2; diff --git a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts index bba1c2bce213..b96da53f2f1e 100644 --- a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts +++ b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts @@ -11,6 +11,7 @@ / { model = "Sony Xperia 10 Plus"; compatible = "sony,mermaid-row", "qcom,sdm636"; + chassis-type = "handset"; /* SDM636 v1 */ qcom,msm-id = <345 0>; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 8d6fd22873e0..a6937642736e 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -15,6 +15,7 @@ / { model = "Fairphone 4"; compatible = "fairphone,fp4", "qcom,sm7225"; + chassis-type = "handset"; /* required for bootloader to select correct board */ qcom,msm-id = <434 0x10000>, <459 0x10000>; From 37613aee217928dddf62d91d3db831827f860833 Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Tue, 26 Oct 2021 20:22:02 +0530 Subject: [PATCH 046/574] arm64: dts: qcom: sc7280: Add venus DT node Add DT entries for the sc7280 venus encoder/decoder. Co-developed-by: Mansur Alisha Shaik Signed-off-by: Mansur Alisha Shaik Signed-off-by: Dikshita Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1635259922-25378-1-git-send-email-quic_dikshita@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 75 ++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 365a2e04e285..e4988ea2011c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -129,6 +129,11 @@ no-map; }; + video_mem: memory@8b200000 { + reg = <0x0 0x8b200000 0x0 0x500000>; + no-map; + }; + ipa_fw_mem: memory@8b700000 { reg = <0 0x8b700000 0 0x10000>; no-map; @@ -2675,6 +2680,76 @@ }; }; + venus: video-codec@aa00000 { + compatible = "qcom,sc7280-venus"; + reg = <0 0x0aa00000 0 0xd0600>; + interrupts = ; + + clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, + <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>, + <&videocc VIDEO_CC_MVS0_CORE_CLK>, + <&videocc VIDEO_CC_MVS0_AXI_CLK>; + clock-names = "core", "bus", "iface", + "vcodec_core", "vcodec_bus"; + + power-domains = <&videocc MVSC_GDSC>, + <&videocc MVS0_GDSC>, + <&rpmhpd SC7280_CX>; + power-domain-names = "venus", "vcodec0", "cx"; + operating-points-v2 = <&venus_opp_table>; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, + <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cpu-cfg", "video-mem"; + + iommus = <&apps_smmu 0x2180 0x20>, + <&apps_smmu 0x2184 0x20>; + memory-region = <&video_mem>; + + video-decoder { + compatible = "venus-decoder"; + }; + + video-encoder { + compatible = "venus-encoder"; + }; + + video-firmware { + iommus = <&apps_smmu 0x21a2 0x0>; + }; + + venus_opp_table: venus-opp-table { + compatible = "operating-points-v2"; + + opp-133330000 { + opp-hz = /bits/ 64 <133330000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-335000000 { + opp-hz = /bits/ 64 <335000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-424000000 { + opp-hz = /bits/ 64 <424000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-460000048 { + opp-hz = /bits/ 64 <460000048>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + + }; + videocc: clock-controller@aaf0000 { compatible = "qcom,sc7280-videocc"; reg = <0 0xaaf0000 0 0x10000>; From 00128a57c0fe6ed90278cfec2adeccb83b7b49f4 Mon Sep 17 00:00:00 2001 From: Kate Doeen Date: Thu, 28 Oct 2021 12:19:57 +0200 Subject: [PATCH 047/574] arm64: dts: qcom: sdm845-oneplus-common: set venus firmware path Enable loading the Qualcomm Venus video accelerator firmware on OnePlus sdm845 devices. Signed-off-by: Kate Doeen Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211028101957.106034-1-jld3103yt@gmail.com --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 3e04aeb479d1..7f42e5315ecb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -646,6 +646,7 @@ &venus { status = "okay"; + firmware-name = "qcom/sdm845/oneplus6/venus.mbn"; }; &wifi { From 42dd1efffebd731e22623008058dd9c659812d1e Mon Sep 17 00:00:00 2001 From: Kate Doeen Date: Thu, 28 Oct 2021 12:20:16 +0200 Subject: [PATCH 048/574] arm64: dts: qcom: sdm845-xiaomi-beryllium: set venus firmware path Enable loading the Qualcomm Venus video accelerator firmware on Xiaomi Pocophone F1. Signed-off-by: Kate Doeen Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211028102016.106063-1-jld3103yt@gmail.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 580d4cc1296f..367389526b41 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -514,6 +514,7 @@ &venus { status = "okay"; + firmware-name = "qcom/sdm845/beryllium/venus.mbn"; }; &wcd9340{ From d201f67714a302b12ad3d78b982963342939629c Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 7 Oct 2021 13:58:46 +0200 Subject: [PATCH 049/574] arm64: dts: qcom: ipq8074: add MDIO bus IPQ8074 uses an IPQ4019 compatible MDIO controller that is already supported in the kernel, so add the DT node in order to use it. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211007115846.26255-1-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 6c6a0f853669..e6cc261201ef 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -230,6 +230,18 @@ }; }; + mdio: mdio@90000 { + compatible = "qcom,ipq4019-mdio"; + reg = <0x00090000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + + status = "disabled"; + }; + prng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; From 801cd261718e44adeb033c428390761adc03e2fc Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 29 Oct 2021 12:33:39 +0200 Subject: [PATCH 050/574] ARM: dts: qcom: update USB nodes with new platform specific compatible To match dwc3 documentation, add compatible for platform. Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211029103340.26828-2-david@ixit.cz --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++-- arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index ff1bdb10ad19..7dec0553636e 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -637,7 +637,7 @@ }; usb3: usb3@8af8800 { - compatible = "qcom,dwc3"; + compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; reg = <0x8af8800 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -669,7 +669,7 @@ }; usb2: usb2@60f8800 { - compatible = "qcom,dwc3"; + compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; reg = <0x60f8800 0x100>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 11481313bdb6..996f4458d9fc 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -1080,7 +1080,7 @@ }; usb3_0: usb3@100f8800 { - compatible = "qcom,dwc3", "syscon"; + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; #address-cells = <1>; #size-cells = <1>; reg = <0x100f8800 0x8000>; @@ -1122,7 +1122,7 @@ }; usb3_1: usb3@110f8800 { - compatible = "qcom,dwc3", "syscon"; + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; #address-cells = <1>; #size-cells = <1>; reg = <0x110f8800 0x8000>; From 52e844ee9a6f460e6160736a43ef13317a91ca74 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 10 Nov 2021 20:15:57 +0100 Subject: [PATCH 051/574] arm64: dts: reneas: rzg2: Add SDnH clocks Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20211110191610.5664-9-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-10-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-11-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-12-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 9 ++++++--- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 12 ++++++++---- 4 files changed, 30 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 6f4fffacfca2..f9c4ae6f26a9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2276,7 +2276,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2288,7 +2289,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2300,7 +2302,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2312,7 +2315,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 0f7bdfc90a0d..0c175b8c2088 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2133,7 +2133,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2145,7 +2146,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2157,7 +2159,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2169,7 +2172,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index d597772c4c37..5e16f6b1771e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1626,7 +1626,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -1638,7 +1639,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -1650,7 +1652,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 379a1300272b..673fcc631972 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2362,7 +2362,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2375,7 +2376,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2388,7 +2390,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2401,7 +2404,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 311>; From eca6ab6e362e3ae22b6c2769c4b6911bd0fb8ab1 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 10 Nov 2021 20:16:01 +0100 Subject: [PATCH 052/574] arm64: dts: reneas: rcar-gen3: Add SDnH clocks Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20211110191610.5664-13-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-14-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-15-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-16-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-17-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-18-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-19-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/r/20211110191610.5664-22-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 9 ++++++--- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 3 ++- 8 files changed, 44 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 1768a3e6bb8d..391ffe6ca03e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2668,7 +2668,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2681,7 +2682,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2694,7 +2696,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2707,7 +2710,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 2bd8169735d3..b1a6cf76633d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2468,7 +2468,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2481,7 +2482,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2494,7 +2496,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2507,7 +2510,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 86d59e7e1a87..1c1da6d7be49 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2312,7 +2312,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77961_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2325,7 +2326,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77961_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2338,7 +2340,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77961_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2351,7 +2354,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77961_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 08df75606430..3a357d958d4a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2315,7 +2315,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77965_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2328,7 +2329,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77965_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2341,7 +2343,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77965_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2354,7 +2357,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77965_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 6347d15e66b6..2a4513e7e2b5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1339,7 +1339,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>; + clock-names = "core", "clkh"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 314>; max-frequency = <200000000>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 0ea300a8147d..8698058f25f3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1788,7 +1788,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77990_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -1801,7 +1802,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77990_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -1814,7 +1816,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77990_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 311>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 16ad5fc23a67..f29f3982a492 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1216,7 +1216,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77995_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 312>; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 43bf2cbfbd8f..940e4990379d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1993,7 +1993,8 @@ "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; - clocks = <&cpg CPG_MOD 706>; + clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779A0_CLK_SD0H>; + clock-names = "core", "clkh"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 706>; max-frequency = <200000000>; From e1a9faddffe7e555304dc2e3284c84fbee0679ee Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 15 Nov 2021 14:28:30 +0000 Subject: [PATCH 053/574] arm64: dts: renesas: cat875: Add rx/tx delays The CAT875 sub board from Silicon Linux uses a Realtek PHY. The phy driver commit bbc4d71d63549bcd003 ("net: phy: realtek: fix rtl8211e rx/tx delay config") introduced NFS mount failures. Now it needs both rx/tx delays for the NFS mount to work. This patch fixes the NFS mount failure issue by adding "rgmii-id" mode to the avb device node. Signed-off-by: Biju Das Fixes: bbc4d71d63549bcd ("net: phy: realtek: fix rtl8211e rx/tx delay config") Link: https://lore.kernel.org/r/20211115142830.12651-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/cat875.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi index a69d24e9c61d..8c9da8b4bd60 100644 --- a/arch/arm64/boot/dts/renesas/cat875.dtsi +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi @@ -18,6 +18,7 @@ pinctrl-names = "default"; renesas,no-ether-link; phy-handle = <&phy0>; + phy-mode = "rgmii-id"; status = "okay"; phy0: ethernet-phy@0 { From a5c29f61466995d0d2c1370c709ef7fda534d386 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 17 Nov 2021 01:12:46 +0000 Subject: [PATCH 054/574] arm64: dts: renesas: r9a07g044: Add RSPI{0,1,2} nodes Add RSPI{0,1,2} nodes to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211117011247.27621-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 358db254c4ea..2dd6eff471cb 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -176,6 +176,54 @@ status = "disabled"; }; + spi0: spi@1004ac00 { + compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; + reg = <0 0x1004ac00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>; + resets = <&cpg R9A07G044_RSPI0_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@1004b000 { + compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b000 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>; + resets = <&cpg R9A07G044_RSPI1_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@1004b400 { + compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b400 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>; + resets = <&cpg R9A07G044_RSPI2_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>; From 7dd4fdec402e196f7a5bf519ea1bdb14b358cfa2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 17 Nov 2021 01:12:47 +0000 Subject: [PATCH 055/574] arm64: dts: renesas: rzg2l-smarc: Enable RSPI1 on carrier board RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the carrier board. This patch adds pinmux and spi1 nodes to the carrier board dtsi file. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211117011247.27621-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 4c32f068a1f0..6f2a8bdfa225 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -263,6 +263,13 @@ input-enable; }; + spi1_pins: spi1 { + pinmux = , /* CK */ + , /* MOSI */ + , /* MISO */ + ; /* SSL */ + }; + ssi0_pins: ssi0 { pinmux = , /* BCK */ , /* RCK */ @@ -318,6 +325,13 @@ status = "okay"; }; +&spi1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &ssi0 { pinctrl-0 = <&ssi0_pins>; pinctrl-names = "default"; From e051025efac3929ca7e3e2f2c8860d3447366ebc Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Nov 2021 17:06:00 +0100 Subject: [PATCH 056/574] dt-bindings: mmc: renesas,sdhi: Add optional SDnH clock This only applies to R-Car Gen2 and later generations, so we need to distinguish. Signed-off-by: Wolfram Sang Acked-by: Ulf Hansson Link: https://lore.kernel.org/r/20211115160600.4455-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/mmc/renesas,sdhi.yaml | 38 ++++++++++++++----- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 9f1e7092cf44..f5107a641790 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -129,15 +129,35 @@ allOf: - clock-names - resets else: - properties: - clocks: - minItems: 1 - maxItems: 2 - clock-names: - minItems: 1 - items: - - const: core - - const: cd + if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-sdhi + - renesas,rcar-gen3-sdhi + then: + properties: + clocks: + minItems: 1 + maxItems: 3 + clock-names: + minItems: 1 + uniqueItems: true + items: + - const: core + - enum: [ clkh, cd ] + - const: cd + else: + properties: + clocks: + minItems: 1 + maxItems: 2 + clock-names: + minItems: 1 + items: + - const: core + - const: cd - if: properties: From 663eede58f83783ff246573937615f0792788876 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 16 Nov 2021 16:41:15 +0900 Subject: [PATCH 057/574] dt-bindings: arm: renesas: Document R-Car S4-8 SoC DT bindings Add device tree bindings documentation for Renesas R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211116074130.107554-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 517206507801..36197f53b310 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -315,6 +315,10 @@ properties: - const: renesas,falcon-cpu - const: renesas,r8a779a0 + - description: R-Car S4-8 (R8A779F0) + items: + - const: renesas,r8a779f0 + - description: R-Car H3e (R8A779M0) items: - enum: From 06bd71cd2ebd98bb177fc7c35c10fed855781b82 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 16 Nov 2021 16:41:17 +0900 Subject: [PATCH 058/574] dt-bindings: reset: renesas,rst: Document r8a779f0 reset module Document bindings for the R-Car S4-8 (R8A779F0) reset module. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211116074130.107554-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/reset/renesas,rst.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml index 620cd0538bbe..bbe313bf1796 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml @@ -48,6 +48,7 @@ properties: - renesas,r8a77990-rst # R-Car E3 - renesas,r8a77995-rst # R-Car D3 - renesas,r8a779a0-rst # R-Car V3U + - renesas,r8a779f0-rst # R-Car S4-8 reg: maxItems: 1 From c014e935596b2637e00dcd32077ac5019d9a7e64 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 16 Nov 2021 16:41:18 +0900 Subject: [PATCH 059/574] dt-bindings: power: renesas,rcar-sysc: Document r8a779f0 SYSC bindings Document bindings for the R-Car S4-8 (aka R8A779F0) SYSC block. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211116074130.107554-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml index 99e8042ac111..62a49ca319ec 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml @@ -41,6 +41,7 @@ properties: - renesas,r8a77990-sysc # R-Car E3 - renesas,r8a77995-sysc # R-Car D3 - renesas,r8a779a0-sysc # R-Car V3U + - renesas,r8a779f0-sysc # R-Car S4-8 reg: maxItems: 1 From 08c40de81b77bd030f2a065464e7362b7467ed78 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 2 Nov 2021 15:42:23 +0100 Subject: [PATCH 060/574] arm64: dts: mediatek: mt8173-elm: Move pwm pinctrl to pwm0 node The PWM pinctrl belongs to the PWM0 node, as it's strictly pwm related. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20211102144224.457446-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index e666ebb28980..f292ca459a9a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -27,8 +27,6 @@ power-supply = <&bl_fixed_reg>; enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&disp_pwm0_pins>; status = "okay"; }; @@ -901,6 +899,8 @@ }; &pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; status = "okay"; }; From 54337a96f31b87e34f62af4c510e2fa80a908400 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 2 Nov 2021 15:42:24 +0100 Subject: [PATCH 061/574] arm64: dts: mediatek: mt8173-elm: Add backlight enable pin config Add the proper pinctrl for GPIO95 backlight enable pin and assign it to the pwm-backlight node. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20211102144224.457446-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index f292ca459a9a..9c75fbb31f98 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -27,6 +27,8 @@ power-supply = <&bl_fixed_reg>; enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_backlight_en_pins>; status = "okay"; }; @@ -825,6 +827,12 @@ }; }; + panel_backlight_en_pins: panel_backlight_en_pins { + pins1 { + pinmux = ; + }; + }; + panel_fixed_pins: panel_fixed_pins { pins1 { pinmux = ; From 7781083fd609f849adcab88bf7467614ed4d29a6 Mon Sep 17 00:00:00 2001 From: Seiya Wang Date: Tue, 2 Nov 2021 17:02:30 +0800 Subject: [PATCH 062/574] arm64: dts: mt8183: support coresight-cpu-debug for mt8183 Add coresight-cpu-debug nodes to mt8183 for dumping EDPRSR, EDPCSR, EDCIDSR, EDVIDSR while kernel panic happens Signed-off-by: Seiya Wang Link: https://lore.kernel.org/r/20211102090230.25013-1-seiya.wang@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 64 ++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index ba4584faca5a..00f2ddd245e1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -367,6 +367,70 @@ reg = <0 0x0c530a80 0 0x50>; }; + cpu_debug0: cpu-debug@d410000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd410000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; + + cpu_debug1: cpu-debug@d510000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd510000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + }; + + cpu_debug2: cpu-debug@d610000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd610000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + }; + + cpu_debug3: cpu-debug@d710000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd710000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + }; + + cpu_debug4: cpu-debug@d810000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd810000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu4>; + }; + + cpu_debug5: cpu-debug@d910000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd910000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu5>; + }; + + cpu_debug6: cpu-debug@da10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xda10000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu6>; + }; + + cpu_debug7: cpu-debug@db10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xdb10000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu7>; + }; + topckgen: syscon@10000000 { compatible = "mediatek,mt8183-topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; From 963070f762137cff817d33c102309ab0a345eb32 Mon Sep 17 00:00:00 2001 From: Philip Chen Date: Fri, 29 Oct 2021 15:27:40 -0700 Subject: [PATCH 063/574] arm64: dts: qcom: sc7180: Include gpio.h in edp bridge dts The edp bridge dts fragment files use the macros defined in 'dt-bindings/gpio/gpio.h'. To help us more flexibly order the #include lines of dts files in a board-revision-specific dts file, let's include the gpio header in the bridge dts fragment files themselves. Signed-off-by: Philip Chen Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211029152647.v3.1.Ie17e51ad3eb91d72826ce651ca2786534a360210@changeid --- arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi index a3d69540d4e4..6a84fba178d6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi @@ -5,6 +5,8 @@ * Copyright 2021 Google LLC. */ +#include + / { pp3300_brij_ps8640: pp3300-brij-ps8640 { compatible = "regulator-fixed"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi index 97d5e45abd1d..6dbf413e4e5b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi @@ -5,6 +5,8 @@ * Copyright 2021 Google LLC. */ +#include + &dsi0_out { remote-endpoint = <&sn65dsi86_in>; data-lanes = <0 1 2 3>; From 0417a86b200b4da1dff73e9f4bd7743346e5565b Mon Sep 17 00:00:00 2001 From: Philip Chen Date: Fri, 29 Oct 2021 15:27:41 -0700 Subject: [PATCH 064/574] arm64: dts: qcom: sc7180: Specify "data-lanes" for DSI host output MSM DSI host driver actually parses "data-lanes" in DT and compare it with the number of DSI lanes the bridge driver sets for mipi_dsi_device. So we need to always specify "data-lanes" for the DSI host output. As of now, "data-lanes" is added to ti-sn65dsi86 dts fragment, but missing in parade-ps8640 dts fragment, which requires a fixup. Since we'll do 4-lane DSI regardless of which bridge chip is used, instead of adding "data-lanes" to parade-ps8640 dts fragment, let's just move "data-lanes" from the bridge dts to sc7180-trogdor.dtsi. Signed-off-by: Philip Chen Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211029152647.v3.2.If23c83a786fc4d318a1986f43803f22b4b1d82cd@changeid --- arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi index 6dbf413e4e5b..f869e6a343c1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi @@ -9,7 +9,6 @@ &dsi0_out { remote-endpoint = <&sn65dsi86_in>; - data-lanes = <0 1 2 3>; }; edp_brij_i2c: &i2c2 { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index d4f4441179fc..bd5909ffb3dc 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -603,6 +603,10 @@ vdda-supply = <&vdda_mipi_dsi0_1p2>; }; +&dsi0_out { + data-lanes = <0 1 2 3>; +}; + &dsi_phy { status = "okay"; vdds-supply = <&vdda_mipi_dsi0_pll>; From 7624b41b3379e664f074137001fc2e44bc1f5eaf Mon Sep 17 00:00:00 2001 From: Philip Chen Date: Fri, 29 Oct 2021 15:27:42 -0700 Subject: [PATCH 065/574] arm64: dts: qcom: sc7180: Support Lazor/Limozeen rev9 Support Lazor/Limozeen rev9 board where Parade ps8640 is added as the second source edp bridge. To support different edp bridge chips in different board revisions, now we move the #incldue line of the edp bridge dts fragment (e.g. sc7180-trogdor-ti-sn65dsi86.dtsi) from "sc7180-trogdor-lazor.dtsi" to per-board-rev dts files. Since the edp bridge dts fragment overrides 'dsi0_out', which is defined in "sc7180.dtsi", move the #incldue line of "sc7180.dtsi" from "sc7180-trogdor-lazor.dtsi" to per-board-rev dts files too, before the #include line of the edp bridge dts fragment. Signed-off-by: Philip Chen Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211029152647.v3.3.Ie56f55924f5c7706fe3194e710bbef6fdb8b5bc6@changeid --- arch/arm64/boot/dts/qcom/Makefile | 9 +++- .../sc7180-trogdor-lazor-limozeen-nots-r4.dts | 2 +- .../sc7180-trogdor-lazor-limozeen-nots-r5.dts | 31 +++++++++++++ ...sc7180-trogdor-lazor-limozeen-nots-r9.dts} | 8 ++-- .../qcom/sc7180-trogdor-lazor-limozeen-r4.dts | 46 +++++++++++++++++++ ...s => sc7180-trogdor-lazor-limozeen-r9.dts} | 6 ++- .../boot/dts/qcom/sc7180-trogdor-lazor-r0.dts | 2 + .../boot/dts/qcom/sc7180-trogdor-lazor-r1.dts | 2 + .../dts/qcom/sc7180-trogdor-lazor-r3-kb.dts | 9 +++- .../dts/qcom/sc7180-trogdor-lazor-r3-lte.dts | 9 +++- .../boot/dts/qcom/sc7180-trogdor-lazor-r3.dts | 8 +++- .../dts/qcom/sc7180-trogdor-lazor-r9-kb.dts | 22 +++++++++ .../dts/qcom/sc7180-trogdor-lazor-r9-lte.dts | 30 ++++++++++++ .../boot/dts/qcom/sc7180-trogdor-lazor-r9.dts | 18 ++++++++ .../boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 3 -- 15 files changed, 188 insertions(+), 17 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts rename arch/arm64/boot/dts/qcom/{sc7180-trogdor-lazor-limozeen-nots.dts => sc7180-trogdor-lazor-limozeen-nots-r9.dts} (60%) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts rename arch/arm64/boot/dts/qcom/{sc7180-trogdor-lazor-limozeen.dts => sc7180-trogdor-lazor-limozeen-r9.dts} (82%) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6b816eb33309..f637c4d3729f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -64,9 +64,14 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9-kb.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r4.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r9.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts index 6ebde0828550..850776c5323d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts @@ -5,7 +5,7 @@ * Copyright 2020 Google LLC. */ -#include "sc7180-trogdor-lazor-limozeen-nots.dts" +#include "sc7180-trogdor-lazor-limozeen-nots-r5.dts" / { model = "Google Lazor Limozeen without Touchscreen (rev4)"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts new file mode 100644 index 000000000000..f360ff27226e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor Limozeen board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-lazor.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Lazor Limozeen without Touchscreen (rev5 - rev8)"; + /* No sku5 post-rev5 */ + compatible = "google,lazor-rev5-sku5", "google,lazor-rev5-sku6", + "google,lazor-rev6-sku6", "google,lazor-rev7-sku6", + "google,lazor-rev8-sku6", "qcom,sc7180"; +}; + +/delete-node/&ap_ts; + +&panel { + compatible = "innolux,n116bca-ea1", "innolux,n116bge"; +}; + +&sdhc_2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts similarity index 60% rename from arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dts rename to arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts index 0456c7e05d00..4e35aec6a1e5 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts @@ -2,17 +2,19 @@ /* * Google Lazor Limozeen board device tree source * - * Copyright 2020 Google LLC. + * Copyright 2021 Google LLC. */ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google Lazor Limozeen without Touchscreen"; - compatible = "google,lazor-sku6", "google,lazor-sku5", "qcom,sc7180"; + model = "Google Lazor Limozeen without Touchscreen (rev9+)"; + compatible = "google,lazor-sku6", "qcom,sc7180"; }; /delete-node/&ap_ts; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts new file mode 100644 index 000000000000..42b4bbcc76f4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor Limozeen board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-lazor.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Lazor Limozeen (rev4 - rev8)"; + compatible = "google,lazor-rev4-sku4", "google,lazor-rev5-sku4", + "google,lazor-rev6-sku4", "google,lazor-rev7-sku4", + "google,lazor-rev8-sku4", "qcom,sc7180"; +}; + +/delete-node/&ap_ts; + +&ap_ts_pen_1v8 { + ap_ts: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + vcc33-supply = <&pp3300_ts>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + }; +}; + +&panel { + compatible = "auo,b116xa01"; +}; + +&sdhc_2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts similarity index 82% rename from arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dts rename to arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts index e6ad6dae4e60..dc47842bc662 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts @@ -2,16 +2,18 @@ /* * Google Lazor Limozeen board device tree source * - * Copyright 2020 Google LLC. + * Copyright 2021 Google LLC. */ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google Lazor Limozeen"; + model = "Google Lazor Limozeen (rev9+)"; compatible = "google,lazor-sku4", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts index 30e3e769d2b4..b142006478ea 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts index c2ef06367baf..59740799fa3a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts index dcb41afdc82a..18ef9da71998 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts @@ -7,12 +7,17 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-lite.dtsi" / { - model = "Google Lazor (rev3+) with KB Backlight"; - compatible = "google,lazor-sku2", "qcom,sc7180"; + model = "Google Lazor (rev3 - 8) with KB Backlight"; + compatible = "google,lazor-rev3-sku2", "google,lazor-rev4-sku2", + "google,lazor-rev5-sku2", "google,lazor-rev6-sku2", + "google,lazor-rev7-sku2", "google,lazor-rev8-sku2", + "qcom,sc7180"; }; &keyboard_backlight { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts index be44900602d7..c5c9feff41b8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts @@ -7,12 +7,17 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google Lazor (rev3+) with LTE"; - compatible = "google,lazor-sku0", "qcom,sc7180"; + model = "Google Lazor (rev3 - 8) with LTE"; + compatible = "google,lazor-rev3-sku0", "google,lazor-rev4-sku0", + "google,lazor-rev5-sku0", "google,lazor-rev6-sku0", + "google,lazor-rev7-sku0", "google,lazor-rev8-sku0", + "qcom,sc7180"; }; &ap_sar_sensor { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts index b474df47cd70..7adcedbf080d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts @@ -7,10 +7,14 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-lite.dtsi" / { - model = "Google Lazor (rev3+)"; - compatible = "google,lazor", "qcom,sc7180"; + model = "Google Lazor (rev3 - 8)"; + compatible = "google,lazor-rev3", "google,lazor-rev4", + "google,lazor-rev5", "google,lazor-rev6", "google,lazor-rev7", + "google,lazor-rev8", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts new file mode 100644 index 000000000000..7f5c015e1ecb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-lazor.dtsi" +#include "sc7180-lite.dtsi" + +/ { + model = "Google Lazor (rev9+) with KB Backlight"; + compatible = "google,lazor-sku2", "qcom,sc7180"; +}; + +&keyboard_backlight { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts new file mode 100644 index 000000000000..344b57c035d0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-lazor.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Lazor (rev9+) with LTE"; + compatible = "google,lazor-sku0", "qcom,sc7180"; +}; + +&ap_sar_sensor { + status = "okay"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; + +&keyboard_backlight { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts new file mode 100644 index 000000000000..83f6a4eb5ae5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-lazor.dtsi" +#include "sc7180-lite.dtsi" + +/ { + model = "Google Lazor (rev9+)"; + compatible = "google,lazor", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 8b79fbb75756..69666f92176a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -5,13 +5,10 @@ * Copyright 2020 Google LLC. */ -#include "sc7180.dtsi" - ap_ec_spi: &spi6 {}; ap_h1_spi: &spi0 {}; #include "sc7180-trogdor.dtsi" -#include "sc7180-trogdor-ti-sn65dsi86.dtsi" &ap_sar_sensor { semtech,cs0-ground; From 3922ccaed4ac9dab5087fc5f20d319cc55765afa Mon Sep 17 00:00:00 2001 From: Philip Chen Date: Fri, 29 Oct 2021 15:27:43 -0700 Subject: [PATCH 066/574] arm64: dts: qcom: sc7180: Support Homestar rev4 Support Homestar rev4 board where Parade ps8640 is added as the second source edp bridge. Support different edp bridge chips in different board revisions, now we move the #incldue line of the edp bridge dts fragment (e.g. sc7180-trogdor-ti-sn65dsi86.dtsi) from "sc7180-trogdor-homestar.dtsi" to per-board-rev dts files. Since the edp bridge dts fragment overrides 'dsi0_out', which is defined in "sc7180.dtsi", move the #incldue line of "sc7180.dtsi" from "sc7180-trogdor-homestar.dtsi" to per-board-rev dts files too, before the #include line of the edp bridge dts fragment. Signed-off-by: Philip Chen Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211029152647.v3.4.If7aaa8e36f1269acae5488035bd62ce543756bf8@changeid --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sc7180-trogdor-homestar-r2.dts | 2 ++ .../dts/qcom/sc7180-trogdor-homestar-r3.dts | 6 ++++-- .../dts/qcom/sc7180-trogdor-homestar-r4.dts | 17 +++++++++++++++++ .../boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 3 --- 5 files changed, 24 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f637c4d3729f..ba99aba1d51a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -57,6 +57,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts index db6c2da67cea..70032983fb65 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-homestar.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts index 3fd8aa5bb7a6..e92e2e9e48ed 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts @@ -7,9 +7,11 @@ /dts-v1/; +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-homestar.dtsi" / { - model = "Google Homestar (rev3+)"; - compatible = "google,homestar", "qcom,sc7180"; + model = "Google Homestar (rev3)"; + compatible = "google,homestar-rev3", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts new file mode 100644 index 000000000000..fb27106bbb4a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Homestar board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-homestar.dtsi" + +/ { + model = "Google Homestar (rev4+)"; + compatible = "google,homestar", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index 4ab890b2a1d4..f32369af1351 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -5,13 +5,10 @@ * Copyright 2021 Google LLC. */ -#include "sc7180.dtsi" - ap_ec_spi: &spi6 {}; ap_h1_spi: &spi0 {}; #include "sc7180-trogdor.dtsi" -#include "sc7180-trogdor-ti-sn65dsi86.dtsi" / { /* BOARD-SPECIFIC TOP LEVEL NODES */ From c41910f257a22dc406c60d8826b4a3b5398003a3 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sat, 30 Oct 2021 12:04:12 +0200 Subject: [PATCH 067/574] arm64: dts: qcom: msm8996: drop not documented adreno properties These properties aren't documented nor implemented in the driver. Drop them. Fixes warnings as: $ make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/display/msm/gpu.yaml ... arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml: gpu@b00000: 'qcom,gpu-quirk-fault-detect-mask', 'qcom,gpu-quirk-two-pass-use-wfi' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/display/msm/gpu.yaml ... Fixes: 69cc3114ab0f ("arm64: dts: Add Adreno GPU definitions") Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211030100413.28370-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index bccc2d0b35a8..1ac78d9909ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -987,9 +987,6 @@ nvmem-cells = <&speedbin_efuse>; nvmem-cell-names = "speed_bin"; - qcom,gpu-quirk-two-pass-use-wfi; - qcom,gpu-quirk-fault-detect-mask; - operating-points-v2 = <&gpu_opp_table>; status = "disabled"; From 30a7f99befc655cb3eacdd3a0f2394a5209a492f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 11 Nov 2021 19:46:28 +0100 Subject: [PATCH 068/574] arm64: dts: qcom: Add support for SONY Xperia XZ2 / XZ2C / XZ3 (Tama platform) Add support for SONY Xperia XZ2, XZ2 Compact and XZ3 smartphones, all based on the Qualcomm SDM845 chipset. There also exists a fourth Tama device, the XZ2 Premium (Aurora) with a 4K display, but it's relatively rare. The devices are affected by a scary UFS behaviour where sending a certain UFS command (which is worked around on downstream) renders the device unbootable, by effectively erasing the bootloader. Therefore UFS AND UFSPHY are strictly disabled for now. Downstream workaround: https://github.com/kholk/kernel/commit/2e7a9ee1c91a016baa0b826a7752ec45663a0561 This platform's bootloader is not very nice either. To boot mainline you need to flash a bogus DTBO (fastboot erasing may cut it, but it takes an inhumane amount of time) - one that's just 4 bytes (all zeroes) seems to work just fine. Of course, one can also provide a "normal" DTBO (device-specific DT overlayed on top of the SoC DT), but that's not yet supported by the mainline kernel build system. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Martin Botka Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211111184630.605035-1-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/Makefile | 3 + .../qcom/sdm845-sony-xperia-tama-akari.dts | 13 + .../qcom/sdm845-sony-xperia-tama-akatsuki.dts | 29 ++ .../qcom/sdm845-sony-xperia-tama-apollo.dts | 13 + .../dts/qcom/sdm845-sony-xperia-tama.dtsi | 438 ++++++++++++++++++ 5 files changed, 496 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ba99aba1d51a..4906712e3cfd 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -97,6 +97,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts new file mode 100644 index 000000000000..34f84f1f1eb4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sdm845-sony-xperia-tama.dtsi" + +/ { + model = "Sony Xperia XZ2"; + compatible = "sony,akari-row", "qcom,sdm845"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts new file mode 100644 index 000000000000..8a0d94e7f598 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sdm845-sony-xperia-tama.dtsi" + +/ { + model = "Sony Xperia XZ3"; + compatible = "sony,akatsuki-row", "qcom,sdm845"; +}; + +/* For the future: WLED + LAB/IBB/OLEDB are not used on Akatsuki */ +&vreg_l14a_1p8 { + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <1840000>; +}; + +&vreg_l22a_2p8 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; +}; + +&vreg_l28a_2p8 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts new file mode 100644 index 000000000000..c9e62c72f60e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sdm845-sony-xperia-tama.dtsi" + +/ { + model = "Sony Xperia XZ2 Compact"; + compatible = "sony,apollo-row", "qcom,sdm845"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi new file mode 100644 index 000000000000..281fe6dea62a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include +#include +#include "sdm845.dtsi" +#include "pm8005.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/ { + qcom,msm-id = <321 0x20001>; /* SDM845 v2.1 */ + qcom,board-id = <8 0>; + + gpio-keys { + compatible = "gpio-keys"; + + /* Neither Camera Focus, nor Camera Shutter seem to work... */ + + vol-down { + label = "volume_down"; + gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8998-smps4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + reserved-memory { + /* SONY was cool and didn't diverge from MTP this time, yay! */ + cont_splash_mem: memory@9d400000 { + reg = <0x0 0x9d400000 0x0 0x2400000>; + no-map; + }; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc00000 0x0 0x100000>; + record-size = <0x10000>; + console-size = <0x60000>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + ecc-size = <16>; + no-map; + }; + }; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_0p9>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p3>; + vdd-l3-l11-supply = <&vreg_s7a_0p9>; + vdd-l4-l5-supply = <&vreg_s7a_0p9>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l9-supply = <&vreg_s5a_1p9>; + vdd-l10-l23-l25-supply = <&src_vreg_bob>; + vdd-l13-l19-l21-supply = <&src_vreg_bob>; + vdd-l16-l28-supply = <&src_vreg_bob>; + vdd-l18-l22-supply = <&src_vreg_bob>; + vdd-l20-l24-supply = <&src_vreg_bob>; + vdd-l26-supply = <&vreg_s3a_1p3>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s2a_1p1: smps2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_s3a_1p3: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_1p9: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_0p9: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vreg_l1a_0p9: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8a_1p2: ldo8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p7: ldo9 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p7: ldo10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l11a_1p0: ldo11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p7: ldo18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l19a_2p7: ldo19 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = ; + + /* + * The driver *really* doesn't want this regualtor to exist, + * saying that it could not get the current voltage (-ENOTRECOVERABLE) + * even though it surely is used on these devices (as a voltage + * source for camera autofocus) + */ + status = "disabled"; + }; + + vreg_l20a_2p7: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p7: ldo21 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l22a_2p8: ldo22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l23a_3p0: ldo23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l24a_3p1: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p0: ldo25 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l28a_2p8: ldo28 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + pmi8998-rpmh-regulators { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + src_vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = ; + }; + }; + + pm8005-rpmh-regulators { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + /* Synaptics touchscreen @ 2c, 3c */ +}; + +&i2c10 { + status = "okay"; + clock-frequency = <400000>; + + /* Qcom SMB1355 @ 8, c */ + /* NXP PN547 NFC @ 28 */ + /* Renesas IDTP9221 Qi charger @ 61 */ +}; + +&i2c14 { + status = "okay"; + clock-frequency = <400000>; + + /* SONY ToF sensor @ 52 */ + /* AMS TCS3490 RGB+IR color sensor @ 72 */ +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l21a_2p7>; + vqmmc-supply = <&vreg_l13a_1p8>; + cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sdc2_default_state>; + pinctrl-names = "default"; + bus-width = <4>; + no-sdio; + no-emmc; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + sdc2_default_state: sdc2-default-state { + clk { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; +}; + +&uart6 { + status = "okay"; +}; + +&uart9 { + status = "okay"; +}; + +/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ +&ufs_mem_hc { status = "disabled"; }; +&ufs_mem_phy { status = "disabled"; }; + +&usb_1 { + status = "okay"; + + qcom,select-utmi-as-pipe-clk; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; + + maximum-speed = "high-speed"; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vreg_l1a_0p9>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p1>; +}; From e2bbebf3b04c62fc3f7e64525c43bf5118a3cc88 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 Nov 2021 03:29:45 +0300 Subject: [PATCH 069/574] arm64: dts: qcom: apq8096-db820c: specify adsp firmware name Specify firmware name to be used for the ADSP. Quoting Bjorn from the respective apq8016-sbc commit: The firmware for the modem and WiFi subsystems platform specific and is signed with a OEM specific key (or a test key). In order to support more than a single device it is therefor not possible to rely on the default path and stash these files directly in the firmware directory. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104002949.2204727-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index d01a512634cf..7e7b416e7d21 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -166,6 +166,7 @@ &adsp_pil { status = "okay"; + firmware-name = "qcom/apq8096/adsp.mbn"; }; &blsp2_i2c1 { From 7c57dcae949d1d39068f1e92233a9bc2dc7dcfba Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 Nov 2021 03:29:46 +0300 Subject: [PATCH 070/574] arm64: dts: qcom: apq8096-db820c: add missing regulator details Specify that S11 (well, whole block of s8+s9+s10+s11) of pm8994 and S2 (s2 + s3) of pmi8994 are supplied by vph_pwr. While we are at it, add regulator name to S11, so that is displayed as VDD_APCC in the system. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104002949.2204727-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 7e7b416e7d21..9dbac589482b 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -633,6 +633,8 @@ &pm8994_spmi_regulators { qcom,saw-reg = <&saw3>; + vdd_s11-supply = <&vph_pwr>; + s9 { qcom,saw-slave; }; @@ -641,6 +643,7 @@ }; s11 { qcom,saw-leader; + regulator-name = "VDD_APCC"; regulator-always-on; regulator-min-microvolt = <980000>; regulator-max-microvolt = <980000>; @@ -673,6 +676,8 @@ }; &pmi8994_spmi_regulators { + vdd_s2-supply = <&vph_pwr>; + vdd_gfx: s2@1700 { reg = <0x1700 0x100>; regulator-name = "VDD_GFX"; From a49c3dd1f7827fa7ee3a861b4292dd7d1c346fb2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 Nov 2021 03:29:47 +0300 Subject: [PATCH 071/574] arm64: dts: qcom: apq8096-db820c: correct lvs1 and lvs2 supply property The qcom_rpm_smd_regulator driver uses vdd_lvs1_2-supply property to specify the supply regulator for LVS1 and LVS2 (following the pin name in the PMIC datasheet). Correct the board's device tree property, so that the regulator supply is setup properly. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104002949.2204727-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 9dbac589482b..28403d2ffd31 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -715,7 +715,7 @@ vdd_l17_l29-supply = <&vph_pwr_bbyp>; vdd_l20_l21-supply = <&vph_pwr_bbyp>; vdd_l25-supply = <&vreg_s3a_1p3>; - vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; + vdd_lvs1_2-supply = <&vreg_s4a_1p8>; vreg_s3a_1p3: s3 { regulator-name = "vreg_s3a_1p3"; From 227ee1583ba4b3bb973e2a3e32351c242fdfc49d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 Nov 2021 03:29:48 +0300 Subject: [PATCH 072/574] arm64: dts: qcom: msm8994-sony-xperia-kitakami: correct lvs1 and lvs2 supply property The qcom_rpm_smd_regulator driver uses vdd_lvs1_2-supply property to specify the supply regulator for LVS1 and LVS2 (following the pin name in the PMIC datasheet). Correct the board's device tree property, so that the regulator supply is setup properly. Cc: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104002949.2204727-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 48de66bf19c4..7cc564d8ca7c 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -223,7 +223,7 @@ vdd_l17_l29-supply = <&pmi8994_bby>; vdd_l20_l21-supply = <&pmi8994_bby>; vdd_l25-supply = <&pm8994_s3>; - vdd_lvs1_lvs2-supply = <&pm8994_s4>; + vdd_lvs1_2-supply = <&pm8994_s4>; /* S1, S2, S6 and S12 are managed by RPMPD */ From 4c821bd42ccceca5e0fdc5491374e3d7e6941c2e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 Nov 2021 03:29:49 +0300 Subject: [PATCH 073/574] arm64: dts: qcom: msm8996-sony-xperia-tone: fix SPMI regulators declaration Device tree for the Sony Xperia tone family of devices specifies S9+S10+S11 SAW regulator as a part of the pmi8994_spmi_regulators device tree node. However PMI8994 does not have these regulators, they are part of the PM8994 device. All other MSM8996-based devices list them in the pm8994_spmi_regulators device tree node. Move them accordingly. Cc: AngeloGioacchino Del Regno Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104002949.2204727-5-dmitry.baryshkov@linaro.org --- .../dts/qcom/msm8996-sony-xperia-tone.dtsi | 35 ++++++++++--------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index ff7f39d29dd5..137b2d14f5e3 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -589,9 +589,27 @@ }; }; -&pmi8994_spmi_regulators { +&pm8994_spmi_regulators { qcom,saw-reg = <&saw3>; + pm8994_s9: s9 { + qcom,saw-slave; + }; + + pm8994_s10: s10 { + qcom,saw-slave; + }; + + pm8994_s11: s11 { + qcom,saw-leader; + regulator-name = "vdd_apcc"; + regulator-always-on; + regulator-min-microvolt = <470000>; + regulator-max-microvolt = <1140000>; + }; +}; + +&pmi8994_spmi_regulators { vdd_gfx: pmi8994_s2: s2 { /* Pinned to a high value for now to avoid random crashes. */ @@ -600,21 +618,6 @@ regulator-name = "vdd_gfx"; regulator-always-on; }; - - pmi8994_s9: s9 { - qcom,saw-slave; - }; - - pmi8994_s10: s10 { - qcom,saw-slave; - }; - - pmi8994_s11: s11 { - qcom,saw-leader; - regulator-always-on; - regulator-min-microvolt = <470000>; - regulator-max-microvolt = <1140000>; - }; }; &pmi8994_wled { From 25fdaae63a6927efad2f6c0428622712f0eb20dd Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 4 Nov 2021 10:49:58 +0000 Subject: [PATCH 074/574] arm64: dts: qcom: msm8996-xiaomi-scorpio: Add touchkey controller Add a node and pin states for Cypress StreetFighter touchkey controller. Signed-off-by: Yassine Oudjana Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104104932.104046-1-y.oudjana@protonmail.com --- .../boot/dts/qcom/msm8996-xiaomi-scorpio.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts index e5b8402b1ed6..27a45ddbb5bd 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts @@ -60,6 +60,20 @@ }; &blsp2_i2c6 { + touchkey: touchkey@28 { + compatible = "cypress,sf3155"; + reg = <0x28>; + interrupt-parent = <&tlmm>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <&vreg_l6a_1p8>; + vdd-supply = <&vdd_3v2_tp>; + linux,keycodes = ; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touchkey_default>; + pinctrl-1 = <&touchkey_sleep>; + }; + touchscreen: atmel-mxt-ts@4a { compatible = "atmel,maxtouch"; reg = <0x4a>; @@ -416,6 +430,20 @@ "RFFE1_DATA", /* GPIO_148 */ "RFFE1_CLK"; /* GPIO_149 */ + touchkey_default: touchkey_default { + pins = "gpio77"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; + + touchkey_sleep: touchkey_sleep { + pins = "gpio77"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + touchscreen_default: touchscreen_default { pins = "gpio75", "gpio125"; function = "gpio"; From de0a2ae359ef9ccbaab86cce44d442cd0ca36985 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 4 Nov 2021 11:15:18 +0000 Subject: [PATCH 075/574] arm64: dts: qcom: msm8996-xiaomi-common: Change TUSB320 to TUSB320L This platform actually doesn't have TUSB320, but rather TUSB320L. The TUSB320 compatible string was used due to lack of support for TUSB320L, and it was close enough to detect cable plug-in and direction, but it was limited to upstream facing port mode only. Now that support for TUSB320L is added[1], change node name and compatible to match and allow it to be properly reset and have its mode set to dual-role port. [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=ce0320bd3872038569be360870e2d5251b975692 Signed-off-by: Yassine Oudjana Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211104111454.105875-1-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 01e573f0dfbf..7a9fcbe9bb31 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -207,8 +207,8 @@ status = "okay"; label = "TYPEC_I2C"; - typec: tusb320@47 { - compatible = "ti,tusb320"; + typec: tusb320l@47 { + compatible = "ti,tusb320l"; reg = <0x47>; interrupt-parent = <&tlmm>; interrupts = <63 IRQ_TYPE_EDGE_RISING>; From 5663ca59bb4f1dfd2501f2af0bfdca93c4d47b3a Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 28 Sep 2021 10:20:02 +0800 Subject: [PATCH 076/574] arm64: dts: qcom: Add missing vdd-supply for QUSB2 PHY QUSB2 PHY requires vdd-supply for digital circuit operation. Add it for platforms that miss it. Signed-off-by: Shawn Guo Acked-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210928022002.26286-4-shawn.guo@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi | 1 + 4 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 28403d2ffd31..f623db8451f1 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -233,6 +233,7 @@ &hsusb_phy1 { status = "okay"; + vdd-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; }; @@ -240,6 +241,7 @@ &hsusb_phy2 { status = "okay"; + vdd-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index 137b2d14f5e3..3bb50cecd62d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -184,6 +184,7 @@ &hsusb_phy1 { status = "okay"; + vdd-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; vdda-phy-dpdm-supply = <&pm8994_l24>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi index 3f60575a351c..b3b352530d76 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi @@ -102,6 +102,7 @@ &qusb2phy { status = "okay"; + vdd-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index 654188027f79..9823d48a91b1 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -260,6 +260,7 @@ &qusb2phy { status = "okay"; + vdd-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; }; From f0360a7c1742681c390f2d94bb876ce80a8012b1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:40 +0100 Subject: [PATCH 077/574] arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI Almost any board that boots and has a way to interact with it (say for the rare cases of just-pstore or let's-rely-on-bootloader-setup) needs to set some GPIOs, so it makes no sense to include gpio.h separately each time. Hence move it to SoC DTSI. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-1-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 - arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 1 - arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index be062377c936..1e5e9405d8b1 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -5,7 +5,6 @@ /dts-v1/; -#include #include #include "sm8350.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index 06eedbe52c42..122c282a62df 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -5,7 +5,6 @@ /dts-v1/; -#include #include #include "sm8350.dtsi" #include "pm8350.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index d134280e2939..ee183f00dbaf 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include From e84d04a2b221153b88f644d98b5902c3705f5348 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:41 +0100 Subject: [PATCH 078/574] arm64: dts: qcom: sm8350: Add missing QUPv3 ID2 Add the missing third QUPv3 master node. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-2-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index ee183f00dbaf..6cfe1f38dae9 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -597,6 +597,18 @@ #mbox-cells = <2>; }; + qupv3_id_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x6000>; From f4d4ca9f3934844b99af289cf38d4892c73f683e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:42 +0100 Subject: [PATCH 079/574] arm64: dts: qcom: sm8350: Add redistributor stride to GICv3 The redistributor properties were missing. Add them. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-3-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 6cfe1f38dae9..a30ba3193d84 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1020,6 +1020,8 @@ compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0 0x20000>; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ interrupts = ; From ed9500c1df59437856d43e657f185fb1eb5d817d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:43 +0100 Subject: [PATCH 080/574] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer Arch timer runs at 19.2 MHz. Specify the rate in the timer node. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-4-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a30ba3193d84..60866a20a55c 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2484,5 +2484,6 @@ , , ; + clock-frequency = <19200000>; }; }; From 9e7f7b65c7f04c5cfda97d6bd0d452a49e60f24e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:44 +0100 Subject: [PATCH 081/574] arm64: dts: qcom: sm[68]350: Use interrupts-extended with pdc interrupts Using interrupts = <&pdc X Y> makes the interrupt framework interpret this as the &pdc-nth range of the main interrupt controller (GIC). Fix it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-5-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 973e18fe3b67..cd55797facf6 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -631,7 +631,7 @@ reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x8>; /* SROT */ #qcom,sensors = <16>; - interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; @@ -642,7 +642,7 @@ reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x8>; /* SROT */ #qcom,sensors = <16>; - interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 60866a20a55c..f3e8549c6572 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -923,7 +923,7 @@ reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x8>; /* SROT */ #qcom,sensors = <15>; - interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; @@ -934,7 +934,7 @@ reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x8>; /* SROT */ #qcom,sensors = <14>; - interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; From f52dd33943ca5f84ae76890f352f6d9e12512c3f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:45 +0100 Subject: [PATCH 082/574] arm64: dts: qcom: sm8350: Shorten camera-thermal-bottom name Thermal zone names should not be longer than 20 names, which is indicated by a message at boot. Change "camera-thermal-bottom" to "cam-thermal-bottom" to fix it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-6-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index f3e8549c6572..7e0aa4c25094 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2462,7 +2462,7 @@ }; }; - camera-thermal-bottom { + cam-thermal-bottom { polling-delay-passive = <250>; polling-delay = <1000>; From 2dab7aac493df72f57498044cb38ca0a6c18e7e1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:46 +0100 Subject: [PATCH 083/574] arm64: dts: qcom: *8350* Consolidate PON/RESIN usage Disable PON/RESIN keys by default and keep the RESIN keycode set-per-board, as these settings are not common between devices (one cannot even assume all devices have buttons nowadays..). Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-7-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/pmk8350.dtsi | 7 ++++--- arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 9 +++++++++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index 769f9726806f..0f94c46a1444 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -19,16 +19,17 @@ compatible = "qcom,pm8998-pon"; reg = <0x1300>; - pwrkey { + pon_pwrkey: pwrkey { compatible = "qcom,pmk8350-pwrkey"; interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; linux,code = ; + status = "disabled"; }; - resin { + pon_resin: resin { compatible = "qcom,pmk8350-resin"; interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index 122c282a62df..52cf3045602f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -289,6 +289,15 @@ status = "okay"; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + linux,code = ; +}; + &qupv3_id_0 { status = "okay"; }; From 9ea9eb36b3c046fc48e737db4de69f7acd12f9be Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:47 +0100 Subject: [PATCH 084/574] arm64: dts: qcom: sm8350: Describe GCC dependency clocks Add all the clock names that the GCC driver expects to get via DT, so that the clock handles can be filled as the development progresses. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-8-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 7e0aa4c25094..3d0d80e61405 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -584,8 +584,30 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clock-names = "bi_tcxo", "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", + "sleep_clk", + "pcie_0_pipe_clk", + "pcie_1_pipe_clk", + "ufs_card_rx_symbol_0_clk", + "ufs_card_rx_symbol_1_clk", + "ufs_card_tx_symbol_0_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk", + "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; }; ipcc: mailbox@408000 { From cf03cd7e12bdb43d624dbd55d8467b29e9b608c2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:48 +0100 Subject: [PATCH 085/574] arm64: dts: qcom: sm8350: Set up WRAP0 QUPs Set up I2C&SPI hosts and UARTs connected to WRAP0 and their respective pins. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-9-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 287 +++++++++++++++++++++++++++ 1 file changed, 287 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 3d0d80e61405..4b864fcb04e0 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -619,6 +619,25 @@ #mbox-cells = <2>; }; + qup_opp_table_100mhz: qup-100mhz-opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -642,6 +661,84 @@ ranges; status = "disabled"; + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00980000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00980000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00984000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00984000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00988000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00988000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart2: serial@98c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x0098c000 0 0x4000>; @@ -650,6 +747,140 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_default_state>; interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* QUP no. 3 seems to be strictly SPI-only */ + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0098c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00990000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00990000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00994000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00994000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart6: serial@998000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart6_default>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; + + i2c7: i2c@99c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@99c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1017,6 +1248,62 @@ }; }; + qup_uart6_default: qup-uart6-default { + pins = "gpio30", "gpio31"; + function = "qup6"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c0_default: qup-i2c0-default { + pins = "gpio4", "gpio5"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default { + pins = "gpio8", "gpio9"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default { + pins = "gpio12", "gpio13"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default { + pins = "gpio20", "gpio21"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default { + pins = "gpio24", "gpio25"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_default: qup-i2c6-default { + pins = "gpio28", "gpio29"; + function = "qup6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_default: qup-i2c7-default { + pins = "gpio32", "gpio33"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + qup_i2c13_default_state: qup-i2c13-default-state { mux { pins = "gpio0", "gpio1"; From 8934535531c875e6ec67876905982a44e8306c1c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:49 +0100 Subject: [PATCH 086/574] arm64: dts: qcom: sm8350: Set up WRAP1 QUPs Set up I2C&SPI hosts and UARTs connected to WRAP1 and their respective pins. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-10-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 213 +++++++++++++++++++++++++-- 1 file changed, 202 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 4b864fcb04e0..033d3984d572 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -638,6 +638,25 @@ }; }; + qup_opp_table_120mhz: qup-120mhz-opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -898,18 +917,161 @@ ranges; status = "disabled"; + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default_state>; + pinctrl-0 = <&qup_i2c13_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; apps_smmu: iommu@15000000 { @@ -1304,17 +1466,46 @@ bias-disable; }; - qup_i2c13_default_state: qup-i2c13-default-state { - mux { - pins = "gpio0", "gpio1"; - function = "qup13"; - }; + qup_i2c8_default: qup-i2c8-default { + pins = "gpio36", "gpio37"; + function = "qup8"; + drive-strength = <2>; + bias-pull-up; + }; - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-pull-up; - }; + qup_i2c9_default: qup-i2c9-default { + pins = "gpio40", "gpio41"; + function = "qup9"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default { + pins = "gpio44", "gpio45"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c11_default: qup-i2c11-default { + pins = "gpio48", "gpio49"; + function = "qup11"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c12_default: qup-i2c12-default { + pins = "gpio52", "gpio53"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c13_default: qup-i2c13-default { + pins = "gpio0", "gpio1"; + function = "qup13"; + drive-strength = <2>; + bias-pull-up; }; }; From 98374e6925b88cfc4e528faed230a835f91a576d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:50 +0100 Subject: [PATCH 087/574] arm64: dts: qcom: sm8350: Set up WRAP2 QUPs Set up I2C&SPI hosts and UARTs connected to WRAP2 and their respective pins. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-11-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 200 +++++++++++++++++++++++++++ 1 file changed, 200 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 033d3984d572..944ad864f73e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -667,6 +667,164 @@ #size-cells = <2>; ranges; status = "disabled"; + + i2c14: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c15: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi15: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c16: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c16_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi16: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c17: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c17_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi17: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* QUP no. 18 seems to be strictly SPI/UART-only */ + + spi18: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart18: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart18_default>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; + + i2c19: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c19_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi19: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts = ; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; qupv3_id_0: geniqup@9c0000 { @@ -1417,6 +1575,13 @@ bias-disable; }; + qup_uart18_default: qup-uart18-default { + pins = "gpio58", "gpio59"; + function = "qup18"; + drive-strength = <2>; + bias-disable; + }; + qup_i2c0_default: qup-i2c0-default { pins = "gpio4", "gpio5"; function = "qup0"; @@ -1507,6 +1672,41 @@ drive-strength = <2>; bias-pull-up; }; + + qup_i2c14_default: qup-i2c14-default { + pins = "gpio56", "gpio57"; + function = "qup14"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c15_default: qup-i2c15-default { + pins = "gpio60", "gpio61"; + function = "qup15"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c16_default: qup-i2c16-default { + pins = "gpio64", "gpio65"; + function = "qup16"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c17_default: qup-i2c17-default { + pins = "gpio72", "gpio73"; + function = "qup17"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c19_default: qup-i2c19-default { + pins = "gpio76", "gpio77"; + function = "qup19"; + drive-strength = <2>; + bias-disable; + }; }; rng: rng@10d3000 { From 9bc2c8fea55c12d3720a80a59f99fdf68b8de773 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:51 +0100 Subject: [PATCH 088/574] arm64: dts: qcom: sm8350: Assign iommus property to QUP WRAPs Assign the iommus property to allow access to QUP hosts that were not set up by the bootloader. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-12-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 944ad864f73e..0ea735d0df49 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -663,6 +663,7 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x5e3 0x0>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -833,6 +834,7 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x5a3 0>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -1070,6 +1072,7 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x43 0>; #address-cells = <2>; #size-cells = <2>; ranges; From c2721b0c23d975c73bce68d40435d66fbab19047 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:52 +0100 Subject: [PATCH 089/574] arm64: dts: qcom: Add support for Xperia 1 III / 5 III Add support for SONY Xperia 1 III (PDX215) and 5 III (PDX214) smartphones. Both are based on the SM8350 Sagami platform and feature some really high-end specs, such as: - 4K (1 III / PRO-I) / 1080p (5 III), 120Hz HDR OLED 10-bit panels - USB-C 3.1 with HDMI in (yes, phone as display!) and DP out - 5G - 8 or 12 gigs of ram, 128/256/512 gigs of storage - A 3.5mm headphone jack, a RGB notification LED and a uSD card slot :) - IP65/68 dust/water resistance - Dual front-firing speakers and a lot of microphones - Crazy complex camera hardware (especially on the PRO-I), which includes 4 cameras, an RGBIR sensor and a 3D iToF The aforementioned PRO-I (PDX217) is not supported in this patch, because even though it shares most of the code with 1 III, nobody really has it (yet?) This only adds basic support for booting to a USB shell with a bootloader-enabled display, support for all the awesome hardware listed above will (hopefully) come (hopefully) soon. In order to get a working boot image, you need to run (e.g. for 1 III): cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm8350-sony-xperia-\ sagami-pdx215.dtb > .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd.img \ --pagesize 4096 \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --tags_offset 0x100 \ --cmdline "SOME_CMDLINE" \ --dtb_offset 0x1f00000 \ --header_version 1 \ --os_version 11 \ --os_patch_level 2021-10 \ # or newer -o boot.img-sony-xperia-pdx215 Then, you need to flash it on the device and get rid of all the vendor_boot/dtbo mess: fastboot flash boot boot.img-sony-xperia-pdx215 fastboot erase vendor_boot fastboot flash dtbo emptydtbo.img fastboot reboot Where emptydtbo.img is a tiny file that consists of 2 bytes (all zeroes), doing a "fastboot erase" won't cut it, the bootloader will go crazy and things will fall apart when it tries to overlay random bytes from an empty partition onto a perfectly good appended DTB. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-13-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/sm8350-sony-xperia-sagami-pdx214.dts | 19 +++ .../qcom/sm8350-sony-xperia-sagami-pdx215.dts | 13 ++ .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 132 ++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4906712e3cfd..50572419dca9 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -116,3 +116,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts new file mode 100644 index 000000000000..cc650508dc2d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sm8350-sony-xperia-sagami.dtsi" + +/ { + model = "Sony Xperia 5 III"; + compatible = "sony,pdx214-generic", "qcom,sm8350"; +}; + +&framebuffer { + width = <1080>; + height = <2520>; + stride = <(1080 * 4)>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts new file mode 100644 index 000000000000..d21bbeb603a6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sm8350-sony-xperia-sagami.dtsi" + +/ { + model = "Sony Xperia 1 III"; + compatible = "sony,pdx215-generic", "qcom,sm8350"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi new file mode 100644 index 000000000000..b50f04ffee95 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include "sm8350.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" +#include "pmr735b.dtsi" + +/ { + /* + * Yes, you are correct, there is NO MORE {msm,board,pmic}-id on SM8350! + * Adding it will cause the bootloader to go crazy and randomly crash + * shortly after closing UEFI boot services.. Perhaps that has something + * to do with the OS running inside a VM now..? + */ + + chassis-type = "handset"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@e1000000 { + compatible = "simple-framebuffer"; + reg = <0 0xe1000000 0 0x2300000>; + + /* The display, even though it's 4K, initializes at 1080-ish p */ + width = <1096>; + height = <2560>; + stride = <(1096 * 4)>; + format = "a8r8g8b8"; + /* + * That's (going to be) a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet + */ + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + /* For reasons still unknown, GAssist key and Camera Focus/Shutter don't work.. */ + + vol-down { + label = "Volume Down"; + linux,code = ; + gpios = <&pmk8350_gpios 3 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; + + reserved-memory { + cont_splash_mem: memory@e1000000 { + reg = <0 0xe1000000 0 0x2300000>; + no-map; + }; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0 0xffc00000 0 0x100000>; + console-size = <0x40000>; + record-size = <0x1000>; + no-map; + }; + }; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + linux,code = ; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <44 4>; +}; + +/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ +&ufs_mem_hc { status = "disabled"; }; +&ufs_mem_phy { status = "disabled"; }; + +/* TODO: Make USB3 work (perhaps needs regulators for higher-current operation?) */ +&usb_1 { + status = "okay"; + + qcom,select-utmi-as-pipe-clk; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; + + maximum-speed = "high-speed"; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + status = "okay"; +}; + +&usb_1_qmpphy { + status = "okay"; +}; From 1209e9246632d93f557c651110533bf44f8335f3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:53 +0100 Subject: [PATCH 090/574] arm64: dts: qcom: sm8350-sagami: Enable and populate I2C/SPI nodes Based on current driver availability, add either nodes or comments regarding peripherals connected via I2C/SPI. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-14-konrad.dybcio@somainline.org --- .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index b50f04ffee95..c44376aa0742 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -75,6 +75,93 @@ }; }; +&i2c1 { + status = "okay"; + clock-frequency = <1000000>; + + /* Some subset of SONY IMX663 camera sensor @ 38 */ +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + /* Richwave RTC6226 FM Radio Receiver @ 64 */ +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + /* Samsung Touchscreen (needs I2C GPI DMA) @ 48 */ +}; + +&i2c11 { + status = "okay"; + clock-frequency = <1000000>; + + cs35l41_l: cs35l41@40 { + compatible = "cirrus,cs35l41"; + reg = <0x40>; + interrupt-parent = <&tlmm>; + interrupts = <36 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,gpio2-src-select = <2>; + cirrus,gpio2-output-enable; + #sound-dai-cells = <1>; + }; + + cs35l41_r: cs35l41@41 { + compatible = "cirrus,cs35l41"; + reg = <0x41>; + interrupt-parent = <&tlmm>; + interrupts = <36 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,gpio2-src-select = <2>; + cirrus,gpio2-output-enable; + #sound-dai-cells = <1>; + }; +}; + +&i2c12 { + status = "okay"; + /* Clock frequency was not specified downstream, let's park it to 100 KHz */ + clock-frequency = <100000>; + + /* AMS TCS3490 RGB+IR color sensor @ 72 */ +}; + +&i2c13 { + status = "okay"; + /* Clock frequency was not specified downstream, let's park it to 100 KHz */ + clock-frequency = <100000>; + + /* Qualcomm PM8008i/PM8008j (?) @ 8, 9, c, d */ + /* Dialog SLG51000 CMIC @ 75 */ +}; + +&i2c15 { + status = "okay"; + clock-frequency = <400000>; + + /* NXP SN1X0 NFC @ 28 */ +}; + +&i2c17 { + status = "okay"; + clock-frequency = <1000000>; + + /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */ +}; + &pmk8350_rtc { status = "okay"; }; @@ -100,8 +187,22 @@ status = "okay"; }; +&spi14 { + status = "okay"; + + /* NXP SN1X0 NFC Secure Element @ 0 */ +}; + &tlmm { gpio-reserved-ranges = <44 4>; + + ts_int_default: ts-int-default { + pin = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; }; /* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ From ce2762aec7378892d398b784a4bfd4856dd71043 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:54 +0100 Subject: [PATCH 091/574] arm64: dts: qcom: sm8350-sagami: Configure remote processors Configure ADSP, CDSP, MPSS, SLPI and IPA on SoMC Sagami. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-15-konrad.dybcio@somainline.org --- .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index c44376aa0742..90b13cbe2fa6 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -75,6 +75,16 @@ }; }; +&adsp { + status = "okay"; + firmware-name = "qcom/adsp.mbn"; +}; + +&cdsp { + status = "okay"; + firmware-name = "qcom/cdsp.mbn"; +}; + &i2c1 { status = "okay"; clock-frequency = <1000000>; @@ -162,6 +172,17 @@ /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */ }; +&ipa { + status = "okay"; + memory-region = <&pil_ipa_fw_mem>; + firmware-name = "qcom/ipa_fws.mbn"; +}; + +&mpss { + status = "okay"; + firmware-name = "qcom/modem.mbn"; +}; + &pmk8350_rtc { status = "okay"; }; @@ -187,6 +208,11 @@ status = "okay"; }; +&slpi { + status = "okay"; + firmware-name = "qcom/slpi.mbn"; +}; + &spi14 { status = "okay"; From 9ac8999e8d6c05826664a61bc89509824f45621d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 14 Nov 2021 02:27:55 +0100 Subject: [PATCH 092/574] arm64: dts: qcom: sm8350: Add LLCC node Configure the Last-Level Cache Controller for SM8350. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211114012755.112226-16-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 0ea735d0df49..7323ed74f41a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2232,6 +2232,12 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + system-cache-controller@9200000 { + compatible = "qcom,sm8350-llcc"; + reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; From 96e1e3a15273a99d89b1389e4487e734c7d37d8e Mon Sep 17 00:00:00 2001 From: yangcong Date: Mon, 15 Nov 2021 11:01:55 +0800 Subject: [PATCH 093/574] arm64: dts: qcom: sc7180: Fix ps8640 power sequence for Homestar rev4 When powering up the ps8640, we need to deassert PD right after we turn on the vdd33 regulator. Unfortunately, the vdd33 regulator takes some time (~4ms) to turn on. Add in the delay for the vdd33 regulator so that when the driver deasserts PD that the regulator has had time to ramp. Signed-off-by: yangcong Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211115030155.9395-1-yangcong5@huaqin.corp-partner.google.com --- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts index fb27106bbb4a..0de0c97f5728 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts @@ -15,3 +15,7 @@ model = "Google Homestar (rev4+)"; compatible = "google,homestar", "qcom,sc7180"; }; + +&pp3300_brij_ps8640 { + regulator-enable-ramp-delay = <4000>; +}; From fa09b2248714c64644576d8064e9bd292a504a0e Mon Sep 17 00:00:00 2001 From: Prasad Malisetty Date: Tue, 16 Nov 2021 16:31:46 +0530 Subject: [PATCH 094/574] arm64: dts: qcom: sc7280: Fix incorrect clock name Replace pcie_1_pipe-clk clock name with pcie_1_pipe_clk To match with dt binding. Fixes: ab7772de8612 ("arm64: dts: qcom: SC7280: Add rpmhcc clock controller node") Signed-off-by: Prasad Malisetty Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1637060508-30375-2-git-send-email-pmaliset@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e4988ea2011c..f14fed538022 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -581,7 +581,7 @@ <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, <0>, <0>, <0>, <0>, <0>, <0>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", - "pcie_0_pipe_clk", "pcie_1_pipe-clk", + "pcie_0_pipe_clk", "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; From bd7d507935ca73fba6b6f0f52a3d08d77b143c58 Mon Sep 17 00:00:00 2001 From: Prasad Malisetty Date: Tue, 16 Nov 2021 16:31:47 +0530 Subject: [PATCH 095/574] arm64: dts: qcom: sc7280: Add pcie clock support Add pcie clock phandle for sc7280 SoC. Signed-off-by: Prasad Malisetty Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1637060508-30375-3-git-send-email-pmaliset@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f14fed538022..5b8f549e1e8b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -579,7 +579,8 @@ reg = <0 0x00100000 0 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <0>, <0>, <0>, <0>, <0>; + <0>, <&pcie1_lane 0>, + <0>, <0>, <0>, <0>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", From 66b788133030f0c69a0ecc7f72f7939b119c9a69 Mon Sep 17 00:00:00 2001 From: Prasad Malisetty Date: Tue, 16 Nov 2021 16:31:48 +0530 Subject: [PATCH 096/574] arm64: dts: qcom: sc7280: Fix 'interrupt-map' parent address cells Update interrupt-map parent address cells for sc7280 Similar to existing Qcom SoCs. Fixes: 92e0ee9f8 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Signed-off-by: Prasad Malisetty Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1637060508-30375-4-git-send-email-pmaliset@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5b8f549e1e8b..40b409f279f5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1598,10 +1598,10 @@ interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, From b139425115b801e56fe2d6dbcd2e798be87e2e06 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sun, 21 Nov 2021 04:42:20 +0700 Subject: [PATCH 097/574] arm64: dts: qcom: sdm630: Assign numbers to eMMC and SD This makes eMMC/SD device number consistent. Reviewed-by: Martin Botka Signed-off-by: Dang Huynh Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-2-danct12@riseup.net --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 3e0165bb61c5..b75bb87ed290 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -19,6 +19,11 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + }; + chosen { }; clocks { From 9f6cbe37a72fc9dafe8f560e557c93209cc100e7 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sun, 21 Nov 2021 04:42:21 +0700 Subject: [PATCH 098/574] arm64: dts: qcom: sdm630-pm660: Move RESIN to pm660 dtsi It's not worth duplicating the same node over and over again, so let's keep the common bits in the pm660 DTSI, making only changing the status and keycode necessary. Also, disable RESIN/PWR by default just in case if there are devices that doesn't use them. Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-3-danct12@riseup.net --- arch/arm64/boot/dts/qcom/pm660.dtsi | 12 +++++++++++- .../boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 16 ++++++++-------- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index d0ef8a1675e2..c482663aad56 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -54,14 +54,24 @@ mode-bootloader = <0x2>; mode-recovery = <0x1>; - pwrkey { + pon_pwrkey: pwrkey { compatible = "qcom,pm8941-pwrkey"; interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; debounce = <15625>; bias-pull-up; linux,code = ; + + status = "disabled"; }; + pon_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + + status = "disabled"; + }; }; pm660_temp: temp-alarm@2400 { diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 11d0a8c1cf35..e90c9ec84675 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -215,14 +215,14 @@ /* HCI Bluetooth */ }; -&pon { - volup { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = ; }; &qusb2phy { From 262a8ad19cdfd8e177d32bfbec1691a2069951b1 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sun, 21 Nov 2021 04:42:22 +0700 Subject: [PATCH 099/574] arm64: dts: qcom: sdm660-xiaomi-lavender: Add RPM and fixed regulators Add most of the RPM PM660/PM660L regulators and the fixed ones, defining the common electrical part of this platform. Signed-off-by: Dang Huynh Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-4-danct12@riseup.net --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 266 ++++++++++++++++++ 1 file changed, 266 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 1edc53fd6941..eccbeecef192 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -1,11 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, Alexey Minnekhanov + * Copyright (c) 2021, Dang Huynh */ /dts-v1/; #include "sdm660.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" / { model = "Xiaomi Redmi Note 7"; @@ -20,6 +23,16 @@ stdout-path = "serial0:115200n8"; }; + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -40,6 +53,259 @@ status = "okay"; }; +&rpm_requests { + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s1b_1p125: s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-enable-ramp-delay = <200>; + }; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + }; + + /* LDOs */ + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + /* SDHCI 3.3V signal doesn't seem to be supported. */ + vreg_l2b_2p95: l2 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2696000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l3b_3p3: l3 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l4b_2p95: l4 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_2p95: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + regulator-system-load = <800000>; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <500>; + }; + }; + + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + /* + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed + * by the Core Power Reduction hardened (CPRh) and the + * Operating State Manager (OSM) HW automatically. + */ + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + }; + + vreg_s6a_0p87: s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + regulator-enable-ramp-delay = <150>; + }; + + /* LDOs */ + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l2a_1p0: l2 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l5a_0p848: l5 { + regulator-min-microvolt = <525000>; + regulator-max-microvolt = <950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + regulator-allow-set-load; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7a_1p2: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l11a_1p8: l11 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + }; + + /* This gives power to the LPDDR4: never turn it off! */ + vreg_l13a_1p8: l13 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l14a_1p8: l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l16a_2p7: l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <250>; + regulator-always-on; + }; + + vreg_l17a_1p8: l17 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <8 4>; }; From 4c420a0449ce0882f225e6e7ae3edc87becd2e85 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sun, 21 Nov 2021 04:42:23 +0700 Subject: [PATCH 100/574] arm64: dts: qcom: sdm660-xiaomi-lavender: Add PWRKEY and RESIN This enables the volume down key as well as the power button. Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-5-danct12@riseup.net --- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index eccbeecef192..9a6684922804 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -53,6 +53,16 @@ status = "okay"; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = ; +}; + &rpm_requests { pm660l-regulators { compatible = "qcom,rpm-pm660l-regulators"; From cf85e9aee210fefd7a85c1ced0a73382e5edcfd0 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sun, 21 Nov 2021 04:42:25 +0700 Subject: [PATCH 101/574] arm64: dts: qcom: sdm660-xiaomi-lavender: Add eMMC and SD This commit enable the SD card slot and internal MMC. Signed-off-by: Dang Huynh Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-7-danct12@riseup.net --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 9a6684922804..264a8f50db66 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -316,6 +316,25 @@ }; }; +&sdhc_1 { + status = "okay"; + supports-cqe; + + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l5b_2p95>; + vqmmc-supply = <&vreg_l2b_2p95>; +}; + &tlmm { gpio-reserved-ranges = <8 4>; }; From e631e904e1d89650e3c8facdfb37cfca3491a52d Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sun, 21 Nov 2021 04:42:26 +0700 Subject: [PATCH 102/574] arm64: dts: qcom: sdm660-xiaomi-lavender: Enable Simple Framebuffer This lets the user sees the framebuffer console. Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-8-danct12@riseup.net --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 264a8f50db66..95c1518bb52d 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -20,7 +20,20 @@ }; chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + stdout-path = "serial0:115200n8"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x9d400000 0 (1080 * 2340 * 4)>; + width = <1080>; + height = <2340>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; }; vph_pwr: vph-pwr-regulator { @@ -46,6 +59,11 @@ ftrace-size = <0x0>; pmsg-size = <0x20000>; }; + + framebuffer_mem: memory@9d400000 { + reg = <0x0 0x9d400000 0x0 0x23ff000>; + no-map; + }; }; }; From e5d3e752b050e03d2046011a3865721a3f200216 Mon Sep 17 00:00:00 2001 From: Alexey Min Date: Sun, 21 Nov 2021 04:42:27 +0700 Subject: [PATCH 103/574] arm64: dts: qcom: sdm660-xiaomi-lavender: Add USB Enable and configure DWC3 and QUSB2 PHY to enable USB functionality on the Redmi Note 7. Signed-off-by: Alexey Min Co-developed-by: Dang Huynh Signed-off-by: Dang Huynh Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211120214227.779742-9-danct12@riseup.net --- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 95c1518bb52d..d042e3883b9e 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -65,6 +65,15 @@ no-map; }; }; + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; }; &blsp1_uart2 { @@ -81,6 +90,13 @@ linux,code = ; }; +&qusb2phy { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + &rpm_requests { pm660l-regulators { compatible = "qcom,rpm-pm660l-regulators"; @@ -356,3 +372,12 @@ &tlmm { gpio-reserved-ranges = <8 4>; }; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +}; From b70bf26a704c74b3b611e8ff639f1262de19aaef Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Sat, 16 Oct 2021 12:20:23 +0200 Subject: [PATCH 104/574] arm64: dts: freescale: add 'chassis-type' property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A new 'chassis-type' root node property has recently been approved for the device-tree specification, in order to provide a simple way for userspace to detect the device form factor and adjust their behavior accordingly. This patch fills in this property for end-user devices (such as laptops, smartphones and tablets) based on NXP ARM64 processors. Signed-off-by: Arnaud Ferraris Reviewed-by: Guido Günther Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 60d47c71499b..515446e99699 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -14,6 +14,7 @@ / { model = "Purism Librem 5"; compatible = "purism,librem5", "fsl,imx8mq"; + chassis-type = "handset"; backlight_dsi: backlight-dsi { compatible = "led-backlight"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index 4f2db6197b39..fa721a13de20 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -12,6 +12,7 @@ / { model = "MNT Reform 2"; compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; + chassis-type = "laptop"; pcie1_refclk: clock-pcie1-refclk { compatible = "fixed-clock"; From 38c0b9496127da7c8ea0e58fdd256a9e54b1ab8d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 18 Oct 2021 15:59:02 +0200 Subject: [PATCH 105/574] arm64: dts: imx: imx8mn-beacon: Drop undocumented clock-names reference The wlf,wm8962 Device Tree bindings do not specify a clock-names property. Drop it. Signed-off-by: Geert Uytterhoeven Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi index 376ca8ff7213..0f40b43ac091 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -126,7 +126,6 @@ compatible = "wlf,wm8962"; reg = <0x1a>; clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; - clock-names = "xclk"; DCVDD-supply = <®_audio>; DBVDD-supply = <®_audio>; AVDD-supply = <®_audio>; From f9d3b807daa69728e59a5171e8e7b40cfa848383 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Wed, 20 Oct 2021 16:50:13 +0100 Subject: [PATCH 106/574] ARM: dts: vf610-zii-dev-rev-b: correct phy-mode for 6185 dsa link DT currently lists the port mode for the 88E6352 switch 1 to 88E6185 switch 2 as "rgmii-id" but referring to the schematics, it is in fact a serdes link. The 88E6352 is configured with P5_MODE=6, S_SEL=1 and S_MODE=1, which means port 5 is configured as 1000BASE-X. This is confirmed by the value in the 88E6352 port 5 status register, 0x4e09, where C_MODE=9 meaning 1000BASE-X. It is also confirmed by the 88E6185 port 9 status register, 0x5e8c, where C_MODE=4 meaning cross-chip SERDES mode is selected. Signed-off-by: Russell King (Oracle) Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 043ddd70372f..80698e98dafe 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -149,7 +149,7 @@ reg = <5>; label = "dsa"; link = <&switch2port9>; - phy-mode = "rgmii-txid"; + phy-mode = "1000base-x"; fixed-link { speed = <1000>; @@ -252,7 +252,7 @@ switch2port9: port@9 { reg = <9>; label = "dsa"; - phy-mode = "rgmii-txid"; + phy-mode = "1000base-x"; link = <&switch1port5 &switch0port5>; From 52c612692848bbe6ae2feb31706911641b17afc9 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Tue, 26 Oct 2021 10:34:23 +0100 Subject: [PATCH 107/574] ARM: dts: vf610-zii-dev-rev-b: specify phy-mode for external PHYs Specify the phy-mode for the external PHYs on the third switch on the ZII development rev B board so phylink and phylib knows what mode these interfaces are configured for. Signed-off-by: Russell King (Oracle) Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 80698e98dafe..1f9686c33a84 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -211,12 +211,14 @@ reg = <0>; label = "lan6"; phy-handle = <&switch2phy0>; + phy-mode = "sgmii"; }; port@1 { reg = <1>; label = "lan7"; phy-handle = <&switch2phy1>; + phy-mode = "sgmii"; }; port@2 { From 745fa3e40ff5245c8551f2ec9ad9d3c77c8065e7 Mon Sep 17 00:00:00 2001 From: Meng Li Date: Wed, 3 Nov 2021 11:38:38 +0800 Subject: [PATCH 108/574] arm64: dts: fsl-ls1043a-rdb: add delay between CS and CLK signal for flash device Based on commit d59c90a2400f("spi: spi-fsl-dspi: Convert TCFQ users to XSPI FIFO mode ") and 6c1c26ecd9a3("spi: spi-fsl-dspi: Accelerate transfers using larger word size if possible"), on ls1043a-rdb platform, the spi work mode is changed from TCFQ mode to XSPI mode. In order to keep the transmission sequence matches with flash device, it is need to add delay between CS and CLK signal. The strategy of generating delay value refers to QorIQ LS1043A Reference Manual. Signed-off-by: Meng Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts index 3516af4726a5..b290605e92cf 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts @@ -94,6 +94,8 @@ compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-max-frequency = <1000000>; /* input clock */ + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <100>; }; slic@2 { From c681c6fcc5ddfa0492ca015b0bf325cd4881ce07 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Wed, 27 Oct 2021 16:37:26 +0200 Subject: [PATCH 109/574] arm64: dts: rockchip: add interrupt and headphone-detection for Rock Pi4's audio codec As schematics at [1] and [2] show C- and plus-revisions have interrupt and headphone detection lines of ES8316 codec connected. Add them to the respective device trees. [1] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf [2] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi4b_plus_v16_sch_20200628.pdf Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20211027143726.165809-2-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 12 +++++++++++- .../boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts | 11 +++++++++++ .../boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts | 11 +++++++++++ arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts | 11 +++++++++++ 4 files changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 98136c88fa49..54f5957e704c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -36,7 +36,7 @@ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; - sound { + sound: sound { compatible = "audio-graph-card"; label = "Analog"; dais = <&i2s0_p0>; @@ -543,6 +543,16 @@ }; }; + es8316 { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hp_int: hp-int { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts index 281a04b2f5e9..f5a68d8d072d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts @@ -12,3 +12,14 @@ model = "Radxa ROCK Pi 4A+"; compatible = "radxa,rockpi4a-plus", "radxa,rockpi4", "rockchip,rk3399"; }; + +&es8316 { + pinctrl-0 = <&hp_detect &hp_int>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = ; +}; + +&sound { + hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts index dfad13d2ab24..81bea953c891 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts @@ -17,6 +17,13 @@ }; }; +&es8316 { + pinctrl-0 = <&hp_detect &hp_int>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = ; +}; + &sdio0 { status = "okay"; @@ -31,6 +38,10 @@ }; }; +&sound { + hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +}; + &uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts index 99169bcd51c0..0ad7b6e22f70 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts @@ -17,6 +17,13 @@ }; }; +&es8316 { + pinctrl-0 = <&hp_detect &hp_int>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = ; +}; + &sdio0 { status = "okay"; @@ -31,6 +38,10 @@ }; }; +&sound { + hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +}; + &uart0 { status = "okay"; From e92df2c61c1046d26379b97141e1e968f3ccc63d Mon Sep 17 00:00:00 2001 From: Dennis Gilmore Date: Tue, 26 Oct 2021 10:07:47 -0500 Subject: [PATCH 110/574] arm64: dts: rockchip: define usb hub and 2.5GbE nic on helios64 Add the 4 ports on the internal hub and define and turn on the 2.5GbE nic. Signed-off-by: Dennis Gilmore Tested-by: Florian Klink Link: https://lore.kernel.org/r/20211026150751.70115-1-dgilmore@redhat.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-kobol-helios64.dts | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index 63c7681843da..8767dd2891ae 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -101,6 +101,18 @@ vin-supply = <&vcc5v0_perdev>; }; + usblan_power: usblan-power { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_lan_en>; + regulator-name = "usblan_power"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_usb>; + }; + vcc1v8_sys_s0: vcc1v8-sys-s0 { compatible = "regulator-fixed"; regulator-name = "vcc1v8_sys_s0"; @@ -432,6 +444,10 @@ vcc5v0_usb_en: vcc5v0-usb-en { rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; + + usb_lan_en: usb-lan-en { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; vcc3v0-sd { @@ -530,5 +546,41 @@ usb@fe900000 { dr_mode = "host"; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb2109,0815"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + + port@3 { + reg = <3>; + #trigger-source-cells = <0>; + }; + + device@4 { + compatible = "usbbda,8156"; + reg = <4>; + #address-cells = <2>; + #size-cells = <0>; + + interface@0 { /* interface 0 of configuration 1 */ + compatible = "usbbda,8156.config1.0"; + reg = <0 1>; + }; + }; + }; }; }; From 755fff528b1b760c700dbf39928ff3dda825f748 Mon Sep 17 00:00:00 2001 From: Dennis Gilmore Date: Thu, 28 Oct 2021 19:53:19 -0500 Subject: [PATCH 111/574] arm64: dts: rockchip: add variables for pcie completion to helios64 without ep-gpios defined u-boot does not initialise PCIe rockchip_pcie pcie@f8000000: failed to find ep-gpios property additionally set max-link-speed and pinctrl-names for completeness with this patch and the ones from Florian Klink applied to the dts file in u-boot sata drives show up in both u-boot and linux Signed-off-by: Dennis Gilmore Acked-By: Florian Klink Link: https://lore.kernel.org/r/20211029005323.144652-1-dgilmore@redhat.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index 8767dd2891ae..ac193e5a2295 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -401,7 +401,10 @@ }; &pcie0 { + ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; num-lanes = <2>; + pinctrl-names = "default"; status = "okay"; vpcie12v-supply = <&vcc12v_dcin>; From 8169b9894dbd2d4e440cfbc5fe9f733e5876a564 Mon Sep 17 00:00:00 2001 From: Florian Klink Date: Wed, 20 Oct 2021 11:59:22 +0200 Subject: [PATCH 112/574] arm64: dts: rockchip: Enable HDD power on helios64 This adds the hdd_{a,b}_power blocks present in the armbian helios64 dts. [1] Without those powered up, no HDDs will appear (except one connected via the m.2 slot). >From https://wiki.kobol.io/helios64/sata/#hdd-power: > The power delivery of the HDDs is divided into two group: > > HDD Rail A (Max. 3x Drives) > HDD Rail B (Max. 2x Drives) > > Helios64 implements a power staggering approach where HDD Rail A will be > powered up first, then few seconds later HDD Rail B will be powered up. > This power control scenario is performed to reduce the inrush current > during disk spin-up. In practice, this power staggering approach will be included in the bootloader (not in the kernel), as we might want to boot from a SATA drive. >From my experiments, if the bootloader doesn't implement the power staggering, only one HDD will get recognized (probably cause the others didn't boot due to few power). Still, it makes sense to expose this block in the device-tree, so the kernel can ensure both rails are on (and this can be shared with u-boot). [1] https://github.com/armbian/build/blob/744ea89a589d62cb6f409baab60fc6664520bc39/patch/kernel/archive/rockchip64-5.14/add-board-helios64.patch Signed-off-by: Florian Klink Tested-by: Dennis Gilmore Link: https://lore.kernel.org/r/20211020095926.735938-1-flokli@flokli.de Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-kobol-helios64.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index ac193e5a2295..627ee88e9dc2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -89,6 +89,30 @@ }; }; + hdd_a_power: hdd-a-power { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&hdd_a_power_en>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-name = "hdd_a_power"; + startup-delay-us = <2000000>; + }; + + hdd_b_power: hdd-b-power { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&hdd_b_power_en>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-name = "hdd_b_power"; + startup-delay-us = <2000000>; + }; + pcie_power: pcie-power { compatible = "regulator-fixed"; enable-active-high; @@ -444,6 +468,14 @@ }; power { + hdd_a_power_en: hdd-a-power-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd_b_power_en: hdd-b-power-en { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_usb_en: vcc5v0-usb-en { rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; From e3f775070e06bb9b5c29c499a98de95cb5cad7cf Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 4 Nov 2021 07:34:11 -0500 Subject: [PATCH 113/574] arm64: dts: imx8mm-beacon: Enable USB Controllers The i.MX8M Mini has two available USB controllers. On the imx8mm-beacon board, USB1 is routed to a mini-USB port with OTG functionality. USB2 is routed to a USB hub which has three host-only ports connected to it. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- .../freescale/imx8mm-beacon-baseboard.dtsi | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index 6f5e63696ec0..4097a66163b2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -43,6 +43,17 @@ enable-active-high; }; + reg_usbotg1: regulator-usbotg1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_otg1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -169,6 +180,24 @@ status = "okay"; }; +&usbotg1 { + vbus-supply = <®_usbotg1>; + disable-over-current; + dr_mode="otg"; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + disable-over-current; + dr_mode="host"; + status = "okay"; +}; + +&usbphynop2 { + reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; @@ -215,6 +244,12 @@ >; }; + pinctrl_reg_usb_otg1: usbotg1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 From b43e6c03a85423db959f88d96ddd682e5c09f8fd Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 4 Nov 2021 14:22:10 +0100 Subject: [PATCH 114/574] arm64: dts: split out a shared imx8mq-librem5-r3.dtsi description The Librem 5 r3 ("Dogwood") and r4 ("Evergreen") revisions are quite similar. Add a shared imx8mq-librem5-r3.dtsi description to be included in r3 and later dts files in order to avoid duplication. This is no change in the descriptions but only refactoring. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-librem5-r3.dts | 25 ++------------- .../boot/dts/freescale/imx8mq-librem5-r3.dtsi | 32 +++++++++++++++++++ .../boot/dts/freescale/imx8mq-librem5-r4.dts | 16 ++-------- 3 files changed, 36 insertions(+), 37 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts index cd3c3edd48fa..4533a84fb0b9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts @@ -1,14 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Purism SPC +// Copyright (C) 2021 Purism SPC /dts-v1/; -#include "imx8mq-librem5.dtsi" - -/ { - model = "Purism Librem 5r3"; - compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; -}; +#include "imx8mq-librem5-r3.dtsi" &a53_opp_table { opp-1000000000 { @@ -16,22 +11,6 @@ }; }; -&accel_gyro { - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; -}; - -&bq25895 { - ti,battery-regulation-voltage = <4200000>; /* uV */ - ti,charge-current = <1500000>; /* uA */ - ti,termination-current = <144000>; /* uA */ -}; - &buck3_reg { regulator-always-on; }; - -&proximity { - proximity-near-level = <25>; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi new file mode 100644 index 000000000000..e872eb4b1cf9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2021 Purism SPC + +/dts-v1/; + +/* + * This file describes hardware that is shared among r3 ("Dogwood") and + * later revisions of the Librem 5 so it has to be included in dts there. + */ + +#include "imx8mq-librem5.dtsi" + +/ { + model = "Purism Librem 5r3"; + compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; +}; + +&accel_gyro { + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; +}; + +&bq25895 { + ti,battery-regulation-voltage = <4200000>; /* uV */ + ti,charge-current = <1500000>; /* uA */ + ti,termination-current = <144000>; /* uA */ +}; + +&proximity { + proximity-near-level = <25>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts index cbfb49aa2563..30d65bef6939 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts @@ -1,31 +1,19 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Purism SPC +// Copyright (C) 2021 Purism SPC /dts-v1/; -#include "imx8mq-librem5.dtsi" +#include "imx8mq-librem5-r3.dtsi" / { model = "Purism Librem 5r4"; compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq"; }; -&accel_gyro { - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; -}; - &bat { maxim,rsns-microohm = <1667>; }; -&bq25895 { - ti,battery-regulation-voltage = <4200000>; /* uV */ - ti,charge-current = <1500000>; /* uA */ - ti,termination-current = <144000>; /* uA */ -}; - &led_backlight { led-max-microamp = <25000>; }; From 1019b783696aa0705517d8a23f29dbbc8ec64048 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 4 Nov 2021 14:22:11 +0100 Subject: [PATCH 115/574] arm64: dts: imx8mq-librem5: describe power supply for cameras CAMERA_PWR_EN controls two different power supplies that cameras will use. The hardware killswitch controls a third one. Describe that appropriately. The pinctrl that describes the gpio that is used in 2 places here is added to the pmic. This is done because pmic is powered early enough to make sure this will work. When we would have put the same pinctrl property into the 2 regulator nodes (instead of the pmic), we'd get: imx8mq-pinctrl 30330000.pinctrl: pin MX8MQ_IOMUXC_GPIO1_IO00 already requested by regulator-csi-1v8; cannot claim for regulator-vcam-2v8 imx8mq-pinctrl 30330000.pinctrl: pin-10 (regulator-vcam-2v8) status -22 imx8mq-pinctrl 30330000.pinctrl: could not request pin 10 (MX8MQ_IOMUXC_GPIO1_IO00) from group camerapwrgrp on device 30330000.pinctrl Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-librem5.dtsi | 50 ++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 515446e99699..0c0e2602c20a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -63,6 +63,40 @@ enable-active-high; }; + /* + * the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC + * since we can't have it twice in the 2 different regulator nodes. + */ + reg_csi_1v8: regulator-csi-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_vdd_3v3>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* controlled by the CAMERA_POWER_KEY HKS */ + reg_vcam_1v2: regulator-vcam-1v2 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <®_vdd_1v8>; + enable-active-high; + }; + + reg_vcam_2v8: regulator-vcam-2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDA_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_vdd_3v3>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_gnss: regulator-gnss { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -330,6 +364,20 @@ >; }; + pinctrl_camera_pwr: camerapwrgrp { + fsl,pins = < + /* CAMERA_PWR_EN_3V3 */ + MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x83 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + /* CSI1_NRST */ + MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x83 + >; + }; + pinctrl_charger_in: chargeringrp { fsl,pins = < /* CHRG_INT */ @@ -726,7 +774,7 @@ compatible = "rohm,bd71837"; reg = <0x4b>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; + pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>; clocks = <&pmic_osc>; clock-names = "osc"; clock-output-names = "pmic_clk"; From fed7603597fa660219eb49ef7ed37fafd42f9869 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 4 Nov 2021 14:22:12 +0100 Subject: [PATCH 116/574] arm64: dts: imx8mq-librem5: describe the selfie cam Enable the CSI1 MIPI RX controller and CSI1 bridge on the SoC. Describe the Librem 5 front-facing camera, connected to the CSI1 MIPI. the following sets formats, streams 10 frames and saves one: #!/bin/bash WIDTH=1632 HEIGHT=1224 SKIP=10 media-ctl -d "platform:30a90000.csi" --set-v4l2 "'csi':0 [fmt:SGBRG10/${WIDTH}x${HEIGHT} colorspace:raw]" media-ctl -d "platform:30a90000.csi" --set-v4l2 "'imx8mq-mipi-csi2 30a70000.csi':0 [fmt:SGBRG10/${WIDTH}x${HEIGHT} colorspace:raw]" media-ctl -d "platform:30a90000.csi" --set-v4l2 "'hi846 2-0020':0 [fmt:SGBRG10/${WIDTH}x${HEIGHT} colorspace:raw]" media-ctl -d "platform:30a90000.csi" -l "'hi846 2-0020':0 -> 'imx8mq-mipi-csi2 30a70000.csi':0 [1]" v4l2-ctl -d "/dev/v4l/by-path/platform-30a90000.csi-video-index0" --set-fmt-video=width=${WIDTH},height=${HEIGHT},pixelformat=GB16 --stream-mmap --stream-to=$WIDTH.raw --stream-skip=$SKIP --stream-count=1 Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-librem5.dtsi | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 0c0e2602c20a..f3e3418f7edc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -272,6 +272,10 @@ cpu-supply = <&buck2_reg>; }; +&csi1 { + status = "okay"; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; @@ -1007,6 +1011,31 @@ >; }; + camera_front: camera@20 { + compatible = "hynix,hi846"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-rates = <25000000>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + vdda-supply = <®_vcam_2v8>; + vddd-supply = <®_vcam_1v2>; + vddio-supply = <®_csi_1v8>; + rotation = <90>; + orientation = <0>; + + port { + camera1_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 + <80000000 200000000 300000000>; + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; + backlight@36 { compatible = "ti,lm36922"; reg = <0x36>; @@ -1080,6 +1109,23 @@ status = "okay"; }; +&mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + mipi1_sensor_ep: endpoint { + remote-endpoint = <&camera1_ep>; + data-lanes = <1 2>; + }; + }; + }; +}; + &mipi_dsi { #address-cells = <1>; #size-cells = <0>; From c190510714df168b9d6387bc29844acbe9a39521 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 4 Nov 2021 14:22:13 +0100 Subject: [PATCH 117/574] arm64: dts: imx8mq-librem5-r3.dtsi: describe selfie cam XSHUTDOWN pin The r3 and later revisions of the Librem 5 phone include an additional switch to control the hi846 XSHUTDOWN pin. Describe it. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi index e872eb4b1cf9..e4f8b47cce4f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi @@ -27,6 +27,19 @@ ti,termination-current = <144000>; /* uA */ }; +&camera_front { + pinctrl-0 = <&pinctrl_csi1>, <&pinctrl_r3_camera_pwr>; + shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; +}; + +&iomuxc { + pinctrl_r3_camera_pwr: r3camerapwrgrp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x83 + >; + }; +}; + &proximity { proximity-near-level = <25>; }; From f7e47d85f3f5913bcf508589c8dabbfbd3f4fe56 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 21 Nov 2021 12:50:02 +0100 Subject: [PATCH 118/574] arm64: dts: allwinner: h6: tanix-tx6: Add I2C node Tanix TX6 has a LED display driven by FD650. Currently there is no Linux driver nor any binding for it. However, we can at least provide I2C node in DT, so user space scripts or programs can manually control it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211121115002.693329-1-jernej.skrabec@gmail.com --- arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts index 6c10ff7f4b1c..7c37aa4c60cb 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts @@ -32,6 +32,14 @@ }; }; + /* used for FD650 LED display driver */ + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&pio 7 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH6 */ + scl-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH5 */ + i2c-gpio,delay-us = <5>; + }; + reg_vcc1v8: regulator-vcc1v8 { compatible = "regulator-fixed"; regulator-name = "vcc1v8"; From 725bc607aa02d570c35c5f21c3eadc3342bf4e06 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 21 Nov 2021 08:03:21 +0100 Subject: [PATCH 119/574] ARM: dts: sun8i: h3: beelink-x2: Sort nodes Nodes are not sorted alphabetically. Do it. There is no functional change. Signed-off-by: Jernej Skrabec Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211121070321.601659-1-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 28 +++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index f0e591e1c771..9dfd1a86b6c6 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -87,11 +87,15 @@ }; }; - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; + r-gpio-keys { + compatible = "gpio-keys"; + + power { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; }; sound_spdif { @@ -112,15 +116,11 @@ compatible = "linux,spdif-dit"; }; - r-gpio-keys { - compatible = "gpio-keys"; - - power { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; }; From 3047444def125d9e1fb788541e8dc18a7058a47a Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 20 Nov 2021 08:34:47 +0100 Subject: [PATCH 120/574] arm64: dts: allwinner: a64: Add CEC clock to HDMI Experimentation determined that HDMI CEC controller inside DW HDMI block depends on 32k clock from RTC. If this clock is tampered with, HDMI CEC communication starts or stops working, depending on situation. SoC user manual doesn't say anything about CEC, so this was overlooked. Fix this by adding dependency to RTC 32k clock. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211120073448.32480-2-jernej.skrabec@gmail.com --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 5ba379078500..741bd19fa8ec 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1220,8 +1220,8 @@ reg-io-width = <1>; interrupts = ; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; + <&ccu CLK_HDMI>, <&rtc 0>; + clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; From 38df5750962c61b96d4e53358f31955fe310d4f5 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 20 Nov 2021 08:34:48 +0100 Subject: [PATCH 121/574] ARM: dts: sunxi: Add CEC clock to DW-HDMI Experimentation determined that HDMI CEC controller inside DW HDMI block depends on 32k clock from RTC. If this clock is tampered with, HDMI CEC communication starts or stops working, depending on situation. SoC user manual doesn't say anything about CEC, so this was overlooked. Fix this by adding dependency to RTC 32k clock. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211120073448.32480-3-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-r40.dtsi | 4 ++-- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 1d87fc0c24ee..f10436b7869c 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -1212,8 +1212,8 @@ reg-io-width = <1>; interrupts = ; clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; + <&ccu CLK_HDMI>, <&rtc 0>; + clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index c7428df9469e..d1e974886fdf 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -813,8 +813,8 @@ reg-io-width = <1>; interrupts = ; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; + <&ccu CLK_HDMI>, <&rtc 0>; + clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; From bbdde16e5d7ebfd2e04bc41f800ebbd5468336b1 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 20 Nov 2021 11:20:24 +0100 Subject: [PATCH 122/574] ARM: dts: sun8i: h3: beelink-x2: Add GPIO CEC node Beelink X2 doesn't use HW CEC controller found in DW HDMI core. It has dedicated GPIO pin for that purpose. Add a node for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211120102024.439456-1-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index 9dfd1a86b6c6..cd9f655e4f92 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -57,6 +57,12 @@ ethernet1 = &sdiowifi; }; + cec-gpio { + compatible = "cec-gpio"; + cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */ + hdmi-phandle = <&hdmi>; + }; + chosen { stdout-path = "serial0:115200n8"; }; From 34734edd06f84290a3fc6f2a4ae61969e9d25801 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Nov 2021 15:32:55 +0100 Subject: [PATCH 123/574] dt-bindings: crypto: Add optional dma properties Some platforms, like the v3s, have DMA channels assigned to the crypto engine, which were in the DTSI but were never documented. Let's make sure they are. Signed-off-by: Maxime Ripard Acked-by: Corentin Labbe Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20211116143255.385480-1-maxime@cerno.tech --- .../bindings/crypto/allwinner,sun4i-a10-crypto.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml index 0429fb774f10..dedc99e34ebc 100644 --- a/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml +++ b/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml @@ -44,6 +44,16 @@ properties: - const: ahb - const: mod + dmas: + items: + - description: RX DMA Channel + - description: TX DMA Channel + + dma-names: + items: + - const: rx + - const: tx + resets: maxItems: 1 From 8e0150fe5cf5b86df55257d800258e57d7d34202 Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Mon, 15 Nov 2021 18:30:53 +0900 Subject: [PATCH 124/574] ARM: dts: milbeaut: add a clock node for M10V Add a clock node for the platform of the Milbeaut M10V. Signed-off-by: Sugaya Taichi Link: https://lore.kernel.org/r/1636968656-14033-2-git-send-email-sugaya.taichi@socionext.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/milbeaut-m10v.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi index aa7c6caeb750..28aee25d939e 100644 --- a/arch/arm/boot/dts/milbeaut-m10v.dtsi +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -65,6 +65,13 @@ <0x1d002000 0x1000>; /* CPU I/f base and size */ }; + clk: clock-ctrl@1d021000 { + compatible = "socionext,milbeaut-m10v-ccu"; + #clock-cells = <1>; + reg = <0x1d021000 0x1000>; + clocks = <&uclk40xi>; + }; + timer@1e000050 { /* 32-bit Reload Timers */ compatible = "socionext,milbeaut-timer"; reg = <0x1e000050 0x20>; From 2fc4dfc294eef022889e56ebcd4f0c6c6e34e3c5 Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Mon, 15 Nov 2021 18:30:54 +0900 Subject: [PATCH 125/574] ARM: dts: milbeaut: set clock phandle to timer node Set clock phandle to timer node for Milbeaut M10V support. Signed-off-by: Sugaya Taichi Link: https://lore.kernel.org/r/1636968656-14033-3-git-send-email-sugaya.taichi@socionext.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/milbeaut-m10v.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi index 28aee25d939e..9f70784bad0c 100644 --- a/arch/arm/boot/dts/milbeaut-m10v.dtsi +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -76,6 +76,7 @@ compatible = "socionext,milbeaut-timer"; reg = <0x1e000050 0x20>; interrupts = <0 91 4>; + clocks = <&clk 4>; }; uart1: serial@1e700010 { /* PE4, PE5 */ From 69a25d34f377b5602d188a05827f6173c26ff0de Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Mon, 15 Nov 2021 18:30:55 +0900 Subject: [PATCH 126/574] ARM: dts: milbeaut: set clock phandle to uart node Set clock phandle to uart node for Milbeaut M10V support. Signed-off-by: Sugaya Taichi Link: https://lore.kernel.org/r/1636968656-14033-4-git-send-email-sugaya.taichi@socionext.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/milbeaut-m10v.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi index 9f70784bad0c..75f0c0af2270 100644 --- a/arch/arm/boot/dts/milbeaut-m10v.dtsi +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -85,6 +85,7 @@ reg = <0x1e700010 0x10>; interrupts = <0 141 0x4>, <0 149 0x4>; interrupt-names = "rx", "tx"; + clocks = <&clk 2>; }; }; From cb551b5e3bab54265f374a394e239f5e492a5742 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Nov 2021 14:26:02 +0800 Subject: [PATCH 127/574] arm64: dts: imx8m: add cache info i.MX8M Family use A53 Cores and has 32KB ICache with 32KB DCache. - Icache is 2-way set associative - Dcache is 4-way set associative - L2cache is 16-way set associative - Line size are 64bytes Except i.MX8MQ has 1MB L2 Cache, others has 512KB L2 Cache. So add the cache info in device tree and let use could see that from /sys/devices/system/cpu/cpu[x]/cache/ Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 28 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 28 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 28 +++++++++++++++++++++++ 4 files changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c2f3f118f82e..5b9c2cca9ac4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -65,6 +65,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; nvmem-cells = <&cpu_speed_grade>; @@ -80,6 +86,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -93,6 +105,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -106,6 +124,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -114,6 +138,10 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index da6c942fb7f9..ba23b416b5e6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -63,6 +63,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; nvmem-cells = <&cpu_speed_grade>; @@ -78,6 +84,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -91,6 +103,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -104,6 +122,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -112,6 +136,10 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 04d259de5667..977783784342 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -51,6 +51,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; @@ -62,6 +68,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; @@ -73,6 +85,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; @@ -84,12 +102,22 @@ clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 972766b67a15..95d8b95d6120 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -102,6 +102,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -116,6 +122,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -128,6 +140,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -140,6 +158,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -147,6 +171,10 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; From b0b46118ed265592b935d7a39098c24f20c49620 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Nov 2021 14:26:03 +0800 Subject: [PATCH 128/574] arm64: dts: imx8qm: add cache info i.MX8QM A53 Cluster has 32KB Icache, 32KB Dcache and 1MB L2 Cache - Icache is 2-way set associative - Dcache is 4-way set associative - L2cache is 16-way set associative - Line size are 64bytes A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache - ICache is 3-way set-associative - Dcache is 2-way set-associative - L2Cache is 16-way set-associative - Line size are 64bytes Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index aebbe2b84aa1..4a7c017b5f31 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -57,6 +57,12 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; }; @@ -65,6 +71,12 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; }; @@ -73,6 +85,12 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; }; @@ -81,6 +99,12 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; }; @@ -89,6 +113,12 @@ compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&A72_L2>; }; @@ -102,10 +132,18 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; A72_L2: l2-cache1 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; From ebd922967f33be0ace3f53b2143f77c167c7e99d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Nov 2021 14:26:04 +0800 Subject: [PATCH 129/574] arm64: dts: imx8qxp: add cache info i.MX8QXP A35 Cluster has 32KB Icache, 32KB Dcache and 512KB L2 Cache - Icache is 2-way set associative - Dcache is 4-way set associative - L2cache is 8-way set associative - Line size are 64bytes Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 617618edf77e..dbec7c106e0b 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -58,6 +58,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -69,6 +75,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -80,6 +92,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x2>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -91,6 +109,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x3>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -99,6 +123,10 @@ A35_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; From 95f04048325cb808f4ca98f0a4d075bbb23576f8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 20 Jun 2021 00:42:59 +0200 Subject: [PATCH 130/574] ARM: dts: ux500: Add reset lines to IP blocks The new reset controller makes is possible to add reset lines to a host of IP blocks in the DB8500/U8500. Cc: Ulf Hansson Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 68607e4ad80c..dc0bcc7020f1 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -300,6 +301,10 @@ #clock-cells = <2>; }; + prcc_reset: prcc-reset-controller { + #reset-cells = <2>; + }; + rtc_clk: rtc32k-clock { #clock-cells = <0>; }; @@ -662,6 +667,7 @@ clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>; status = "disabled"; }; @@ -680,6 +686,7 @@ clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>; status = "disabled"; }; @@ -698,6 +705,7 @@ clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>; status = "disabled"; }; @@ -716,6 +724,7 @@ clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>; status = "disabled"; }; @@ -734,6 +743,7 @@ clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>; status = "disabled"; }; @@ -750,6 +760,7 @@ <&dma 8 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>; status = "disabled"; }; @@ -766,6 +777,7 @@ <&dma 9 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>; status = "disabled"; }; @@ -834,6 +846,7 @@ <&dma 40 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>; status = "disabled"; }; @@ -849,6 +862,7 @@ clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; clock-names = "uart", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>; status = "disabled"; }; @@ -864,6 +878,7 @@ clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; clock-names = "uart", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>; status = "disabled"; }; @@ -879,6 +894,7 @@ clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; clock-names = "uart", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>; status = "disabled"; }; @@ -895,6 +911,7 @@ clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>; status = "disabled"; }; @@ -911,6 +928,7 @@ clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>; status = "disabled"; }; @@ -927,6 +945,7 @@ clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>; status = "disabled"; }; @@ -943,6 +962,7 @@ clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>; status = "disabled"; }; @@ -959,6 +979,7 @@ clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>; status = "disabled"; }; @@ -975,6 +996,7 @@ clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>; status = "disabled"; }; @@ -996,6 +1018,7 @@ clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>; status = "disabled"; }; @@ -1012,6 +1035,7 @@ clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>; status = "disabled"; }; @@ -1030,6 +1054,7 @@ clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>; status = "disabled"; }; @@ -1046,6 +1071,7 @@ clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>; status = "disabled"; }; From 71b597ef5d46a326fb0d5cbfc1c6ff1d73cdc7f9 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:36 -0600 Subject: [PATCH 131/574] dt-bindings: clock: sunxi: Export CLK_DRAM for devfreq The MBUS node needs to reference the CLK_DRAM clock, as the MBUS hardware implements memory dynamic frequency scaling using this clock. Export this clock for SoCs which will be getting a devfreq driver. Acked-by: Rob Herring Reviewed-by: Chanwoo Choi Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-2-samuel@sholland.org --- drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 2 -- drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 2 -- include/dt-bindings/clock/sun50i-a64-ccu.h | 2 +- include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +- 4 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h index 54d1f96f4b68..a8c11c0b4e06 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h @@ -51,8 +51,6 @@ #define CLK_USB_OHCI1_12M 92 -#define CLK_DRAM 94 - /* All the DRAM gates are exported */ /* And the DSI and GPU module clock is exported */ diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h index d8c38447e11b..e13f3c4b57d0 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h @@ -42,8 +42,6 @@ /* The first bunch of module clocks are exported */ -#define CLK_DRAM 96 - /* All the DRAM gates are exported */ /* Some more module clocks are exported */ diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h index 318eb15c414c..175892189e9d 100644 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -113,7 +113,7 @@ #define CLK_USB_OHCI0 91 #define CLK_USB_OHCI1 93 - +#define CLK_DRAM 94 #define CLK_DRAM_VE 95 #define CLK_DRAM_CSI 96 #define CLK_DRAM_DEINTERLACE 97 diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h index 30d2d15373a2..5d4ada2c22e6 100644 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ b/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -126,7 +126,7 @@ #define CLK_USB_OHCI1 93 #define CLK_USB_OHCI2 94 #define CLK_USB_OHCI3 95 - +#define CLK_DRAM 96 #define CLK_DRAM_VE 97 #define CLK_DRAM_CSI 98 #define CLK_DRAM_DEINTERLACE 99 From 245578ba9f03e07132bcaf60cbdfeb0e89457104 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:37 -0600 Subject: [PATCH 132/574] dt-bindings: arm: sunxi: Expand MBUS binding The MBUS provides more than address translation and bandwidth control. It also provides a PMU to measure bandwidth usage by certain masters, and it provides notification via IRQ when they are active or idle. The MBUS is also tightly integrated with the DRAM controller to provide a Memory Dynamic Frequency Scaling (MDFS) feature. In view of this, the MBUS binding needs to represent the hardware resources needed for MDFS, which include the clocks and MMIO range of the adjacent DRAM controller. Add the additional resources for the H3 and A64 compatibles, and a new example showing how they are used. Reviewed-by: Chanwoo Choi Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-3-samuel@sholland.org --- .../arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 89 ++++++++++++++++++- 1 file changed, 86 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index 29c9961ee2d8..2b3829e0e240 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -34,10 +34,35 @@ properties: - allwinner,sun50i-a64-mbus reg: - maxItems: 1 + minItems: 1 + items: + - description: MBUS interconnect/bandwidth limit/PMU registers + - description: DRAM controller/PHY registers + + reg-names: + minItems: 1 + items: + - const: mbus + - const: dram clocks: + minItems: 1 + items: + - description: MBUS interconnect module clock + - description: DRAM controller/PHY module clock + - description: Register bus clock, shared by MBUS and DRAM + + clock-names: + minItems: 1 + items: + - const: mbus + - const: dram + - const: bus + + interrupts: maxItems: 1 + description: + MBUS PMU activity interrupt. dma-ranges: description: @@ -54,13 +79,54 @@ required: - clocks - dma-ranges +if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-h3-mbus + - allwinner,sun50i-a64-mbus + +then: + properties: + reg: + minItems: 2 + + reg-names: + minItems: 2 + + clocks: + minItems: 3 + + clock-names: + minItems: 3 + + required: + - reg-names + - clock-names + +else: + properties: + reg: + maxItems: 1 + + reg-names: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + additionalProperties: false examples: - | - #include + #include + #include - mbus: dram-controller@1c01000 { + dram-controller@1c01000 { compatible = "allwinner,sun5i-a13-mbus"; reg = <0x01c01000 0x1000>; clocks = <&ccu CLK_MBUS>; @@ -70,4 +136,21 @@ examples: #interconnect-cells = <1>; }; + - | + dram-controller@1c62000 { + compatible = "allwinner,sun50i-a64-mbus"; + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0xc0000000>; + #interconnect-cells = <1>; + }; + ... From 9f193dedd6efeb4e193d706856f26fcf11ae0ff2 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:38 -0600 Subject: [PATCH 133/574] dt-bindings: arm: sunxi: Add H5 MBUS compatible The H5 SoC has a MBUS very similar to the H3 SoC, but it has a smaller MDFS divider range (1-4 instead of 1-16). Add a separate compatible for this variant. Acked-by: Rob Herring Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-4-samuel@sholland.org --- .../devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index 2b3829e0e240..8eee312c2e6f 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -32,6 +32,7 @@ properties: - allwinner,sun8i-h3-mbus - allwinner,sun8i-r40-mbus - allwinner,sun50i-a64-mbus + - allwinner,sun50i-h5-mbus reg: minItems: 1 @@ -86,6 +87,7 @@ if: enum: - allwinner,sun8i-h3-mbus - allwinner,sun50i-a64-mbus + - allwinner,sun50i-h5-mbus then: properties: From c8f7b50785ca3a8b81f615da6e2f4e7b6380b20a Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:39 -0600 Subject: [PATCH 134/574] ARM: dts: sunxi: h3/h5: Update MBUS node In order to support memory dynamic frequency scaling (MDFS), the MBUS binding now requires enumerating more resources. Provide them in the device tree. Since the H3 and H5 have different clock divider limits, they need separate compatibles. Reviewed-by: Chanwoo Choi Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-5-samuel@sholland.org --- arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 11 ++++++++--- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ++++ 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index ae4f933abb89..845f25235407 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -282,6 +282,10 @@ compatible = "allwinner,sun8i-h3-de2-clk"; }; +&mbus { + compatible = "allwinner,sun8i-h3-mbus"; +}; + &mmc0 { compatible = "allwinner,sun7i-a20-mmc"; clocks = <&ccu CLK_BUS_MMC0>, diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index d1e974886fdf..4aeca9e7e30d 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -568,9 +568,14 @@ }; mbus: dram-controller@1c62000 { - compatible = "allwinner,sun8i-h3-mbus"; - reg = <0x01c62000 0x1000>; - clocks = <&ccu CLK_MBUS>; + /* compatible is in per SoC .dtsi file */ + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0xc0000000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index 9988e87ea7b3..a56fae761a1f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -233,6 +233,10 @@ compatible = "allwinner,sun50i-h5-de2-clk"; }; +&mbus { + compatible = "allwinner,sun50i-h5-mbus"; +}; + &mmc0 { compatible = "allwinner,sun50i-h5-mmc", "allwinner,sun50i-a64-mmc"; From 00b9773b128a509581555faef838b09468236d48 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:40 -0600 Subject: [PATCH 135/574] arm64: dts: allwinner: a64: Update MBUS node In order to support memory dynamic frequency scaling (MDFS), the MBUS binding now requires enumerating more resources. Provide them in the device tree. Reviewed-by: Chanwoo Choi Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-6-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 741bd19fa8ec..de77c87481fd 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1146,8 +1146,14 @@ mbus: dram-controller@1c62000 { compatible = "allwinner,sun50i-a64-mbus"; - reg = <0x01c62000 0x1000>; - clocks = <&ccu 112>; + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + interrupts = ; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0xc0000000>; From 1aa590c85ae4a66bd686146392708704828691a2 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Sat, 13 Nov 2021 11:21:56 +0800 Subject: [PATCH 136/574] ARM: dts: imx: Fix typo in pinfunc comments Remove the repeated `configurable' in some comments in imx1-pinfunc.h and imx27-pinfunc.h. Signed-off-by: Jason Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx1-pinfunc.h | 6 +++--- arch/arm/boot/dts/imx27-pinfunc.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx1-pinfunc.h b/arch/arm/boot/dts/imx1-pinfunc.h index 050a1fc46a77..bd2e679cb26c 100644 --- a/arch/arm/boot/dts/imx1-pinfunc.h +++ b/arch/arm/boot/dts/imx1-pinfunc.h @@ -26,9 +26,9 @@ * 2 - 0 * 3 - 1 * - * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable - * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin - * number on the specific port (between 0 and 31). + * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is + * the pin number on the specific port (between 0 and 31). */ #define MX1_PAD_A24__A24 0x00 0x004 diff --git a/arch/arm/boot/dts/imx27-pinfunc.h b/arch/arm/boot/dts/imx27-pinfunc.h index 1514d80a3112..75aea0c701d4 100644 --- a/arch/arm/boot/dts/imx27-pinfunc.h +++ b/arch/arm/boot/dts/imx27-pinfunc.h @@ -26,9 +26,9 @@ * 2 - 0 * 3 - 1 * - * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable - * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin - * number on the specific port (between 0 and 31). + * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is + * the pin number on the specific port (between 0 and 31). */ #define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000 From 11611eecb8aa1ab07f78e9bf0f2d8c40188e7826 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 23 Nov 2021 11:23:11 +0100 Subject: [PATCH 137/574] ARM: dts: ux500: Fixup Gavini magnetometer The Gavini device tree had the wrong magnetometer specified, this should be a YAS530. Signed-off-by: Linus Walleij --- .../arm/boot/dts/ste-ux500-samsung-gavini.dts | 39 +++++++++---------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts index 47bbf5ab267f..1c0e5cfeddac 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts @@ -232,19 +232,18 @@ #address-cells = <1>; #size-cells = <0>; - /* TODO: Memsic MMC328 magnetometer */ - magnetometer@30 { - compatible = "memsic,mmc328"; - reg = <0x30>; - /* TODO: if you have the schematic, check if both voltages come from AUX2 */ - /* VDA 1.8 V */ - vda-supply = <&ab8500_ldo_aux2_reg>; - /* VDD 1.8V */ - vdd-supply = <&ab8500_ldo_aux2_reg>; - /* GPIO204 */ + /* Yamaha YAS530 magnetometer */ + magnetometer@2e { + compatible = "yamaha,yas530"; + reg = <0x2e>; + /* VDD 3V */ + vdd-supply = <&ab8500_ldo_aux1_reg>; + /* IOVDD 1.8V */ + iovdd-supply = <&ab8500_ldo_aux2_reg>; + /* GPIO204 COMPASS_RST_N */ reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&mmc328_default>; + pinctrl-0 = <&yas530_default>; }; /* TODO: this should also be used by the NCP6914 Camera power management unit */ }; @@ -645,6 +644,15 @@ }; }; }; + /* Reset line for the Yamaha YAS530 magnetometer */ + yas530 { + yas530_default: yas530_janice { + janice_cfg1 { + pins = "GPIO204_AF23"; + ste,config = <&gpio_out_hi>; + }; + }; + }; /* Flash and torch */ flash { gpio_flash_default_mode: flash_default { @@ -747,15 +755,6 @@ }; }; }; - /* Reset line for the Memsic MMC328 magnetometer */ - mmc328 { - mmc328_default: mmc328_gavini { - gavini_cfg1 { - pins = "GPIO204_AF23"; - ste,config = <&gpio_out_hi>; - }; - }; - }; /* Interrupt line for Invensense MPU3050 gyroscope */ mpu3050 { mpu3050_default: mpu3050 { From 1a46061a2a4130a08841941ce6dcaa32be2ce312 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 23 Nov 2021 10:03:33 +0100 Subject: [PATCH 138/574] ARM: dts: BCM5301X: use non-deprecated USB 2.0 PHY binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The new binding covers a single reg and uses syscon to reference shared register. References: 55b9b741712d ("dt-bindings: phy: brcm,ns-usb2-phy: bind just a PHY block") Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index e1cffef4935a..588e57db6859 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -148,15 +148,6 @@ }; }; - usb2_phy: usb2-phy@1800c000 { - compatible = "brcm,ns-usb2-phy"; - reg = <0x1800c000 0x1000>; - reg-names = "dmu"; - #phy-cells = <0>; - clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; - clock-names = "phy-ref-clk"; - }; - axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; @@ -448,7 +439,16 @@ "sata1", "sata2"; }; - syscon@180 { + usb2_phy: phy@164 { + compatible = "brcm,ns-usb2-phy"; + reg = <0x164 0x4>; + brcm,syscon-clkset = <&cru_clkset>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + #phy-cells = <0>; + }; + + cru_clkset: syscon@180 { compatible = "brcm,cru-clkset", "syscon"; reg = <0x180 0x4>; }; From b046049e59dca5e5830dc75ed16acf7657a95161 Mon Sep 17 00:00:00 2001 From: Dillon Min Date: Sat, 24 Jul 2021 11:44:02 +0800 Subject: [PATCH 139/574] ARM: dts: stm32: fix dtbs_check warning on ili9341 dts binding on stm32f429 disco Since the compatible string defined from ilitek,ili9341.yaml is "st,sf-tc240t-9370-t", "ilitek,ili9341" so, append "ilitek,ili9341" to avoid the below dtbs_check warning. arch/arm/boot/dts/stm32f429-disco.dt.yaml: display@1: compatible: ['st,sf-tc240t-9370-t'] is too short Fixes: a726e2f000ec ("ARM: dts: stm32: enable ltdc binding with ili9341, gyro l3gd20 on stm32429-disco board") Signed-off-by: Dillon Min Reported-by: kernel test robot Reviewed-by: Linus Walleij Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429-disco.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 075ac57d0bf4..6435e099c632 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -192,7 +192,7 @@ display: display@1{ /* Connect panel-ilitek-9341 to ltdc */ - compatible = "st,sf-tc240t-9370-t"; + compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341"; reg = <1>; spi-3wire; spi-max-frequency = <10000000>; From 958b18a404152a982b511bc251768ca969a87630 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Wed, 20 Oct 2021 17:03:11 +0200 Subject: [PATCH 140/574] ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins on STM32MP15 DKx boards Add pull-up to USART3 and UART7 RX pins to allow loop tests between USART3 and UART7 on stm32mp15 DKx boards. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 2ebafe27a865..1c413a04ba9c 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1816,7 +1816,7 @@ }; pins2 { pinmux = ; /* UART7_RX */ - bias-disable; + bias-pull-up; }; }; @@ -1826,7 +1826,7 @@ }; pins2 { pinmux = ; /* UART7_RX */ - bias-disable; + bias-pull-up; }; }; @@ -1971,7 +1971,7 @@ pins2 { pinmux = , /* USART3_RX */ ; /* USART3_CTS_NSS */ - bias-disable; + bias-pull-up; }; }; @@ -1988,7 +1988,7 @@ }; pins3 { pinmux = ; /* USART3_RX */ - bias-disable; + bias-pull-up; }; }; @@ -2012,7 +2012,7 @@ pins2 { pinmux = , /* USART3_RX */ ; /* USART3_CTS_NSS */ - bias-disable; + bias-pull-up; }; }; @@ -2029,7 +2029,7 @@ }; pins3 { pinmux = ; /* USART3_RX */ - bias-disable; + bias-pull-up; }; }; From a2368f89660728284b749cc14537d7628e3fc318 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Wed, 20 Oct 2021 17:02:30 +0200 Subject: [PATCH 141/574] ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15 Clean useless spaces in uart4_idle_pins_a node. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 1c413a04ba9c..5f060feaf639 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1737,20 +1737,20 @@ }; uart4_idle_pins_a: uart4-idle-0 { - pins1 { - pinmux = ; /* UART4_TX */ - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; }; uart4_sleep_pins_a: uart4-sleep-0 { - pins { + pins { pinmux = , /* UART4_TX */ ; /* UART4_RX */ - }; + }; }; uart4_pins_b: uart4-1 { From 2312a6e7b301f43f02fb30b1dee932df5a87a7d0 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 25 Oct 2021 17:17:49 +0200 Subject: [PATCH 142/574] ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx This patch adds phy tuning parameters for usbphyc port0 (USBH controller) and usbphyc port1 (OTG controller). Phy tuning parameters are used to adjust the phy settings to compensate parasitics, which can be due to USB receptacle, routing, and ESD protection component. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 48beed0f1f30..6caeb448c190 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -694,10 +694,26 @@ &usbphyc_port0 { phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; }; &usbphyc_port1 { phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; }; &vrefbuf { From 28f645fc9424bf455528cb92bd6a7120281bca45 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 25 Oct 2021 17:17:50 +0200 Subject: [PATCH 143/574] ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1 This patch adds phy tuning parameters for usbphyc port0 (USBH controller) and usbphyc port1 (OTG controller). Phy tuning parameters are used to adjust the phy settings to compensate parasitics, which can be due to USB receptacle, routing, and ESD protection component. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 5c5b1ddf7bfd..e222d2d2cb44 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -375,3 +375,25 @@ &usbphyc { status = "okay"; }; + +&usbphyc_port0 { + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; From 7a0df1f969c14939f60a7f9a6af72adcc314675f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Nov 2021 14:31:55 +0800 Subject: [PATCH 144/574] arm64: dts: ti: k3-j721e: correct cache-sets info A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache - ICache is 3-way set-associative - Dcache is 2-way set-associative - Line size are 64bytes So correct the cache-sets info. Fixes: 2d87061e70dea ("arm64: dts: ti: Add Support for J721E SoC") Signed-off-by: Peng Fan Reviewed-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211112063155.3485777-1-peng.fan@oss.nxp.com --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 214359e7288b..a5967ba139d7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -64,7 +64,7 @@ i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; @@ -78,7 +78,7 @@ i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; }; From 217c7d1840b5377543eff84fe28409d0bd4d3433 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 22 Nov 2021 10:39:04 +0000 Subject: [PATCH 145/574] dt-bindings: mmc: renesas,sdhi: Rename RZ/G2L clocks Rename the below RZ/G2L clocks to match with the clock names used in R-Car Gen2 and later generations. imclk->core clk_hs->clkh imclk2->cd This changes will avoid using fallback for RZ/G2L high speed clock, if "clkh" is not used in device tree and also the code changes in driver related to this clocks. Signed-off-by: Biju Das Reviewed-by: Wolfram Sang Acked-by: Ulf Hansson Link: https://lore.kernel.org/r/20211122103905.14439-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/mmc/renesas,sdhi.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index f5107a641790..9ce6e06c19db 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -113,17 +113,17 @@ allOf: clocks: items: - description: IMCLK, SDHI channel main clock1. + - description: CLK_HS, SDHI channel High speed clock which operates + 4 times that of SDHI channel main clock1. - description: IMCLK2, SDHI channel main clock2. When this clock is turned off, external SD card detection cannot be detected. - - description: CLK_HS, SDHI channel High speed clock which operates - 4 times that of SDHI channel main clock1. - description: ACLK, SDHI channel bus clock. clock-names: items: - - const: imclk - - const: imclk2 - - const: clk_hs + - const: core + - const: clkh + - const: cd - const: aclk required: - clock-names From 5fcf8b0656cf842ae642298c2874ea6148d0129d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 12 Nov 2021 08:10:02 +0000 Subject: [PATCH 146/574] arm64: dts: renesas: r9a07g044: Sort psci node Sort psci node alphabetically. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211112081003.15453-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 2dd6eff471cb..a7818dbeb271 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -42,11 +42,6 @@ clock-frequency = <0>; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -85,6 +80,11 @@ }; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; From 59a7d68b69846ac012c33c1ac425b9388661d1f2 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 18 Nov 2021 19:18:24 +0000 Subject: [PATCH 147/574] arm64: dts: renesas: r9a07g044: Add OSTM nodes Add OSTM{0,1,2} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211118191826.2026-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index a7818dbeb271..be9e5c495553 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -791,6 +791,39 @@ power-domains = <&cpg>; status = "disabled"; }; + + ostm0: timer@12801000 { + compatible = "renesas,r9a07g044-ostm", + "renesas,ostm"; + reg = <0x0 0x12801000 0x0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>; + resets = <&cpg R9A07G044_OSTM0_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm1: timer@12801400 { + compatible = "renesas,r9a07g044-ostm", + "renesas,ostm"; + reg = <0x0 0x12801400 0x0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>; + resets = <&cpg R9A07G044_OSTM1_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm2: timer@12801800 { + compatible = "renesas,r9a07g044-ostm", + "renesas,ostm"; + reg = <0x0 0x12801800 0x0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>; + resets = <&cpg R9A07G044_OSTM2_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; }; timer { From 00d071e23c61b1be528227427da3f805feddef19 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 18 Nov 2021 19:18:25 +0000 Subject: [PATCH 148/574] arm64: dts: renesas: rzg2l-smarc-som: Enable OSTM Enable OSTM{1, 2} interfaces on RZ/G2L SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211118191826.2026-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 7e84a29dddfa..3bea97f16557 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -130,6 +130,14 @@ clock-frequency = <24000000>; }; +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + &pinctrl { adc_pins: adc { pinmux = ; /* ADC_TRG */ From c81bd70f47cef36f88074d119e6e49cf92707fdb Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 21 Nov 2021 23:49:06 +0000 Subject: [PATCH 149/574] arm64: dts: renesas: rzg2l-smarc-som: Enable serial NOR flash Enable mt25qu512a flash connected to QSPI0. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211121234906.9602-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 3bea97f16557..28af63324422 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -186,6 +186,18 @@ line-name = "gpio_sd0_pwr_en"; }; + qspi0_pins: qspi0 { + qspi0-data { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; + power-source = <1800>; + }; + + qspi0-ctrl { + pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; + power-source = <1800>; + }; + }; + /* * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] * The below switch logic can be used to select the device between @@ -251,6 +263,34 @@ }; }; +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,mt25qu512a", "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x00000000 0x2000000>; + read-only; + }; + user@2000000 { + reg = <0x2000000 0x2000000>; + }; + }; + }; +}; + #if SDHI &sdhi0 { pinctrl-0 = <&sdhi0_pins>; From fee3eae1334a454a8c2e16313a374cc53ff722d8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 22 Nov 2021 10:39:05 +0000 Subject: [PATCH 150/574] arm64: dts: renesas: r9a07g044: Rename SDHI clocks Rename the below SDHI clocks to match with the clocks used in driver. imclk->core clk_hs->clkh imclk2->cd Also re-arrange the clocks to match with the sorting order used in the binding document. Signed-off-by: Biju Das Acked-by: Ulf Hansson Link: https://lore.kernel.org/r/20211122103905.14439-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index be9e5c495553..71f1701a1b66 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -613,10 +613,10 @@ interrupts = , ; clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>, - <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; - clock-names = "imclk", "imclk2", "clk_hs", "aclk"; + clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G044_SDHI0_IXRST>; power-domains = <&cpg>; status = "disabled"; @@ -629,10 +629,10 @@ interrupts = , ; clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>, - <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; - clock-names = "imclk", "imclk2", "clk_hs", "aclk"; + clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G044_SDHI1_IXRST>; power-domains = <&cpg>; status = "disabled"; From eb7621ce3362639025e7db125559e235a76d814f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 23 Nov 2021 14:14:19 +0000 Subject: [PATCH 151/574] arm64: dts: renesas: r9a07g044: Add WDT nodes Add WDT{0, 1, 2} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211123141420.23529-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 71f1701a1b66..82d9c620a4de 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -792,6 +792,51 @@ status = "disabled"; }; + wdt0: watchdog@12800800 { + compatible = "renesas,r9a07g044-wdt", + "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>, + <&cpg CPG_MOD R9A07G044_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G044_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt1: watchdog@12800c00 { + compatible = "renesas,r9a07g044-wdt", + "renesas,rzg2l-wdt"; + reg = <0 0x12800C00 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>, + <&cpg CPG_MOD R9A07G044_WDT1_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G044_WDT1_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@12800400 { + compatible = "renesas,r9a07g044-wdt", + "renesas,rzg2l-wdt"; + reg = <0 0x12800400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>, + <&cpg CPG_MOD R9A07G044_WDT2_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G044_WDT2_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + ostm0: timer@12801000 { compatible = "renesas,r9a07g044-ostm", "renesas,ostm"; From 44c2d2c2d25e87741b84aaa9e0dad396abdd148d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 23 Nov 2021 14:14:20 +0000 Subject: [PATCH 152/574] arm64: dts: renesas: rzg2l-smarc-som: Enable watchdog Enable watchdog{0, 1, 2} interfaces on RZ/G2L SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211123141420.23529-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 28af63324422..41fdae7ba66b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -321,3 +321,18 @@ status = "okay"; }; #endif + +&wdt0 { + status = "okay"; + timeout-sec = <60>; +}; + +&wdt1 { + status = "okay"; + timeout-sec = <60>; +}; + +&wdt2 { + status = "okay"; + timeout-sec = <60>; +}; From 7744b393c95ac470a3ac279fa277e50d947f1bea Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 24 Nov 2021 15:39:40 +0100 Subject: [PATCH 153/574] arm64: dts: renesas: Fix operating point table node names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align the node names of device nodes representing operating point v2 tables with the expectations of the DT bindings in Documentation/devicetree/bindings/opp/opp-v2.yaml. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/ac885456ffb00fa4cc4069b9967761df2c98c3d8.1637764588.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +- 9 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index f9c4ae6f26a9..09976adf99c2 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -58,7 +58,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -80,7 +80,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 0c175b8c2088..c504f5028380 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -47,7 +47,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 5e16f6b1771e..b8dcbbbf3db5 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -44,7 +44,7 @@ clock-frequency = <0>; }; - cluster1_opp: opp_table10 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; opp-800000000 { diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 673fcc631972..e4dd6ccc8b10 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -47,7 +47,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -69,7 +69,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 391ffe6ca03e..2353d3034bb5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -62,7 +62,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -96,7 +96,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index b1a6cf76633d..0f2424f12546 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -57,7 +57,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -97,7 +97,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 1c1da6d7be49..7468a2df1808 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -46,7 +46,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -86,7 +86,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 3a357d958d4a..0c44de866996 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -62,7 +62,7 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 8698058f25f3..14caedd0c959 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -55,7 +55,7 @@ clock-frequency = <0>; }; - cluster1_opp: opp_table10 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; opp-800000000 { From 36959e2108b6e3d66a3a6a1526e8e45f8abad14c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 24 Nov 2021 15:43:16 +0000 Subject: [PATCH 154/574] arm64: dts: renesas: r9a07g044: Add OPP table Add OPP table for RZ/G2L SoC. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211124154316.28365-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 82d9c620a4de..439870930fb3 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -42,6 +42,33 @@ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -63,6 +90,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -71,6 +100,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { From 9fd8bbefc31286e702e8cc9fe8766301f02fd4be Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 24 Nov 2021 15:28:14 +0000 Subject: [PATCH 155/574] arm64: dts: renesas: ulcb: Merge hdmi0_con The remote endpoint for the hdmi connector is specfied through a reference to the hdmi0_con endpoint, which is in the same file. Simplify by specifying the remote-endpoint directly in the hdmi0_con endpoint. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20211124152815.3926961-2-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 7edffe7f8cfa..a7e93df4ced8 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -48,6 +48,7 @@ port { hdmi0_con: endpoint { + remote-endpoint = <&rcar_dw_hdmi0_out>; }; }; }; @@ -199,10 +200,6 @@ }; }; -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; From bd4fa23731a5786a8aa711945a5b76aa62b86117 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 24 Nov 2021 15:28:15 +0000 Subject: [PATCH 156/574] arm64: dts: renesas: salvator-common: Merge hdmi0_con The remote endpoint for the hdmi connector is specfied through a reference to the hdmi0_con endpoint, which is in the same file. Simplify by specifying the remote-endpoint directly in the hdmi0_con endpoint. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20211124152815.3926961-3-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index bf37777dca31..6092dc4531ad 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -97,6 +97,7 @@ port { hdmi0_con: endpoint { + remote-endpoint = <&rcar_dw_hdmi0_out>; }; }; }; @@ -424,10 +425,6 @@ }; }; -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - #ifdef SOC_HAS_HDMI1 &hdmi1 { status = "okay"; From cdda01947bbae8f1b1d19f8aac1f81ae5ce6f37e Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Fri, 26 Nov 2021 09:54:42 +0000 Subject: [PATCH 157/574] arm64: dts: renesas: r8a779a0: Add DU support Provide the device nodes for the DU on the V3U platforms. Reviewed-by: Laurent Pinchart Signed-off-by: Kieran Bingham Link: https://lore.kernel.org/r/20211126095445.932930-2-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 940e4990379d..6e83bcb0287c 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2269,6 +2269,38 @@ }; }; + du: display@feb00000 { + compatible = "renesas,du-r8a779a0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du.0"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 411>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>, <&vspd1 0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + }; + }; + + port@1 { + reg = <1>; + du_out_dsi1: endpoint { + }; + }; + }; + }; + isp0: isp@fed00000 { compatible = "renesas,r8a779a0-isp"; reg = <0 0xfed00000 0 0x10000>; From 1149ccc5e89145a344cfdd8832d83bcc919dc1ed Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 26 Nov 2021 12:33:40 +0100 Subject: [PATCH 158/574] ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk A pinctrl handle is used to setup a pull-up on the stusb1600 IRQ pin (that is open drain). When in ANALOG state, no pull-up can be applied in the GPIO HW controller, still the setting is done into the register. The pull-up is effective currently, only when the GPIO IRQ is requested. The correct setting is to use directly the GPIO, instead of ANALOG state. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 5f060feaf639..3b65130affec 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1718,7 +1718,7 @@ stusb1600_pins_a: stusb1600-0 { pins { - pinmux = ; + pinmux = ; bias-pull-up; }; }; From f4c35356e0fce4bbe2994185cc014f13630a1a1d Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 30 Nov 2021 14:10:44 -0600 Subject: [PATCH 159/574] arm64: dts: n5x: add qspi, usb, and ethernet support Populate the N5X board dts file with support for QSPI, USB, and ethernet. Signed-off-by: Dinh Nguyen --- .../boot/dts/intel/socfpga_n5x_socdk.dts | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 01f1307ce4ac..f3c1310dae0a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -29,6 +29,36 @@ compatible = "intel,easic-n5x-clkmgr"; }; +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + &mmc { status = "okay"; cap-sd-highspeed; @@ -40,10 +70,51 @@ clock-frequency = <25000000>; }; +&qspi { + status = "okay"; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x03FE0000>; + }; + + qspi_rootfs: partition@3FE0000 { + label = "Root Filesystem - JFFS2"; + reg = <0x03FE0000 0x0C020000>; + }; + }; + }; +}; + &uart0 { status = "okay"; }; +&usb0 { + status = "okay"; + disable-over-current; +}; + &watchdog0 { status = "okay"; }; From 8e0e8016cb797c38eea8641e8b77a5780c4614ac Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Wed, 10 Nov 2021 16:53:30 -0500 Subject: [PATCH 160/574] arm64: dts: qcom: sm8250: Add CPU opp tables Add OPP tables to scale DDR and L3 with CPUs for SM8250 SoCs. Signed-off-by: Thara Gopinath Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211110215330.74257-1-thara.gopinath@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 314 +++++++++++++++++++++++++++ 1 file changed, 314 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index c46c35a74601..40f18d539d80 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -99,6 +99,9 @@ dynamic-power-coefficient = <205>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; @@ -118,6 +121,9 @@ dynamic-power-coefficient = <205>; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; @@ -134,6 +140,9 @@ dynamic-power-coefficient = <205>; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; @@ -150,6 +159,9 @@ dynamic-power-coefficient = <205>; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; @@ -166,6 +178,9 @@ dynamic-power-coefficient = <379>; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; @@ -182,6 +197,9 @@ dynamic-power-coefficient = <379>; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; @@ -199,6 +217,9 @@ dynamic-power-coefficient = <379>; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; @@ -215,6 +236,9 @@ dynamic-power-coefficient = <444>; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; + operating-points-v2 = <&cpu7_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; @@ -259,6 +283,296 @@ }; }; + cpu0_opp_table: cpu0_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <800000 9600000>; + }; + + cpu0_opp2: opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + opp-peak-kBps = <800000 9600000>; + }; + + cpu0_opp3: opp-518400000 { + opp-hz = /bits/ 64 <518400000>; + opp-peak-kBps = <800000 16588800>; + }; + + cpu0_opp4: opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-peak-kBps = <800000 16588800>; + }; + + cpu0_opp5: opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <800000 19660800>; + }; + + cpu0_opp6: opp-787200000 { + opp-hz = /bits/ 64 <787200000>; + opp-peak-kBps = <1804000 19660800>; + }; + + cpu0_opp7: opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-peak-kBps = <1804000 23347200>; + }; + + cpu0_opp8: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <1804000 26419200>; + }; + + cpu0_opp9: opp-1075200000 { + opp-hz = /bits/ 64 <1075200000>; + opp-peak-kBps = <1804000 29491200>; + }; + + cpu0_opp10: opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <1804000 32563200>; + }; + + cpu0_opp11: opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <1804000 36249600>; + }; + + cpu0_opp12: opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <2188000 36249600>; + }; + + cpu0_opp13: opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + opp-peak-kBps = <2188000 39321600>; + }; + + cpu0_opp14: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <3072000 42393600>; + }; + + cpu0_opp15: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <3072000 42393600>; + }; + + cpu0_opp16: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <4068000 42393600>; + }; + + cpu0_opp17: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <4068000 42393600>; + }; + }; + + cpu4_opp_table: cpu4_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu4_opp1: opp-710400000 { + opp-hz = /bits/ 64 <710400000>; + opp-peak-kBps = <1804000 19660800>; + }; + + cpu4_opp2: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <2188000 23347200>; + }; + + cpu4_opp3: opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <2188000 26419200>; + }; + + cpu4_opp4: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <3072000 26419200>; + }; + + cpu4_opp5: opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <3072000 29491200>; + }; + + cpu4_opp6: opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <4068000 29491200>; + }; + + cpu4_opp7: opp-1382400000 { + opp-hz = /bits/ 64 <1382400000>; + opp-peak-kBps = <4068000 32563200>; + }; + + cpu4_opp8: opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-peak-kBps = <4068000 32563200>; + }; + + cpu4_opp9: opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <5412000 39321600>; + }; + + cpu4_opp10: opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <5412000 42393600>; + }; + + cpu4_opp11: opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <5412000 45465600>; + }; + + cpu4_opp12: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6220000 45465600>; + }; + + cpu4_opp13: opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <6220000 48537600>; + }; + + cpu4_opp14: opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <7216000 48537600>; + }; + + cpu4_opp15: opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; + opp-peak-kBps = <7216000 51609600>; + }; + + cpu4_opp16: opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <7216000 51609600>; + }; + + cpu4_opp17: opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu4_opp18: opp-2419200000 { + opp-hz = /bits/ 64 <2419200000>; + opp-peak-kBps = <8368000 51609600>; + }; + }; + + cpu7_opp_table: cpu7_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu7_opp1: opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <2188000 19660800>; + }; + + cpu7_opp2: opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-peak-kBps = <2188000 26419200>; + }; + + cpu7_opp3: opp-1075200000 { + opp-hz = /bits/ 64 <1075200000>; + opp-peak-kBps = <3072000 26419200>; + }; + + cpu7_opp4: opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <3072000 29491200>; + }; + + cpu7_opp5: opp-1305600000 { + opp-hz = /bits/ 64 <1305600000>; + opp-peak-kBps = <4068000 32563200>; + }; + + cpu7_opp6: opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <4068000 32563200>; + }; + + cpu7_opp7: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <4068000 36249600>; + }; + + cpu7_opp8: opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <5412000 39321600>; + }; + + cpu7_opp9: opp-1747200000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <5412000 42393600>; + }; + + cpu7_opp10: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6220000 45465600>; + }; + + cpu7_opp11: opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-peak-kBps = <6220000 48537600>; + }; + + cpu7_opp12: opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <7216000 48537600>; + }; + + cpu7_opp13: opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + opp-peak-kBps = <7216000 51609600>; + }; + + cpu7_opp14: opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + opp-peak-kBps = <7216000 51609600>; + }; + + cpu7_opp15: opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp16: opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp17: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp18: opp-2649600000 { + opp-hz = /bits/ 64 <2649600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp19: opp-2745600000 { + opp-hz = /bits/ 64 <2745600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp20: opp-2841600000 { + opp-hz = /bits/ 64 <2841600000>; + opp-peak-kBps = <8368000 51609600>; + }; + }; + firmware { scm: scm { compatible = "qcom,scm"; From 1c0ac047bbfb3efd6549d18c3ca47aa0afedcfbe Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 19 Nov 2021 22:39:53 +0100 Subject: [PATCH 161/574] arm64: dts: qcom: msm8916: Add RPM sleep stats MSM8916 is similar to the other SoCs that had the RPM stats node added in commit 290bc6846547 ("arm64: dts: qcom: Enable RPM Sleep stats"). However, the dynamic offset readable at 0x14 seems only available on some of the newer firmware versions. To be absolutely sure, make use of the new qcom,msm8916-rpm-stats compatible that reads the sleep stats from a fixed offset of 0xdba0. Statistics are available for a "vmin" and "xosd" low power mode: $ cat /sys/kernel/debug/qcom_stats/vmin Count: 0 Last Entered At: 0 Last Exited At: 0 Accumulated Duration: 0 Client Votes: 0x0 $ cat /sys/kernel/debug/qcom_stats/xosd Count: 0 Last Entered At: 0 Last Exited At: 0 Accumulated Duration: 0 Client Votes: 0x0 Cc: Maulik Shah Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211119213953.31970-4-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c1c42f26b61e..9044eb41a81d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -453,6 +453,11 @@ reg = <0x00060000 0x8000>; }; + sram@290000 { + compatible = "qcom,msm8916-rpm-stats"; + reg = <0x00290000 0x10000>; + }; + bimc: interconnect@400000 { compatible = "qcom,msm8916-bimc"; reg = <0x00400000 0x62000>; From 6867430332655cfb0880e0e7576ea4eb786d50fc Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Mon, 22 Nov 2021 00:04:49 +0700 Subject: [PATCH 162/574] arm64: dts: qcom: sdm660-xiaomi-lavender: Add volume up button This enables the volume up key. Signed-off-by: Dang Huynh Tested-by: Alexey Minnekhanov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211121170449.1124048-1-danct12@riseup.net --- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index d042e3883b9e..dcbaacf18f66 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -9,6 +9,8 @@ #include "sdm660.dtsi" #include "pm660.dtsi" #include "pm660l.dtsi" +#include +#include / { model = "Xiaomi Redmi Note 7"; @@ -46,6 +48,17 @@ regulator-boot-on; }; + gpio-keys { + compatible = "gpio-keys"; + + volup { + label = "Volume Up"; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; From 254a27585eb135f35887579ebc7d0e02b9788b92 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:15 +0530 Subject: [PATCH 163/574] ARM: dts: qcom: sdx55: Add support for PCIe PHY Add devicetree support for PCIe PHY used in SDX55 platform. This PHY is used by the PCIe EP controller. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-2-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 35 +++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 44526ad9d210..16995782dfdf 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -309,6 +309,41 @@ status = "disabled"; }; + pcie0_phy: phy@1c07000 { + compatible = "qcom,sdx55-qmp-pcie-phy"; + reg = <0x01c07000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06000 { + reg = <0x01c06000 0x104>, /* tx0 */ + <0x01c06200 0x328>, /* rx0 */ + <0x01c07200 0x1e8>, /* pcs */ + <0x01c06800 0x104>, /* tx1 */ + <0x01c06a00 0x328>, /* rx1 */ + <0x01c07600 0x800>; /* pcs_misc */ + clocks = <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + }; + }; + ipa: ipa@1e40000 { compatible = "qcom,sdx55-ipa"; From a5a2661287b450f2b1f751ae7b4da4f39976571b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:16 +0530 Subject: [PATCH 164/574] ARM: dts: qcom: sdx55-fn980: Enable PCIE0 PHY Enable PCIE0 PHY on Telit FN980 TLB for PCIE EP. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-3-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index 80c40da79604..e8b5327afbe7 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -236,6 +236,13 @@ status = "ok"; }; +&pcie0_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1e_bb_1p2>; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; +}; + &qpic_bam { status = "ok"; }; From e6b69813283f9babc6892c1324d2c3bd2a577d9c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:17 +0530 Subject: [PATCH 165/574] ARM: dts: qcom: sdx55: Add support for PCIe EP Add support for PCIe Endpoint controller on the Qualcomm SDX55 platform. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-4-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 45 +++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 16995782dfdf..5d769b3f2d35 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -391,6 +392,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fcb000 { + compatible = "syscon"; + reg = <0x01fc0000 0x1000>; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; @@ -403,6 +409,45 @@ status = "disabled"; }; + pcie_ep: pcie-ep@40000000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40002000 0x10000>, + <0x01c03000 0x3000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie0_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; From 7cecfb53cad8e9f564fdf11e56502c7d8607b3a3 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:18 +0530 Subject: [PATCH 166/574] ARM: dts: qcom: sdx55-fn980: Enable PCIe EP Enable PCIe Endpoint controller on the Telit FN980 TLB board based on Qualcomm SDX55 platform. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-5-manivannan.sadhasivam@linaro.org --- .../boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index e8b5327afbe7..01ac91738f34 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -243,6 +243,14 @@ vdda-pll-supply = <&vreg_l4e_bb_0p875>; }; +&pcie_ep { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; +}; + &qpic_bam { status = "ok"; }; @@ -267,6 +275,44 @@ memory-region = <&mpss_adsp_mem>; }; +&tlmm { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + config { + pins = "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; +}; + &usb_hsphy { status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; From e1fb17ee85bc85808eeb103afa63581d065c7328 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:19 +0530 Subject: [PATCH 167/574] ARM: dts: qcom: sdx55-fn980: Enable IPA Enable IP Accelerator (IPA) on Telit FN980 TLB for getting data connectivity from modem. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-6-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index 01ac91738f34..a4fa468a095f 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -236,6 +236,12 @@ status = "ok"; }; +&ipa { + status = "okay"; + + memory-region = <&ipa_fw_mem>; +}; + &pcie0_phy { status = "okay"; From 1f7fe79d03b2ac0991c8a229ca50a9f45b71df80 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:20 +0530 Subject: [PATCH 168/574] ARM: dts: qcom: sdx55-t55: Enable IPA Enable IP Accelerator (IPA) on Thundercomm T55 board for getting data connectivity from modem. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-7-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index 2ffcd085904d..7ed8feb99afb 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -236,6 +236,12 @@ status = "ok"; }; +&ipa { + status = "okay"; + + memory-region = <&ipa_fw_mem>; +}; + &qpic_bam { status = "ok"; }; From 95dcb997772e966919987b6dd96eb9a6212402eb Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Tue, 23 Nov 2021 23:24:37 +0700 Subject: [PATCH 169/574] arm64: dts: qcom: Drop input-name property This property doesn't seem to exist in the documentation nor in source code, but for some reason it is defined in a bunch of device trees. Signed-off-by: Dang Huynh Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211123162436.1507341-1-danct12@riseup.net --- arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 1 - arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 3 --- arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 2 -- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 1 - arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 1 - 7 files changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index 69fcb6b0398d..84558ab5fe86 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -42,7 +42,6 @@ gpio_keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 3a3790a52a2c..cc038f9b641f 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -62,7 +62,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; autorepeat; volupkey { diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 7cc564d8ca7c..dde7ed159c4d 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -29,7 +29,6 @@ gpio_keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 3d495ce3f46a..dc5b9b274df3 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -29,7 +29,6 @@ gpio-hall-sensors { compatible = "gpio-keys"; - input-name = "hall-sensors"; label = "Hall sensors"; pinctrl-names = "default"; pinctrl-0 = <&hall_sensor1_default>; @@ -46,7 +45,6 @@ gpio-kb-extra-keys { compatible = "gpio-keys"; - input-name = "extra-kb-keys"; label = "Keyboard extra keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_kb_pins_extra>; @@ -102,7 +100,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "side-buttons"; label = "Side buttons"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 91e391282181..47488a1aecae 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -93,7 +93,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; label = "Side buttons"; pinctrl-names = "default"; pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>, @@ -126,7 +125,6 @@ gpio-hall-sensor { compatible = "gpio-keys"; - input-name = "hall-sensors"; label = "Hall sensors"; pinctrl-names = "default"; pinctrl-0 = <&hall_sensor0_default>; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index e90c9ec84675..42af1fade461 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -90,7 +90,6 @@ gpio_keys { status = "okay"; compatible = "gpio-keys"; - input-name = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 45eab0235d66..871ccbba445b 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -42,7 +42,6 @@ gpio-keys { status = "okay"; compatible = "gpio-keys"; - input-name = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; From 7a21328bb3ade238e35c4de81da3ad8d76437b72 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 29 Nov 2021 17:01:34 +0530 Subject: [PATCH 170/574] dt-bindings: arm: qcom: Document qcom,sc7280-crd board Document the qcom,sc7280-crd board based off sc7280 SoC, The board is also known as hoglin in the Chrome OS builds, so document the google,hoglin compatible as well. Signed-off-by: Rajendra Nayak Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1638185497-26477-2-git-send-email-quic_rjendra@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c8808e0f9e64..41e1d781e43f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -201,8 +201,10 @@ properties: - items: - enum: + - qcom,sc7280-crd - qcom,sc7280-idp - qcom,sc7280-idp2 + - google,hoglin - google,piglin - google,senor - const: qcom,sc7280 From 427b249504ea48e9af2014df4b22fe8b31ddb563 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 29 Nov 2021 17:01:35 +0530 Subject: [PATCH 171/574] arm64: dts: qcom: sc7280-crd: Add device tree files for CRD CRD (Compute Reference Design) is a sc7280 based board, largely derived from the existing IDP board design with some key deltas 1. has EC and H1 over SPI similar to IDP2 2. touchscreen and trackpad support 3. eDP display We just add the barebones dts file here, subsequent patches will add support for EC/H1 and other components. Signed-off-by: Rajendra Nayak Reviewed-by: Matthias Kaehlcke Tested-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1638185497-26477-3-git-send-email-quic_rjendra@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7280-crd.dts | 31 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-crd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 50572419dca9..7f26ec20d238 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts new file mode 100644 index 000000000000..2da6603c38dc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 CRD board device tree source + * + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "sc7280-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sc7280 CRD platform"; + compatible = "qcom,sc7280-crd", "google,hoglin", "qcom,sc7280"; + + aliases { + serial0 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&nvme_3v3_regulator { + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; +}; + +&nvme_pwren { + pins = "gpio51"; +}; From 248da168fbae5ab7294a37428256acc570ed552a Mon Sep 17 00:00:00 2001 From: Kshitiz Godara Date: Mon, 29 Nov 2021 17:01:36 +0530 Subject: [PATCH 172/574] arm64: dts: qcom: sc7280: Define EC and H1 nodes for IDP/CRD The IDP2 and CRD boards share the EC and H1 parts, so define all related device nodes into a common file and include them in the idp2 and crd dts files to avoid duplication. Signed-off-by: Kshitiz Godara Signed-off-by: Rajendra Nayak Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1638185497-26477-4-git-send-email-quic_rjendra@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-crd.dts | 1 + .../arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 105 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 1 + 3 files changed, 107 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts index 2da6603c38dc..1e3e2f360b6e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280-idp.dtsi" +#include "sc7280-idp-ec-h1.dtsi" / { model = "Qualcomm Technologies, Inc. sc7280 CRD platform"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi new file mode 100644 index 000000000000..0896a6151817 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 EC/H1 over SPI (common between IDP2 and CRD) + * + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +ap_ec_spi: &spi10 { + status = "okay"; + + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>; + cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ap_ec_int_l>; + spi-max-frequency = <3000000>; + + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "left"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "right"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; +}; + +#include +#include + +ap_h1_spi: &spi14 { + status = "okay"; + + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs_gpio_init_high>, <&qup_spi14_cs_gpio>; + cs-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>; + + cr50: tpm@0 { + compatible = "google,cr50"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&h1_ap_int_odl>; + spi-max-frequency = <800000>; + interrupt-parent = <&tlmm>; + interrupts = <104 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&tlmm { + ap_ec_int_l: ap-ec-int-l { + pins = "gpio18"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + h1_ap_int_odl: h1-ap-int-odl { + pins = "gpio104"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high { + pins = "gpio43"; + output-high; + }; + + qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high { + pins = "gpio59"; + output-high; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts index 3ae99697d893..0382c770650a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280-idp.dtsi" +#include "sc7280-idp-ec-h1.dtsi" / { model = "Qualcomm Technologies, Inc. sc7280 IDP SKU2 platform"; From 3ebf11fa4a355116eb2a69a46114ec92f245dbcc Mon Sep 17 00:00:00 2001 From: Kshitiz Godara Date: Mon, 29 Nov 2021 17:01:37 +0530 Subject: [PATCH 173/574] arm64: dts: qcom: sc7280-crd: Add Touchscreen and touchpad support Add Touchscreen and touchpad hid-over-i2c node for the sc7280 CRD board Signed-off-by: Kshitiz Godara Signed-off-by: Rajendra Nayak Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1638185497-26477-5-git-send-email-quic_rjendra@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-crd.dts | 61 +++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts index 1e3e2f360b6e..cd2755ce530d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts @@ -23,6 +23,47 @@ }; }; +ap_tp_i2c: &i2c0 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + vdd-supply = <&vreg_l18b_1p8>; + + wakeup-source; + }; +}; + +ap_ts_pen_1v8: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@5c { + compatible = "hid-over-i2c"; + reg = <0x5c>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <500>; + hid-descr-addr = <0x0000>; + + vdd-supply = <&vreg_l19b_1p8>; + }; +}; + &nvme_3v3_regulator { gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; }; @@ -30,3 +71,23 @@ &nvme_pwren { pins = "gpio51"; }; + +&tlmm { + tp_int_odl: tp-int-odl { + pins = "gpio7"; + function = "gpio"; + bias-disable; + }; + + ts_int_l: ts-int-l { + pins = "gpio55"; + function = "gpio"; + bias-pull-up; + }; + + ts_reset_l: ts-reset-l { + pins = "gpio54"; + function = "gpio"; + bias-disable; + }; +}; From d0bfc92303dde7f13fac1873c25a3bee913bfef3 Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Tue, 30 Nov 2021 22:23:31 +0100 Subject: [PATCH 174/574] arm64: dts: qcom: sm6125: Add RPMPD node Add RPM Power Distribution node for sm6125 SoC. Signed-off-by: Martin Botka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211130212332.25401-3-martin.botka@somainline.org --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 50 ++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 51286ddbdb10..a501e8788c51 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -302,6 +302,56 @@ compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; #clock-cells = <1>; }; + + rpmpd: power-controller { + compatible = "qcom,sm6125-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level = ; + }; + }; + }; }; }; From 556a9f3ae17ef19deecac130fea38f258d5abeb2 Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Tue, 30 Nov 2021 22:23:32 +0100 Subject: [PATCH 175/574] arm64: dts: qcom: sm6125: Add power domains to sdhc Add RPM Power Domains to internal eMMC and SDCard. Signed-off-by: Martin Botka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211130212332.25401-4-martin.botka@somainline.org --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index a501e8788c51..e81b2a7794fb 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -448,6 +448,9 @@ <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + + power-domains = <&rpmpd SM6125_VDDCX>; + bus-width = <8>; non-removable; status = "disabled"; @@ -471,6 +474,8 @@ pinctrl-1 = <&sdc2_state_off>; pinctrl-names = "default", "sleep"; + power-domains = <&rpmpd SM6125_VDDCX>; + bus-width = <4>; status = "disabled"; }; From b0293c19d42f6d6951c2fab9a47fed50baf2c14d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 Dec 2021 05:05:59 +0300 Subject: [PATCH 176/574] arm64: dts: qcom: msm8916: fix MMC controller aliases Change sdhcN aliases to mmcN to make them actually work. Currently the board uses non-standard aliases sdhcN, which do not work, resulting in mmc0 and mmc1 hosts randomly changing indices between boots. Fixes: c4da5a561627 ("arm64: dts: qcom: Add msm8916 sdhci configuration nodes") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201020559.1611890-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 9044eb41a81d..41897eb3736a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -19,8 +19,8 @@ #size-cells = <2>; aliases { - sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ - sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ }; chosen { }; From 145988cff2a10ec8c720eccdcfc94748f497cd8d Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 29 Nov 2021 17:55:10 +0100 Subject: [PATCH 177/574] ARM: dts: sun8i: Adjust power key nodes Several H3 and one H2+ board have power key nodes, which are slightly off. Some are missing wakeup-source property and some have BTN_0 code assigned instead of KEY_POWER. Adjust them, so they can function as intended by designer. Co-developed-by: Michael Klein Signed-off-by: Michael Klein Signed-off-by: Jernej Skrabec Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211129165510.370717-1-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 3 ++- arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 1 + arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 3 ++- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 3 ++- arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 3 ++- arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi | 1 + 6 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index 8e8634ff2f9d..d5c7b7984d85 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -52,8 +52,9 @@ sw4 { label = "power"; - linux,code = ; + linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index c7c3e7d8b3c8..fc45d5aaa67f 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -81,6 +81,7 @@ label = "k1"; linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 597c425d08ec..9daffd90c12f 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -99,8 +99,9 @@ sw4 { label = "sw4"; - linux,code = ; + linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index 5aff8ecc66cb..90f75fa85e68 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -91,8 +91,9 @@ sw4 { label = "sw4"; - linux,code = ; + linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; }; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi index 7a6af54dd342..d03f5853ef7b 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi @@ -82,8 +82,9 @@ sw4 { label = "power"; - linux,code = ; + linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi index c44fd726945a..9e14fe5fdcde 100644 --- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi +++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi @@ -49,6 +49,7 @@ label = "power"; linux,code = ; gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + wakeup-source; }; }; From 75fb3b1be53c85901d45ddb7cc2db6967876b99e Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 30 Nov 2021 11:01:58 +0100 Subject: [PATCH 178/574] arm64: dts: meson: p241: add vcc_5v regulator Add the VCC_5V regulator, which feeds the HDMI, USB and audio amplifier. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211130100159.214489-2-jbrunet@baylibre.com --- .../arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts index eb7f5a3fefd4..9d0684a8264b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts @@ -84,6 +84,14 @@ regulator-max-microvolt = <3300000>; }; + vcc_5v: regulator-vcc-5v { + compatible = "regulator-fixed"; + regulator-name = "VCC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + emmc_pwrseq: emmc-pwrseq { compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; @@ -136,6 +144,7 @@ status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; pinctrl-names = "default"; + hdmi-supply = <&vcc_5v>; }; &hdmi_tx_tmds_port { @@ -220,3 +229,7 @@ status = "okay"; dr_mode = "host"; }; + +&usb2_phy0 { + phy-supply = <&vcc_5v>; +}; From 0a62b3cc0af9322e650fe89bea0bacdedf01960a Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 30 Nov 2021 11:01:59 +0100 Subject: [PATCH 179/574] arm64: dts: meson: p241: add sound support Add the p241 sound card support. This board can play audio through HDMI and the internal DAC. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20211130100159.214489-3-jbrunet@baylibre.com --- .../boot/dts/amlogic/meson-gxl-s805x-p241.dts | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts index 9d0684a8264b..ff906becd2ab 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts @@ -8,6 +8,7 @@ /dts-v1/; #include +#include #include "meson-gxl-s805x.dtsi" @@ -21,6 +22,13 @@ ethernet0 = ðmac; }; + au2: analog-amplifier { + compatible = "simple-audio-amplifier"; + sound-name-prefix = "AU2"; + VCC-supply = <&vcc_5v>; + enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -110,6 +118,68 @@ clocks = <&wifi32k>; clock-names = "ext_clock"; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXL-P241"; + audio-aux-devs = <&au2>; + audio-widgets = "Line", "Lineout"; + audio-routing = "AU2 INL", "ACODEC LOLN", + "AU2 INR", "ACODEC LORN", + "Lineout", "AU2 OUTL", + "Lineout", "AU2 OUTR"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + + codec-1 { + sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + + dai-link-3 { + sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; + + codec-0 { + sound-dai = <&acodec>; + }; + }; + }; +}; + +&acodec { + AVDD-supply = <&vddio_ao18>; + status = "okay"; +}; + +&aiu { + status = "okay"; }; &cec_AO { From 8dce88fe80a858f34bb5b46470218fe478d251ee Mon Sep 17 00:00:00 2001 From: Sin Hui Kho Date: Wed, 1 Dec 2021 18:13:53 +0800 Subject: [PATCH 180/574] arm64: dts: Update NAND MTD partition for Agilex and Stratix 10 Change NAND flash MTD partition in device tree after implementation of UBI and UBIFS. "u-boot" partition remain for raw u-boot image, but "root" partition is use for UBI image containing all other components. Signed-off-by: Sin Hui Kho Signed-off-by: Dinh Nguyen --- .../altera/socfpga_stratix10_socdk_nand.dts | 24 ++----------------- .../dts/intel/socfpga_agilex_socdk_nand.dts | 20 ++-------------- 2 files changed, 4 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index f9b4a39683cf..bbc3db42d6e8 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -119,28 +119,8 @@ }; partition@200000 { - label = "env"; - reg = <0x200000 0x40000>; - }; - - partition@240000 { - label = "dtb"; - reg = <0x240000 0x40000>; - }; - - partition@280000 { - label = "kernel"; - reg = <0x280000 0x2000000>; - }; - - partition@2280000 { - label = "misc"; - reg = <0x2280000 0x2000000>; - }; - - partition@4280000 { - label = "rootfs"; - reg = <0x4280000 0x3bd80000>; + label = "root"; + reg = <0x200000 0x3fe00000>; }; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts index cc2dcabf34e3..57f83481f551 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts @@ -91,24 +91,8 @@ reg = <0 0x200000>; }; partition@200000 { - label = "env"; - reg = <0x200000 0x40000>; - }; - partition@240000 { - label = "dtb"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "kernel"; - reg = <0x280000 0x2000000>; - }; - partition@2280000 { - label = "misc"; - reg = <0x2280000 0x2000000>; - }; - partition@4280000 { - label = "rootfs"; - reg = <0x4280000 0x3bd80000>; + label = "root"; + reg = <0x200000 0x3fe00000>; }; }; }; From ad1569476e7644ac5754ac9a710ce771a7b4976f Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 23 Nov 2021 23:49:22 +0100 Subject: [PATCH 181/574] dt-bindings: arm: apple: Add iMac (24-inch 2021) to Apple bindings This introduces compatible strings for both 2021 Apple iMac M1 devices: * apple,j456 - iMac (24-inch, 4x USB-C, M1, 2021) * apple,j457 - iMac (24-inch, 2x USB-C, M1, 2021) Reviewed-by: Mark Kettenis Signed-off-by: Janne Grunau Tested-by: Hector Martin Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/arm/apple.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index 1e772c85206c..b23c8dc5a27d 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -12,12 +12,12 @@ maintainers: description: | ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon". - This currently includes devices based on the "M1" SoC, starting with the - three Mac models released in late 2020: + This currently includes devices based on the "M1" SoC: - Mac mini (M1, 2020) - MacBook Pro (13-inch, M1, 2020) - MacBook Air (M1, 2020) + - iMac (24-inch, M1, 2021) The compatible property should follow this format: @@ -56,6 +56,8 @@ properties: - apple,j274 # Mac mini (M1, 2020) - apple,j293 # MacBook Pro (13-inch, M1, 2020) - apple,j313 # MacBook Air (M1, 2020) + - apple,j456 # iMac (24-inch, 4x USB-C, M1, 2021) + - apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021) - const: apple,t8103 - const: apple,arm-platform From 7c77ab91b33d2ef06c4f3eab633ceed8e7bfedcc Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 23 Nov 2021 23:49:23 +0100 Subject: [PATCH 182/574] arm64: dts: apple: Add missing M1 (t8103) devices This adds support for following Apple M1 devices: - MacBook Pro (13-inch, M1, 2020) - MacBook Air (M1, 2020) - iMac (24-inch 2021) Reviewed-by: Mark Kettenis Signed-off-by: Janne Grunau Tested-by: Hector Martin Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/Makefile | 4 ++ arch/arm64/boot/dts/apple/t8103-j274.dts | 29 +------------- arch/arm64/boot/dts/apple/t8103-j293.dts | 33 +++++++++++++++ arch/arm64/boot/dts/apple/t8103-j313.dts | 33 +++++++++++++++ arch/arm64/boot/dts/apple/t8103-j456.dts | 41 +++++++++++++++++++ arch/arm64/boot/dts/apple/t8103-j457.dts | 47 ++++++++++++++++++++++ arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 49 +++++++++++++++++++++++ 7 files changed, 208 insertions(+), 28 deletions(-) create mode 100644 arch/arm64/boot/dts/apple/t8103-j293.dts create mode 100644 arch/arm64/boot/dts/apple/t8103-j313.dts create mode 100644 arch/arm64/boot/dts/apple/t8103-j456.dts create mode 100644 arch/arm64/boot/dts/apple/t8103-j457.dts create mode 100644 arch/arm64/boot/dts/apple/t8103-jxxx.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index cbbd701ebf05..c0510c25ca6a 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -1,2 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_APPLE) += t8103-j274.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8103-j293.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8103-j313.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8103-j456.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8103-j457.dtb diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts/apple/t8103-j274.dts index 02c36301e985..9e01ef70039d 100644 --- a/arch/arm64/boot/dts/apple/t8103-j274.dts +++ b/arch/arm64/boot/dts/apple/t8103-j274.dts @@ -10,39 +10,15 @@ /dts-v1/; #include "t8103.dtsi" +#include "t8103-jxxx.dtsi" / { compatible = "apple,j274", "apple,t8103", "apple,arm-platform"; model = "Apple Mac mini (M1, 2020)"; aliases { - serial0 = &serial0; ethernet0 = ðernet0; }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - stdout-path = "serial0"; - - framebuffer0: framebuffer@0 { - compatible = "apple,simple-framebuffer", "simple-framebuffer"; - reg = <0 0 0 0>; /* To be filled by loader */ - /* Format properties will be added by loader */ - status = "disabled"; - }; - }; - - memory@800000000 { - device_type = "memory"; - reg = <0x8 0 0x2 0>; /* To be filled by loader */ - }; -}; - -&serial0 { - status = "okay"; }; /* @@ -50,9 +26,6 @@ * on-board devices and properties that are populated by the bootloader * (such as MAC addresses). */ -&port00 { - bus-range = <1 1>; -}; &port01 { bus-range = <2 2>; diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts new file mode 100644 index 000000000000..466035f00b69 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Pro (13-inch, M1, 2020) + * + * target-type: J293 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8103.dtsi" +#include "t8103-jxxx.dtsi" + +/ { + compatible = "apple,j293", "apple,t8103", "apple,arm-platform"; + model = "Apple MacBook Pro (13-inch, M1, 2020)"; +}; + +/* + * Remove unused PCIe ports and disable the associated DARTs. + */ + +&pcie0_dart_1 { + status = "disabled"; +}; + +&pcie0_dart_2 { + status = "disabled"; +}; + +/delete-node/ &port01; +/delete-node/ &port02; diff --git a/arch/arm64/boot/dts/apple/t8103-j313.dts b/arch/arm64/boot/dts/apple/t8103-j313.dts new file mode 100644 index 000000000000..b0ebb45bdb6f --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8103-j313.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Air (M1, 2020) + * + * target-type: J313 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8103.dtsi" +#include "t8103-jxxx.dtsi" + +/ { + compatible = "apple,j313", "apple,t8103", "apple,arm-platform"; + model = "Apple MacBook Air (M1, 2020)"; +}; + +/* + * Remove unused PCIe ports and disable the associated DARTs. + */ + +&pcie0_dart_1 { + status = "disabled"; +}; + +&pcie0_dart_2 { + status = "disabled"; +}; + +/delete-node/ &port01; +/delete-node/ &port02; diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts/apple/t8103-j456.dts new file mode 100644 index 000000000000..7267e069355b --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8103-j456.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iMac (24-inch, 4x USB-C, M1, 2020) + * + * target-type: J456 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8103.dtsi" +#include "t8103-jxxx.dtsi" + +/ { + compatible = "apple,j456", "apple,t8103", "apple,arm-platform"; + model = "Apple iMac (24-inch, 4x USB-C, M1, 2020)"; + + aliases { + ethernet0 = ðernet0; + }; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ + +&port01 { + bus-range = <2 2>; +}; + +&port02 { + bus-range = <3 3>; + ethernet0: ethernet@0,0 { + reg = <0x30000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 10 18 00 00 00]; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts/apple/t8103-j457.dts new file mode 100644 index 000000000000..d7c622931627 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8103-j457.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iMac (24-inch, 2x USB-C, M1, 2020) + * + * target-type: J457 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8103.dtsi" +#include "t8103-jxxx.dtsi" + +/ { + compatible = "apple,j457", "apple,t8103", "apple,arm-platform"; + model = "Apple iMac (24-inch, 2x USB-C, M1, 2020)"; + + aliases { + ethernet0 = ðernet0; + }; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ + +&port02 { + bus-range = <3 3>; + ethernet0: ethernet@0,0 { + reg = <0x30000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 10 18 00 00 00]; + }; +}; + +/* + * Remove unused PCIe port and disable the associated DART. + */ + +&pcie0_dart_1 { + status = "disabled"; +}; + +/delete-node/ &port01; diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi new file mode 100644 index 000000000000..53d22b434d76 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple M1 Mac mini, MacBook Air/Pro, iMac 24" (M1, 2020/2021) + * + * This file contains parts common to all Apple M1 devices using the t8103. + * + * target-type: J274, J293, J313, J456, J457 + * + * Copyright The Asahi Linux Contributors + */ + +/ { + aliases { + serial0 = &serial0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + }; + }; + + memory@800000000 { + device_type = "memory"; + reg = <0x8 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ +&port00 { + bus-range = <1 1>; +}; From 90458f6eec42aafb7688eca0ec1d3c00adc31fb7 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 23 Nov 2021 23:49:24 +0100 Subject: [PATCH 183/574] arm64: dts: apple: t8103: Add i2c nodes Apple M1 has at least 5 i2c controllers. i2c0, i2c1 and i2c3 are used on all M1 Mac devices. The 2020 Mac Mini uses i2c2 and the 13-inch MacBook Pro uses i2c2 and i2c4. Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Tested-by: Hector Martin Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-j274.dts | 4 ++ arch/arm64/boot/dts/apple/t8103-j293.dts | 8 +++ arch/arm64/boot/dts/apple/t8103.dtsi | 87 ++++++++++++++++++++++++ 3 files changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts/apple/t8103-j274.dts index 9e01ef70039d..2cd429efba5b 100644 --- a/arch/arm64/boot/dts/apple/t8103-j274.dts +++ b/arch/arm64/boot/dts/apple/t8103-j274.dts @@ -39,3 +39,7 @@ local-mac-address = [00 10 18 00 00 00]; }; }; + +&i2c2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts index 466035f00b69..49cdf4b560a3 100644 --- a/arch/arm64/boot/dts/apple/t8103-j293.dts +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -31,3 +31,11 @@ /delete-node/ &port01; /delete-node/ &port02; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index c320c8baeb41..c62d9082c6a3 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -111,6 +111,68 @@ ranges; nonposted-mmio; + i2c0: i2c@235010000 { + compatible = "apple,t8103-i2c", "apple,i2c"; + reg = <0x2 0x35010000 0x0 0x4000>; + clocks = <&clk24>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + i2c1: i2c@235014000 { + compatible = "apple,t8103-i2c", "apple,i2c"; + reg = <0x2 0x35014000 0x0 0x4000>; + clocks = <&clk24>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + i2c2: i2c@235018000 { + compatible = "apple,t8103-i2c", "apple,i2c"; + reg = <0x2 0x35018000 0x0 0x4000>; + clocks = <&clk24>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; /* not used in all devices */ + }; + + i2c3: i2c@23501c000 { + compatible = "apple,t8103-i2c", "apple,i2c"; + reg = <0x2 0x3501c000 0x0 0x4000>; + clocks = <&clk24>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + i2c4: i2c@235020000 { + compatible = "apple,t8103-i2c", "apple,i2c"; + reg = <0x2 0x35020000 0x0 0x4000>; + clocks = <&clk24>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; /* only used in J293 */ + }; + serial0: serial@235200000 { compatible = "apple,s5l-uart"; reg = <0x2 0x35200000 0x0 0x1000>; @@ -153,6 +215,31 @@ , ; + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; + + i2c4_pins: i2c4-pins { + pinmux = , + ; + }; + pcie_pins: pcie-pins { pinmux = , , From c03edf1c0fc8648ab2f3f81ce1c00fff5fe7f69b Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 23 Nov 2021 23:49:25 +0100 Subject: [PATCH 184/574] arm64: dts: apple: t8103: Add cd321x nodes All M1 Mac devices have 2 SoC connected USB-C ports and use cd321x USB type C port switch and power deliver controllers. I2c bus and addresses configuration are for all devices equal. The iMac (24-inch, 2021) has a configuration with 2 additional USB-C ports (j456) using two additional cd321x controllers. Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Tested-by: Hector Martin Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-j456.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 18 ++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts/apple/t8103-j456.dts index 7267e069355b..884fddf7d363 100644 --- a/arch/arm64/boot/dts/apple/t8103-j456.dts +++ b/arch/arm64/boot/dts/apple/t8103-j456.dts @@ -21,6 +21,24 @@ }; }; +&i2c0 { + hpm2: usb-pd@3b { + compatible = "apple,cd321x"; + reg = <0x3b>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <106 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm3: usb-pd@3c { + compatible = "apple,cd321x"; + reg = <0x3c>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <106 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi index 53d22b434d76..876278fe0afe 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -39,6 +39,24 @@ status = "okay"; }; +&i2c0 { + hpm0: usb-pd@38 { + compatible = "apple,cd321x"; + reg = <0x38>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <106 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm1: usb-pd@3f { + compatible = "apple,cd321x"; + reg = <0x3f>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <106 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader From 6f8260557d490364c2b49872127c379de9b141ac Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 15:12:03 +0900 Subject: [PATCH 185/574] dt-bindings: i2c: apple,i2c: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The i2c driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/i2c/apple,i2c.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml index 82b953181a52..47dd6c107a6d 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -40,6 +40,9 @@ properties: used. This frequency is generated by dividing the reference clock. Allowed values are between ref_clk/(16*4) and ref_clk/(16*255). + power-domains: + maxItems: 1 + required: - compatible - reg From 364609125e2ca745c698ec157615ff179b239344 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 15:13:15 +0900 Subject: [PATCH 186/574] dt-bindings: iommu: apple,dart: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The DART driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/iommu/apple,dart.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/apple,dart.yaml b/Documentation/devicetree/bindings/iommu/apple,dart.yaml index 94aa9e9afa59..82ad669feef7 100644 --- a/Documentation/devicetree/bindings/iommu/apple,dart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,dart.yaml @@ -41,6 +41,9 @@ properties: Has to be one. The single cell describes the stream id emitted by a master to the IOMMU. + power-domains: + maxItems: 1 + required: - compatible - reg From 1ed162b56baae221da049ba8641ddd4fca33c0b9 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 15:14:12 +0900 Subject: [PATCH 187/574] dt-bindings: pinctrl: apple,pinctrl: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The pinctrl driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 07b00de79755..200d411621e7 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -50,6 +50,9 @@ properties: '#interrupt-cells': const: 2 + power-domains: + maxItems: 1 + patternProperties: '-pins$': type: object From 72baffdd26fb4e5b3c7215728e98e2681a9ebc4f Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 15:15:41 +0900 Subject: [PATCH 188/574] dt-bindings: interrupt-controller: apple,aic: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The AIC driver doesn't do runtime-pm and likely never will (since it is system-critical), but it makes sense to describe the power domain relationship the devicetree properly. Acked-by: Rob Herring Signed-off-by: Hector Martin --- .../devicetree/bindings/interrupt-controller/apple,aic.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml index cf6c091a07b1..97359024709a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -65,6 +65,9 @@ properties: Specifies base physical address and size of the AIC registers. maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - '#interrupt-cells' From 8ff8d6936ec9134754e9a3eef1f641358dac7457 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 1 Dec 2021 19:21:14 +0100 Subject: [PATCH 189/574] arm64: dts: allwinner: h6: tanix-tx6: Split to DT and DTSI There is another very similar device to Tanix TX6, namely Tanix TX6 mini. Because most of the board design is shared, it makes sense to have common nodes in DTSI file. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 164 +---------------- .../boot/dts/allwinner/sun50i-h6-tanix.dtsi | 173 ++++++++++++++++++ 2 files changed, 174 insertions(+), 163 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts index 7c37aa4c60cb..a6e69f4b2666 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts @@ -3,175 +3,13 @@ /dts-v1/; -#include "sun50i-h6.dtsi" -#include "sun50i-h6-cpu-opp.dtsi" - -#include +#include "sun50i-h6-tanix.dtsi" / { model = "Tanix TX6"; compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - /* used for FD650 LED display driver */ - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&pio 7 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH6 */ - scl-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH5 */ - i2c-gpio,delay-us = <5>; - }; - - reg_vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu { - compatible = "regulator-fixed"; - regulator-name = "vdd-cpu-gpu"; - regulator-min-microvolt = <1135000>; - regulator-max-microvolt = <1135000>; - }; - - sound-spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "sun50i-h6-spdif"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpu_gpu>; -}; - -&de { - status = "okay"; -}; - -&dwc3 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&gpu { - mali-supply = <®_vdd_cpu_gpu>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc1v8>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-hs200-1_8v; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_vcc1v8>; - vcc-pd-supply = <®_vcc3v3>; - vcc-pg-supply = <®_vcc1v8>; }; &r_ir { linux,rc-map-name = "rc-tanix-tx5max"; - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb2otg { - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy { - status = "okay"; -}; - -&usb3phy { - status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi new file mode 100644 index 000000000000..166b6a7a586c --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2019 Jernej Skrabec + +/dts-v1/; + +#include "sun50i-h6.dtsi" +#include "sun50i-h6-cpu-opp.dtsi" + +#include + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + /* used for FD650 LED display driver */ + i2c { + compatible = "i2c-gpio"; + sda-gpios = <&pio 7 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH6 */ + scl-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH5 */ + i2c-gpio,delay-us = <5>; + }; + + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu { + compatible = "regulator-fixed"; + regulator-name = "vdd-cpu-gpu"; + regulator-min-microvolt = <1135000>; + regulator-max-microvolt = <1135000>; + }; + + sound-spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "sun50i-h6-spdif"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpu_gpu>; +}; + +&de { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&gpu { + mali-supply = <®_vdd_cpu_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v3>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_vcc1v8>; + vcc-pd-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc1v8>; +}; + +&r_ir { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usb2otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb3phy { + status = "okay"; +}; From fcad81d944e7cb8f2d0aeaec0e4109638e873036 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 1 Dec 2021 19:21:15 +0100 Subject: [PATCH 190/574] dt-bindings: arm: sunxi: Add Tanix TX6 mini Tanix TX6 mini is, as its name suggest, very similar to Tanix TX6, but with less features. It misses bluetooth support, it has less RAM, wifi supports only 2.4G, it comes with different IR remote, etc. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 889128acf49a..c8a3102c0fde 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -808,6 +808,11 @@ properties: - const: oranth,tanix-tx6 - const: allwinner,sun50i-h6 + - description: Tanix TX6 mini + items: + - const: oranth,tanix-tx6-mini + - const: allwinner,sun50i-h6 + - description: TBS A711 Tablet items: - const: tbs-biometrics,a711 From fa33ec5157b08ea8bd57dd6a0bbf920dc304aca1 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 1 Dec 2021 19:21:16 +0100 Subject: [PATCH 191/574] arm64: dts: allwinner: h6: Add Tanix TX6 mini dts Tanix TX6 mini is less capable version of Tanix TX6 although it comes with some features not present on Tanix TX6. Basic specs: - H6 SoC - 2 GiB DDR3 RAM - HDMI - SPDIF - 2x USB - analogue audio - CVBS - SD card - IR remote - LED display - fast ethernet - XR819 wifi - 16 GiB eMMC Currently supported features doesn't differ that much from Tanix TX6, but that will change soon. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun50i-h6-tanix-tx6-mini.dts | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index a96d9d2d8dd8..8fa5c060a4fe 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -37,3 +37,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts new file mode 100644 index 000000000000..08d84160d88f --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2021 Jernej Skrabec + +/dts-v1/; + +#include "sun50i-h6-tanix.dtsi" + +/ { + model = "Tanix TX6 mini"; + compatible = "oranth,tanix-tx6-mini", "allwinner,sun50i-h6"; +}; + +&r_ir { + linux,rc-map-name = "rc-tanix-tx3mini"; +}; From 0835819309540e83325ad10fb920b59c7495b419 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 1 Dec 2021 19:21:17 +0100 Subject: [PATCH 192/574] arm64: dts: allwinner: h6: tanix: Add MMC1 node Both, Tanix TX6 and Tanix TX6 mini, have SDIO wifi module, albeit different. However, driver can be autoprobed via SDIO ID. Add MMC1 node, so kernel can discover wifi module and load driver for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- .../boot/dts/allwinner/sun50i-h6-tanix.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi index 166b6a7a586c..edb71e4a0304 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi @@ -75,6 +75,13 @@ #sound-dai-cells = <0>; compatible = "linux,spdif-dit"; }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc 1>; + clock-names = "ext_clock"; + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ + }; }; &cpu0 { @@ -121,6 +128,15 @@ status = "okay"; }; +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + &mmc2 { vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc1v8>; From a8a051984a75f8123c1805fdadb5a4ec6f1a50b0 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 1 Dec 2021 19:21:18 +0100 Subject: [PATCH 193/574] arm64: dts: allwinner: h6: tanix-tx6: Enable bluetooth Tanix TX6 comes either with RTL8822BS or RTL8822CS wifi+bt combo module. Wifi part is already enabled in tanix DTSI. Let's enable also bluetooth. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- .../boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts index a6e69f4b2666..9a38ff9b3fc7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts @@ -13,3 +13,17 @@ &r_ir { linux,rc-map-name = "rc-tanix-tx5max"; }; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + device-wake-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ + host-wake-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ + enable-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ + }; +}; From 4d3984906397581dc0ccb6a02bf16b6ff82c9192 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Fri, 26 Nov 2021 14:15:54 +0530 Subject: [PATCH 194/574] arm64: dts: ti: j7200-main: Fix 'dtbs_check' serdes_ln_ctrl node Fix 'dtbs_check' in serdes_ln_ctrl (serdes-ln-ctrl@4080) node by changing the node name to mux-controller@4080. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211126084555.17797-2-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index d60ef4f7dd0b..05a627ad6cdc 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -32,7 +32,7 @@ #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; - serdes_ln_ctrl: serdes-ln-ctrl@4080 { + serdes_ln_ctrl: mux-controller@4080 { compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ From 3f92a5be6084b77f764a8bbb881ac0d12cb9e863 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Fri, 26 Nov 2021 14:15:55 +0530 Subject: [PATCH 195/574] arm64: dts: ti: j721e-main: Fix 'dtbs_check' in serdes_ln_ctrl node Fix 'dtbs_check' in serdes_ln_ctrl (mux@4080) node by changing the node name to mux-controller@4080. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211126084555.17797-3-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 08c8d1b47dcd..e85c89eebfa3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -42,7 +42,7 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; - serdes_ln_ctrl: mux@4080 { + serdes_ln_ctrl: mux-controller@4080 { compatible = "mmio-mux"; reg = <0x00004080 0x50>; #mux-control-cells = <1>; From a27a93bf70045be54b594fa8482959ffb84166d7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 12 Nov 2021 22:36:35 -0600 Subject: [PATCH 196/574] arm64: dts: ti: k3-am642: Fix the L2 cache sets A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 256KB of L2 / 64 (line length) = 4096 ways 4096 ways / 16 = 256 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en [2] https://www.ti.com/lit/pdf/spruim2 Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Reported-by: Peng Fan Signed-off-by: Nishanth Menon Reviewed-by: Pratyush Yadav Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211113043635.4296-1-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am642.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi index e2b397c88401..8a76f4821b11 100644 --- a/arch/arm64/boot/dts/ti/k3-am642.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi @@ -60,6 +60,6 @@ cache-level = <2>; cache-size = <0x40000>; cache-line-size = <64>; - cache-sets = <512>; + cache-sets = <256>; }; }; From d0c826106f3fc11ff97285102b576b65576654ae Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 12 Nov 2021 22:36:38 -0600 Subject: [PATCH 197/574] arm64: dts: ti: k3-j7200: Fix the L2 cache sets A72's L2 cache[1] on J7200[2] is 1MB. A72's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 1MB of L2 / 64 (line length) = 16384 ways 16384 ways / 16 = 1024 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system [2] https://www.ti.com/lit/pdf/spruiu1 Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Reported-by: Peng Fan Signed-off-by: Nishanth Menon Reviewed-by: Pratyush Yadav Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211113043638.4358-1-nm@ti.com --- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index 47567cb260c2..a99a4d305b7e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -86,7 +86,7 @@ cache-level = <2>; cache-size = <0x100000>; cache-line-size = <64>; - cache-sets = <2048>; + cache-sets = <1024>; next-level-cache = <&msmc_l3>; }; From e9ba3a5bc6fdc2c796c69fdaf5ed6c9957cf9f9d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 12 Nov 2021 22:36:39 -0600 Subject: [PATCH 198/574] arm64: dts: ti: k3-j721e: Fix the L2 cache sets A72's L2 cache[1] on J721e[2] is 1MB. A72's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 1MB of L2 / 64 (line length) = 16384 ways 16384 ways / 16 = 1024 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system [2] http://www.ti.com/lit/pdf/spruil1 Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC") Reported-by: Peng Fan Signed-off-by: Nishanth Menon Reviewed-by: Pratyush Yadav Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211113043639.4413-1-nm@ti.com --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index a5967ba139d7..4a3872fce533 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -88,7 +88,7 @@ cache-level = <2>; cache-size = <0x100000>; cache-line-size = <64>; - cache-sets = <2048>; + cache-sets = <1024>; next-level-cache = <&msmc_l3>; }; From a172c86931709d6663318609d71a811333bdf4b0 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 12 Nov 2021 22:26:40 -0600 Subject: [PATCH 199/574] arm64: dts: ti: k3-j7200: Correct the d-cache-sets info A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache - ICache is 3-way set-associative - Dcache is 2-way set-associative - Line size are 64bytes 32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways 512 ways / 2 (Dcache is 2-way per set) = 256 sets. So, correct the d-cache-sets info. [1] https://www.ti.com/lit/pdf/spruiu1 Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Reported-by: Peng Fan Signed-off-by: Nishanth Menon Reviewed-by: Pratyush Yadav Reviewed-by: Kishon Vijay Abraham I Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20211113042640.30955-1-nm@ti.com --- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index a99a4d305b7e..64fef4e67d76 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -62,7 +62,7 @@ i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; @@ -76,7 +76,7 @@ i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; }; From 44226253e6514b8ef3ddc8710055548d22a230f0 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Thu, 2 Dec 2021 18:30:18 +0100 Subject: [PATCH 200/574] arm64: dts: ti: k3-am64-main: add timesync router node The Time Sync Event Router (TIMESYNC_INTRTR0) implements a set of multiplexers to provide selection of active CPTS time sync events for routing to CPTS capable modules. This patch adds DT node TIMESYNC_INTRTR0 using "pinctrl-single" bindings. Signed-off-by: Grygorii Strashko Signed-off-by: Vignesh Raghavendra Signed-off-by: Christian Gmeiner Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20211202173114.9936-1-christian.gmeiner@gmail.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 5ad638b95ffc..e16d2ccdd818 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -564,6 +564,14 @@ ti,cpts-ext-ts-inputs = <8>; }; + timesync_router: pinctrl@a40000 { + compatible = "pinctrl-single"; + reg = <0x0 0xa40000 0x0 0x800>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000107ff>; + }; + usbss0: cdns-usb@f900000{ compatible = "ti,am64-usb"; reg = <0x00 0xf900000 0x00 0x100>; From 3e63d6a197d57f94abff0fbd71efd8f98e254e1c Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 22 Nov 2021 11:19:15 +0100 Subject: [PATCH 201/574] dt-bindings: vendor-prefixes: Add an entry for JOZ BV Add "joz" entry for JOZ BV: https://joz.nl/en/about-joz/ Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 66d6432fd781..6414f5fdcb91 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -593,6 +593,8 @@ patternProperties: description: JetHome (IP Sokolov P.A.) "^jianda,.*": description: Jiandangjing Technology Co., Ltd. + "^joz,.*": + description: JOZ BV "^kam,.*": description: Kamstrup A/S "^karo,.*": From 74fb79574d26fc79a04e5a75e137317870843e7d Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 22 Nov 2021 11:19:16 +0100 Subject: [PATCH 202/574] dt-bindings: arm: fsl: add JOZ Access Point Add imx6ull based JOZ Access Point. Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0b595b26061f..a0eb42595ee2 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -580,6 +580,7 @@ properties: items: - enum: - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board + - joz,jozacp # JOZ Access Point - kontron,imx6ull-n6411-som # Kontron N6411 SOM - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board - toradex,colibri-imx6ull # Colibri iMX6ULL Modules From 2db0624b78c42abe1bcada7dd62068ef978e1e35 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 22 Nov 2021 11:19:17 +0100 Subject: [PATCH 203/574] ARM: dts: add JOZ Access Point JOZ Access Point is imx6ull based device designed for agricultural cleaning machines. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6ull-jozacp.dts | 456 +++++++++++++++++++++++++++ 2 files changed, 457 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-jozacp.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..9753faf0f1aa 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -688,6 +688,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-colibri-emmc-eval-v3.dtb \ imx6ull-colibri-eval-v3.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ + imx6ull-jozacp.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-opos6uldev.dtb \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-jozacp.dts b/arch/arm/boot/dts/imx6ull-jozacp.dts new file mode 100644 index 000000000000..a152eeb78e88 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-jozacp.dts @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; + +#include +#include +#include "imx6ull.dtsi" + +/ { + model = "JOZ Access Point"; + compatible = "joz,jozacp", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + /* On board name LED_RGB1 */ + led-controller-1 { + compatible = "pwm-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <0>; + pwms = <&pwm1 0 10000000 0>; + max-brightness = <255>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + pwms = <&pwm3 0 10000000 0>; + max-brightness = <255>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + pwms = <&pwm5 0 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* On board name LED_RGB2 */ + led-controller-2 { + compatible = "pwm-leds"; + + led-3 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + pwms = <&pwm2 0 10000000 0>; + max-brightness = <255>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <4>; + pwms = <&pwm4 0 10000000 0>; + max-brightness = <255>; + }; + + led-5 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <5>; + pwms = <&pwm6 0 10000000 0>; + max-brightness = <255>; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_5v0>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vbus: regulator-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vbus>; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v0>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&cpu0 { + clock-frequency = <792000000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + interrupts-extended = <&gpio1 29 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + dtr-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + vbus-supply = <®_vbus>; + dr_mode = "host"; + over-current-active-low; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vmmc-supply = <®_3v3>; + bus-width = <8>; + no-1-8-v; + non-removable; + cap-mmc-hw-reset; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sd; + non-removable; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x038b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x170b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* HW Revision */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 + + /* HW ID */ + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 + + /* Digital inputs */ + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x11000 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x11000 + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x11000 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x11000 + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x11000 + + /* Isolated outputs */ + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x01020 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x01020 + MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x01020 + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x01020 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x01020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001f8b1 + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b1 + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x01010 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x01010 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x01010 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x01010 + >; + }; + + pinctrl_pwm5: pwm5grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x01010 + >; + }; + + pinctrl_pwm6: pwm6grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x01010 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b0 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b0 + MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x1b0b0 + MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x1b0b0 + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x1b0b0 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x17099 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1f099 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10099 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17099 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17099 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17099 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17099 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17099 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17099 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17099 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17099 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9 + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_vbus: vbus0grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x030b0 + >; + }; + + pinctrl_wifi_npd: wifigrp { + fsl,pins = < + /* WL_REG_ON */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x03020 + >; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_hog>; + + pinctrl_snvs_hog: snvs-hog-grp { + fsl,pins = < + /* Digital outputs */ + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x00020 + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x00020 + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x00020 + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x00020 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x00020 + + /* Digital outputs fault feedback */ + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17000 + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17000 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x17000 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17000 + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17000 + >; + }; +}; From 2439d70c52c51f991b00b0ae5644e96033bd8165 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 22 Nov 2021 12:37:39 +0100 Subject: [PATCH 204/574] ARM: dts: imx6qdl-tqma6: add ERR006687 hardware workaround for "a" variant The TQMa6x "a" has a workaround for ERR006687 implemented in hardware. Add the required pinmuxing and related setup to make use of this. As board DTS files based on the TQMa6x SoMs will define their own pinmuxing for the FEC ethernet controller as well, we can't apply this pin group unconditionally; instead, it is the responsibility of the board DTs derived from imx6qdl-tqma6a.dtsi to include this group. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-tqma6a.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi index b679bec78e6c..bfb67da64b96 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi @@ -4,6 +4,12 @@ * Copyright 2013-2017 Markus Niebel */ +&fec { + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; @@ -26,3 +32,17 @@ pagesize = <32>; }; }; + +&iomuxc { + /* + * This pinmuxing is required for the ERR006687 workaround. Board + * DTS files that enable the FEC controller with + * fsl,err006687-workaround-present must include this group. + */ + pinctrl_enet_fix: enetfixgrp { + fsl,pins = < + /* ENET ping patch */ + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; +}; From ef3846247b41391434c23fcd9560daa57d14bb7a Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 22 Nov 2021 12:37:40 +0100 Subject: [PATCH 205/574] ARM: dts: imx6qdl: add TQ-Systems MBa6x device trees Add device trees for the MBa6x mainboard with TQMa6Q/QP/DL SoMs. As discussed, all new files are added with GPL-2.0-only license, as they are too tightly intertwined with the SoC DTSIs imx6dl.dtsi and imx6q.dtsi, which are GPL-2.0. Signed-off-by: Markus Niebel Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 5 + arch/arm/boot/dts/imx6dl-mba6.dtsi | 22 ++ arch/arm/boot/dts/imx6dl-mba6a.dts | 21 ++ arch/arm/boot/dts/imx6dl-mba6b.dts | 21 ++ arch/arm/boot/dts/imx6q-mba6.dtsi | 44 +++ arch/arm/boot/dts/imx6q-mba6a.dts | 20 + arch/arm/boot/dts/imx6q-mba6b.dts | 20 + arch/arm/boot/dts/imx6qdl-mba6.dtsi | 526 +++++++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-mba6a.dtsi | 36 ++ arch/arm/boot/dts/imx6qdl-mba6b.dtsi | 52 +++ arch/arm/boot/dts/imx6qp-mba6b.dts | 18 + 11 files changed, 785 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-mba6.dtsi create mode 100644 arch/arm/boot/dts/imx6dl-mba6a.dts create mode 100644 arch/arm/boot/dts/imx6dl-mba6b.dts create mode 100644 arch/arm/boot/dts/imx6q-mba6.dtsi create mode 100644 arch/arm/boot/dts/imx6q-mba6a.dts create mode 100644 arch/arm/boot/dts/imx6q-mba6b.dts create mode 100644 arch/arm/boot/dts/imx6qdl-mba6.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-mba6a.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-mba6b.dtsi create mode 100644 arch/arm/boot/dts/imx6qp-mba6b.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9753faf0f1aa..e462dbe75f6a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -483,6 +483,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-icore-rqs.dtb \ imx6dl-lanmcu.dtb \ imx6dl-mamoj.dtb \ + imx6dl-mba6a.dtb \ + imx6dl-mba6b.dtb \ imx6dl-nit6xlite.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-phytec-mira-rdk-nand.dtb \ @@ -584,6 +586,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-kp-tpc.dtb \ imx6q-logicpd.dtb \ imx6q-marsboard.dtb \ + imx6q-mba6a.dtb \ + imx6q-mba6b.dtb \ imx6q-mccmon6.dtb \ imx6q-nitrogen6x.dtb \ imx6q-nitrogen6_max.dtb \ @@ -629,6 +633,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-wandboard-revb1.dtb \ imx6q-wandboard-revd1.dtb \ imx6q-zii-rdu2.dtb \ + imx6qp-mba6b.dtb \ imx6qp-nitrogen6_max.dtb \ imx6qp-nitrogen6_som2.dtb \ imx6qp-phytec-mira-rdk-nand.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-mba6.dtsi b/arch/arm/boot/dts/imx6dl-mba6.dtsi new file mode 100644 index 000000000000..b749b424bbd6 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-mba6.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +ðphy { + rxdv-skew-ps = <180>; + txen-skew-ps = <0>; + rxd3-skew-ps = <180>; + rxd2-skew-ps = <180>; + rxd1-skew-ps = <180>; + rxd0-skew-ps = <180>; + txd3-skew-ps = <120>; + txd2-skew-ps = <0>; + txd1-skew-ps = <300>; + txd0-skew-ps = <120>; + txc-skew-ps = <1860>; + rxc-skew-ps = <1860>; +}; diff --git a/arch/arm/boot/dts/imx6dl-mba6a.dts b/arch/arm/boot/dts/imx6dl-mba6a.dts new file mode 100644 index 000000000000..df0a96b28af0 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-mba6a.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include +#include "imx6dl-tqma6a.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6a.dtsi" +#include "imx6dl-mba6.dtsi" + +/ { + model = "TQ TQMa6S/DL on MBa6x"; + compatible = "tq,imx6dl-mba6x-a", "tq,mba6a", + "tq,imx6dl-tqma6dl-a", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-mba6b.dts b/arch/arm/boot/dts/imx6dl-mba6b.dts new file mode 100644 index 000000000000..610b19d2db0f --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-mba6b.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include +#include "imx6dl-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6dl-mba6.dtsi" + +/ { + model = "TQ TQMa6S/DL on MBa6x"; + compatible = "tq,imx6dl-mba6x-b", "tq,mba6b", + "tq,imx6dl-tqma6dl-b", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6q-mba6.dtsi b/arch/arm/boot/dts/imx6q-mba6.dtsi new file mode 100644 index 000000000000..0d7be4567291 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-mba6.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +&ecspi5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5_mba6x>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +}; + +ðphy { + rxdv-skew-ps = <180>; + txen-skew-ps = <120>; + rxd3-skew-ps = <180>; + rxd2-skew-ps = <180>; + rxd1-skew-ps = <180>; + rxd0-skew-ps = <180>; + txd3-skew-ps = <120>; + txd2-skew-ps = <0>; + txd1-skew-ps = <180>; + txd0-skew-ps = <360>; + txc-skew-ps = <1860>; + rxc-skew-ps = <1860>; +}; + +&sata { + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi5_mba6x: ecspi5grp-mba6x { + fsl,pins = < + /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b099 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0xb099 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0xb099 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0xb099 /* eCSPI5 SS0 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-mba6a.dts b/arch/arm/boot/dts/imx6q-mba6a.dts new file mode 100644 index 000000000000..349a08605a5e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-mba6a.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6q-tqma6a.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6a.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6Q on MBa6x"; + compatible = "tq,imx6q-mba6x-a", "tq,mba6a", + "tq,imx6q-tqma6q-a", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-mba6b.dts b/arch/arm/boot/dts/imx6q-mba6b.dts new file mode 100644 index 000000000000..02c9f3e91b8f --- /dev/null +++ b/arch/arm/boot/dts/imx6q-mba6b.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6q-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6Q on MBa6x"; + compatible = "tq,imx6q-mba6x-b", "tq,mba6b", + "tq,imx6q-tqma6q-b", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/imx6qdl-mba6.dtsi new file mode 100644 index 000000000000..daf76345b179 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-mba6.dtsi @@ -0,0 +1,526 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include +#include +#include +#include + +/ { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + /delete-property/ mmc2; + /delete-property/ mmc3; + }; + + chosen { + stdout-path = &uart2; + }; + + beeper: gpio-beeper { + compatible = "gpio-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobeeper>; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + }; + + gpio_buttons: gpio-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobuttons>; + + button1 { + label = "s6"; + linux,code = ; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + }; + + button2 { + label = "s7"; + linux,code = ; + gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + }; + + button3 { + label = "s8"; + linux,code = ; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led1 { + label = "led1"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_mba6_3p3v: regulator-mba6-3p3v { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6-3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "supply-pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* PCIE.PWR_EN */ + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_mba6_3p3v>; + }; + + reg_vcc3v3_audio: regulator-vcc3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3-audio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_mba6_3p3v>; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&ssi1>; + audio-codec = <&tlv320aic32x4>; + audio-asrc = <&asrc>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + status = "okay"; + + ssi0 { + fsl,audmux-port = ; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) + >; + }; + + aud3 { + fsl,audmux-port = ; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>; + cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>; +}; + +&fec { + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <100000>; + micrel,force-master; + max-speed = <1000>; + }; + }; +}; + +&i2c1 { + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + ldoin-supply = <®_vcc3v3_audio>; + iov-supply = <®_mba6_3p3v>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + power-active-high; + over-current-active-low; + srp-disable; + hnp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +/* SD card slot */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_mba6_3p3v>; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + /* does not work on unmodified starter kit */ + /* fsl,ext-reset-output; */ + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099 + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */ + >; + }; + + pinctrl_ecspi1_mba6: ecspimba6grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* FEC phy IRQ */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008 + /* FEC phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099 + /* DSE = 100, 100k up, SPEED = MED */ + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0 + /* DSE = 111, pull 100k up */ + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038 + /* DSE = 111, pull external */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038 + /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0 + >; + }; + + pinctrl_gpiobeeper: gpiobeepergrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099 + >; + }; + + pinctrl_gpiobuttons: gpiobuttongrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099 + >; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 + + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099 + + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099 + + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099 + + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099 + + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099 + + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */ + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */ + /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */ + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071 + /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059 + + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059 + MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + /* Watchdog out */ + MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi new file mode 100644 index 000000000000..a61f2705a340 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/ { + aliases { + rtc0 = &rtc0; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>; +}; + +&i2c1 { + lm75: temperature-sensor@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + m24c64_57: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi new file mode 100644 index 000000000000..9f9f7037c9e4 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/ { + aliases { + rtc0 = &rtc0; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c3 { + lm75: temperature-sensor@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + m24c64_57: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-mba6b.dts b/arch/arm/boot/dts/imx6qp-mba6b.dts new file mode 100644 index 000000000000..eee2e09d6e94 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-mba6b.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2015-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ +/dts-v1/; + +#include +#include "imx6qp-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6QP on MBa6x"; + compatible = "tq,imx6qp-mba6x-b", "tq,mba6b", + "tq,imx6qp-tqma6qp-b", "fsl,imx6qp"; +}; From 5a759dac6503e1432f5c30a01df483608b500a54 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 22 Nov 2021 12:37:38 +0100 Subject: [PATCH 206/574] dt-bindings: arm: fsl: add TQ-Systems boards based on i.MX6Q/QP/DL The TQ-Systems MBa6x mainboard can be used with TQMa6 variants with i.MX6Q/QP/DL SoCs (TQMa6Q/QP/DL). The TQMa6Q and DL exist in two variants: The newer variants "A" have a hardware workaround for Erratum ERR006687, while variants "B" are missing such a workaround, so it needs to be handled in software. The erratum was fixed in i.MX6QP, so no "A" variant of the TQMa6QP exists. Signed-off-by: Matthias Schiffer Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a0eb42595ee2..d6a3a67e4d37 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -323,6 +323,20 @@ properties: - const: toradex,apalis_imx6q - const: fsl,imx6q + - description: TQ-Systems TQMa6Q SoM (variant A) on MBa6x + items: + - const: tq,imx6q-mba6x-a + - const: tq,mba6a # Expected by bootloader, to be removed in the future + - const: tq,imx6q-tqma6q-a + - const: fsl,imx6q + + - description: TQ-Systems TQMa6Q SoM (variant B) on MBa6x + items: + - const: tq,imx6q-mba6x-b + - const: tq,mba6b # Expected by bootloader, to be removed in the future + - const: tq,imx6q-tqma6q-b + - const: fsl,imx6q + - description: i.MX6QP based Boards items: - enum: @@ -344,6 +358,13 @@ properties: - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6 - const: fsl,imx6qp + - description: TQ-Systems TQMa6QP SoM on MBa6x + items: + - const: tq,imx6qp-mba6x-b + - const: tq,mba6b # Expected by bootloader, to be removed in the future + - const: tq,imx6qp-tqma6qp-b + - const: fsl,imx6qp + - description: i.MX6DL based Boards items: - enum: @@ -482,6 +503,20 @@ properties: - const: dh,imx6s-dhcom-som - const: fsl,imx6dl + - description: TQ-Systems TQMa6DL SoM (variant A) on MBa6x + items: + - const: tq,imx6dl-mba6x-a + - const: tq,mba6a # Expected by bootloader, to be removed in the future + - const: tq,imx6dl-tqma6dl-a + - const: fsl,imx6dl + + - description: TQ-Systems TQMa6DL SoM (variant B) on MBa6x + items: + - const: tq,imx6dl-mba6x-b + - const: tq,mba6b # Expected by bootloader, to be removed in the future + - const: tq,imx6dl-tqma6dl-b + - const: fsl,imx6dl + - description: i.MX6SL based Boards items: - enum: From 97164c0419fc3985921f9be4c235748a68f9095e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Mon, 22 Nov 2021 17:25:19 +0100 Subject: [PATCH 207/574] dt-bindings: arm: fsl: Add Y Soft IOTA Crux/Crux+ boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devicetree binding for Crux/Crux+ boards from the IOTA family. These boards have the very same HW configuration as the Orion board except the usage of Quad/QuadPlus SoC. Signed-off-by: Michal Vokáč Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d6a3a67e4d37..9679e3cd946a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -240,6 +240,7 @@ properties: - uniwest,imx6q-evi # Uniwest Evi - variscite,dt6customboard - wand,imx6q-wandboard # Wandboard i.MX6 Quad Board + - ysoft,imx6q-yapp4-crux # i.MX6 Quad Y Soft IOTA Crux board - zealz,imx6q-gk802 # Zealz GK802 - zii,imx6q-zii-rdu2 # ZII RDU2 Board - const: fsl,imx6q @@ -348,6 +349,7 @@ properties: - kvg,vicutp # Kverneland UT1P board - prt,prtwd3 # Protonic WD3 board - wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board + - ysoft,imx6qp-yapp4-crux-plus # i.MX6 Quad Plus Y Soft IOTA Crux+ board - zii,imx6qp-zii-rdu2 # ZII RDU2+ Board - const: fsl,imx6qp From c25b80c560b8a2bb9ca60155553abff6223c73a8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 22 Nov 2021 11:22:28 +0100 Subject: [PATCH 208/574] ARM: dts: Add FSG3 system controller and LEDs This adds the system controller on CS2 and the LEDs on it. Signed-off-by: Linus Walleij --- .../boot/dts/intel-ixp42x-freecom-fsg-3.dts | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts index 598586fc0862..b740403b05a9 100644 --- a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts +++ b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts @@ -97,6 +97,65 @@ fis-index-block = <0x1f>; }; }; + + /* Small syscon with some LEDs at CS2 */ + syscon@2,0 { + compatible = "freecom,fsg-cs2-system-controller", "syscon"; + reg = <2 0x0 0x200>; + reg-io-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <2 0x0 0x0 0x200>; + + led@0,0 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x01>; + label = "fsg:blue:wlan"; + linux,default-trigger = "wlan"; + default-state = "on"; + }; + led@0,1 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x02>; + label = "fsg:blue:wan"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,2 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x04>; + label = "fsg:blue:sata"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,3 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x04>; + label = "fsg:blue:usb"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,4 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x08>; + label = "fsg:blue:sync"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,5 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x10>; + label = "fsg:blue:ring"; + linux,default-trigger = ""; + default-state = "on"; + }; + }; }; pci@c0000000 { From 65248dde81528d7f6cdd091e397d2d6e0b49dae1 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 29 Jul 2021 01:34:39 +0200 Subject: [PATCH 209/574] ARM: dts: Add Goramo MultiLink device tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds a device tree for the Goramo MultiLink IXP425-based WAN router. Cc: Krzysztof Hałasa Cc: openwrt-devel@lists.openwrt.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 1 + .../dts/intel-ixp42x-goramo-multilink.dts | 180 ++++++++++++++++++ arch/arm/boot/dts/intel-ixp4xx.dtsi | 17 ++ 3 files changed, 198 insertions(+) create mode 100644 arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..4084535c6489 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -263,6 +263,7 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp46x-ixdp465.dtb \ intel-ixp42x-adi-coyote.dtb \ intel-ixp42x-ixdpg425.dtb \ + intel-ixp42x-goramo-multilink.dtb \ intel-ixp42x-iomega-nas100d.dtb \ intel-ixp42x-dlink-dsm-g600.dtb \ intel-ixp42x-gateworks-gw2348.dtb \ diff --git a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts new file mode 100644 index 000000000000..f80388b17a9e --- /dev/null +++ b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Goramo MultiLink Router + * There are two variants: + * - MultiLink Basic (a box) + * - MultiLink Max (19" rack mount) + * This device tree supports MultiLink Basic. + * This machine is based on IXP425. + * This is one of the few devices supporting the IXP4xx High-Speed Serial + * (HSS) link for a V.35 WAN interface. + * The hardware originates in Poland. + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Goramo MultiLink Router"; + compatible = "goramo,multilink-router", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* + * 64 MB of RAM according to the manual. The MultiLink + * Max has 128 MB. + */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + /* + * 74HC4094 which is used as a rudimentary GPIO expander + * FIXME: + * - Create device tree bindings for this as GPIO expander + * - Write a pure DT GPIO driver using these bindings + * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different) + */ + gpio_74: gpio-74hc4094 { + compatible = "nxp,74hc4094"; + cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + /* oe-gpios is optional */ + gpio-controller; + #gpio-cells = <2>; + /* We are not cascaded */ + registers-number = <1>; + gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N", + "CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET", + "CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N"; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* 16 MB of Flash mapped in at CS0 */ + reg = <0 0x00000000 0x1000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x0fe0000 */ + fis-index-block = <0x7f>; + }; + }; + }; + + pci@c0000000 { + status = "ok"; + + /* + * The device has 4 slots (IDSEL) with one dedicated IRQ per slot. + * The slots have Ethernet, Ethernet, NEC and MPCI. + * The IDSELs are 11, 12, 13, 14. + */ + interrupt-map = + /* IDSEL 11 - Ethernet A */ + <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */ + <0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */ + <0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */ + <0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */ + /* IDSEL 12 - Ethernet B */ + <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */ + <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */ + <0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */ + <0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */ + /* IDSEL 13 - MPCI */ + <0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */ + <0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */ + <0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */ + <0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */ + /* IDSEL 14 - NEC */ + <0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */ + <0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */ + <0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */ + <0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */ + }; + + /* HSS links */ + npe@c8006000 { + hss@0 { + status = "okay"; + intel,queue-chl-rxtrig = <&qmgr 12>; + intel,queue-chl-txready = <&qmgr 34>; + intel,queue-pkt-rx = <&qmgr 13>; + intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>; + intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>; + intel,queue-pkt-txdone = <&qmgr 22>; + /* The Goramo GPIO-based clock etc control */ + cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>; + clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>; + }; + hss@1 { + status = "okay"; + intel,queue-chl-rxtrig = <&qmgr 10>; + intel,queue-chl-txready = <&qmgr 35>; + intel,queue-pkt-rx = <&qmgr 0>; + intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>; + intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>; + intel,queue-pkt-txdone = <&qmgr 9>; + /* The Goramo GPIO-based clock etc control */ + cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>; + clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>; + }; + }; + + /* EthB */ + ethernet@c8009000 { + status = "ok"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 32>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + /* EthC */ + ethernet@c800a000 { + status = "ok"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 33>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi index 46fede021476..51a716c59669 100644 --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi @@ -139,6 +139,23 @@ npe: npe@c8006000 { compatible = "intel,ixp4xx-network-processing-engine"; reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + /* NPE-A contains two high-speed serial links */ + hss@0 { + compatible = "intel,ixp4xx-hss"; + reg = <0>; + intel,npe-handle = <&npe 0>; + status = "disabled"; + }; + + hss@1 { + compatible = "intel,ixp4xx-hss"; + reg = <1>; + intel,npe-handle = <&npe 0>; + status = "disabled"; + }; /* NPE-C contains a crypto accelerator */ crypto { From 4172986a64dae744abe625075533ce38f6670019 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Wed, 24 Nov 2021 14:32:14 +0530 Subject: [PATCH 210/574] arm64: dts: lx2162a: Add CAN nodes for LX2162A-QDS Enable CAN support for LX2162A-QDS in board dts. Signed-off-by: Kuldeep Singh Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index e1defee1ad27..67e07a8a42bd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -167,6 +167,14 @@ }; }; +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + &crypto { status = "okay"; }; From 474b61a7106b4b5b29eb2d98b0c2ba1e675019d5 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sat, 27 Nov 2021 14:01:18 +0100 Subject: [PATCH 211/574] arm64: dts: imx8mq: fix the schema check errors for fsl,tmu-calibration fsl,tmu-calibration is in u32-matrix. Use matching property syntax. No functional changes. Fixes warnings as: $ make dtbs_check ... arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dt.yaml: tmu@30260000: \ fsl,tmu-calibration:0: Additional items are not allowed (1, 41, 2, 47, \ 3, 53, 4, 61, 5, 67, 6, 75, 7, 81, 8, 87, 9, 95, 10, 103, 11, 111, 65536, \ 27, 65537, 35, 65538, 43, 65539, 51, 65540, 59, 65541, 67, 65542, 75, \ 65543, 85, 65544, 93, 65545, 103, 65546, 112, 131072, 23, 131073, 35, \ 131074, 45, 131075, 55, 131076, 65, 131077, 75, 131078, 87, 131079, 99, \ 131080, 111, 196608, 21, 196609, 33, 196610, 45, 196611, 57, 196612, 69, \ 196613, 83, 196614, 95, 196615, 113 were unexpected) From schema: Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml ... Signed-off-by: David Heidelberg Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 80 +++++++++++------------ 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 95d8b95d6120..5ab9e02bd929 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -457,49 +457,49 @@ clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; little-endian; fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; - fsl,tmu-calibration = <0x00000000 0x00000023 - 0x00000001 0x00000029 - 0x00000002 0x0000002f - 0x00000003 0x00000035 - 0x00000004 0x0000003d - 0x00000005 0x00000043 - 0x00000006 0x0000004b - 0x00000007 0x00000051 - 0x00000008 0x00000057 - 0x00000009 0x0000005f - 0x0000000a 0x00000067 - 0x0000000b 0x0000006f + fsl,tmu-calibration = <0x00000000 0x00000023>, + <0x00000001 0x00000029>, + <0x00000002 0x0000002f>, + <0x00000003 0x00000035>, + <0x00000004 0x0000003d>, + <0x00000005 0x00000043>, + <0x00000006 0x0000004b>, + <0x00000007 0x00000051>, + <0x00000008 0x00000057>, + <0x00000009 0x0000005f>, + <0x0000000a 0x00000067>, + <0x0000000b 0x0000006f>, - 0x00010000 0x0000001b - 0x00010001 0x00000023 - 0x00010002 0x0000002b - 0x00010003 0x00000033 - 0x00010004 0x0000003b - 0x00010005 0x00000043 - 0x00010006 0x0000004b - 0x00010007 0x00000055 - 0x00010008 0x0000005d - 0x00010009 0x00000067 - 0x0001000a 0x00000070 + <0x00010000 0x0000001b>, + <0x00010001 0x00000023>, + <0x00010002 0x0000002b>, + <0x00010003 0x00000033>, + <0x00010004 0x0000003b>, + <0x00010005 0x00000043>, + <0x00010006 0x0000004b>, + <0x00010007 0x00000055>, + <0x00010008 0x0000005d>, + <0x00010009 0x00000067>, + <0x0001000a 0x00000070>, - 0x00020000 0x00000017 - 0x00020001 0x00000023 - 0x00020002 0x0000002d - 0x00020003 0x00000037 - 0x00020004 0x00000041 - 0x00020005 0x0000004b - 0x00020006 0x00000057 - 0x00020007 0x00000063 - 0x00020008 0x0000006f + <0x00020000 0x00000017>, + <0x00020001 0x00000023>, + <0x00020002 0x0000002d>, + <0x00020003 0x00000037>, + <0x00020004 0x00000041>, + <0x00020005 0x0000004b>, + <0x00020006 0x00000057>, + <0x00020007 0x00000063>, + <0x00020008 0x0000006f>, - 0x00030000 0x00000015 - 0x00030001 0x00000021 - 0x00030002 0x0000002d - 0x00030003 0x00000039 - 0x00030004 0x00000045 - 0x00030005 0x00000053 - 0x00030006 0x0000005f - 0x00030007 0x00000071>; + <0x00030000 0x00000015>, + <0x00030001 0x00000021>, + <0x00030002 0x0000002d>, + <0x00030003 0x00000039>, + <0x00030004 0x00000045>, + <0x00030005 0x00000053>, + <0x00030006 0x0000005f>, + <0x00030007 0x00000071>; #thermal-sensor-cells = <1>; }; From e523b7c54c05caec488cc062f0b6c497b1837ed6 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 Nov 2021 06:50:08 -0600 Subject: [PATCH 212/574] arm64: dts: imx8mm: Add CSI nodes There is a csi bridge and csis interface that tie together to allow csi2 capture. Signed-off-by: Adam Ford Reviewed-by: Laurent Pinchart Reviewed-by: Tim Harvey Tested-by: Tim Harvey Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 51 +++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 5b9c2cca9ac4..a31cf2b9769c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1096,6 +1096,22 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + csi: csi@32e20000 { + compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; + reg = <0x32e20000 0x1000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_CSI1_ROOT>; + clock-names = "mclk"; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>; + status = "disabled"; + + port { + csi_in: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_out>; + }; + }; + }; + disp_blk_ctrl: blk-ctrl@32e28000 { compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; @@ -1123,6 +1139,41 @@ #power-domain-cells = <1>; }; + mipi_csi: mipi-csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi2"; + reg = <0x32e30000 0x1000>; + interrupts = ; + assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL2_1000M>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + imx8mm_mipi_csi_out: endpoint { + remote-endpoint = <&csi_in>; + }; + }; + }; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>; From 9f046930657e9e231a2f9139cdcb611805b19d7c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 Nov 2021 06:50:10 -0600 Subject: [PATCH 213/574] arm64: dts: imx8mm-beacon: Enable OV5640 Camera The baseboard has support for a TDNext 5640 Camera which uses an OV5640 connected to a 2-lane CSI2 interface. With the CSI and mipi_csi2 drivers pointing to an OV5640 camera, the media pipeline can be configured with the following: media-ctl --links "'ov5640 1-003c':0->'imx7-mipi-csis.0':0[1]" The camera and various nodes in the pipeline can be configured for UYVY: media-ctl -v -V "'ov5640 1-003c':0 [fmt:UYVY8_1X16/640x480 field:none]" media-ctl -v -V "'csi':0 [fmt:UYVY8_1X16/640x480 field:none]" Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- .../freescale/imx8mm-beacon-baseboard.dtsi | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index 4097a66163b2..0da311898e01 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -54,6 +54,16 @@ enable-active-high; }; + reg_camera: regulator-camera { + compatible = "regulator-fixed"; + regulator-name = "mipi_pwr"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -78,6 +88,10 @@ }; }; +&csi { + status = "okay"; +}; + &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_espi2>; @@ -101,6 +115,30 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clk IMX8MM_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <24000000>; + AVDD-supply = <®_camera>; /* 2.8v */ + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + + port { + /* MIPI CSI-2 bus endpoint */ + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; }; &i2c4 { @@ -152,6 +190,18 @@ }; }; +&mipi_csi { + status = "okay"; + ports { + port@0 { + imx8mm_mipi_csi_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + }; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -238,6 +288,14 @@ >; }; + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + pinctrl_pcal6414: pcal6414-gpiogrp { fsl,pins = < MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 From 8355d48fd1ec1c01b5ab1f8071562cf3e3884214 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 26 Nov 2021 15:40:00 +0800 Subject: [PATCH 214/574] dt-bindings: arm: fsl: Add binding for imx8ulp evk Add the dt binding for i.MX8ULP EVK board. i.MX 8ULP is part of the ULP family with emphasis on extreme low-power techniques using the 28 nm fully depleted silicon on insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be based on asymmetric architecture, however will add a third DSP domain for advanced voice/audio capability and a Graphics domain where it is possible to access graphics resources from the application side or the realtime side. Reviewed-by: Dong Aisheng Acked-by: Rob Herring Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 9679e3cd946a..6604aea7d646 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -872,6 +872,12 @@ properties: - const: toradex,colibri-imx8x - const: fsl,imx8qxp + - description: i.MX8ULP based Boards + items: + - enum: + - fsl,imx8ulp-evk # i.MX8ULP EVK Board + - const: fsl,imx8ulp + - description: Freescale Vybrid Platform Device Tree Bindings From fe6291e963134d3609defff4547beeb2bb5bf158 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 26 Nov 2021 15:40:01 +0800 Subject: [PATCH 215/574] arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp Add the basic dtsi support for i.MX8ULP. i.MX 8ULP is part of the ULP family with emphasis on extreme low-power techniques using the 28 nm fully depleted silicon on insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be based on asymmetric architecture, however will add a third DSP domain for advanced voice/audio capability and a Graphics domain where it is possible to access graphics resources from the application side or the realtime side. Reviewed-by: Dong Aisheng Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8ulp-pinfunc.h | 978 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 396 +++++++ 2 files changed, 1374 insertions(+) create mode 100755 arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h new file mode 100755 index 000000000000..b204ac79b449 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h @@ -0,0 +1,978 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * Copyright 2021 NXP + */ + +#ifndef __DTS_IMX8ULP_PINFUNC_H +#define __DTS_IMX8ULP_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1 +#define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1 +#define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD1__PTD1 0x0004 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD1__I2S6_RX_FS 0x0004 0x0B48 0x7 0x1 +#define MX8ULP_PAD_PTD1__SDHC0_CMD 0x0004 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA7 0x0004 0x0970 0x9 0x1 +#define MX8ULP_PAD_PTD1__EPDC0_SDCLK 0x0004 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD1__DPI0_PCLK 0x0004 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD1__LP_APD_DBG_MUX_1 0x0004 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD1__DEBUG_MUX0_1 0x0004 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD1__DEBUG_MUX1_1 0x0004 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD2__PTD2 0x0008 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD2__I2S6_RXD0 0x0008 0x0B34 0x7 0x1 +#define MX8ULP_PAD_PTD2__SDHC0_CLK 0x0008 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA6 0x0008 0x096C 0x9 0x1 +#define MX8ULP_PAD_PTD2__EPDC0_SDLE 0x0008 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD2__DPI0_HSYNC 0x0008 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD2__LP_APD_DBG_MUX_2 0x0008 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD2__DEBUG_MUX0_2 0x0008 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD2__DEBUG_MUX1_2 0x0008 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD3__PTD3 0x000C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD3__I2S6_RXD1 0x000C 0x0B38 0x7 0x1 +#define MX8ULP_PAD_PTD3__SDHC0_D7 0x000C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD3__FLEXSPI2_B_DATA5 0x000C 0x0968 0x9 0x1 +#define MX8ULP_PAD_PTD3__EPDC0_GDSP 0x000C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD3__DPI0_VSYNC 0x000C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD3__LP_APD_DBG_MUX_3 0x000C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD3__DEBUG_MUX0_3 0x000C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD3__DEBUG_MUX1_3 0x000C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD4__PTD4 0x0010 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD4__EXT_AUD_MCLK3 0x0010 0x0B14 0x4 0x1 +#define MX8ULP_PAD_PTD4__SDHC0_VS 0x0010 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD4__TPM8_CH5 0x0010 0x0B2C 0x6 0x1 +#define MX8ULP_PAD_PTD4__I2S6_MCLK 0x0010 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD4__SDHC0_D6 0x0010 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD4__FLEXSPI2_B_DATA4 0x0010 0x0964 0x9 0x1 +#define MX8ULP_PAD_PTD4__EPDC0_SDCE0 0x0010 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD4__DPI0_DE 0x0010 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD4__LP_APD_DBG_MUX_4 0x0010 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD4__DEBUG_MUX0_4 0x0010 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD4__DEBUG_MUX1_4 0x0010 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD5__PTD5 0x0014 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD5__SDHC0_CD 0x0014 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD5__TPM8_CH4 0x0014 0x0B28 0x6 0x1 +#define MX8ULP_PAD_PTD5__I2S6_TX_BCLK 0x0014 0x0B4C 0x7 0x1 +#define MX8ULP_PAD_PTD5__SDHC0_D5 0x0014 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SS0_B 0x0014 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SCLK_B 0x0014 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD5__EPDC0_D0 0x0014 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD5__DPI0_D0 0x0014 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD5__LP_APD_DBG_MUX_5 0x0014 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD5__DEBUG_MUX0_5 0x0014 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD5__DEBUG_MUX1_5 0x0014 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD6__PTD6 0x0018 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD6__SDHC0_WP 0x0018 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD6__TPM8_CH3 0x0018 0x0B24 0x6 0x1 +#define MX8ULP_PAD_PTD6__I2S6_TX_FS 0x0018 0x0B50 0x7 0x1 +#define MX8ULP_PAD_PTD6__SDHC0_D4 0x0018 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD6__FLEXSPI2_B_SCLK 0x0018 0x0978 0x9 0x1 +#define MX8ULP_PAD_PTD6__EPDC0_D1 0x0018 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD6__DPI0_D1 0x0018 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD6__LP_APD_DBG_MUX_6 0x0018 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD6__DEBUG_MUX0_6 0x0018 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD6__DEBUG_MUX1_6 0x0018 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD7__PTD7 0x001C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD7__TPM8_CH2 0x001C 0x0B20 0x6 0x1 +#define MX8ULP_PAD_PTD7__I2S6_TXD0 0x001C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD7__SDHC0_D3 0x001C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD7__FLEXSPI2_B_DATA3 0x001C 0x0960 0x9 0x1 +#define MX8ULP_PAD_PTD7__EPDC0_D2 0x001C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD7__DPI0_D2 0x001C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD7__LP_APD_DBG_MUX_7 0x001C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD7__DEBUG_MUX0_7 0x001C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD7__DEBUG_MUX1_7 0x001C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD8__PTD8 0x0020 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD8__TPM8_CH1 0x0020 0x0B1C 0x6 0x1 +#define MX8ULP_PAD_PTD8__I2S6_TXD1 0x0020 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD8__SDHC0_D2 0x0020 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD8__FLEXSPI2_B_DATA2 0x0020 0x095C 0x9 0x1 +#define MX8ULP_PAD_PTD8__EPDC0_D3 0x0020 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD8__DPI0_D3 0x0020 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD8__LP_APD_DBG_MUX_8 0x0020 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD8__DEBUG_MUX1_8 0x0020 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD9__PTD9 0x0024 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD9__TPM8_CLKIN 0x0024 0x0B30 0x6 0x1 +#define MX8ULP_PAD_PTD9__I2S6_TXD2 0x0024 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD9__SDHC0_D1 0x0024 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD9__FLEXSPI2_B_DATA1 0x0024 0x0958 0x9 0x1 +#define MX8ULP_PAD_PTD9__EPDC0_D4 0x0024 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD9__DPI0_D4 0x0024 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD9__LP_APD_DBG_MUX_9 0x0024 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD9__DEBUG_MUX1_9 0x0024 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD10__PTD10 0x0028 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD10__TPM8_CH0 0x0028 0x0B18 0x6 0x1 +#define MX8ULP_PAD_PTD10__I2S6_TXD3 0x0028 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD10__SDHC0_D0 0x0028 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD10__FLEXSPI2_B_DATA0 0x0028 0x0954 0x9 0x1 +#define MX8ULP_PAD_PTD10__EPDC0_D5 0x0028 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD10__DPI0_D5 0x0028 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD10__LP_APD_DBG_MUX_10 0x0028 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD10__DEBUG_MUX1_10 0x0028 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD11__PTD11 0x002C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD11__TPM8_CH5 0x002C 0x0B2C 0x6 0x2 +#define MX8ULP_PAD_PTD11__I2S6_RXD2 0x002C 0x0B3C 0x7 0x1 +#define MX8ULP_PAD_PTD11__SDHC0_DQS 0x002C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD11__FLEXSPI2_B_SS0_B 0x002C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD11__FLEXSPI2_A_SS1_B 0x002C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD11__EPDC0_D6 0x002C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD11__DPI0_D6 0x002C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD11__LP_APD_DBG_MUX_11 0x002C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD12__PTD12 0x0030 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD12__USB0_ID 0x0030 0x0AC8 0x5 0x1 +#define MX8ULP_PAD_PTD12__SDHC2_D3 0x0030 0x0AA4 0x6 0x1 +#define MX8ULP_PAD_PTD12__I2S7_RX_BCLK 0x0030 0x0B64 0x7 0x1 +#define MX8ULP_PAD_PTD12__SDHC1_DQS 0x0030 0x0A84 0x8 0x1 +#define MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x0030 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD12__FLEXSPI2_B_SS1_B 0x0030 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD12__EPDC0_D7 0x0030 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD12__DPI0_D7 0x0030 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD12__LP_APD_DBG_MUX_12 0x0030 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD13__PTD13 0x0034 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD13__SPDIF_IN3 0x0034 0x0B80 0x4 0x1 +#define MX8ULP_PAD_PTD13__USB0_PWR 0x0034 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD13__SDHC2_D2 0x0034 0x0AA0 0x6 0x1 +#define MX8ULP_PAD_PTD13__I2S7_RX_FS 0x0034 0x0B68 0x7 0x1 +#define MX8ULP_PAD_PTD13__SDHC1_RESET_B 0x0034 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x0034 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD13__CLKOUT2 0x0034 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD13__EPDC0_D8 0x0034 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD13__DPI0_D8 0x0034 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD13__CLKOUT1 0x0034 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD13__LP_APD_DBG_MUX_13 0x0034 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD14__PTD14 0x0038 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD14__SPDIF_OUT3 0x0038 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD14__USB0_OC 0x0038 0x0AC0 0x5 0x1 +#define MX8ULP_PAD_PTD14__SDHC2_D1 0x0038 0x0A9C 0x6 0x1 +#define MX8ULP_PAD_PTD14__I2S7_RXD0 0x0038 0x0B54 0x7 0x1 +#define MX8ULP_PAD_PTD14__SDHC1_D7 0x0038 0x0A80 0x8 0x1 +#define MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x0038 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD14__TRACE0_D7 0x0038 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD14__EPDC0_D9 0x0038 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD14__DPI0_D9 0x0038 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD14__LP_APD_DBG_MUX_14 0x0038 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD15__PTD15 0x003C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD15__SPDIF_IN2 0x003C 0x0B7C 0x4 0x1 +#define MX8ULP_PAD_PTD15__SDHC1_VS 0x003C 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD15__SDHC2_D0 0x003C 0x0A98 0x6 0x1 +#define MX8ULP_PAD_PTD15__I2S7_TX_BCLK 0x003C 0x0B6C 0x7 0x1 +#define MX8ULP_PAD_PTD15__SDHC1_D6 0x003C 0x0A7C 0x8 0x1 +#define MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x003C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD15__TRACE0_D6 0x003C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD15__EPDC0_D10 0x003C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD15__DPI0_D10 0x003C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD15__LP_APD_DBG_MUX_15 0x003C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD16__PTD16 0x0040 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD16__FXIO1_D31 0x0040 0x08A0 0x2 0x1 +#define MX8ULP_PAD_PTD16__LPSPI4_PCS1 0x0040 0x08F8 0x3 0x1 +#define MX8ULP_PAD_PTD16__SPDIF_OUT2 0x0040 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD16__SDHC1_CD 0x0040 0x0A58 0x5 0x1 +#define MX8ULP_PAD_PTD16__SDHC2_CLK 0x0040 0x0A90 0x6 0x1 +#define MX8ULP_PAD_PTD16__I2S7_TX_FS 0x0040 0x0B70 0x7 0x1 +#define MX8ULP_PAD_PTD16__SDHC1_D5 0x0040 0x0A78 0x8 0x1 +#define MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x0040 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD16__TRACE0_D5 0x0040 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD16__EPDC0_D11 0x0040 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD16__DPI0_D11 0x0040 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD16__LP_APD_DBG_MUX_16 0x0040 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD17__PTD17 0x0044 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD17__FXIO1_D30 0x0044 0x089C 0x2 0x1 +#define MX8ULP_PAD_PTD17__LPSPI4_PCS2 0x0044 0x08FC 0x3 0x1 +#define MX8ULP_PAD_PTD17__EXT_AUD_MCLK3 0x0044 0x0B14 0x4 0x2 +#define MX8ULP_PAD_PTD17__SDHC1_WP 0x0044 0x0A88 0x5 0x1 +#define MX8ULP_PAD_PTD17__SDHC2_CMD 0x0044 0x0A94 0x6 0x1 +#define MX8ULP_PAD_PTD17__I2S7_TXD0 0x0044 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD17__SDHC1_D4 0x0044 0x0A74 0x8 0x1 +#define MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x0044 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD17__TRACE0_D4 0x0044 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD17__EPDC0_D12 0x0044 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD17__DPI0_D12 0x0044 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD17__LP_APD_DBG_MUX_17 0x0044 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD18__PTD18 0x0048 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD18__FXIO1_D29 0x0048 0x0894 0x2 0x1 +#define MX8ULP_PAD_PTD18__LPSPI4_PCS3 0x0048 0x0900 0x3 0x1 +#define MX8ULP_PAD_PTD18__SPDIF_CLK 0x0048 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD18__EXT_AUD_MCLK3 0x0048 0x0B14 0x5 0x3 +#define MX8ULP_PAD_PTD18__TPM8_CH0 0x0048 0x0B18 0x6 0x2 +#define MX8ULP_PAD_PTD18__I2S7_MCLK 0x0048 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD18__SDHC1_D3 0x0048 0x0A70 0x8 0x1 +#define MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x0048 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD18__TRACE0_D3 0x0048 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD18__EPDC0_D13 0x0048 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD18__DPI0_D13 0x0048 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD18__LP_APD_DBG_MUX_18 0x0048 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD19__PTD19 0x004C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD19__FXIO1_D28 0x004C 0x0890 0x2 0x1 +#define MX8ULP_PAD_PTD19__SPDIF_IN0 0x004C 0x0B74 0x4 0x1 +#define MX8ULP_PAD_PTD19__TPM8_CH1 0x004C 0x0B1C 0x6 0x2 +#define MX8ULP_PAD_PTD19__I2S6_RXD3 0x004C 0x0B40 0x7 0x1 +#define MX8ULP_PAD_PTD19__SDHC1_D2 0x004C 0x0A6C 0x8 0x1 +#define MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x004C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD19__TRACE0_D2 0x004C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD19__EPDC0_D14 0x004C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD19__DPI0_D14 0x004C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD19__LP_APD_DBG_MUX_19 0x004C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD20__PTD20 0x0050 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD20__FXIO1_D27 0x0050 0x088C 0x2 0x1 +#define MX8ULP_PAD_PTD20__LPSPI4_SIN 0x0050 0x0908 0x3 0x1 +#define MX8ULP_PAD_PTD20__SPDIF_OUT0 0x0050 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD20__TPM8_CLKIN 0x0050 0x0B30 0x6 0x2 +#define MX8ULP_PAD_PTD20__I2S7_RXD1 0x0050 0x0B58 0x7 0x1 +#define MX8ULP_PAD_PTD20__SDHC1_D1 0x0050 0x0A68 0x8 0x1 +#define MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x0050 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD20__TRACE0_D1 0x0050 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD20__EPDC0_D15 0x0050 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD20__DPI0_D15 0x0050 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD20__LP_APD_DBG_MUX_20 0x0050 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD21__PTD21 0x0054 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD21__FXIO1_D26 0x0054 0x0888 0x2 0x1 +#define MX8ULP_PAD_PTD21__LPSPI4_SOUT 0x0054 0x090C 0x3 0x1 +#define MX8ULP_PAD_PTD21__SPDIF_IN1 0x0054 0x0B78 0x4 0x1 +#define MX8ULP_PAD_PTD21__USB1_PWR 0x0054 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD21__TPM8_CH2 0x0054 0x0B20 0x6 0x2 +#define MX8ULP_PAD_PTD21__I2S7_TXD1 0x0054 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD21__SDHC1_D0 0x0054 0x0A64 0x8 0x1 +#define MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x0054 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD21__TRACE0_D0 0x0054 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD21__DPI0_D16 0x0054 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD21__WDOG5_RST 0x0054 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD21__LP_APD_DBG_MUX_21 0x0054 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD22__PTD22 0x0058 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD22__FXIO1_D25 0x0058 0x0884 0x2 0x1 +#define MX8ULP_PAD_PTD22__LPSPI4_SCK 0x0058 0x0904 0x3 0x1 +#define MX8ULP_PAD_PTD22__SPDIF_OUT1 0x0058 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD22__USB1_OC 0x0058 0x0AC4 0x5 0x1 +#define MX8ULP_PAD_PTD22__TPM8_CH3 0x0058 0x0B24 0x6 0x2 +#define MX8ULP_PAD_PTD22__I2S7_TXD2 0x0058 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD22__SDHC1_CLK 0x0058 0x0A5C 0x8 0x1 +#define MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x0058 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD22__TRACE0_CLKOUT 0x0058 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD22__DPI0_D17 0x0058 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD22__LP_APD_DBG_MUX_22 0x0058 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD23__PTD23 0x005C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD23__FXIO1_D24 0x005C 0x0880 0x2 0x1 +#define MX8ULP_PAD_PTD23__LPSPI4_PCS0 0x005C 0x08F4 0x3 0x1 +#define MX8ULP_PAD_PTD23__USB1_ID 0x005C 0x0ACC 0x5 0x1 +#define MX8ULP_PAD_PTD23__TPM8_CH4 0x005C 0x0B28 0x6 0x2 +#define MX8ULP_PAD_PTD23__I2S7_TXD3 0x005C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD23__SDHC1_CMD 0x005C 0x0A60 0x8 0x1 +#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SS0_B 0x005C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SCLK_B 0x005C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD23__DPI0_D18 0x005C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD23__LP_APD_DBG_MUX_23 0x005C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE0__PTE0 0x0080 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE0__FXIO1_D23 0x0080 0x087C 0x2 0x1 +#define MX8ULP_PAD_PTE0__SPDIF_IN3 0x0080 0x0B80 0x3 0x2 +#define MX8ULP_PAD_PTE0__LPUART4_CTS_B 0x0080 0x08DC 0x4 0x1 +#define MX8ULP_PAD_PTE0__LPI2C4_SCL 0x0080 0x08C8 0x5 0x1 +#define MX8ULP_PAD_PTE0__TPM8_CLKIN 0x0080 0x0B30 0x6 0x3 +#define MX8ULP_PAD_PTE0__I2S7_RXD2 0x0080 0x0B5C 0x7 0x1 +#define MX8ULP_PAD_PTE0__SDHC2_D1 0x0080 0x0A9C 0x8 0x2 +#define MX8ULP_PAD_PTE0__FLEXSPI2_B_DQS 0x0080 0x0974 0x9 0x2 +#define MX8ULP_PAD_PTE0__ENET0_CRS 0x0080 0x0AE8 0xa 0x1 +#define MX8ULP_PAD_PTE0__DBI0_WRX 0x0080 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE0__DPI0_D19 0x0080 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE0__WUU1_P0 0x0080 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE0__DEBUG_MUX0_8 0x0080 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE0__DEBUG_MUX1_11 0x0080 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE1__PTE1 0x0084 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE1__FXIO1_D22 0x0084 0x0878 0x2 0x1 +#define MX8ULP_PAD_PTE1__SPDIF_OUT3 0x0084 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE1__LPUART4_RTS_B 0x0084 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE1__LPI2C4_SDA 0x0084 0x08CC 0x5 0x1 +#define MX8ULP_PAD_PTE1__TPM8_CH0 0x0084 0x0B18 0x6 0x3 +#define MX8ULP_PAD_PTE1__I2S7_RXD3 0x0084 0x0B60 0x7 0x1 +#define MX8ULP_PAD_PTE1__SDHC2_D0 0x0084 0x0A98 0x8 0x2 +#define MX8ULP_PAD_PTE1__FLEXSPI2_B_DATA7 0x0084 0x0970 0x9 0x2 +#define MX8ULP_PAD_PTE1__ENET0_COL 0x0084 0x0AE4 0xa 0x1 +#define MX8ULP_PAD_PTE1__DBI0_CSX 0x0084 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE1__DPI0_D20 0x0084 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE1__WUU1_P1 0x0084 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE1__DEBUG_MUX0_9 0x0084 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE1__DEBUG_MUX1_12 0x0084 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE2__PTE2 0x0088 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE2__FXIO1_D21 0x0088 0x0874 0x2 0x1 +#define MX8ULP_PAD_PTE2__SPDIF_IN2 0x0088 0x0B7C 0x3 0x2 +#define MX8ULP_PAD_PTE2__LPUART4_TX 0x0088 0x08E4 0x4 0x1 +#define MX8ULP_PAD_PTE2__LPI2C4_HREQ 0x0088 0x08C4 0x5 0x1 +#define MX8ULP_PAD_PTE2__TPM8_CH1 0x0088 0x0B1C 0x6 0x3 +#define MX8ULP_PAD_PTE2__EXT_AUD_MCLK3 0x0088 0x0B14 0x7 0x4 +#define MX8ULP_PAD_PTE2__SDHC2_CLK 0x0088 0x0A90 0x8 0x2 +#define MX8ULP_PAD_PTE2__FLEXSPI2_B_DATA6 0x0088 0x096C 0x9 0x2 +#define MX8ULP_PAD_PTE2__ENET0_TXER 0x0088 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE2__DBI0_DCX 0x0088 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE2__DPI0_D21 0x0088 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE2__LP_HV_DBG_MUX_0 0x0088 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE2__DEBUG_MUX0_10 0x0088 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE2__DEBUG_MUX1_13 0x0088 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE3__PTE3 0x008C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE3__FXIO1_D20 0x008C 0x0870 0x2 0x1 +#define MX8ULP_PAD_PTE3__SPDIF_OUT2 0x008C 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE3__LPUART4_RX 0x008C 0x08E0 0x4 0x1 +#define MX8ULP_PAD_PTE3__TPM8_CH2 0x008C 0x0B20 0x6 0x3 +#define MX8ULP_PAD_PTE3__I2S6_MCLK 0x008C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE3__SDHC2_CMD 0x008C 0x0A94 0x8 0x2 +#define MX8ULP_PAD_PTE3__FLEXSPI2_B_DATA5 0x008C 0x0968 0x9 0x2 +#define MX8ULP_PAD_PTE3__ENET0_TXCLK 0x008C 0x0B10 0xa 0x1 +#define MX8ULP_PAD_PTE3__DBI0_RWX 0x008C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE3__DPI0_D22 0x008C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE3__WUU1_P2 0x008C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE3__DEBUG_MUX0_11 0x008C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE3__DEBUG_MUX1_14 0x008C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE4__PTE4 0x0090 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE4__FXIO1_D19 0x0090 0x0868 0x2 0x1 +#define MX8ULP_PAD_PTE4__SPDIF_CLK 0x0090 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE4__LPUART5_CTS_B 0x0090 0x08E8 0x4 0x1 +#define MX8ULP_PAD_PTE4__LPI2C5_SCL 0x0090 0x08D4 0x5 0x1 +#define MX8ULP_PAD_PTE4__TPM8_CH3 0x0090 0x0B24 0x6 0x3 +#define MX8ULP_PAD_PTE4__I2S6_RX_BCLK 0x0090 0x0B44 0x7 0x2 +#define MX8ULP_PAD_PTE4__SDHC2_D3 0x0090 0x0AA4 0x8 0x2 +#define MX8ULP_PAD_PTE4__FLEXSPI2_B_DATA4 0x0090 0x0964 0x9 0x2 +#define MX8ULP_PAD_PTE4__ENET0_TXD3 0x0090 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE4__DBI0_E 0x0090 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE4__DPI0_D23 0x0090 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE4__WUU1_P3 0x0090 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE4__DEBUG_MUX0_12 0x0090 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE4__DEBUG_MUX1_15 0x0090 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE5__PTE5 0x0094 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE5__FXIO1_D18 0x0094 0x0864 0x2 0x1 +#define MX8ULP_PAD_PTE5__SPDIF_IN0 0x0094 0x0B74 0x3 0x2 +#define MX8ULP_PAD_PTE5__LPUART5_RTS_B 0x0094 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE5__LPI2C5_SDA 0x0094 0x08D8 0x5 0x1 +#define MX8ULP_PAD_PTE5__TPM8_CH4 0x0094 0x0B28 0x6 0x3 +#define MX8ULP_PAD_PTE5__I2S6_RX_FS 0x0094 0x0B48 0x7 0x2 +#define MX8ULP_PAD_PTE5__SDHC2_D2 0x0094 0x0AA0 0x8 0x2 +#define MX8ULP_PAD_PTE5__FLEXSPI2_B_SS0_B 0x0094 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE5__ENET0_TXD2 0x0094 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE5__DBI0_D0 0x0094 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE5__LP_HV_DBG_MUX_1 0x0094 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE5__DEBUG_MUX0_13 0x0094 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE5__DEBUG_MUX1_16 0x0094 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE6__PTE6 0x0098 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE6__FXIO1_D17 0x0098 0x0860 0x2 0x1 +#define MX8ULP_PAD_PTE6__SPDIF_OUT0 0x0098 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE6__LPUART5_TX 0x0098 0x08F0 0x4 0x1 +#define MX8ULP_PAD_PTE6__LPI2C5_HREQ 0x0098 0x08D0 0x5 0x1 +#define MX8ULP_PAD_PTE6__TPM8_CH5 0x0098 0x0B2C 0x6 0x3 +#define MX8ULP_PAD_PTE6__I2S6_RXD0 0x0098 0x0B34 0x7 0x2 +#define MX8ULP_PAD_PTE6__SDHC2_D4 0x0098 0x0AA8 0x8 0x1 +#define MX8ULP_PAD_PTE6__FLEXSPI2_B_SCLK 0x0098 0x0978 0x9 0x2 +#define MX8ULP_PAD_PTE6__ENET0_RXCLK 0x0098 0x0B0C 0xa 0x1 +#define MX8ULP_PAD_PTE6__DBI0_D1 0x0098 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE6__LP_HV_DBG_MUX_2 0x0098 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE6__WDOG5_RST 0x0098 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE6__DEBUG_MUX0_14 0x0098 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE6__DEBUG_MUX1_17 0x0098 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE7__PTE7 0x009C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE7__FXIO1_D16 0x009C 0x085C 0x2 0x1 +#define MX8ULP_PAD_PTE7__SPDIF_IN1 0x009C 0x0B78 0x3 0x2 +#define MX8ULP_PAD_PTE7__LPUART5_RX 0x009C 0x08EC 0x4 0x1 +#define MX8ULP_PAD_PTE7__LPI2C6_HREQ 0x009C 0x09B4 0x5 0x1 +#define MX8ULP_PAD_PTE7__TPM4_CLKIN 0x009C 0x081C 0x6 0x1 +#define MX8ULP_PAD_PTE7__I2S6_RXD1 0x009C 0x0B38 0x7 0x2 +#define MX8ULP_PAD_PTE7__SDHC2_D5 0x009C 0x0AAC 0x8 0x1 +#define MX8ULP_PAD_PTE7__FLEXSPI2_B_DATA3 0x009C 0x0960 0x9 0x2 +#define MX8ULP_PAD_PTE7__ENET0_RXD3 0x009C 0x0B04 0xa 0x1 +#define MX8ULP_PAD_PTE7__DBI0_D2 0x009C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE7__EPDC0_BDR1 0x009C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE7__WUU1_P4 0x009C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE7__DEBUG_MUX0_15 0x009C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE7__DEBUG_MUX1_18 0x009C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE8__PTE8 0x00A0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE8__FXIO1_D15 0x00A0 0x0858 0x2 0x1 +#define MX8ULP_PAD_PTE8__LPSPI4_PCS1 0x00A0 0x08F8 0x3 0x2 +#define MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x00A0 0x09CC 0x4 0x1 +#define MX8ULP_PAD_PTE8__LPI2C6_SCL 0x00A0 0x09B8 0x5 0x1 +#define MX8ULP_PAD_PTE8__TPM4_CH0 0x00A0 0x0804 0x6 0x1 +#define MX8ULP_PAD_PTE8__I2S6_RXD2 0x00A0 0x0B3C 0x7 0x2 +#define MX8ULP_PAD_PTE8__SDHC2_D6 0x00A0 0x0AB0 0x8 0x1 +#define MX8ULP_PAD_PTE8__FLEXSPI2_B_DATA2 0x00A0 0x095C 0x9 0x2 +#define MX8ULP_PAD_PTE8__ENET0_RXD2 0x00A0 0x0B00 0xa 0x1 +#define MX8ULP_PAD_PTE8__DBI0_D3 0x00A0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE8__EPDC0_BDR0 0x00A0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE8__LP_HV_DBG_MUX_3 0x00A0 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE8__DEBUG_MUX1_19 0x00A0 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE9__PTE9 0x00A4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE9__FXIO1_D14 0x00A4 0x0854 0x2 0x1 +#define MX8ULP_PAD_PTE9__LPSPI4_PCS2 0x00A4 0x08FC 0x3 0x2 +#define MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x00A4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE9__LPI2C6_SDA 0x00A4 0x09BC 0x5 0x1 +#define MX8ULP_PAD_PTE9__TPM4_CH1 0x00A4 0x0808 0x6 0x1 +#define MX8ULP_PAD_PTE9__I2S6_RXD3 0x00A4 0x0B40 0x7 0x2 +#define MX8ULP_PAD_PTE9__SDHC2_D7 0x00A4 0x0AB4 0x8 0x1 +#define MX8ULP_PAD_PTE9__FLEXSPI2_B_DATA1 0x00A4 0x0958 0x9 0x2 +#define MX8ULP_PAD_PTE9__ENET0_1588_TMR3 0x00A4 0x0AE0 0xa 0x1 +#define MX8ULP_PAD_PTE9__DBI0_D4 0x00A4 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE9__EPDC0_VCOM1 0x00A4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE9__LP_HV_DBG_MUX_4 0x00A4 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE9__DEBUG_MUX1_20 0x00A4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE10__PTE10 0x00A8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE10__FXIO1_D13 0x00A8 0x0850 0x2 0x1 +#define MX8ULP_PAD_PTE10__LPSPI4_PCS3 0x00A8 0x0900 0x3 0x2 +#define MX8ULP_PAD_PTE10__LPUART6_TX 0x00A8 0x09D4 0x4 0x1 +#define MX8ULP_PAD_PTE10__I3C2_SCL 0x00A8 0x08BC 0x5 0x1 +#define MX8ULP_PAD_PTE10__TPM4_CH2 0x00A8 0x080C 0x6 0x1 +#define MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x00A8 0x0B4C 0x7 0x2 +#define MX8ULP_PAD_PTE10__SDHC2_DQS 0x00A8 0x0AB8 0x8 0x1 +#define MX8ULP_PAD_PTE10__FLEXSPI2_B_DATA0 0x00A8 0x0954 0x9 0x2 +#define MX8ULP_PAD_PTE10__ENET0_1588_TMR2 0x00A8 0x0ADC 0xa 0x1 +#define MX8ULP_PAD_PTE10__DBI0_D5 0x00A8 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE10__EPDC0_VCOM0 0x00A8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE10__LP_HV_DBG_MUX_5 0x00A8 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE10__DEBUG_MUX1_21 0x00A8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE11__PTE11 0x00AC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE11__FXIO1_D12 0x00AC 0x084C 0x2 0x1 +#define MX8ULP_PAD_PTE11__SPDIF_OUT1 0x00AC 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE11__LPUART6_RX 0x00AC 0x09D0 0x4 0x1 +#define MX8ULP_PAD_PTE11__I3C2_SDA 0x00AC 0x08C0 0x5 0x1 +#define MX8ULP_PAD_PTE11__TPM4_CH3 0x00AC 0x0810 0x6 0x1 +#define MX8ULP_PAD_PTE11__I2S6_TX_FS 0x00AC 0x0B50 0x7 0x2 +#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SCLK_B 0x00AC 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SS0_B 0x00AC 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE11__ENET0_1588_TMR1 0x00AC 0x0AD8 0xa 0x1 +#define MX8ULP_PAD_PTE11__DBI0_D6 0x00AC 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE11__EPDC0_PWRCTRL0 0x00AC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE11__LP_HV_DBG_MUX_6 0x00AC 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE12__PTE12 0x00B0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE12__FXIO1_D11 0x00B0 0x0848 0x2 0x1 +#define MX8ULP_PAD_PTE12__LPSPI4_SIN 0x00B0 0x0908 0x3 0x2 +#define MX8ULP_PAD_PTE12__LPUART7_CTS_B 0x00B0 0x09D8 0x4 0x1 +#define MX8ULP_PAD_PTE12__LPI2C7_SCL 0x00B0 0x09C4 0x5 0x1 +#define MX8ULP_PAD_PTE12__TPM4_CH4 0x00B0 0x0814 0x6 0x1 +#define MX8ULP_PAD_PTE12__I2S6_TXD0 0x00B0 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE12__SDHC2_RESET_B 0x00B0 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE12__FLEXSPI2_B_SS1_B 0x00B0 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE12__ENET0_1588_TMR0 0x00B0 0x0AD4 0xa 0x1 +#define MX8ULP_PAD_PTE12__DBI0_D7 0x00B0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE12__EPDC0_PWRCTRL1 0x00B0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE12__WUU1_P5 0x00B0 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE13__PTE13 0x00B4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE13__FXIO1_D10 0x00B4 0x0844 0x2 0x1 +#define MX8ULP_PAD_PTE13__LPSPI4_SOUT 0x00B4 0x090C 0x3 0x2 +#define MX8ULP_PAD_PTE13__LPUART7_RTS_B 0x00B4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE13__LPI2C7_SDA 0x00B4 0x09C8 0x5 0x1 +#define MX8ULP_PAD_PTE13__TPM4_CH5 0x00B4 0x0818 0x6 0x1 +#define MX8ULP_PAD_PTE13__I2S6_TXD1 0x00B4 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE13__SDHC1_WP 0x00B4 0x0A88 0x8 0x2 +#define MX8ULP_PAD_PTE13__ENET0_1588_CLKIN 0x00B4 0x0AD0 0xa 0x1 +#define MX8ULP_PAD_PTE13__DBI0_D8 0x00B4 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE13__EPDC0_PWRCTRL2 0x00B4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE13__LP_HV_DBG_MUX_7 0x00B4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE14__PTE14 0x00B8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE14__FXIO1_D9 0x00B8 0x08B8 0x2 0x1 +#define MX8ULP_PAD_PTE14__LPSPI4_SCK 0x00B8 0x0904 0x3 0x2 +#define MX8ULP_PAD_PTE14__LPUART7_TX 0x00B8 0x09E0 0x4 0x1 +#define MX8ULP_PAD_PTE14__LPI2C7_HREQ 0x00B8 0x09C0 0x5 0x1 +#define MX8ULP_PAD_PTE14__TPM5_CLKIN 0x00B8 0x0838 0x6 0x1 +#define MX8ULP_PAD_PTE14__I2S6_TXD2 0x00B8 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE14__SDHC1_CD 0x00B8 0x0A58 0x8 0x2 +#define MX8ULP_PAD_PTE14__ENET0_MDIO 0x00B8 0x0AF0 0xa 0x1 +#define MX8ULP_PAD_PTE14__DBI0_D9 0x00B8 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE14__EPDC0_PWRCTRL3 0x00B8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE14__LP_HV_DBG_MUX_8 0x00B8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE15__PTE15 0x00BC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE15__FXIO1_D8 0x00BC 0x08B4 0x2 0x1 +#define MX8ULP_PAD_PTE15__LPSPI4_PCS0 0x00BC 0x08F4 0x3 0x2 +#define MX8ULP_PAD_PTE15__LPUART7_RX 0x00BC 0x09DC 0x4 0x1 +#define MX8ULP_PAD_PTE15__I3C2_PUR 0x00BC 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTE15__TPM5_CH0 0x00BC 0x0820 0x6 0x1 +#define MX8ULP_PAD_PTE15__I2S6_TXD3 0x00BC 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE15__MQS1_LEFT 0x00BC 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE15__ENET0_MDC 0x00BC 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE15__DBI0_D10 0x00BC 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE15__EPDC0_PWRCOM 0x00BC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE15__WUU1_P6 0x00BC 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE16__PTE16 0x00C0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE16__FXIO1_D7 0x00C0 0x08B0 0x2 0x1 +#define MX8ULP_PAD_PTE16__LPSPI5_PCS1 0x00C0 0x0914 0x3 0x1 +#define MX8ULP_PAD_PTE16__LPUART4_CTS_B 0x00C0 0x08DC 0x4 0x2 +#define MX8ULP_PAD_PTE16__LPI2C4_SCL 0x00C0 0x08C8 0x5 0x2 +#define MX8ULP_PAD_PTE16__TPM5_CH1 0x00C0 0x0824 0x6 0x1 +#define MX8ULP_PAD_PTE16__MQS1_LEFT 0x00C0 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE16__MQS1_RIGHT 0x00C0 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE16__USB0_ID 0x00C0 0x0AC8 0x9 0x2 +#define MX8ULP_PAD_PTE16__ENET0_TXEN 0x00C0 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE16__DBI0_D11 0x00C0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE16__EPDC0_PWRIRQ 0x00C0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE16__WDOG3_RST 0x00C0 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE16__LP_HV_DBG_MUX_9 0x00C0 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE17__PTE17 0x00C4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE17__FXIO1_D6 0x00C4 0x08AC 0x2 0x1 +#define MX8ULP_PAD_PTE17__LPSPI5_PCS2 0x00C4 0x0918 0x3 0x1 +#define MX8ULP_PAD_PTE17__LPUART4_RTS_B 0x00C4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE17__LPI2C4_SDA 0x00C4 0x08CC 0x5 0x2 +#define MX8ULP_PAD_PTE17__MQS1_RIGHT 0x00C4 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE17__SDHC1_VS 0x00C4 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE17__USB0_PWR 0x00C4 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE17__ENET0_RXER 0x00C4 0x0B08 0xa 0x1 +#define MX8ULP_PAD_PTE17__DBI0_D12 0x00C4 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE17__EPDC0_PWRSTAT 0x00C4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE17__LP_HV_DBG_MUX_10 0x00C4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE18__PTE18 0x00C8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE18__FXIO1_D5 0x00C8 0x08A8 0x2 0x1 +#define MX8ULP_PAD_PTE18__LPSPI5_PCS3 0x00C8 0x091C 0x3 0x1 +#define MX8ULP_PAD_PTE18__LPUART4_TX 0x00C8 0x08E4 0x4 0x2 +#define MX8ULP_PAD_PTE18__LPI2C4_HREQ 0x00C8 0x08C4 0x5 0x2 +#define MX8ULP_PAD_PTE18__I2S7_TX_BCLK 0x00C8 0x0B6C 0x7 0x2 +#define MX8ULP_PAD_PTE18__USB0_OC 0x00C8 0x0AC0 0x9 0x2 +#define MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x00C8 0x0AEC 0xa 0x1 +#define MX8ULP_PAD_PTE18__DBI0_D13 0x00C8 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE18__EPDC0_PWRWAKE 0x00C8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE18__LP_HV_DBG_MUX_11 0x00C8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE19__PTE19 0x00CC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE19__FXIO1_D4 0x00CC 0x08A4 0x2 0x1 +#define MX8ULP_PAD_PTE19__LPUART4_RX 0x00CC 0x08E0 0x4 0x2 +#define MX8ULP_PAD_PTE19__LPI2C5_HREQ 0x00CC 0x08D0 0x5 0x2 +#define MX8ULP_PAD_PTE19__I3C2_PUR 0x00CC 0x0000 0x6 0x0 +#define MX8ULP_PAD_PTE19__I2S7_TX_FS 0x00CC 0x0B70 0x7 0x2 +#define MX8ULP_PAD_PTE19__USB1_PWR 0x00CC 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE19__ENET0_REFCLK 0x00CC 0x0AF4 0xa 0x1 +#define MX8ULP_PAD_PTE19__DBI0_D14 0x00CC 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE19__EPDC0_GDCLK 0x00CC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE19__WUU1_P7 0x00CC 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE20__PTE20 0x00D0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE20__FXIO1_D3 0x00D0 0x0898 0x2 0x1 +#define MX8ULP_PAD_PTE20__LPSPI5_SIN 0x00D0 0x0924 0x3 0x1 +#define MX8ULP_PAD_PTE20__LPUART5_CTS_B 0x00D0 0x08E8 0x4 0x2 +#define MX8ULP_PAD_PTE20__LPI2C5_SCL 0x00D0 0x08D4 0x5 0x2 +#define MX8ULP_PAD_PTE20__I2S7_TXD0 0x00D0 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE20__USB1_OC 0x00D0 0x0AC4 0x9 0x2 +#define MX8ULP_PAD_PTE20__ENET0_RXD1 0x00D0 0x0AFC 0xa 0x1 +#define MX8ULP_PAD_PTE20__DBI0_D15 0x00D0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE20__EPDC0_GDOE 0x00D0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE20__LP_HV_DBG_MUX_12 0x00D0 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE21__PTE21 0x00D4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE21__FXIO1_D2 0x00D4 0x086C 0x2 0x1 +#define MX8ULP_PAD_PTE21__LPSPI5_SOUT 0x00D4 0x0928 0x3 0x1 +#define MX8ULP_PAD_PTE21__LPUART5_RTS_B 0x00D4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE21__LPI2C5_SDA 0x00D4 0x08D8 0x5 0x2 +#define MX8ULP_PAD_PTE21__TPM6_CLKIN 0x00D4 0x0994 0x6 0x1 +#define MX8ULP_PAD_PTE21__I2S7_TXD1 0x00D4 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE21__USB1_ID 0x00D4 0x0ACC 0x9 0x2 +#define MX8ULP_PAD_PTE21__ENET0_RXD0 0x00D4 0x0AF8 0xa 0x1 +#define MX8ULP_PAD_PTE21__EPDC0_GDRL 0x00D4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE21__WDOG4_RST 0x00D4 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE21__LP_HV_DBG_MUX_13 0x00D4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE22__PTE22 0x00D8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE22__FXIO1_D1 0x00D8 0x0840 0x2 0x1 +#define MX8ULP_PAD_PTE22__LPSPI5_SCK 0x00D8 0x0920 0x3 0x1 +#define MX8ULP_PAD_PTE22__LPUART5_TX 0x00D8 0x08F0 0x4 0x2 +#define MX8ULP_PAD_PTE22__I3C2_SCL 0x00D8 0x08BC 0x5 0x2 +#define MX8ULP_PAD_PTE22__TPM6_CH0 0x00D8 0x097C 0x6 0x1 +#define MX8ULP_PAD_PTE22__I2S7_TXD2 0x00D8 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE22__EXT_AUD_MCLK3 0x00D8 0x0B14 0x9 0x5 +#define MX8ULP_PAD_PTE22__ENET0_TXD1 0x00D8 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE22__EPDC0_SDOED 0x00D8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE22__CLKOUT2 0x00D8 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE22__LP_HV_DBG_MUX_14 0x00D8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE23__PTE23 0x00DC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE23__FXIO1_D0 0x00DC 0x083C 0x2 0x1 +#define MX8ULP_PAD_PTE23__LPSPI5_PCS0 0x00DC 0x0910 0x3 0x1 +#define MX8ULP_PAD_PTE23__LPUART5_RX 0x00DC 0x08EC 0x4 0x2 +#define MX8ULP_PAD_PTE23__I3C2_SDA 0x00DC 0x08C0 0x5 0x2 +#define MX8ULP_PAD_PTE23__TPM6_CH1 0x00DC 0x0980 0x6 0x1 +#define MX8ULP_PAD_PTE23__I2S7_TXD3 0x00DC 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE23__EXT_AUD_MCLK2 0x00DC 0x0800 0x9 0x1 +#define MX8ULP_PAD_PTE23__ENET0_TXD0 0x00DC 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE23__EPDC0_SDOEZ 0x00DC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE23__CLKOUT1 0x00DC 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE23__LP_HV_DBG_MUX_15 0x00DC 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF0__PTF0 0x0100 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF0__FXIO1_D0 0x0100 0x083C 0x2 0x2 +#define MX8ULP_PAD_PTF0__LPUART6_CTS_B 0x0100 0x09CC 0x4 0x2 +#define MX8ULP_PAD_PTF0__LPI2C6_SCL 0x0100 0x09B8 0x5 0x2 +#define MX8ULP_PAD_PTF0__I2S7_RX_BCLK 0x0100 0x0B64 0x7 0x2 +#define MX8ULP_PAD_PTF0__SDHC1_D1 0x0100 0x0A68 0x8 0x2 +#define MX8ULP_PAD_PTF0__ENET0_RXD1 0x0100 0x0AFC 0x9 0x2 +#define MX8ULP_PAD_PTF0__USB1_ID 0x0100 0x0ACC 0xa 0x3 +#define MX8ULP_PAD_PTF0__EPDC0_SDOE 0x0100 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF0__DPI0_D23 0x0100 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF0__WUU1_P8 0x0100 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF1__PTF1 0x0104 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF1__FXIO1_D1 0x0104 0x0840 0x2 0x2 +#define MX8ULP_PAD_PTF1__LPUART6_RTS_B 0x0104 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF1__LPI2C6_SDA 0x0104 0x09BC 0x5 0x2 +#define MX8ULP_PAD_PTF1__I2S7_RX_FS 0x0104 0x0B68 0x7 0x2 +#define MX8ULP_PAD_PTF1__SDHC1_D0 0x0104 0x0A64 0x8 0x2 +#define MX8ULP_PAD_PTF1__ENET0_RXD0 0x0104 0x0AF8 0x9 0x2 +#define MX8ULP_PAD_PTF1__LP_HV_DBG_MUX_16 0x0104 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF1__EPDC0_SDSHR 0x0104 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF1__DPI0_D22 0x0104 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF1__WDOG3_RST 0x0104 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF1__DEBUG_MUX0_16 0x0104 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF1__DEBUG_MUX1_22 0x0104 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF2__PTF2 0x0108 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF2__FXIO1_D2 0x0108 0x086C 0x2 0x2 +#define MX8ULP_PAD_PTF2__LPUART6_TX 0x0108 0x09D4 0x4 0x2 +#define MX8ULP_PAD_PTF2__LPI2C6_HREQ 0x0108 0x09B4 0x5 0x2 +#define MX8ULP_PAD_PTF2__I2S7_RXD0 0x0108 0x0B54 0x7 0x2 +#define MX8ULP_PAD_PTF2__SDHC1_CLK 0x0108 0x0A5C 0x8 0x2 +#define MX8ULP_PAD_PTF2__ENET0_TXD1 0x0108 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF2__USB0_ID 0x0108 0x0AC8 0xa 0x3 +#define MX8ULP_PAD_PTF2__EPDC0_SDCE9 0x0108 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF2__DPI0_D21 0x0108 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF2__LP_HV_DBG_MUX_17 0x0108 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF2__DEBUG_MUX0_17 0x0108 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF2__DEBUG_MUX1_23 0x0108 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF3__PTF3 0x010C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF3__FXIO1_D3 0x010C 0x0898 0x2 0x2 +#define MX8ULP_PAD_PTF3__LPUART6_RX 0x010C 0x09D0 0x4 0x2 +#define MX8ULP_PAD_PTF3__LPI2C7_HREQ 0x010C 0x09C0 0x5 0x2 +#define MX8ULP_PAD_PTF3__I2S7_RXD1 0x010C 0x0B58 0x7 0x2 +#define MX8ULP_PAD_PTF3__SDHC1_CMD 0x010C 0x0A60 0x8 0x2 +#define MX8ULP_PAD_PTF3__ENET0_TXD0 0x010C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF3__USB0_PWR 0x010C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF3__EPDC0_SDCE8 0x010C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF3__DPI0_D20 0x010C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF3__WUU1_P9 0x010C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF3__DEBUG_MUX1_24 0x010C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF4__PTF4 0x0110 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF4__FXIO1_D4 0x0110 0x08A4 0x2 0x2 +#define MX8ULP_PAD_PTF4__LPSPI4_PCS1 0x0110 0x08F8 0x3 0x3 +#define MX8ULP_PAD_PTF4__LPUART7_CTS_B 0x0110 0x09D8 0x4 0x2 +#define MX8ULP_PAD_PTF4__LPI2C7_SCL 0x0110 0x09C4 0x5 0x2 +#define MX8ULP_PAD_PTF4__TPM7_CLKIN 0x0110 0x09B0 0x6 0x1 +#define MX8ULP_PAD_PTF4__I2S7_RXD2 0x0110 0x0B5C 0x7 0x2 +#define MX8ULP_PAD_PTF4__SDHC1_D3 0x0110 0x0A70 0x8 0x2 +#define MX8ULP_PAD_PTF4__ENET0_TXEN 0x0110 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF4__USB0_OC 0x0110 0x0AC0 0xa 0x3 +#define MX8ULP_PAD_PTF4__EPDC0_SDCE7 0x0110 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF4__DPI0_D19 0x0110 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF4__WUU1_P10 0x0110 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF4__DEBUG_MUX1_25 0x0110 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF5__PTF5 0x0114 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF5__FXIO1_D5 0x0114 0x08A8 0x2 0x2 +#define MX8ULP_PAD_PTF5__LPSPI4_PCS2 0x0114 0x08FC 0x3 0x3 +#define MX8ULP_PAD_PTF5__LPUART7_RTS_B 0x0114 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF5__LPI2C7_SDA 0x0114 0x09C8 0x5 0x2 +#define MX8ULP_PAD_PTF5__TPM7_CH0 0x0114 0x0998 0x6 0x1 +#define MX8ULP_PAD_PTF5__I2S7_RXD3 0x0114 0x0B60 0x7 0x2 +#define MX8ULP_PAD_PTF5__SDHC1_D2 0x0114 0x0A6C 0x8 0x2 +#define MX8ULP_PAD_PTF5__ENET0_RXER 0x0114 0x0B08 0x9 0x2 +#define MX8ULP_PAD_PTF5__USB1_PWR 0x0114 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF5__EPDC0_SDCE6 0x0114 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF5__DPI0_D18 0x0114 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF5__LP_HV_DBG_MUX_18 0x0114 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF5__DEBUG_MUX0_18 0x0114 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF5__DEBUG_MUX1_26 0x0114 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF6__LP_HV_DBG_MUX_19 0x0118 0x0000 0x0 0x0 +#define MX8ULP_PAD_PTF6__PTF6 0x0118 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF6__FXIO1_D6 0x0118 0x08AC 0x2 0x2 +#define MX8ULP_PAD_PTF6__LPSPI4_PCS3 0x0118 0x0900 0x3 0x3 +#define MX8ULP_PAD_PTF6__LPUART7_TX 0x0118 0x09E0 0x4 0x2 +#define MX8ULP_PAD_PTF6__I3C2_SCL 0x0118 0x08BC 0x5 0x3 +#define MX8ULP_PAD_PTF6__TPM7_CH1 0x0118 0x099C 0x6 0x1 +#define MX8ULP_PAD_PTF6__I2S7_MCLK 0x0118 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF6__SDHC1_D4 0x0118 0x0A74 0x8 0x2 +#define MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x0118 0x0AEC 0x9 0x2 +#define MX8ULP_PAD_PTF6__USB1_OC 0x0118 0x0AC4 0xa 0x3 +#define MX8ULP_PAD_PTF6__EPDC0_SDCE5 0x0118 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF6__DPI0_D17 0x0118 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF6__WDOG4_RST 0x0118 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF6__DEBUG_MUX0_19 0x0118 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF6__DEBUG_MUX1_27 0x0118 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF7__PTF7 0x011C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF7__FXIO1_D7 0x011C 0x08B0 0x2 0x2 +#define MX8ULP_PAD_PTF7__LPUART7_RX 0x011C 0x09DC 0x4 0x2 +#define MX8ULP_PAD_PTF7__I3C2_SDA 0x011C 0x08C0 0x5 0x3 +#define MX8ULP_PAD_PTF7__TPM7_CH2 0x011C 0x09A0 0x6 0x1 +#define MX8ULP_PAD_PTF7__MQS1_LEFT 0x011C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF7__SDHC1_D5 0x011C 0x0A78 0x8 0x2 +#define MX8ULP_PAD_PTF7__ENET0_REFCLK 0x011C 0x0AF4 0x9 0x2 +#define MX8ULP_PAD_PTF7__TRACE0_D15 0x011C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF7__EPDC0_SDCE4 0x011C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF7__DPI0_D16 0x011C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF7__WUU1_P11 0x011C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF7__DEBUG_MUX1_28 0x011C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF8__PTF8 0x0120 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF8__FXIO1_D8 0x0120 0x08B4 0x2 0x2 +#define MX8ULP_PAD_PTF8__LPSPI4_SIN 0x0120 0x0908 0x3 0x3 +#define MX8ULP_PAD_PTF8__LPUART4_CTS_B 0x0120 0x08DC 0x4 0x3 +#define MX8ULP_PAD_PTF8__LPI2C4_SCL 0x0120 0x08C8 0x5 0x3 +#define MX8ULP_PAD_PTF8__TPM7_CH3 0x0120 0x09A4 0x6 0x1 +#define MX8ULP_PAD_PTF8__MQS1_RIGHT 0x0120 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF8__SDHC1_D6 0x0120 0x0A7C 0x8 0x2 +#define MX8ULP_PAD_PTF8__ENET0_MDIO 0x0120 0x0AF0 0x9 0x2 +#define MX8ULP_PAD_PTF8__TRACE0_D14 0x0120 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF8__EPDC0_D15 0x0120 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF8__DPI0_D15 0x0120 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF8__LP_HV_DBG_MUX_24 0x0120 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF8__DEBUG_MUX1_29 0x0120 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF9__PTF9 0x0124 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF9__FXIO1_D9 0x0124 0x08B8 0x2 0x2 +#define MX8ULP_PAD_PTF9__LPSPI4_SOUT 0x0124 0x090C 0x3 0x3 +#define MX8ULP_PAD_PTF9__LPUART4_RTS_B 0x0124 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF9__LPI2C4_SDA 0x0124 0x08CC 0x5 0x3 +#define MX8ULP_PAD_PTF9__TPM7_CH4 0x0124 0x09A8 0x6 0x1 +#define MX8ULP_PAD_PTF9__EXT_AUD_MCLK2 0x0124 0x0800 0x7 0x2 +#define MX8ULP_PAD_PTF9__SDHC1_D7 0x0124 0x0A80 0x8 0x2 +#define MX8ULP_PAD_PTF9__ENET0_MDC 0x0124 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF9__TRACE0_D13 0x0124 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF9__EPDC0_D14 0x0124 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF9__DPI0_D14 0x0124 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF9__LP_HV_DBG_MUX_25 0x0124 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF9__DEBUG_MUX1_30 0x0124 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF10__LP_HV_DBG_MUX_26 0x0128 0x0000 0x0 0x0 +#define MX8ULP_PAD_PTF10__PTF10 0x0128 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF10__FXIO1_D10 0x0128 0x0844 0x2 0x2 +#define MX8ULP_PAD_PTF10__LPSPI4_SCK 0x0128 0x0904 0x3 0x3 +#define MX8ULP_PAD_PTF10__LPUART4_TX 0x0128 0x08E4 0x4 0x3 +#define MX8ULP_PAD_PTF10__LPI2C4_HREQ 0x0128 0x08C4 0x5 0x3 +#define MX8ULP_PAD_PTF10__TPM7_CH5 0x0128 0x09AC 0x6 0x1 +#define MX8ULP_PAD_PTF10__I2S4_RX_BCLK 0x0128 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF10__SDHC1_DQS 0x0128 0x0A84 0x8 0x2 +#define MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x0128 0x0AD0 0x9 0x2 +#define MX8ULP_PAD_PTF10__TRACE0_D12 0x0128 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF10__EPDC0_D13 0x0128 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF10__DPI0_D13 0x0128 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF10__DEBUG_MUX0_20 0x0128 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF10__DEBUG_MUX1_31 0x0128 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF11__PTF11 0x012C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF11__FXIO1_D11 0x012C 0x0848 0x2 0x2 +#define MX8ULP_PAD_PTF11__LPSPI4_PCS0 0x012C 0x08F4 0x3 0x3 +#define MX8ULP_PAD_PTF11__LPUART4_RX 0x012C 0x08E0 0x4 0x3 +#define MX8ULP_PAD_PTF11__TPM4_CLKIN 0x012C 0x081C 0x6 0x2 +#define MX8ULP_PAD_PTF11__I2S4_RX_FS 0x012C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF11__ENET0_1588_TMR0 0x012C 0x0AD4 0x9 0x2 +#define MX8ULP_PAD_PTF11__TRACE0_D11 0x012C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF11__EPDC0_D12 0x012C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF11__DPI0_D12 0x012C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF11__LP_HV_DBG_MUX_27 0x012C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF11__DEBUG_MUX1_32 0x012C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF12__PTF12 0x0130 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF12__FXIO1_D12 0x0130 0x084C 0x2 0x2 +#define MX8ULP_PAD_PTF12__LPSPI5_PCS1 0x0130 0x0914 0x3 0x2 +#define MX8ULP_PAD_PTF12__LPUART5_CTS_B 0x0130 0x08E8 0x4 0x3 +#define MX8ULP_PAD_PTF12__LPI2C5_SCL 0x0130 0x08D4 0x5 0x3 +#define MX8ULP_PAD_PTF12__TPM4_CH0 0x0130 0x0804 0x6 0x2 +#define MX8ULP_PAD_PTF12__I2S4_RXD0 0x0130 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF12__SDHC2_WP 0x0130 0x0ABC 0x8 0x1 +#define MX8ULP_PAD_PTF12__ENET0_1588_TMR1 0x0130 0x0AD8 0x9 0x2 +#define MX8ULP_PAD_PTF12__TRACE0_D10 0x0130 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF12__EPDC0_D11 0x0130 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF12__DPI0_D11 0x0130 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF12__LP_HV_DBG_MUX_28 0x0130 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF12__DEBUG_MUX1_33 0x0130 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF13__PTF13 0x0134 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF13__FXIO1_D13 0x0134 0x0850 0x2 0x2 +#define MX8ULP_PAD_PTF13__LPSPI5_PCS2 0x0134 0x0918 0x3 0x2 +#define MX8ULP_PAD_PTF13__LPUART5_RTS_B 0x0134 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF13__LPI2C5_SDA 0x0134 0x08D8 0x5 0x3 +#define MX8ULP_PAD_PTF13__TPM4_CH1 0x0134 0x0808 0x6 0x2 +#define MX8ULP_PAD_PTF13__I2S4_RXD1 0x0134 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF13__SDHC2_CD 0x0134 0x0A8C 0x8 0x1 +#define MX8ULP_PAD_PTF13__ENET0_1588_TMR2 0x0134 0x0ADC 0x9 0x2 +#define MX8ULP_PAD_PTF13__TRACE0_D9 0x0134 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF13__EPDC0_D10 0x0134 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF13__DPI0_D10 0x0134 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF13__DEBUG_MUX0_21 0x0134 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF13__LP_HV_DBG_MUX_29 0x0134 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF14__PTF14 0x0138 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF14__FXIO1_D14 0x0138 0x0854 0x2 0x2 +#define MX8ULP_PAD_PTF14__LPSPI5_PCS3 0x0138 0x091C 0x3 0x2 +#define MX8ULP_PAD_PTF14__LPUART5_TX 0x0138 0x08F0 0x4 0x3 +#define MX8ULP_PAD_PTF14__LPI2C5_HREQ 0x0138 0x08D0 0x5 0x3 +#define MX8ULP_PAD_PTF14__TPM4_CH2 0x0138 0x080C 0x6 0x2 +#define MX8ULP_PAD_PTF14__I2S4_MCLK 0x0138 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF14__SDHC2_VS 0x0138 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF14__ENET0_1588_TMR3 0x0138 0x0AE0 0x9 0x2 +#define MX8ULP_PAD_PTF14__TRACE0_D8 0x0138 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF14__EPDC0_D9 0x0138 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF14__DPI0_D9 0x0138 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF14__DEBUG_MUX0_22 0x0138 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF14__LP_HV_DBG_MUX_30 0x0138 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF15__PTF15 0x013C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF15__FXIO1_D15 0x013C 0x0858 0x2 0x2 +#define MX8ULP_PAD_PTF15__LPUART5_RX 0x013C 0x08EC 0x4 0x3 +#define MX8ULP_PAD_PTF15__TPM4_CH3 0x013C 0x0810 0x6 0x2 +#define MX8ULP_PAD_PTF15__I2S4_TX_BCLK 0x013C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF15__SDHC2_D1 0x013C 0x0A9C 0x8 0x3 +#define MX8ULP_PAD_PTF15__ENET0_RXD2 0x013C 0x0B00 0x9 0x2 +#define MX8ULP_PAD_PTF15__TRACE0_D7 0x013C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF15__EPDC0_D8 0x013C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF15__DPI0_D8 0x013C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF15__LP_HV_DBG_MUX_31 0x013C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF16__PTF16 0x0140 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF16__FXIO1_D16 0x0140 0x085C 0x2 0x2 +#define MX8ULP_PAD_PTF16__LPSPI5_SIN 0x0140 0x0924 0x3 0x2 +#define MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x0140 0x09CC 0x4 0x3 +#define MX8ULP_PAD_PTF16__LPI2C6_SCL 0x0140 0x09B8 0x5 0x3 +#define MX8ULP_PAD_PTF16__TPM4_CH4 0x0140 0x0814 0x6 0x2 +#define MX8ULP_PAD_PTF16__I2S4_TX_FS 0x0140 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF16__SDHC2_D0 0x0140 0x0A98 0x8 0x3 +#define MX8ULP_PAD_PTF16__ENET0_RXD3 0x0140 0x0B04 0x9 0x2 +#define MX8ULP_PAD_PTF16__TRACE0_D6 0x0140 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF16__EPDC0_D7 0x0140 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF16__DPI0_D7 0x0140 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF16__LP_HV_DBG_MUX_32 0x0140 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF17__PTF17 0x0144 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF17__FXIO1_D17 0x0144 0x0860 0x2 0x2 +#define MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x0144 0x0928 0x3 0x2 +#define MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x0144 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF17__LPI2C6_SDA 0x0144 0x09BC 0x5 0x3 +#define MX8ULP_PAD_PTF17__TPM4_CH5 0x0144 0x0818 0x6 0x2 +#define MX8ULP_PAD_PTF17__I2S4_TXD0 0x0144 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF17__SDHC2_CLK 0x0144 0x0A90 0x8 0x3 +#define MX8ULP_PAD_PTF17__ENET0_RXCLK 0x0144 0x0B0C 0x9 0x2 +#define MX8ULP_PAD_PTF17__TRACE0_D5 0x0144 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF17__EPDC0_D6 0x0144 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF17__DPI0_D6 0x0144 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF17__DEBUG_MUX0_23 0x0144 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF17__LP_HV_DBG_MUX_33 0x0144 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF18__PTF18 0x0148 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF18__FXIO1_D18 0x0148 0x0864 0x2 0x2 +#define MX8ULP_PAD_PTF18__LPSPI5_SCK 0x0148 0x0920 0x3 0x2 +#define MX8ULP_PAD_PTF18__LPUART6_TX 0x0148 0x09D4 0x4 0x3 +#define MX8ULP_PAD_PTF18__LPI2C6_HREQ 0x0148 0x09B4 0x5 0x3 +#define MX8ULP_PAD_PTF18__TPM5_CLKIN 0x0148 0x0838 0x6 0x2 +#define MX8ULP_PAD_PTF18__I2S4_TXD1 0x0148 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF18__SDHC2_CMD 0x0148 0x0A94 0x8 0x3 +#define MX8ULP_PAD_PTF18__ENET0_TXD2 0x0148 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF18__TRACE0_D4 0x0148 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF18__EPDC0_D5 0x0148 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF18__DPI0_D5 0x0148 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF19__PTF19 0x014C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF19__FXIO1_D19 0x014C 0x0868 0x2 0x2 +#define MX8ULP_PAD_PTF19__LPSPI5_PCS0 0x014C 0x0910 0x3 0x2 +#define MX8ULP_PAD_PTF19__LPUART6_RX 0x014C 0x09D0 0x4 0x3 +#define MX8ULP_PAD_PTF19__TPM5_CH0 0x014C 0x0820 0x6 0x2 +#define MX8ULP_PAD_PTF19__I2S5_RX_BCLK 0x014C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF19__SDHC2_D3 0x014C 0x0AA4 0x8 0x3 +#define MX8ULP_PAD_PTF19__ENET0_TXD3 0x014C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF19__TRACE0_D3 0x014C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF19__EPDC0_D4 0x014C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF19__DPI0_D4 0x014C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF20__PTF20 0x0150 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF20__FXIO1_D20 0x0150 0x0870 0x2 0x2 +#define MX8ULP_PAD_PTF20__LPUART7_CTS_B 0x0150 0x09D8 0x4 0x3 +#define MX8ULP_PAD_PTF20__LPI2C7_SCL 0x0150 0x09C4 0x5 0x3 +#define MX8ULP_PAD_PTF20__TPM5_CH1 0x0150 0x0824 0x6 0x2 +#define MX8ULP_PAD_PTF20__I2S5_RX_FS 0x0150 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF20__SDHC2_D2 0x0150 0x0AA0 0x8 0x3 +#define MX8ULP_PAD_PTF20__ENET0_TXCLK 0x0150 0x0B10 0x9 0x2 +#define MX8ULP_PAD_PTF20__TRACE0_D2 0x0150 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF20__EPDC0_D3 0x0150 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF20__DPI0_D3 0x0150 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF21__PTF21 0x0154 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF21__FXIO1_D21 0x0154 0x0874 0x2 0x2 +#define MX8ULP_PAD_PTF21__SPDIF_CLK 0x0154 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF21__LPUART7_RTS_B 0x0154 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF21__LPI2C7_SDA 0x0154 0x09C8 0x5 0x3 +#define MX8ULP_PAD_PTF21__TPM6_CLKIN 0x0154 0x0994 0x6 0x2 +#define MX8ULP_PAD_PTF21__I2S5_RXD0 0x0154 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF21__SDHC2_D4 0x0154 0x0AA8 0x8 0x2 +#define MX8ULP_PAD_PTF21__ENET0_CRS 0x0154 0x0AE8 0x9 0x2 +#define MX8ULP_PAD_PTF21__TRACE0_D1 0x0154 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF21__EPDC0_D2 0x0154 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF21__DPI0_D2 0x0154 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF22__PTF22 0x0158 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF22__FXIO1_D22 0x0158 0x0878 0x2 0x2 +#define MX8ULP_PAD_PTF22__SPDIF_IN0 0x0158 0x0B74 0x3 0x3 +#define MX8ULP_PAD_PTF22__LPUART7_TX 0x0158 0x09E0 0x4 0x3 +#define MX8ULP_PAD_PTF22__LPI2C7_HREQ 0x0158 0x09C0 0x5 0x3 +#define MX8ULP_PAD_PTF22__TPM6_CH0 0x0158 0x097C 0x6 0x2 +#define MX8ULP_PAD_PTF22__I2S5_RXD1 0x0158 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF22__SDHC2_D5 0x0158 0x0AAC 0x8 0x2 +#define MX8ULP_PAD_PTF22__ENET0_COL 0x0158 0x0AE4 0x9 0x2 +#define MX8ULP_PAD_PTF22__TRACE0_D0 0x0158 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF22__EPDC0_D1 0x0158 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF22__DPI0_D1 0x0158 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF23__PTF23 0x015C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF23__FXIO1_D23 0x015C 0x087C 0x2 0x2 +#define MX8ULP_PAD_PTF23__SPDIF_OUT0 0x015C 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF23__LPUART7_RX 0x015C 0x09DC 0x4 0x3 +#define MX8ULP_PAD_PTF23__I3C2_PUR 0x015C 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTF23__TPM6_CH1 0x015C 0x0980 0x6 0x2 +#define MX8ULP_PAD_PTF23__I2S5_RXD2 0x015C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF23__SDHC2_D6 0x015C 0x0AB0 0x8 0x2 +#define MX8ULP_PAD_PTF23__ENET0_TXER 0x015C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF23__TRACE0_CLKOUT 0x015C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF23__EPDC0_D0 0x015C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF23__DPI0_D0 0x015C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF24__PTF24 0x0160 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF24__FXIO1_D24 0x0160 0x0880 0x2 0x2 +#define MX8ULP_PAD_PTF24__SPDIF_IN1 0x0160 0x0B78 0x3 0x3 +#define MX8ULP_PAD_PTF24__I3C2_SCL 0x0160 0x08BC 0x5 0x4 +#define MX8ULP_PAD_PTF24__I2S5_RXD3 0x0160 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF24__SDHC2_D7 0x0160 0x0AB4 0x8 0x2 +#define MX8ULP_PAD_PTF24__DBI0_WRX 0x0160 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF24__EPDC0_SDCLK 0x0160 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF24__DPI0_PCLK 0x0160 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF24__WUU1_P12 0x0160 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF25__PTF25 0x0164 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF25__FXIO1_D25 0x0164 0x0884 0x2 0x2 +#define MX8ULP_PAD_PTF25__SPDIF_OUT1 0x0164 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF25__I3C2_SDA 0x0164 0x08C0 0x5 0x4 +#define MX8ULP_PAD_PTF25__TPM7_CH5 0x0164 0x09AC 0x6 0x2 +#define MX8ULP_PAD_PTF25__I2S5_MCLK 0x0164 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF25__SDHC2_DQS 0x0164 0x0AB8 0x8 0x2 +#define MX8ULP_PAD_PTF25__EXT_AUD_MCLK2 0x0164 0x0800 0x9 0x3 +#define MX8ULP_PAD_PTF25__EPDC0_GDSP 0x0164 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF25__DPI0_VSYNC 0x0164 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF25__WUU1_P13 0x0164 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF26__PTF26 0x0168 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF26__FXIO1_D26 0x0168 0x0888 0x2 0x2 +#define MX8ULP_PAD_PTF26__SPDIF_IN2 0x0168 0x0B7C 0x3 0x3 +#define MX8ULP_PAD_PTF26__TPM7_CLKIN 0x0168 0x09B0 0x6 0x2 +#define MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x0168 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF26__SDHC2_RESET_B 0x0168 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF26__EPDC0_SDLE 0x0168 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF26__DPI0_HSYNC 0x0168 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF26__WUU1_P14 0x0168 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF27__PTF27 0x016C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF27__FXIO1_D27 0x016C 0x088C 0x2 0x2 +#define MX8ULP_PAD_PTF27__SPDIF_OUT2 0x016C 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF27__TPM7_CH0 0x016C 0x0998 0x6 0x2 +#define MX8ULP_PAD_PTF27__I2S5_TX_FS 0x016C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF27__SDHC2_WP 0x016C 0x0ABC 0x8 0x2 +#define MX8ULP_PAD_PTF27__EPDC0_SDCE0 0x016C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF27__DPI0_DE 0x016C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF27__WUU1_P15 0x016C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF28__PTF28 0x0170 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF28__FXIO1_D28 0x0170 0x0890 0x2 0x2 +#define MX8ULP_PAD_PTF28__SPDIF_IN3 0x0170 0x0B80 0x3 0x3 +#define MX8ULP_PAD_PTF28__TPM7_CH1 0x0170 0x099C 0x6 0x2 +#define MX8ULP_PAD_PTF28__I2S5_TXD0 0x0170 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF28__SDHC2_CD 0x0170 0x0A8C 0x8 0x2 +#define MX8ULP_PAD_PTF28__EPDC0_SDCLK_B 0x0170 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF28__LP_HV_DBG_MUX_20 0x0170 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF29__PTF29 0x0174 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF29__FXIO1_D29 0x0174 0x0894 0x2 0x2 +#define MX8ULP_PAD_PTF29__SPDIF_OUT3 0x0174 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF29__TPM7_CH2 0x0174 0x09A0 0x6 0x2 +#define MX8ULP_PAD_PTF29__I2S5_TXD1 0x0174 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF29__SDHC2_VS 0x0174 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF29__EPDC0_SDCE1 0x0174 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF29__WDOG3_RST 0x0174 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF29__LP_HV_DBG_MUX_21 0x0174 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF30__PTF30 0x0178 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF30__FXIO1_D30 0x0178 0x089C 0x2 0x2 +#define MX8ULP_PAD_PTF30__TPM7_CH3 0x0178 0x09A4 0x6 0x2 +#define MX8ULP_PAD_PTF30__I2S5_TXD2 0x0178 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF30__MQS1_LEFT 0x0178 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF30__EPDC0_SDCE2 0x0178 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF30__WDOG4_RST 0x0178 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF30__LP_HV_DBG_MUX_22 0x0178 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF31__PTF31 0x017C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF31__FXIO1_D31 0x017C 0x08A0 0x2 0x2 +#define MX8ULP_PAD_PTF31__TPM7_CH4 0x017C 0x09A8 0x6 0x2 +#define MX8ULP_PAD_PTF31__I2S5_TXD3 0x017C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF31__MQS1_RIGHT 0x017C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF31__EPDC0_SDCE3 0x017C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF31__WDOG5_RST 0x017C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF31__LP_HV_DBG_MUX_23 0x017C 0x0000 0xf 0x0 +#define MX8ULP_PAD_BOOT_MODE0__BOOT_MODE0 0x0400 0x0000 0x0 0x0 +#define MX8ULP_PAD_BOOT_MODE1__BOOT_MODE1 0x0404 0x0000 0x0 0x0 + +#endif /* __DTS_IMX8ULP_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi new file mode 100644 index 000000000000..fb8714379026 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include +#include +#include + +#include "imx8ulp-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpiod; + gpio1 = &gpioe; + gpio2 = &gpiof; + mmc0 = &usdhc0; + mmc1 = &usdhc1; + mmc2 = &usdhc2; + serial0 = &lpuart4; + serial1 = &lpuart5; + serial2 = &lpuart6; + serial3 = &lpuart7; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@2d400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ + <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + frosc: clock-frosc { + compatible = "fixed-clock"; + clock-frequency = <192000000>; + clock-output-names = "frosc"; + #clock-cells = <0>; + }; + + lposc: clock-lposc { + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "lposc"; + #clock-cells = <0>; + }; + + rosc: clock-rosc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "rosc"; + #clock-cells = <0>; + }; + + sosc: clock-sosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "sosc"; + #clock-cells = <0>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x40000000>; + + per_bridge3: bus@29000000 { + compatible = "simple-bus"; + reg = <0x29000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + wdog3: watchdog@292a0000 { + compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt"; + reg = <0x292a0000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; + assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + timeout-sec = <40>; + }; + + cgc1: clock-controller@292c0000 { + compatible = "fsl,imx8ulp-cgc1"; + reg = <0x292c0000 0x10000>; + clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>; + clock-names = "rosc", "sosc", "frosc", "lposc"; + #clock-cells = <1>; + }; + + pcc3: clock-controller@292d0000 { + compatible = "fsl,imx8ulp-pcc3"; + reg = <0x292d0000 0x10000>; + #clock-cells = <1>; + }; + + tpm5: tpm@29340000 { + compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; + reg = <0x29340000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_TPM5>, + <&pcc3 IMX8ULP_CLK_TPM5>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + lpi2c4: i2c@29370000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29370000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, + <&pcc3 IMX8ULP_CLK_LPI2C4>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c5: i2c@29380000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29380000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, + <&pcc3 IMX8ULP_CLK_LPI2C5>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart4: serial@29390000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29390000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@293a0000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x293a0000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpspi4: spi@293b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; + reg = <0x293b0000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, + <&pcc3 IMX8ULP_CLK_LPSPI4>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <16000000>; + status = "disabled"; + }; + + lpspi5: spi@293c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; + reg = <0x293c0000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, + <&pcc3 IMX8ULP_CLK_LPSPI5>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <16000000>; + status = "disabled"; + }; + }; + + per_bridge4: bus@29800000 { + compatible = "simple-bus"; + reg = <0x29800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pcc4: clock-controller@29800000 { + compatible = "fsl,imx8ulp-pcc4"; + reg = <0x29800000 0x10000>; + #clock-cells = <1>; + }; + + lpi2c6: i2c@29840000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29840000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, + <&pcc4 IMX8ULP_CLK_LPI2C6>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c7: i2c@29850000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29850000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, + <&pcc4 IMX8ULP_CLK_LPI2C7>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart6: serial@29860000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29860000 0x1000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart7: serial@29870000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29870000 0x1000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; + clock-names = "ipg"; + status = "disabled"; + }; + + iomuxc1: pinctrl@298c0000 { + compatible = "fsl,imx8ulp-iomuxc1"; + reg = <0x298c0000 0x10000>; + }; + + usdhc0: mmc@298d0000 { + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x298d0000 0x10000>; + interrupts = ; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, + <&pcc4 IMX8ULP_CLK_USDHC0>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc1: mmc@298e0000 { + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x298e0000 0x10000>; + interrupts = ; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, + <&pcc4 IMX8ULP_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@298f0000 { + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x298f0000 0x10000>; + interrupts = ; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, + <&pcc4 IMX8ULP_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + }; + + gpioe: gpio@2d000000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, + <&pcc4 IMX8ULP_CLK_PCTLE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 32 24>; + }; + + gpiof: gpio@2d010000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, + <&pcc4 IMX8ULP_CLK_PCTLF>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 64 32>; + }; + + per_bridge5: bus@2d800000 { + compatible = "simple-bus"; + reg = <0x2d800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cgc2: clock-controller@2da60000 { + compatible = "fsl,imx8ulp-cgc2"; + reg = <0x2da60000 0x10000>; + clocks = <&sosc>, <&frosc>; + clock-names = "sosc", "frosc"; + #clock-cells = <1>; + }; + + pcc5: clock-controller@2da70000 { + compatible = "fsl,imx8ulp-pcc5"; + reg = <0x2da70000 0x10000>; + #clock-cells = <1>; + }; + }; + + gpiod: gpio@2e200000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, + <&pcc5 IMX8ULP_CLK_RGPIOD>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 0 24>; + }; + }; +}; From a6e917b7366c5d91accafa2b7b45090e6b632987 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 26 Nov 2021 15:40:02 +0800 Subject: [PATCH 216/574] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board Add the basic dts file for i.MX8ULP EVK board. Only the necessary devices for minimal system boot up are enabled: enet, emmc, usb, console uart. some of the devices' pin status may lost during low power mode, so additional sleep pinctrl properties are included by default. Reviewed-by: Dong Aisheng Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 64 +++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a14a6173b765..c64616192794 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts new file mode 100644 index 000000000000..33e84c4e9ed8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx8ulp.dtsi" + +/ { + model = "NXP i.MX8ULP EVK"; + compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; + + chosen { + stdout-path = &lpuart5; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; +}; + +&lpuart5 { + /* console */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart5>; + pinctrl-1 = <&pinctrl_lpuart5>; + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart5: lpuart5grp { + fsl,pins = < + MX8ULP_PAD_PTF14__LPUART5_TX 0x3 + MX8ULP_PAD_PTF15__LPUART5_RX 0x3 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 + MX8ULP_PAD_PTD10__SDHC0_D0 0x43 + MX8ULP_PAD_PTD9__SDHC0_D1 0x43 + MX8ULP_PAD_PTD8__SDHC0_D2 0x43 + MX8ULP_PAD_PTD7__SDHC0_D3 0x43 + MX8ULP_PAD_PTD6__SDHC0_D4 0x43 + MX8ULP_PAD_PTD5__SDHC0_D5 0x43 + MX8ULP_PAD_PTD4__SDHC0_D6 0x43 + MX8ULP_PAD_PTD3__SDHC0_D7 0x43 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 + >; + }; +}; From ee6302d90db96e1f0a49305ba9db4969b378d585 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:42 +0100 Subject: [PATCH 217/574] dt-bindings: arm: fsl: add TQMa8MxML boards TQMa8MxML is a SOM family using NXP i.MX8MM[Q,QL,DL,S,SL] CPU MBa8Mx is an evaluation mainbord for this SOM The SOM needs a mainboard, therefore we provide two compatibles here: "tq,imx8mm-" for the module and "tq,imx8mm--" for the module on that mainboard Signed-off-by: Alexander Stein Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 6604aea7d646..79789e64f673 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -792,6 +792,17 @@ properties: - const: variscite,var-som-mx8mm - const: fsl,imx8mm + - description: + TQMa8MxML is a series of SOM featuring NXP i.MX8MM system-on-chip + variants. It is designed to be soldered on different carrier boards. + All variants (TQMa8M[Q,D,S][L]ML) use the same device tree, hence only + one compatible is needed. + items: + - enum: + - tq,imx8mm-tqma8mqml-mba8mx # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM on MBa8Mx + - const: tq,imx8mm-tqma8mqml # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM + - const: fsl,imx8mm + - description: i.MX8MN based Boards items: - enum: From 50ef92d89c12809fe8f98d0e0cab7b6765e10898 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:45 +0100 Subject: [PATCH 218/574] dt-bindings: arm: fsl: add TQMa8MxNL boards TQMa8MxNL is a SOM family using NXP i.MX8MN[Q,QL,DL,S,SL] CPU MBa8Mx is an evaluation mainbord for this SOM The SOM needs a mainboard, therefore we provide two compatibles here: "tq,imx8mn-" for the module and "tq,imx8mn--" for mainboards Signed-off-by: Alexander Stein Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 79789e64f673..a705eabe1cfc 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -818,6 +818,17 @@ properties: - const: variscite,var-som-mx8mn - const: fsl,imx8mn + - description: + TQMa8MxNL is a series of SOM featuring NXP i.MX8MN system-on-chip + variants. It is designed to be soldered on different carrier boards. + All variants (TQMa8M[Q,D,S][L]NL) use the same device tree, hence only + one compatible is needed. + items: + - enum: + - tq,imx8mn-tqma8mqnl-mba8mx # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM on MBa8Mx + - const: tq,imx8mn-tqma8mqnl # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM + - const: fsl,imx8mn + - description: i.MX8MP based Boards items: - enum: From 9aa637b5673ca100f219b13b16dbc19a0b77ef73 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:47 +0100 Subject: [PATCH 219/574] dt-bindings: arm: fsl: add TQMa8Mx boards TQMa8Mx is a SOM family using NXP i.MX8M[Q,QL, D] CPU MBa8Mx is a evaluation mainbord for this SOM The SOM needs a mainboard, therefore we provide two compatibles here: "tq,imx8mq-" for the module and "tq,imx8mq--" for the module on that mainboard Signed-off-by: Alexander Stein Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a705eabe1cfc..c35076cc551d 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -865,6 +865,15 @@ properties: - const: purism,librem5 - const: fsl,imx8mq + - description: + TQMa8Mx is a series of SOM featuring NXP i.MX8MQ system-on-chip + variants. It is designed to be clicked on different carrier boards. + items: + - enum: + - tq,imx8mq-tqma8mq-mba8mx # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM on MBa8Mx + - const: tq,imx8mq-tqma8mq # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM + - const: fsl,imx8mq + - description: Zodiac Inflight Innovations Ultra Boards items: - enum: From dfcd1b6f7620eef1f0060b64408c05419297456a Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:43 +0100 Subject: [PATCH 220/574] arm64: dts: freescale: add initial device tree for TQMa8MQML with i.MX8MM This adds support for TQMa8MQML module on MBa8Mx board. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-tqma8mqml-mba8mx.dts | 253 +++++++++++++ .../boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 335 ++++++++++++++++++ arch/arm64/boot/dts/freescale/mba8mx.dtsi | 282 +++++++++++++++ 4 files changed, 871 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi create mode 100644 arch/arm64/boot/dts/freescale/mba8mx.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c64616192794..aed0d0c80a43 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts new file mode 100644 index 000000000000..7844878788f4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +/dts-v1/; + +#include "imx8mm-tqma8mqml.dtsi" +#include "mba8mx.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx"; + compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + + aliases { + eeprom0 = &eeprom3; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + extcon_usbotg1: extcon-usbotg1 { + compatible = "linux,extcon-usb-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_extcon>; + id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + expander2: gpio@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&sai3 { + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; +}; + +&tlv320aic3x04 { + clock-names = "mclk"; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; +}; + +&uart1 { + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; +}; + +&uart2 { + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + dr_mode = "otg"; + extcon = <&extcon_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + over-current-active-low; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_hub_vbus>; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_expander: expandergrp { + fsl,pins = ; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_gpiobutton: gpiobuttongrp { + fsl,pins = , + , + ; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = , + ; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = , + ; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = , + ; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = ; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = , + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = , + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = , + ; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = , + ; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = , + ; + }; + + pinctrl_usb1_extcon: usb1-extcongrp { + fsl,pins = ; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi new file mode 100644 index 000000000000..284e62acc0b4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +#include "imx8mm.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MM TQMa8MxML"; + compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXML_VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* identical to buck4_reg, but should never change */ + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXML_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 640 MiB */ + size = <0 0x28000000>; + /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <84000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&gpu_2d { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + sensor0: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V85_SOC: 0.85 */ + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-ramp-delay = <3125>; + }; + + /* V_0V85_GPU / DRAM / VPU */ + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VCC3V3 -> VMMC, ... must not be changed */ + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 -> RAM, ... must not be changed */ + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V8_SNVS */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_ANA */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V9_MIPI */ + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VCC SD IO - switched using SD2 VSELECT */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x53>; + pagesize = <16>; + }; + + eeprom0: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +/* + * Attention: + * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR + * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. + */ +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi: flexspigrp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = , + ; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = ; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = ; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + /* option USDHC3_RESET_B not defined, only in RM */ + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + /* option USDHC3_RESET_B not defined, only in RM */ + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + /* option USDHC3_RESET_B not defined, only in RM */ + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi new file mode 100644 index 000000000000..f27e3c8de916 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +#include + +/* TQ-Systems GmbH MBa8Mx baseboard */ + +/ { + beeper { + compatible = "pwm-beeper"; + pwms = <&pwm4 0 250000 0>; + beeper-hz = <4000>; + amp-supply = <®_vcc_3v3>; + }; + + chosen { + // bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200"; + stdout-path = &uart3; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobutton>; + autorepeat; + + switch1 { + label = "switch1"; + linux,code = ; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + btn2: switch2 { + label = "switch2"; + linux,code = ; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch3 { + label = "switch3"; + linux,code = ; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led1 { + label = "led1"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2: led2 { + label = "led2"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_hub_vbus: regulator-hub-vbus { + compatible = "regulator-fixed"; + regulator-name = "MBA8MX_HUB_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_sn65dsi83_1v8: regulator-sn65dsi83-1v8 { + compatible = "regulator-fixed"; + regulator-name = "SN65DSI83_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&expander0 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "MBA8MX_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + ssi-controller = <&sai3>; + audio-codec = <&tlv320aic3x04>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-supply = <®_vcc_3v3>; + fsl,magic-packet; + mac-address = [ 00 00 00 00 00 00 ]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@e { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0xe>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + enet-phy-lane-no-swap; + reset-gpios = <&expander2 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <500>; + }; + }; +}; + +&i2c1 { + expander0: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + sd-mux-oe-hog { + gpio-hog; + gpios = <8 0>; + output-low; + line-name = "SD_MUX_EN#"; + }; + + boot-cfg-oe-hog { + gpio-hog; + gpios = <12 0>; + output-high; + line-name = "BOOT_CFG_OE#"; + }; + + rst-usb-hub-hog { + gpio-hog; + gpios = <13 0>; + output-high; + line-name = "RST_USB_HUB#"; + }; + }; + + expander1: gpio@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + reset-gpios = <&expander2 0 GPIO_ACTIVE_LOW>; + iov-supply = <®_vcc_3v3>; + ldoin-supply = <®_vcc_3v3>; + }; + + sensor1: sensor@1f { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1f>; + }; + + eeprom3: eeprom@57 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + #sound-dai-cells = <0>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* console */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* UART4 is assigned to Cortex-M4 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; From 3e56e354db6d34b211fc76b3ac228fc3613663d3 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:46 +0100 Subject: [PATCH 221/574] arm64: dts: freescale: add initial device tree for TQMa8MQNL with i.MX8MN This adds support for TQMa8MQNL module on MBa8Mx board. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts | 237 +++++++++++++ .../boot/dts/freescale/imx8mn-tqma8mqnl.dtsi | 322 ++++++++++++++++++ 3 files changed, 560 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index aed0d0c80a43..53b70941427b 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -50,6 +50,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts new file mode 100644 index 000000000000..3f1e49bfe38f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +/dts-v1/; + +#include "imx8mn-tqma8mqnl.dtsi" +#include "mba8mx.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MN TQMa8MxNL on MBa8Mx"; + compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; + + aliases { + eeprom0 = &eeprom3; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +/* Located on TQMa8MxML-ADAP */ +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0hub_sel>; + + sel-usb-hub-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&i2c1 { + expander2: gpio@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander2>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&sai3 { + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; +}; + +&tlv320aic3x04 { + clock-names = "mclk"; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + power-active-high; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_expander2: expander2grp { + fsl,pins = ; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_gpiobutton: gpiobuttongrp { + fsl,pins = , + , + ; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = , + ; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = , + ; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = , + ; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = ; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = , + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = , + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = , + ; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = , + ; + }; + + pinctrl_usb0hub_sel: usb0hub-selgrp { + /* SEL_USB_HUB_B */ + fsl,pins = ; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = , + , + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi new file mode 100644 index 000000000000..9ea28941068d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +#include "imx8mn.dtsi" + +/ { + model = "TQ-Systems i.MX8MN TQMa8MxNL"; + compatible = "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; + + memory@40000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXNL_VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXNL_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 640 MiB */ + size = <0 0x28000000>; + /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <84000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + sensor0: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V85_SOC: 0.85 .. 0.95 */ + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-ramp-delay = <3125>; + }; + + /* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */ + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VCC3V3 -> VMMC, ... must not be changed */ + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 -> RAM, ... must not be changed */ + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V8_SNVS */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_ANA */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V9_MIPI */ + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VCC SD IO - switched using SD2 VSELECT */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x53>; + pagesize = <16>; + }; + + eeprom0: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +/* + * Attention: + * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR + * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. + */ +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi: flexspigrp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = , + ; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = ; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = ; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = ; + }; +}; From b186b8b6e770570706f533dcf4c70b39e9ee31d2 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:48 +0100 Subject: [PATCH 222/574] arm64: dts: freescale: add initial device tree for TQMa8Mx with i.MX8M This adds support for TQMa8Mx module on MBa8Mx board. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 349 +++++++++++++++++ .../boot/dts/freescale/imx8mq-tqma8mq.dtsi | 360 ++++++++++++++++++ 3 files changed, 710 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 53b70941427b..58971bd89901 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -62,6 +62,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r4.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-tqma8mq-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-mnt-reform2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts new file mode 100644 index 000000000000..d7660eab68b9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2021 TQ-Systems GmbH + */ + +/dts-v1/; + +#include "imx8mq-tqma8mq.dtsi" +#include "mba8mx.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx"; + compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq"; + + aliases { + eeprom0 = &eeprom3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + }; + + extcon_usbotg: extcon-usbotg0 { + compatible = "linux,extcon-usb-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon0>; + id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie1_refclk: pcie1-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regotgvbus>; + regulator-name = "MBA8MQ_OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&btn2 { + gpios = <&gpio3 17 GPIO_ACTIVE_LOW>; +}; + +&gpio_leds { + led3 { + label = "led3"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + expander2: gpio@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + mpcie-rst-hog { + gpio-hog; + gpios = <13 0>; + output-high; + line-name = "MPCIE_RST#"; + }; + }; +}; + +&irqsteer { + status = "okay"; +}; + +&led2 { + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; +}; + +&pcie0 { + reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + epdev_on-supply = <®_vcc_3v3>; + hard-wired = <1>; + status = "okay"; +}; + +/* + * miniPCIe, also usable for cards with USB. Therefore configure the reset as + * static gpio hog. + */ +&pcie1 { + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + epdev_on-supply = <®_vcc_3v3>; + hard-wired = <1>; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; +}; + +&tlv320aic3x04 { + clock-names = "mclk"; + clocks = <&clk IMX8MQ_CLK_SAI3_ROOT>; +}; + +&uart1 { + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +}; + +&uart2 { + assigned-clocks = <&clk IMX8MQ_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +}; + +/* console */ +&uart3 { + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; +}; + +&usb3_phy0 { + vbus-supply = <®_otg_vbus>; + status = "okay"; +}; + +&usb_dwc3_0 { + /* we implement dual role but not full featured OTG */ + extcon = <&extcon_usbotg>; + hnp-disable; + srp-disable; + adp-disable; + /* OC not supported due to non matching active polarity */ + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_expander: expandergrp { + fsl,pins = ; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_gpiobutton: gpiobuttongrp { + fsl,pins = , + , + ; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = , + , + ; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = , + ; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = , + ; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = ; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = ; + }; + + pinctrl_regotgvbus: reggotgvbusgrp { + /* USB1 OTG PWR as GPIO */ + fsl,pins = ; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = , + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = , + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = , + ; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = , + ; + }; + + pinctrl_usbcon0: usb0congrp { + /* ID: floating / high: device, low: host -> use PU */ + fsl,pins = ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi new file mode 100644 index 000000000000..8aedcddfeab8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2021 TQ-Systems GmbH + */ + +#include "imx8mq.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ"; + compatible = "tq,imx8mq-tqma8mq", "fsl,imx8mq"; + + memory@40000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MX_VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MX_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vdd_arm: regulator-vdd-arm { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + regulator-name = "TQMa8Mx_DVFS"; + regulator-type = "voltage"; + regulator-settling-time-us = <150000>; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + states = <900000 0x1 1000000 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 640 MiB */ + size = <0 0x28000000>; + /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&gpu { + status = "okay"; +}; + +&pgc_gpu { + power-supply = <&sw1a_reg>; +}; + +&pgc_vpu { + power-supply = <&sw1c_reg>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + fsl,pfuze-support-disable-sw; + reg = <0x8>; + + regulators { + /* VDD_GPU */ + sw1a_reg: sw1ab { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + /* VDD_VPU */ + sw1c_reg: sw1c { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + /* NVCC_DRAM */ + sw2_reg: sw2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + /* VDD_DRAM */ + sw3a_reg: sw3ab { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + /* 1.8 V for QSPI NOR, e-MMC IO, must not be changed */ + nvcc_1v8_reg: sw4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + /* not used */ + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + /* VDD_PHY_0V9 */ + vgen2_reg: vgen2 { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <975000>; + regulator-always-on; + }; + + /* VDD_PHY_1V8 */ + vgen3_reg: vgen3 { + regulator-min-microvolt = <1675000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + /* VDDA_1V8 */ + vgen4_reg: vgen4 { + regulator-min-microvolt = <1625000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + /* VDD_PHY_3V3 */ + vgen5_reg: vgen5 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3625000>; + regulator-always-on; + }; + + /* not used */ + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + sensor0: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-names = "irq"; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + quartz-load-femtofarads = <7000>; + + clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + read-only; + }; + + eeprom0: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&pcie0 { + /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */ + vph-supply = <&vgen5_reg>; +}; + +&pcie1 { + /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */ + vph-supply = <&vgen5_reg>; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + assigned-clocks = <&clk IMX8MQ_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <84000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +/* Attention: wdog reset forcing POR needs baseboard support */ +&wdog1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_dvfs: dvfsgrp { + fsl,pins = ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = , + ; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = ; + }; +}; From 29bf0ff5ae18ad1a6dd183569cc097e578052c57 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Sat, 4 Dec 2021 23:58:19 +0200 Subject: [PATCH 223/574] ARM: dts: exynos: Rename hsi2c nodes to i2c for Exynos5260 In Device Tree specification it's recommended to use "i2c" name for I2C nodes. Now that i2c-exynos5 dt-schema binding was added, it shows some warnings like this when validating HS-I2C nodes: hsi2c@xxxxxxxxx: $nodename:0: 'hsi2c@xxxxxxxx' does not match '^i2c(@.*)?' From schema: Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Rename hsi2c@* to i2c@* to fix those warnings. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211204215820.17378-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5260.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 52fa211525ce..524d244050e0 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -368,7 +368,7 @@ status = "disabled"; }; - hsi2c_0: hsi2c@12da0000 { + hsi2c_0: i2c@12da0000 { compatible = "samsung,exynos5260-hsi2c"; reg = <0x12DA0000 0x1000>; interrupts = ; @@ -381,7 +381,7 @@ status = "disabled"; }; - hsi2c_1: hsi2c@12db0000 { + hsi2c_1: i2c@12db0000 { compatible = "samsung,exynos5260-hsi2c"; reg = <0x12DB0000 0x1000>; interrupts = ; @@ -394,7 +394,7 @@ status = "disabled"; }; - hsi2c_2: hsi2c@12dc0000 { + hsi2c_2: i2c@12dc0000 { compatible = "samsung,exynos5260-hsi2c"; reg = <0x12DC0000 0x1000>; interrupts = ; @@ -407,7 +407,7 @@ status = "disabled"; }; - hsi2c_3: hsi2c@12dd0000 { + hsi2c_3: i2c@12dd0000 { compatible = "samsung,exynos5260-hsi2c"; reg = <0x12DD0000 0x1000>; interrupts = ; From 8858f8622e82170ec184971b66c7a455816190f8 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Sat, 4 Dec 2021 23:58:20 +0200 Subject: [PATCH 224/574] arm64: dts: exynos: Rename hsi2c nodes to i2c for Exynos5433 and Exynos7 In Device Tree specification it's recommended to use "i2c" name for I2C nodes. Now that i2c-exynos5 dt-schema binding was added, it shows some warnings like this when validating HS-I2C nodes: hsi2c@xxxxxxxxx: $nodename:0: 'hsi2c@xxxxxxxx' does not match '^i2c(@.*)?' From schema: Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Rename hsi2c@* to i2c@* to fix those warnings. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211204215820.17378-9-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 24 +++++++++++----------- arch/arm64/boot/dts/exynos/exynos7.dtsi | 24 +++++++++++----------- 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 4422021cf4b2..bfe4ed8a23d6 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1585,7 +1585,7 @@ status = "disabled"; }; - hsi2c_0: hsi2c@14e40000 { + hsi2c_0: i2c@14e40000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e40000 0x1000>; interrupts = ; @@ -1598,7 +1598,7 @@ status = "disabled"; }; - hsi2c_1: hsi2c@14e50000 { + hsi2c_1: i2c@14e50000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e50000 0x1000>; interrupts = ; @@ -1611,7 +1611,7 @@ status = "disabled"; }; - hsi2c_2: hsi2c@14e60000 { + hsi2c_2: i2c@14e60000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e60000 0x1000>; interrupts = ; @@ -1624,7 +1624,7 @@ status = "disabled"; }; - hsi2c_3: hsi2c@14e70000 { + hsi2c_3: i2c@14e70000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e70000 0x1000>; interrupts = ; @@ -1637,7 +1637,7 @@ status = "disabled"; }; - hsi2c_4: hsi2c@14ec0000 { + hsi2c_4: i2c@14ec0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14ec0000 0x1000>; interrupts = ; @@ -1650,7 +1650,7 @@ status = "disabled"; }; - hsi2c_5: hsi2c@14ed0000 { + hsi2c_5: i2c@14ed0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14ed0000 0x1000>; interrupts = ; @@ -1663,7 +1663,7 @@ status = "disabled"; }; - hsi2c_6: hsi2c@14ee0000 { + hsi2c_6: i2c@14ee0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14ee0000 0x1000>; interrupts = ; @@ -1676,7 +1676,7 @@ status = "disabled"; }; - hsi2c_7: hsi2c@14ef0000 { + hsi2c_7: i2c@14ef0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14ef0000 0x1000>; interrupts = ; @@ -1689,7 +1689,7 @@ status = "disabled"; }; - hsi2c_8: hsi2c@14d90000 { + hsi2c_8: i2c@14d90000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14d90000 0x1000>; interrupts = ; @@ -1702,7 +1702,7 @@ status = "disabled"; }; - hsi2c_9: hsi2c@14da0000 { + hsi2c_9: i2c@14da0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14da0000 0x1000>; interrupts = ; @@ -1715,7 +1715,7 @@ status = "disabled"; }; - hsi2c_10: hsi2c@14de0000 { + hsi2c_10: i2c@14de0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14de0000 0x1000>; interrupts = ; @@ -1728,7 +1728,7 @@ status = "disabled"; }; - hsi2c_11: hsi2c@14df0000 { + hsi2c_11: i2c@14df0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14df0000 0x1000>; interrupts = ; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index c73a597ca66e..c3efbc8add38 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -359,7 +359,7 @@ interrupts = ; }; - hsi2c_0: hsi2c@13640000 { + hsi2c_0: i2c@13640000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13640000 0x1000>; interrupts = ; @@ -372,7 +372,7 @@ status = "disabled"; }; - hsi2c_1: hsi2c@13650000 { + hsi2c_1: i2c@13650000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13650000 0x1000>; interrupts = ; @@ -385,7 +385,7 @@ status = "disabled"; }; - hsi2c_2: hsi2c@14e60000 { + hsi2c_2: i2c@14e60000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e60000 0x1000>; interrupts = ; @@ -398,7 +398,7 @@ status = "disabled"; }; - hsi2c_3: hsi2c@14e70000 { + hsi2c_3: i2c@14e70000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e70000 0x1000>; interrupts = ; @@ -411,7 +411,7 @@ status = "disabled"; }; - hsi2c_4: hsi2c@13660000 { + hsi2c_4: i2c@13660000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13660000 0x1000>; interrupts = ; @@ -424,7 +424,7 @@ status = "disabled"; }; - hsi2c_5: hsi2c@13670000 { + hsi2c_5: i2c@13670000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13670000 0x1000>; interrupts = ; @@ -437,7 +437,7 @@ status = "disabled"; }; - hsi2c_6: hsi2c@14e00000 { + hsi2c_6: i2c@14e00000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e00000 0x1000>; interrupts = ; @@ -450,7 +450,7 @@ status = "disabled"; }; - hsi2c_7: hsi2c@13e10000 { + hsi2c_7: i2c@13e10000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13e10000 0x1000>; interrupts = ; @@ -463,7 +463,7 @@ status = "disabled"; }; - hsi2c_8: hsi2c@14e20000 { + hsi2c_8: i2c@14e20000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e20000 0x1000>; interrupts = ; @@ -476,7 +476,7 @@ status = "disabled"; }; - hsi2c_9: hsi2c@13680000 { + hsi2c_9: i2c@13680000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13680000 0x1000>; interrupts = ; @@ -489,7 +489,7 @@ status = "disabled"; }; - hsi2c_10: hsi2c@13690000 { + hsi2c_10: i2c@13690000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13690000 0x1000>; interrupts = ; @@ -502,7 +502,7 @@ status = "disabled"; }; - hsi2c_11: hsi2c@136a0000 { + hsi2c_11: i2c@136a0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x136a0000 0x1000>; interrupts = ; From 856732adc1acbfdf457ec7a875a252d6fb039294 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 3 Dec 2021 22:24:33 +0530 Subject: [PATCH 225/574] ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit has plugged with 7" LVDS panel. Engicam i.Core STM32MP1 SoM has SN65DSI84 DSI to LVDS bridge. This patch adds a display pipeline to connect DSI to SN65DSI84 to 7" LVDS panel. Signed-off-by: Jagan Teki Signed-off-by: Alexandre Torgue --- .../stm32mp157a-icore-stm32mp1-edimm2.2.dts | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts index ec9f1d1cd50f..a797eaa917b7 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -24,6 +24,91 @@ chosen { stdout-path = "serial0:115200n8"; }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + default-on; + }; + + panel { + compatible = "yes-optoelectronics,ytc700tlag-05-201c"; + backlight = <&backlight>; + power-supply = <&v3v3>; + + port { + panel_out_bridge: endpoint { + remote-endpoint = <&bridge_out_panel>; + }; + }; + }; +}; + +&dsi { + status = "okay"; + phy-dsi-supply = <®18>; + + ports { + port@0 { + reg = <0>; + dsi_in_ltdc: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out_bridge: endpoint { + remote-endpoint = <&bridge_in_dsi>; + }; + }; + }; +}; + +&i2c6 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_a>; + pinctrl-1 = <&i2c6_sleep_pins_a>; + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in_dsi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + data-lanes = <1 2>; + }; + }; + + port@2 { + reg = <2>; + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_out_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in_ltdc>; + }; + }; }; &sdmmc1 { From 854b020b165fbdf040ab6872a75a6094803a6932 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 3 Dec 2021 22:24:34 +0530 Subject: [PATCH 226/574] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0 10.1" Open Frame board. Add bindings for it. Signed-off-by: Jagan Teki Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index bcaf7be3ab37..b07720ea9611 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -77,6 +77,7 @@ properties: items: - enum: - engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 + - engicam,icore-stm32mp1-ctouch2-of10 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF - engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit - const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM - const: st,stm32mp157 From 3ff0810ffc4793bfde454a452837484d0815aa14 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 3 Dec 2021 22:24:35 +0530 Subject: [PATCH 227/574] ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - 10" LVDS Panel (SN65DSI84 DSI-LVDS bridge on SoM) i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0 10.1" Open Frame board. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + ...tm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 132 ++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..641220e970e8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1140,6 +1140,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ stm32mp157a-icore-stm32mp1-ctouch2.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \ stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts new file mode 100644 index 000000000000..2a2829283456 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-icore-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1\" Open Frame"; + compatible = "engicam,icore-stm32mp1-ctouch2-of10", + "engicam,icore-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + default-on; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + panel { + compatible = "ampire,am-1280800n3tzqw-t00h"; + backlight = <&backlight>; + power-supply = <&v3v3>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; +}; + +&dsi { + status = "okay"; + phy-dsi-supply = <®18>; + + ports { + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&i2c6 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_a>; + pinctrl-1 = <&i2c6_sleep_pins_a>; + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <1 2>; + }; + }; + + port@2 { + reg = <2>; + bridge_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; From 1bf6751c8d8e2989b7b8611080b3b3b1bc0b83f4 Mon Sep 17 00:00:00 2001 From: Andrei Kartashev Date: Fri, 19 Nov 2021 15:00:56 +0300 Subject: [PATCH 228/574] dt-bindings: vendor-prefixes: add YADRO Add vendor prefix for YADRO (https://www.yadro.com/) Signed-off-by: Andrei Kartashev Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211119120057.12118-2-a.kartashev@yadro.com Signed-off-by: Joel Stanley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 66d6432fd781..f0cb7dd11698 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1350,6 +1350,8 @@ patternProperties: description: Shenzhen Xunlong Software CO.,Limited "^xylon,.*": description: Xylon + "^yadro,.*": + description: YADRO "^yamaha,.*": description: Yamaha Corporation "^yes-optoelectronics,.*": From 67ac01d03862b274d4ca3fa76092e96b00f478af Mon Sep 17 00:00:00 2001 From: Andrei Kartashev Date: Fri, 19 Nov 2021 15:00:57 +0300 Subject: [PATCH 229/574] ARM: dts: aspeed: add device tree for YADRO VEGMAN BMC YADRO VEGMAN is x86 based servers family with ASPEED AST2500-based BMC. Currently there are three models: * VEGMAN N110 * VEGMAN S220/320 * VEGMAN R120/220 The dts files provides configuration for BMC system. Signed-off-by: Andrei Kartashev Link: https://lore.kernel.org/r/20211119120057.12118-3-a.kartashev@yadro.com Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 5 +- arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts | 149 +++++++++ arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts | 255 +++++++++++++++ arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts | 154 +++++++++ arch/arm/boot/dts/aspeed-bmc-vegman.dtsi | 311 +++++++++++++++++++ 5 files changed, 873 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-vegman.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..78b71e02624c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1519,4 +1519,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-quanta-q71l.dtb \ aspeed-bmc-supermicro-x11spi.dtb \ aspeed-bmc-inventec-transformers.dtb \ - aspeed-bmc-tyan-s7106.dtb + aspeed-bmc-tyan-s7106.dtb \ + aspeed-bmc-vegman-n110.dtb \ + aspeed-bmc-vegman-rx20.dtb \ + aspeed-bmc-vegman-sx20.dtb diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts b/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts new file mode 100644 index 000000000000..24319267d550 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO +/dts-v1/; + +#include "aspeed-bmc-vegman.dtsi" + +/ { + model = "YADRO VEGMAN N110 BMC"; + compatible = "yadro,vegman-n110-bmc", "aspeed,ast2500"; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", + /*F0-F7*/ "NMI_OUT","PCIE_NIC_ALERT","","","SKT0_FAULT_LED","","RST_RGMII_PHYRST_DNP","", + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", + /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", + /*AA0-AA7*/ "","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpio { + ngpios = <80>; + bus-frequency = <2000000>; + status = "okay"; + /* SGPIO lines. even: input, odd: output */ + gpio-line-names = + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", + /*D0-D7*/ "","","","","","","","","","","","","","","","", + /*E0-E7*/ "","","","","","","","","","","","","","","","", + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", + /*H0-H7*/ "","","","","","","","","","","","","","","","", + /*I0-I7*/ "","","","","","","","","","","","","","","","", + /*J0-J7*/ "","","","","","","","","","","","","","","",""; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "", "", "", "", "", "", "PE_PCH_SCR_CLKREQ", "", + /*IO1.0-1.7*/ "", "PE_PCH_MEZ_PRSNT", "PE_PCH_MEZ_PRSNT_", "NIC_4_PE_PRSNT", "NIC_3_PE_PRSNT", "NIC_2_PE_PRSNT", "NIC_1_PE_PRSNT", ""; + }; + gpio@27 { + compatible = "nxp,pca9698"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "", "", "", + /*IO3.0-3.7*/ "", "", "", "", "", "", "", "", + /*IO4.0-4.7*/ "", "", "", "", "", "", "", ""; + }; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + mux-expa@73 { + compatible = "nxp,pca9545"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; + mux-sata@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + mux-expb@71 { + compatible = "nxp,pca9545"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x06>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts b/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts new file mode 100644 index 000000000000..ebbb68b55559 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO +/dts-v1/; + +#include "aspeed-bmc-vegman.dtsi" + +/ { + model = "YADRO VEGMAN Rx20 BMC"; + compatible = "yadro,vegman-rx20-bmc", "aspeed,ast2500"; + + leds { + compatible = "gpio-leds"; + + temp_alarm { + label = "temp:red:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 4) GPIO_ACTIVE_LOW>; + }; + + temp_ok { + label = "temp:green:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; + }; + + psu_fault { + label = "psu:red:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_LOW>; + }; + + psu_ok { + label = "psu:green:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "CASE_OPEN_DNP","CASE_OPEN_FAULT_RST_DNP","BEZEL_ON_PWR_P3V3","PWM_PWRGD_EXP_EN","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","LED_TEMP_STATUS_R","LED_TEMP_STATUS_G","LED_PWR_STATUS_R","LED_PWR_STATUS_G", + /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED_DNP","SKT1_FAULT_LED_DNP","RST_RGMII_PHYRST_DNP","", + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","SPI_BMC_BOOT_HD","IRQ_NMI_EVENT","SPI_BMC_BOOT_WP","SPI_BMC_BOOT_WP1","", + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "SEL_FLASH_SOFT","STATUS_SEL_BMC","","","BMC_WDT_P","ID_BUTTON","PS_PWROK","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","SPI_BIOS_ACTIVE_FLASH_SEL","STATUS_SEL_BIOS", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "_SPI_BMC_BOOT_CS1","","","","","","","", + /*S0-S7*/ "_SPI2_BMC_CS1","RSR_A_SMBEXP_RST_INT","RSR_B_SMBEXP_RST_INT","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", + /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","BMC_WDT_RST1","BMC_WDT_RST2","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpio { + ngpios = <80>; + bus-frequency = <2000000>; + status = "okay"; + /* SGPIO lines. even: input, odd: output */ + gpio-line-names = + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", + /*D0-D7*/ "","","","","","","","","","","","","","","","", + /*E0-E7*/ "","","","","","","","","","","","","","","","", + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", + /*H0-H7*/ "","","","","","","","","","","","","","","","", + /*I0-I7*/ "","","","","","","","","","","","","","","","", + /*J0-J7*/ "","","","","","","","","","","","","","","",""; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "ETH3_CLK_REQ", "ETH2_CLK_REQ", "RSR_A_PCIE_X16_2_PRSNT", "RSR_B_PCIE_X16_2_PRSNT", "", "RSR_B_PCIE_X8_3_PRSNT", "RSR_B_PCIE_X8_4_PRSNT", "RSR_B_PCIE_X16_PRSNT_N", + /*IO1.0-1.7*/ "RSR_B_PCIE_X8_2_PRSNT", "RSR_B_PCIE_X8_1_PRSNT", "NIC_1_PE_BUF_PRSNT", "RSR_A_PCIE_X16_PRSNT", "RSR_A_PCIE_X8_3_PRSNT", "RSR_A_PCIE_X8_2_PRSNT", "RSR_A_PCIE_X8_1_PRSNT_N", ""; + }; + gpio@23 { + compatible = "nxp,pcal9535"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "", "", "", + /*IO1.0-1.7*/ "", "", "", "", "", "", "", ""; + }; + gpio@27 { + compatible = "nxp,pca9698"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", + /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", + /*IO4.0-4.7*/ "PCH_PWR_RESET_N", "FM_BOARD_SKU_ID0", "FM_BOARD_SKU_ID1", "FM_BOARD_SKU_ID2", "FM_BOARD_SKU_ID3", "FM_BOARD_SKU_ID4", "FM_BOARD_REV_ID0", "FM_BOARD_REV_ID1"; + }; + gpio@39 { + compatible = "nxp,pca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "FAN_FAULT_0", "FAN_FAULT_1", "FAN_FAULT_2", "FAN_FAULT_3", "FAN_FAULT_4", "FAN_FAULT_5", "FAN_FAULT_6", ""; + }; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + mux-expa@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + rsra-mux@72 { + compatible = "nxp,pca9548"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + }; + }; + }; + }; + mux-sata@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + mux-expb@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rsrb-mux@72 { + compatible = "nxp,pca9548"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + }; + }; + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + }; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x07>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0C>; + }; + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0D>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts b/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts new file mode 100644 index 000000000000..e36ee4704994 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO +/dts-v1/; + +#include "aspeed-bmc-vegman.dtsi" + +/ { + model = "YADRO VEGMAN Sx20 BMC"; + compatible = "yadro,vegman-sx20-bmc", "aspeed,ast2500"; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", + /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED","SKT1_FAULT_LED","RST_RGMII_PHYRST_DNP","", + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","BMC_GPU_RISER_ID1","BMC_GPU_RISER_ID0","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", + /*P0-P7*/ "","P12V_HDDS_A_EN","P12V_HDDS_B_EN","P5V_HDDS_A_EN","PWRGD_P5V_HDDS_A","P5V_HDDS_B_EN","PWRGD_P5V_HDDS_B","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", + /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", + /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpio { + ngpios = <80>; + bus-frequency = <2000000>; + status = "okay"; + /* SGPIO lines. even: input, odd: output */ + gpio-line-names = + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", + /*D0-D7*/ "","","","","","","","","","","","","","","","", + /*E0-E7*/ "","","","","","","","","","","","","","","","", + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", + /*H0-H7*/ "","","","","","","","","","","","","","","","", + /*I0-I7*/ "","","","","","","","","","","","","","","","", + /*J0-J7*/ "","","","","","","","","","","","","","","",""; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "", "", "CPU1_PE3_0_SLOT_PRSNT", "", "CPU1_PE1_GPU_PRSNT", "CPU1_PE3_1_SLOT_PRSNT", "PE_PCH_MEZ_PRSNT", "CPU0_PE3_1_SLOT_PRSNT", + /*IO1.0-1.7*/ "CPU0_PE1_GPU_PRSNT", "CPU0_PE2_NVME2_PRSNT", "CPU1_PE2_NVME3_PRSNT", "CPU1_PE2_SLOT_PRSNT", "CPU1_PE2_NVME4_PRSNT", "", "CPU0_PE2_NVME1_PRSNT", "CPU0_PE3_0_RAID_PRSNT"; + }; + gpio@27 { + compatible = "nxp,pca9698"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", + /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", + /*IO4.0-4.7*/ "PWRGD_P5V_HDDS_A_R", "PWRGD_P5V_HDDS_B_R", "", "", "", "", "", ""; + }; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + mux-expa@73 { + compatible = "nxp,pca9545"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; + mux-sata@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + mux-expb@71 { + compatible = "nxp,pca9545"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi b/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi new file mode 100644 index 000000000000..1a5b25b2ea29 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO + +#include "aspeed-g5.dtsi" +#include + +/ { + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + ramoops@9eff0000{ + compatible = "ramoops"; + reg = <0x9eff0000 0x10000>; + record-size = <0x2000>; + console-size = <0x2000>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; + + leds { + compatible = "gpio-leds"; + + identify { + label = "platform:blue:indicator"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; + }; + + status_amber { + label = "platform:red:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(S, 5) GPIO_ACTIVE_LOW>; + }; + + status_green { + label = "platform:green:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(S, 4) GPIO_ACTIVE_LOW>; + }; + + power_fault { + label = "platform:red:power"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>; + }; + + power_ok { + label = "platform:green:power"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(AA, 5) GPIO_ACTIVE_LOW>; + }; + }; + + beeper { + compatible = "pwm-beeper"; + pwms = <&timer 5 1000000 0>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2ck_default + &pinctrl_spi2miso_default + &pinctrl_spi2mosi_default + &pinctrl_spi2cs0_default>; + flash@0 { + status = "okay"; + label = "bios"; + m25p,fast-read; + }; +}; + +&mac0 { + status = "okay"; + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; + + phy-mode = "rgmii"; + phy-handle = <&phy>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + /* KSZ9131 */ + compatible = "ethernet-phy-id0022.1640"; + reg = <1>; + + micrel,led-mode = <0>; + }; + }; +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&sdmmc { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_default>; + disable-wp; +}; + +&timer { + fttmr010,pwm-outputs = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_timer5_default>; + #pwm-cells = <3>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xCA2>; + status = "okay"; +}; + +&kcs4 { + aspeed,lpc-io-reg = <0xCA4>; + status = "okay"; +}; + +&lpc_snoop { + snoop-ports = <0x80>; + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + +&i2c0 { + /* SMB_IPMB_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c1 { + /* SMB_CHASSENSOR_STBY_LVC3 */ + status = "okay"; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + status = "okay"; +}; + +&i2c3 { + /* SMB_HOST_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c4 { + /* BMC_PMBUS2_STBY */ + status = "okay"; +}; + +&i2c5 { + /* SMB_SMLINK0_STBY_LVC3 */ + bus-frequency = <1000000>; + multi-master; + status = "okay"; +}; + +&i2c6 { + /* SMB_TEMPSENSOR_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c7 { + /* SMB_SM_PMB1_SML1_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c9 { + /* SMB_BMC_ETH3_LVC3 */ + status = "okay"; +}; + +&i2c10 { + /* SMB_BMC_ETH2_LVC3 */ + status = "okay"; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + status = "okay"; + + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; +}; + +&i2c12 { + /* SMB_BMC_FAULT_EXP_LVC3 */ + status = "okay"; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + status = "okay"; +}; From 9e9652862ac253e7b589e6c624ac6f40df5fa297 Mon Sep 17 00:00:00 2001 From: Sven Peter Date: Tue, 30 Nov 2021 17:18:08 +0100 Subject: [PATCH 230/574] dt-bindings: watchdog: Add Apple Watchdog Apple SoCs come with a simple embedded watchdog. This watchdog is also required in order to reset the SoC. Reviewed-by: Mark Kettenis Reviewed-by: Rob Herring Signed-off-by: Sven Peter Reviewed-by: Guenter Roeck Signed-off-by: Hector Martin --- .../bindings/watchdog/apple,wdt.yaml | 52 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/apple,wdt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml new file mode 100644 index 000000000000..e58c56a6fdf6 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/apple,wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC Watchdog + +allOf: + - $ref: "watchdog.yaml#" + +maintainers: + - Sven Peter + +properties: + compatible: + items: + - enum: + - apple,t8103-wdt + - apple,t6000-wdt + - const: apple,wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + + wdt: watchdog@50000000 { + compatible = "apple,t8103-wdt", "apple,wdt"; + reg = <0x50000000 0x4000>; + clocks = <&clk>; + interrupts = ; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 7a2345ce8521..1e280e6abaf7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1750,6 +1750,7 @@ F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml F: Documentation/devicetree/bindings/pci/apple,pcie.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml F: arch/arm64/boot/dts/apple/ F: drivers/i2c/busses/i2c-pasemi-core.c F: drivers/i2c/busses/i2c-pasemi-platform.c From bd4d13ed210a6d3aadaaa9c93ee7e0671579cd10 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Mon, 25 Oct 2021 23:31:16 +0900 Subject: [PATCH 231/574] MAINTAINERS: Add PMGR power state files to ARM/APPLE MACHINE This covers the PMGR power state driver and its DT bindings, as well as any other future stuff in drivers/soc/apple. Signed-off-by: Hector Martin --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1e280e6abaf7..03ffcf49f5cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1745,11 +1745,13 @@ B: https://github.com/AsahiLinux/linux/issues C: irc://irc.oftc.net/asahi-dev T: git https://github.com/AsahiLinux/linux.git F: Documentation/devicetree/bindings/arm/apple.yaml +F: Documentation/devicetree/bindings/arm/apple/* F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml F: Documentation/devicetree/bindings/pci/apple,pcie.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +F: Documentation/devicetree/bindings/power/apple* F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml F: arch/arm64/boot/dts/apple/ F: drivers/i2c/busses/i2c-pasemi-core.c @@ -1757,6 +1759,7 @@ F: drivers/i2c/busses/i2c-pasemi-platform.c F: drivers/irqchip/irq-apple-aic.c F: drivers/mailbox/apple-mailbox.c F: drivers/pinctrl/pinctrl-apple-gpio.c +F: drivers/soc/apple/* F: include/dt-bindings/interrupt-controller/apple-aic.h F: include/dt-bindings/pinctrl/apple.h F: include/linux/apple-mailbox.h From e8117f85b95b932069b9db73ccb3ee973ade2fc9 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 16:34:16 +0900 Subject: [PATCH 232/574] dt-bindings: power: Add apple,pmgr-pwrstate binding This syscon child node represents a single SoC device controlled by the PMGR block. This layout allows us to declare all device power state controls (power/clock gating and reset) in the device tree, including dependencies, instead of hardcoding it into the driver. The register layout is uniform. Each pmgr-pwrstate node provides genpd and reset features, to be consumed by downstream device nodes. Future SoCs are expected to use backwards compatible registers, and the "apple,pmgr-pwrstate" represents any such interfaces (possibly with additional features gated by the more specific compatible), allowing them to be bound without driver updates. If a backwards incompatible change is introduced in future SoCs, it will require a new compatible, such as "apple,pmgr-pwrstate-v2". Reviewed-by: Mark Kettenis Reviewed-by: Rob Herring Signed-off-by: Hector Martin --- .../bindings/power/apple,pmgr-pwrstate.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml new file mode 100644 index 000000000000..5056d08b8261 --- /dev/null +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC PMGR Power States + +maintainers: + - Hector Martin + +allOf: + - $ref: "power-domain.yaml#" + +description: | + Apple SoCs include PMGR blocks responsible for power management, + which can control various clocks, resets, power states, and + performance features. This binding describes the device power + state registers, which control power states and resets. + + Each instance of a power controller within the PMGR syscon node + represents a generic power domain provider, as documented in + Documentation/devicetree/bindings/power/power-domain.yaml. + The provider controls a single SoC block. The power hierarchy is + represented via power-domains relationships between these nodes. + + See Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml + for the top-level PMGR node documentation. + +properties: + compatible: + items: + - enum: + - apple,t8103-pmgr-pwrstate + - apple,t6000-pmgr-pwrstate + - const: apple,pmgr-pwrstate + + reg: + maxItems: 1 + + "#power-domain-cells": + const: 0 + + "#reset-cells": + const: 0 + + power-domains: + description: + Reference to parent power domains. A domain may have multiple parents, + and all will be powered up when it is powered. + minItems: 1 + maxItems: 8 # Arbitrary, should be enough + + label: + description: + Specifies the name of the SoC domain being controlled. This is used to + name the power/reset domains. + + apple,always-on: + description: + Forces this power domain to always be powered up. + type: boolean + +required: + - compatible + - reg + - "#power-domain-cells" + - "#reset-cells" + - label + +additionalProperties: false From c83eeec79ff64f777cbd59a8bd15d0a3fe1f92c0 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 16:34:17 +0900 Subject: [PATCH 233/574] dt-bindings: arm: apple: Add apple,pmgr binding The PMGR block in Apple Silicon SoCs is responsible for SoC power management. There are two PMGRs in T8103, with different register layouts but compatible registers. In order to support this as well as future SoC generations with backwards-compatible registers, we declare these blocks as syscons and bind to individual registers in child nodes. Each register controls one SoC device. The respective apple compatibles are defined in case device-specific quirks are necessary in the future, but currently these nodes are expected to be bound by the generic syscon driver. Reviewed-by: Mark Kettenis Reviewed-by: Rob Herring Signed-off-by: Hector Martin --- .../bindings/arm/apple/apple,pmgr.yaml | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml new file mode 100644 index 000000000000..b6b5d3a912b3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/apple/apple,pmgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC Power Manager (PMGR) + +maintainers: + - Hector Martin + +description: | + Apple SoCs include PMGR blocks responsible for power management, + which can control various clocks, resets, power states, and + performance features. This node represents the PMGR as a syscon, + with sub-nodes representing individual features. + +properties: + $nodename: + pattern: "^power-management@[0-9a-f]+$" + + compatible: + items: + - enum: + - apple,t8103-pmgr + - apple,t6000-pmgr + - const: apple,pmgr + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +patternProperties: + "power-controller@[0-9a-f]+$": + description: + The individual power management domains within this controller + type: object + $ref: /power/apple,pmgr-pwrstate.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + power-management@23b700000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3b700000 0x0 0x14000>; + + ps_sio: power-controller@1c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + apple,always-on; + }; + + ps_uart_p: power-controller@220 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x220 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_p"; + power-domains = <&ps_sio>; + }; + + ps_uart0: power-controller@270 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_uart_p>; + }; + }; + + power-management@23d280000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3d280000 0x0 0xc000>; + + ps_aop_filter: power-controller@4000 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4000 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_aop_base: power-controller@4010 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4010 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_base"; + power-domains = <&ps_aop_filter>; + }; + + ps_aop_shim: power-controller@4038 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4038 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_shim"; + power-domains = <&ps_aop_base>; + }; + + ps_aop_uart0: power-controller@4048 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4048 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_uart0"; + power-domains = <&ps_aop_shim>; + }; + }; + }; From 106ba3b48a35ddf819ec5786208cf109c81da161 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 16:34:19 +0900 Subject: [PATCH 234/574] arm64: dts: apple: t8103: Add PMGR nodes This adds the two PMGR nodes and all known power state subnodes. Since there are a large number of them, let's put them in a separate file to include. Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-pmgr.dtsi | 1136 +++++++++++++++++++++ arch/arm64/boot/dts/apple/t8103.dtsi | 29 + 2 files changed, 1165 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8103-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi new file mode 100644 index 000000000000..1310be74df1d --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -0,0 +1,1136 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8103 "M1" SoC + * + * Copyright The Asahi Linux Contributors + */ + + +&pmgr { + ps_sbr: power-controller@100 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@108 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@110 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + apple,always-on; /* Core device */ + }; + + ps_soc_spmi0: power-controller@118 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_spmi0"; + }; + + ps_soc_spmi1: power-controller@120 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_spmi1"; + }; + + ps_soc_spmi2: power-controller@128 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_spmi2"; + }; + + ps_gpio: power-controller@130 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms_busif: power-controller@138 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_busif"; + apple,always-on; /* Core device */ + }; + + ps_pms: power-controller@140 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_pms_fpwm0: power-controller@148 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm0"; + power-domains = <&ps_pms>; + }; + + ps_pms_fpwm1: power-controller@150 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm1"; + power-domains = <&ps_pms>; + }; + + ps_pms_fpwm2: power-controller@158 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm2"; + power-domains = <&ps_pms>; + }; + + ps_pms_fpwm3: power-controller@160 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm3"; + power-domains = <&ps_pms>; + }; + + ps_pms_fpwm4: power-controller@168 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm4"; + power-domains = <&ps_pms>; + }; + + ps_soc_dpe: power-controller@170 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_dpe"; + apple,always-on; /* Core device */ + }; + + ps_pmgr_soc_ocla: power-controller@178 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmgr_soc_ocla"; + }; + + ps_ispsens0: power-controller@180 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_ispsens1: power-controller@188 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens1"; + }; + + ps_ispsens2: power-controller@190 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens2"; + }; + + ps_ispsens3: power-controller@198 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens3"; + }; + + ps_pcie_ref: power-controller@1a0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_aft0: power-controller@1a8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aft0"; + }; + + ps_devc0_ivdmc: power-controller@1b0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "devc0_ivdmc"; + }; + + ps_imx: power-controller@1b8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "imx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sio_busif: power-controller@1c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio: power-controller@1c8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_busif>; + }; + + ps_sio_cpu: power-controller@1d0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_cpu"; + power-domains = <&ps_sio>; + }; + + ps_fpwm0: power-controller@1d8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm0"; + }; + + ps_fpwm1: power-controller@1e0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm1"; + }; + + ps_fpwm2: power-controller@1e8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm2"; + }; + + ps_i2c0: power-controller@1f0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio>; + }; + + ps_i2c1: power-controller@1f8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio>; + }; + + ps_i2c2: power-controller@200 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio>; + }; + + ps_i2c3: power-controller@208 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio>; + }; + + ps_i2c4: power-controller@210 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c4"; + power-domains = <&ps_sio>; + }; + + ps_spi_p: power-controller@218 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi_p"; + power-domains = <&ps_sio>; + }; + + ps_uart_p: power-controller@220 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_p"; + power-domains = <&ps_sio>; + }; + + ps_audio_p: power-controller@228 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "audio_p"; + power-domains = <&ps_sio>; + }; + + ps_sio_adma: power-controller@230 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_adma"; + power-domains = <&ps_sio>, <&ps_pms>; + }; + + ps_aes: power-controller@238 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes"; + power-domains = <&ps_sio>; + }; + + ps_spi0: power-controller@240 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio>, <&ps_spi_p>; + }; + + ps_spi1: power-controller@248 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio>, <&ps_spi_p>; + }; + + ps_spi2: power-controller@250 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio>, <&ps_spi_p>; + }; + + ps_spi3: power-controller@258 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio>, <&ps_spi_p>; + }; + + ps_uart_n: power-controller@268 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_n"; + power-domains = <&ps_uart_p>; + }; + + ps_uart0: power-controller@270 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_uart_p>; + }; + + ps_uart1: power-controller@278 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_uart_p>; + }; + + ps_uart2: power-controller@280 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_uart_p>; + }; + + ps_uart3: power-controller@288 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_uart_p>; + }; + + ps_uart4: power-controller@290 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_uart_p>; + }; + + ps_uart5: power-controller@298 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_uart_p>; + }; + + ps_uart6: power-controller@2a0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_uart_p>; + }; + + ps_uart7: power-controller@2a8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_uart_p>; + }; + + ps_uart8: power-controller@2b0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_uart_p>; + }; + + ps_mca0: power-controller@2b8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_audio_p>, <&ps_sio_adma>; + }; + + ps_mca1: power-controller@2c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_audio_p>, <&ps_sio_adma>; + }; + + ps_mca2: power-controller@2c8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_audio_p>, <&ps_sio_adma>; + }; + + ps_mca3: power-controller@2d0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_audio_p>, <&ps_sio_adma>; + }; + + ps_mca4: power-controller@2d8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_audio_p>, <&ps_sio_adma>; + }; + + ps_mca5: power-controller@2e0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca5"; + power-domains = <&ps_audio_p>, <&ps_sio_adma>; + }; + + ps_dpa0: power-controller@2e8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa0"; + power-domains = <&ps_audio_p>; + }; + + ps_dpa1: power-controller@2f0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa1"; + power-domains = <&ps_audio_p>; + }; + + ps_mcc: power-controller@2f8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory controller */ + }; + + ps_spi4: power-controller@260 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi4"; + power-domains = <&ps_sio>, <&ps_spi_p>; + }; + + ps_dcs0: power-controller@300 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@310 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@308 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@318 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_smx: power-controller@340 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_apcie: power-controller@348 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie"; + power-domains = <&ps_imx>, <&ps_pcie_ref>; + }; + + ps_rmx: power-controller@350 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rmx"; + /* Apple Fabric, display/image stuff: this can power down */ + }; + + ps_mmx: power-controller@358 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x358 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mmx"; + /* Apple Fabric, media stuff: this can power down */ + }; + + ps_disp0_fe: power-controller@360 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x360 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_fe"; + power-domains = <&ps_rmx>; + apple,always-on; /* TODO: figure out if we can enable PM here */ + }; + + ps_dispext_fe: power-controller@368 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x368 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext_fe"; + power-domains = <&ps_rmx>; + }; + + ps_dispext_cpu0: power-controller@378 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x378 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext_cpu0"; + power-domains = <&ps_dispext_fe>; + }; + + ps_jpg: power-controller@3c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_mmx>; + }; + + ps_msr: power-controller@3c8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_mmx>; + }; + + ps_msr_ase_core: power-controller@3d0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr_ase_core"; + }; + + ps_pmp: power-controller@3d8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@3e0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_apcie_gp: power-controller@3e8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_gp"; + power-domains = <&ps_apcie>; + }; + + ps_ans2: power-controller@3f0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans2"; + /* + * The ADT makes ps_apcie_st depend on ps_ans2 instead, but this + * doesn't make much sense since ANS2 uses APCIE_ST. + */ + power-domains = <&ps_apcie_st>; + }; + + ps_gfx: power-controller@3f8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_dcs4: power-controller@320 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs4"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs5: power-controller@330 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs5"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs6: power-controller@328 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs6"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs7: power-controller@338 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs7"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dispdfr_fe: power-controller@3a8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispdfr_fe"; + power-domains = <&ps_rmx>; + }; + + ps_dispdfr_be: power-controller@3b0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispdfr_be"; + power-domains = <&ps_dispdfr_fe>; + }; + + ps_mipi_dsi: power-controller@3b8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_dispdfr_be>; + }; + + ps_isp_sys: power-controller@400 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + power-domains = <&ps_rmx>; + }; + + ps_venc_sys: power-controller@408 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x408 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + power-domains = <&ps_mmx>; + }; + + ps_avd_sys: power-controller@410 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x410 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "avd_sys"; + power-domains = <&ps_mmx>; + }; + + ps_apcie_st: power-controller@418 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x418 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_st"; + power-domains = <&ps_apcie>; + }; + + ps_ane_sys: power-controller@470 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x470 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ane_sys"; + }; + + ps_atc0_common: power-controller@420 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x420 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_common"; + }; + + ps_atc0_pcie: power-controller@428 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x428 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_pcie"; + power-domains = <&ps_atc0_common>; + }; + + ps_atc0_cio: power-controller@430 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x430 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio"; + power-domains = <&ps_atc0_common>; + }; + + ps_atc0_cio_pcie: power-controller@438 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x438 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio_pcie"; + power-domains = <&ps_atc0_cio>; + }; + + ps_atc0_cio_usb: power-controller@440 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x440 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio_usb"; + power-domains = <&ps_atc0_cio>; + }; + + ps_atc1_common: power-controller@448 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x448 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_common"; + }; + + ps_atc1_pcie: power-controller@450 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x450 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_pcie"; + power-domains = <&ps_atc1_common>; + }; + + ps_atc1_cio: power-controller@458 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x458 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio"; + power-domains = <&ps_atc1_common>; + }; + + ps_atc1_cio_pcie: power-controller@460 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x460 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio_pcie"; + power-domains = <&ps_atc1_cio>; + }; + + ps_atc1_cio_usb: power-controller@468 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x468 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio_usb"; + power-domains = <&ps_atc1_cio>; + }; + + ps_sep: power-controller@c00 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xc00 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_venc_dma: power-controller@8000 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_dma"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_pipe4: power-controller@8008 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + power-domains = <&ps_venc_dma>; + }; + + ps_venc_pipe5: power-controller@8010 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + power-domains = <&ps_venc_dma>; + }; + + ps_venc_me0: power-controller@8018 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>; + }; + + ps_venc_me1: power-controller@8020 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>; + }; + + ps_ane_sys_cpu: power-controller@c000 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xc000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ane_sys_cpu"; + power-domains = <&ps_ane_sys>; + }; + + ps_disp0_cpu0: power-controller@10018 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x10018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_cpu0"; + power-domains = <&ps_disp0_fe>; + apple,always-on; /* TODO: figure out if we can enable PM here */ + }; +}; + +&pmgr_mini { + ps_debug: power-controller@58 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x58 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_spmi0: power-controller@60 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x60 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi0"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_aon: power-controller@70 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x70 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_aon"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_gpio: power-controller@80 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_gpio"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_fabric: power-controller@a8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xa8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_fabric"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_sram: power-controller@b0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xb0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_sram"; + apple,always-on; /* Core AON device */ + }; + + ps_debug_usb: power-controller@b8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xb8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug_usb"; + apple,always-on; /* Core AON device */ + power-domains = <&ps_debug>; + }; + + ps_debug_auth: power-controller@c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xc0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug_auth"; + apple,always-on; /* Core AON device */ + power-domains = <&ps_debug>; + }; + + ps_nub_spmi1: power-controller@68 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x68 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi1"; + apple,always-on; /* Core AON device */ + }; + + ps_msg: power-controller@78 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x78 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msg"; + }; + + ps_atc0_usb_aon: power-controller@88 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_usb_aon"; + }; + + ps_atc1_usb_aon: power-controller@90 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x90 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_usb_aon"; + }; + + ps_atc0_usb: power-controller@98 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x98 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_usb"; + power-domains = <&ps_atc0_usb_aon>, <&ps_atc0_common>; + }; + + ps_atc1_usb: power-controller@a0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xa0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_usb"; + power-domains = <&ps_atc1_usb_aon>, <&ps_atc1_common>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index c62d9082c6a3..1055a38ed299 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -121,6 +121,7 @@ pinctrl-names = "default"; #address-cells = <0x1>; #size-cells = <0x0>; + power-domains = <&ps_i2c0>; }; i2c1: i2c@235014000 { @@ -133,6 +134,7 @@ pinctrl-names = "default"; #address-cells = <0x1>; #size-cells = <0x0>; + power-domains = <&ps_i2c1>; }; i2c2: i2c@235018000 { @@ -146,6 +148,7 @@ #address-cells = <0x1>; #size-cells = <0x0>; status = "disabled"; /* not used in all devices */ + power-domains = <&ps_i2c2>; }; i2c3: i2c@23501c000 { @@ -158,6 +161,7 @@ pinctrl-names = "default"; #address-cells = <0x1>; #size-cells = <0x0>; + power-domains = <&ps_i2c3>; }; i2c4: i2c@235020000 { @@ -170,6 +174,7 @@ pinctrl-names = "default"; #address-cells = <0x1>; #size-cells = <0x0>; + power-domains = <&ps_i2c4>; status = "disabled"; /* only used in J293 */ }; @@ -185,6 +190,7 @@ */ clocks = <&clk24>, <&clk24>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; @@ -193,11 +199,20 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x2 0x3b100000 0x0 0x8000>; + power-domains = <&ps_aic>; + }; + + pmgr: power-management@23b700000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3b700000 0 0x14000>; }; pinctrl_ap: pinctrl@23c100000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x3c100000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -247,6 +262,13 @@ }; }; + pmgr_mini: power-management@23d280000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3d280000 0 0x4000>; + }; + pinctrl_aop: pinctrl@24a820000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x4a820000 0x0 0x4000>; @@ -271,6 +293,7 @@ pinctrl_nub: pinctrl@23d1f0000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x3d1f0000 0x0 0x4000>; + power-domains = <&ps_nub_gpio>; gpio-controller; #gpio-cells = <2>; @@ -316,6 +339,7 @@ #iommu-cells = <1>; interrupt-parent = <&aic>; interrupts = ; + power-domains = <&ps_apcie_gp>; }; pcie0_dart_1: dart@682008000 { @@ -324,6 +348,7 @@ #iommu-cells = <1>; interrupt-parent = <&aic>; interrupts = ; + power-domains = <&ps_apcie_gp>; }; pcie0_dart_2: dart@683008000 { @@ -332,6 +357,7 @@ #iommu-cells = <1>; interrupt-parent = <&aic>; interrupts = ; + power-domains = <&ps_apcie_gp>; }; pcie0: pcie@690000000 { @@ -366,6 +392,7 @@ ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; + power-domains = <&ps_apcie_gp>; pinctrl-0 = <&pcie_pins>; pinctrl-names = "default"; @@ -431,3 +458,5 @@ }; }; }; + +#include "t8103-pmgr.dtsi" From 2ba22cfeda44566aeb333f519ade0633e405aade Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Mon, 20 Sep 2021 02:28:20 +0900 Subject: [PATCH 235/574] arm64: dts: apple: t8103: Add UART2 This UART is connected to the debug port of the WLAN module. It is mostly useless, but makes for a good test case for runtime-pm without having to unbind the console from the main system UART. Reviewed-by: Mark Kettenis Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 5 +++++ arch/arm64/boot/dts/apple/t8103.dtsi | 12 ++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi index 876278fe0afe..e11d5def94b4 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -12,6 +12,7 @@ / { aliases { serial0 = &serial0; + serial2 = &serial2; }; chosen { @@ -39,6 +40,10 @@ status = "okay"; }; +&serial2 { + status = "okay"; +}; + &i2c0 { hpm0: usb-pd@38 { compatible = "apple,cd321x"; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 1055a38ed299..15ee8c8c5fa0 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -194,6 +194,18 @@ status = "disabled"; }; + serial2: serial@235208000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x35208000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = ; + clocks = <&clk24>, <&clk24>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart2>; + status = "disabled"; + }; + aic: interrupt-controller@23b100000 { compatible = "apple,t8103-aic", "apple,aic"; #interrupt-cells = <3>; From bf2c05b619ffc0bccf60d2108bfadc880ee7f5c7 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Mon, 6 Dec 2021 19:38:16 +0100 Subject: [PATCH 236/574] arm64: dts: apple: t8103: Expose PCI node for the WiFi MAC address Expose the PCI node corresponding to the WiFi device and give it a 'local-mac-address' property. The bootloader will update it (m1n1 already has the required feature). Signed-off-by: Mark Kettenis Acked-by: Marc Zyngier Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi index e11d5def94b4..fe2ae40fa9dd 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -13,6 +13,7 @@ aliases { serial0 = &serial0; serial2 = &serial2; + wifi0 = &wifi0; }; chosen { @@ -69,4 +70,9 @@ */ &port00 { bus-range = <1 1>; + wifi0: network@0,0 { + reg = <0x10000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 00 00 00 00 00]; + }; }; From c3e4ea557ddb0a7fa431564bb1bb023ffbf823f4 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Mon, 22 Nov 2021 19:11:53 +0530 Subject: [PATCH 237/574] arm64: dts: ti: k3-am65-mcu: Add Support for MCAN Add Support for two MCAN controllers present on the am65x SOC. Both support classic CAN messages as well as CAN-FD. Signed-off-by: Faiz Abbas Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20211122134159.29936-2-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index c93ff1520a0e..8d592bf41d6f 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -159,6 +159,36 @@ }; }; + m_can0: mcan@40528000 { + compatible = "bosch,m_can"; + reg = <0x0 0x40528000 0x0 0x400>, + <0x0 0x40500000 0x0 0x4400>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 5>, <&k3_clks 102 0>; + clock-names = "hclk", "cclk"; + interrupt-parent = <&gic500>; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + m_can1: mcan@40568000 { + compatible = "bosch,m_can"; + reg = <0x0 0x40568000 0x0 0x400>, + <0x0 0x40540000 0x0 0x4400>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 103 5>, <&k3_clks 103 0>; + clock-names = "hclk", "cclk"; + interrupt-parent = <&gic500>; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + fss: fss@47000000 { compatible = "simple-bus"; #address-cells = <2>; From f533bb82def8b923668df97c36c1f8fe6a3a8f1f Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Mon, 22 Nov 2021 19:11:54 +0530 Subject: [PATCH 238/574] arm64: dts: ti: am654-base-board/am65-iot2050-common: Disable mcan nodes AM654 base board and iot platforms do not have mcan instances pinned out. Therefore, disable all the mcan instances. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20211122134159.29936-3-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 65da226847f4..1e0112b90d9f 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -646,6 +646,14 @@ reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; }; +&m_can0 { + status = "disabled"; +}; + +&m_can1 { + status = "disabled"; +}; + &pcie1_ep { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index cfbcebfa37c1..9043f91c9bec 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -416,6 +416,14 @@ status = "disabled"; }; +&m_can0 { + status = "disabled"; +}; + +&m_can1 { + status = "disabled"; +}; + &mailbox0_cluster0 { interrupts = <436>; From 4688a4fcb7a20d347a52c1f2dc9bc6fad9df1174 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Mon, 22 Nov 2021 19:11:55 +0530 Subject: [PATCH 239/574] arm64: dts: ti: k3-j721e: Add support for MCAN nodes Add support for 14 MCAN controllers in main domain and 2 MCAN controllers present in mcu domain. All the MCAN controllers support classic CAN messages as well as CAN_FD messages. Signed-off-by: Faiz Abbas Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20211122134159.29936-4-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 196 ++++++++++++++++++ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 28 +++ 2 files changed, 224 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index e85c89eebfa3..599861259a30 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1940,4 +1940,200 @@ bus_freq = <1000000>; }; }; + + main_mcan0: can@2701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02701000 0x00 0x200>, + <0x00 0x02708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan1: can@2711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02711000 0x00 0x200>, + <0x00 0x02718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan2: can@2721000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02721000 0x00 0x200>, + <0x00 0x02728000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan3: can@2731000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02731000 0x00 0x200>, + <0x00 0x02738000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan4: can@2741000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02741000 0x00 0x200>, + <0x00 0x02748000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan5: can@2751000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02751000 0x00 0x200>, + <0x00 0x02758000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan6: can@2761000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02761000 0x00 0x200>, + <0x00 0x02768000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan7: can@2771000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02771000 0x00 0x200>, + <0x00 0x02778000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan8: can@2781000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02781000 0x00 0x200>, + <0x00 0x02788000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan9: can@2791000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02791000 0x00 0x200>, + <0x00 0x02798000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan10: can@27a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027a1000 0x00 0x200>, + <0x00 0x027a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan11: can@27b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027b1000 0x00 0x200>, + <0x00 0x027b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan12: can@27c1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027c1000 0x00 0x200>, + <0x00 0x027c8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan13: can@27d1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027d1000 0x00 0x200>, + <0x00 0x027d8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index d2dceda72fe9..b4972dfb7da8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -390,4 +390,32 @@ ti,loczrama = <1>; }; }; + + mcu_mcan0: can@40528000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40528000 0x00 0x200>, + <0x00 0x40500000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 172 0>, <&k3_clks 172 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + mcu_mcan1: can@40568000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40568000 0x00 0x200>, + <0x00 0x40540000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 173 0>, <&k3_clks 173 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; }; From 87d60c4663b6eb964cca6a03adfcf8976f374559 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Mon, 22 Nov 2021 19:11:56 +0530 Subject: [PATCH 240/574] arm64: dts: ti: k3-j721e-common-proc-board: Add support for mcu and main mcan nodes Add four MCAN nodes present on the common processor board and set a maximum data rate of 5 Mbps. Disable all other nodes as they are not brought out on the common processor board. Signed-off-by: Faiz Abbas Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20211122134159.29936-5-a-govindraju@ti.com --- .../dts/ti/k3-j721e-common-proc-board.dts | 155 ++++++++++++++++++ 1 file changed, 155 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index dc2bc67f9f48..2d7596911b27 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -112,6 +112,42 @@ "cpb-codec-scki", "cpb-codec-scki-48000", "cpb-codec-scki-44100"; }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>; + enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; + enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; + }; + + transceiver4: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan2_gpio_pins_default>; + standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; + }; }; &main_pmx0 { @@ -207,6 +243,26 @@ J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ >; }; + + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ + J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ + >; + }; + + main_mcan2_pins_default: main-mcan2-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */ + J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */ + >; + }; + + main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ + >; + }; }; &wkup_pmx0 { @@ -252,6 +308,33 @@ J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ >; }; + + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ + J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */ + J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ + >; + }; }; &wkup_uart0 { @@ -773,3 +856,75 @@ &icssg1_mdio { status = "disabled"; }; + +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver3>; +}; + +&main_mcan1 { + status = "disabled"; +}; + +&main_mcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan2_pins_default>; + phys = <&transceiver4>; +}; + +&main_mcan3 { + status = "disabled"; +}; + +&main_mcan4 { + status = "disabled"; +}; + +&main_mcan5 { + status = "disabled"; +}; + +&main_mcan6 { + status = "disabled"; +}; + +&main_mcan7 { + status = "disabled"; +}; + +&main_mcan8 { + status = "disabled"; +}; + +&main_mcan9 { + status = "disabled"; +}; + +&main_mcan10 { + status = "disabled"; +}; + +&main_mcan11 { + status = "disabled"; +}; + +&main_mcan12 { + status = "disabled"; +}; + +&main_mcan13 { + status = "disabled"; +}; From 9c4441ad3da1fad75aabfd68e90558c20a2818d2 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Mon, 22 Nov 2021 19:11:57 +0530 Subject: [PATCH 241/574] arm64: dts: ti: k3-am64-main: Add support for MCAN Add Support for two MCAN controllers present on the am64x SOC. Both support classic CAN messages as well as CAN-FD. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20211122134159.29936-6-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 28 ++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index e16d2ccdd818..012011dc619a 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1261,4 +1261,32 @@ bus_freq = <1000000>; }; }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan1: can@20711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20711000 0x00 0x200>, + <0x00 0x20718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; }; From 2f474da98caf9a75d7777c5465d281240c706bc6 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Mon, 22 Nov 2021 19:11:58 +0530 Subject: [PATCH 242/574] arm64: dts: ti: k3-am642-evm/sk: Add support for main domain mcan nodes in EVM and disable them on SK AM642 EVM has two CAN connecters brought out from the two MCAN instances in the main domain through transceivers. Add device tree nodes for transceivers and set the required properties in the mcan device tree nodes, in EVM device tree file. On AM642 SK there are no connectors brought out for CAN. Therefore, disable the mcan device tree nodes in the SK device tree file. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Apurva Nandan Link: https://lore.kernel.org/r/20211122134159.29936-7-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 40 +++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 8 +++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 6726c4c7c28c..e94ae178b1ae 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -184,6 +184,20 @@ }; }; }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; + }; }; &main_pmx0 { @@ -294,6 +308,20 @@ AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ >; }; + + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ + AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ + >; + }; + + main_mcan1_pins_default: main-mcan1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ + AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ + >; + }; }; &main_uart0 { @@ -638,3 +666,15 @@ &icssg1_mdio { status = "disabled"; }; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&main_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_pins_default>; + phys = <&transceiver2>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 6b04745147be..a9785bec12df 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -525,3 +525,11 @@ &icssg1_mdio { status = "disabled"; }; + +&main_mcan0 { + status = "disabled"; +}; + +&main_mcan1 { + status = "disabled"; +}; From 111659c2a570ab1d62615040249dd37f39034d68 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Tue, 7 Dec 2021 14:34:58 +0900 Subject: [PATCH 243/574] arm64: dts: apple: t8103: Remove PCIe max-link-speed properties The driver doesn't support these, they shouldn't be in the SoC include anyway, and we're now configuring this in the bootloader instead. This also solves the j274 1G/10G Ethernet variant discrepancy, since that will now be configured properly based on the dynamic ADT property. Acked-by: Marc Zyngier Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 15ee8c8c5fa0..8d1628e0b0c7 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -412,7 +412,6 @@ device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 152 0>; - max-link-speed = <2>; #address-cells = <3>; #size-cells = <2>; @@ -432,7 +431,6 @@ device_type = "pci"; reg = <0x800 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 153 0>; - max-link-speed = <2>; #address-cells = <3>; #size-cells = <2>; @@ -452,7 +450,6 @@ device_type = "pci"; reg = <0x1000 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 33 0>; - max-link-speed = <1>; #address-cells = <3>; #size-cells = <2>; From 82ce79391d0ec25ec8aaae3c0617b71048ff0836 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Thu, 4 Nov 2021 22:40:25 +0000 Subject: [PATCH 244/574] arm64: dts: renesas: Fix thermal bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding node names for the thermal zones are not successfully validated by the dt-schemas. Fix the validation by changing from sensor-thermalN or thermal-sensor-N to sensorN-thermal. Provide node labels of the form sensorN_thermal to ensure consistency with the other platform implementations. Signed-off-by: Kieran Bingham Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20211104224033.3997504-1-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 10 +++++----- 9 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 09976adf99c2..eda6a840371a 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2788,7 +2788,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2803,7 +2803,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2818,7 +2818,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index c504f5028380..44f79fbd75dc 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2633,7 +2633,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2648,7 +2648,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2663,7 +2663,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index e4dd6ccc8b10..e6d8610730a8 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2908,7 +2908,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2923,7 +2923,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2938,7 +2938,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 2353d3034bb5..9265a5702792 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -3379,7 +3379,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -3394,7 +3394,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -3409,7 +3409,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 0f2424f12546..26f7103d11da 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2976,7 +2976,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2991,7 +2991,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -3006,7 +3006,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 7468a2df1808..ac9b587f6fc5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2734,7 +2734,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2749,7 +2749,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2764,7 +2764,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 0c44de866996..f898aad72b9d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2788,7 +2788,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2803,7 +2803,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2818,7 +2818,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 2a4513e7e2b5..347c068ff2c5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1581,7 +1581,7 @@ }; thermal-zones { - thermal-sensor-1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -1600,7 +1600,7 @@ }; }; - thermal-sensor-2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 6e83bcb0287c..8ac1a31e4146 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2640,7 +2640,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2654,7 +2654,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2668,7 +2668,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; @@ -2682,7 +2682,7 @@ }; }; - sensor_thermal4: sensor-thermal4 { + sensor4_thermal: sensor4-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 3>; @@ -2696,7 +2696,7 @@ }; }; - sensor_thermal5: sensor-thermal5 { + sensor5_thermal: sensor5-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 4>; From d01986bec3887a3dbf61cbd821979f91cf0bb2dc Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:32:55 +0900 Subject: [PATCH 245/574] dt-bindings: arm: renesas: Document Renesas Spider boards Add device tree bindings documentation for Renesas R-Car S4-8 Spider CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 36197f53b310..6a9350ee690b 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -317,6 +317,14 @@ properties: - description: R-Car S4-8 (R8A779F0) items: + - enum: + - renesas,spider-cpu # Spider CPU board (RTP8A779F0ASKB0SC2S) + - const: renesas,r8a779f0 + + - items: + - enum: + - renesas,spider-breakout # Spider BreakOut board (RTP8A779F0ASKB0SB0S) + - const: renesas,spider-cpu - const: renesas,r8a779f0 - description: R-Car H3e (R8A779M0) From c62331e8222f8f21faae600effd32b972bb43850 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:33:06 +0900 Subject: [PATCH 246/574] arm64: dts: renesas: Add Renesas R8A779F0 SoC support Add initial support for the Renesas R8A779F0 (R-Car S4-8) SoC. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-13-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 121 ++++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi new file mode 100644 index 000000000000..eda597766eaf --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a779f0"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a55_0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu_a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779f0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779f0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779f0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a779f0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = ; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; From 08b8699eb369d1b416c146922edfe827b41757a4 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:33:07 +0900 Subject: [PATCH 247/574] arm64: dts: renesas: Add Renesas Spider boards support Initial support for the Renesas Spider CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda Tested-by: Takehito Nakamura Link: https://lore.kernel.org/r/20211201073308.1003945-14-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 36 +++++++++++++++++++ .../boot/dts/renesas/r8a779f0-spider.dts | 22 ++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0-spider.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d1c5c21d8d14..5bc8065a7864 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -63,6 +63,8 @@ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb +dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb + dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi new file mode 100644 index 000000000000..156586532c84 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the Spider CPU board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include "r8a779f0.dtsi" + +/ { + model = "Renesas Spider CPU board"; + compatible = "renesas,spider-cpu", "renesas,r8a779f0"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&scif3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts new file mode 100644 index 000000000000..f286254b41d8 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the Spider CPU and BreakOut boards + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779f0-spider-cpu.dtsi" + +/ { + model = "Renesas Spider CPU and Breakout boards based on r8a779f0"; + compatible = "renesas,spider-breakout", "renesas,spider-cpu", "renesas,r8a779f0"; + + aliases { + serial0 = &scif3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; From 12f332d2dd3187472f595b678246adb10d886bd0 Mon Sep 17 00:00:00 2001 From: Hari Prasath Date: Wed, 8 Dec 2021 12:05:53 +0530 Subject: [PATCH 248/574] ARM: dts: at91: update alternate function of signal PD20 The alternate function of PD20 is 4 as per the datasheet of sama7g5 and not 5 as defined earlier. Signed-off-by: Hari Prasath Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Cc: # v5.15+ Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211208063553.19807-1-Hari.PrasathGE@microchip.com --- arch/arm/boot/dts/sama7g5-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sama7g5-pinfunc.h b/arch/arm/boot/dts/sama7g5-pinfunc.h index 22fe9e522a97..4eb30445d205 100644 --- a/arch/arm/boot/dts/sama7g5-pinfunc.h +++ b/arch/arm/boot/dts/sama7g5-pinfunc.h @@ -765,7 +765,7 @@ #define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) #define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) #define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) -#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 5, 2) +#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 4, 2) #define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) #define PIN_PD21 117 #define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) From 6133d84228895c28d2a706176f1fa45bcf39792d Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:00 +0800 Subject: [PATCH 249/574] arm64: dts: imx8mn-evk: add hardware reset for FEC PHY Add hardware reset for FEC PHY. Signed-off-by: Joakim Zhang Reviewed-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 85e65f8719ea..30e7c9d56090 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -97,6 +97,8 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; }; }; }; From e0aa402b40a276ac2a02c005f62a12dcd9786aca Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:01 +0800 Subject: [PATCH 250/574] arm64: dts: imx8mp-evk: add hardware reset for EQOS PHY As commit 798a1807ab13 ("arm64: dts: imx8mp-evk: Improve the Ethernet PHY description") described, add hardware reset for EQOS PHY. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 7b99fad6e4d6..a7dc0d160f79 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -97,6 +97,9 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; eee-broken-1000t; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; }; }; }; From 20b6559ecf5d49ee75ae519bf9da5ef3d2f02148 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:02 +0800 Subject: [PATCH 251/574] arm64: dts: imx8m: disable smart eee for FEC PHY As commit 390b4cad8148 ("net: phy: at803x: add support for configuring SmartEEE") described, disable PHY smart eee by default. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index e033d0257b5a..50b3bbb662d5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -116,6 +116,7 @@ reg = <0>; reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + qca,disable-smarteee; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 30e7c9d56090..342f57e8cf61 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -99,6 +99,7 @@ reg = <0>; reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + qca,disable-smarteee; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index b83df77195ec..a9e33548a2f3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -169,6 +169,7 @@ reg = <0>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + qca,disable-smarteee; }; }; }; From 09e5ccdd866c35ac55e11a5fa3f818d6a471fe0f Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:03 +0800 Subject: [PATCH 252/574] arm64: dts: imx8m: configure FEC PHY VDDIO voltage As commit 2f664823a470 ("net: phy: at803x: add device tree binding") described, configure FEC PHY VDDIO voltage according to board design. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++ 3 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 50b3bbb662d5..3bac87b7e142 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -117,6 +117,12 @@ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; qca,disable-smarteee; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 342f57e8cf61..c3f15192b76c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -100,6 +100,12 @@ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; qca,disable-smarteee; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index a9e33548a2f3..c96d23fe3010 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -170,6 +170,10 @@ reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; qca,disable-smarteee; + vddio-supply = <&vddh>; + + vddh: vddh-regulator { + }; }; }; }; From 311ad460c4fa3911cca36118b18feff233ae9e76 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:04 +0800 Subject: [PATCH 253/574] arm64: dts: imx8mp-evk: disable CLKOUT clock for ENET PHY According to commit 0a4355c2b7f8 ("net: phy: realtek: add dt property to disable CLKOUT clock"), diable CLKOUT clock for FEC PHY to save power on i.MX8MP EVK board. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index a7dc0d160f79..cf03a82f9dcd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -100,6 +100,7 @@ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; + realtek,clkout-disable; }; }; }; @@ -123,6 +124,7 @@ reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; + realtek,clkout-disable; }; }; }; From baf55c1509fec59a734a987b44e318c99610ce4f Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:05 +0800 Subject: [PATCH 254/574] arm64: dts: imx8m: remove unused "nvmem_macaddr_swap" property for FEC Remove unused "nvmem_macaddr_swap" property for FEC, there is no info in both dt-binding and driver, so it's safe to remove it. Reviewed-by: Ahmad Fatoum Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 - arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 - arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 - arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 - 4 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index a31cf2b9769c..c84d76860441 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1082,7 +1082,6 @@ fsl,num-rx-queues = <3>; nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; - nvmem_macaddr_swap; fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index ba23b416b5e6..b8d49d5f2668 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -976,7 +976,6 @@ fsl,num-rx-queues = <3>; nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; - nvmem_macaddr_swap; fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 977783784342..20687f9c973c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -860,7 +860,6 @@ nvmem-cells = <ð_mac1>; nvmem-cell-names = "mac-address"; fsl,stop-mode = <&gpr 0x10 3>; - nvmem_macaddr_swap; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 5ab9e02bd929..5f57deee5794 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1320,7 +1320,6 @@ fsl,num-rx-queues = <3>; nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; - nvmem_macaddr_swap; fsl,stop-mode = <&iomuxc_gpr 0x10 3>; status = "disabled"; }; From 44d0dfee53ffff733de6baabea986e72af08f7bb Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Tue, 23 Nov 2021 16:05:06 +0800 Subject: [PATCH 255/574] arm64: dts: imx8mp: add mac address for EQOS Add mac address in efuse, so that EQOS driver can parse it from nvmem cell. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 20687f9c973c..6b840c05dd77 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -397,6 +397,10 @@ eth_mac1: mac-address@90 { reg = <0x90 6>; }; + + eth_mac2: mac-address@96 { + reg = <0x96 6>; + }; }; anatop: anatop@30360000 { @@ -881,6 +885,8 @@ <&clk IMX8MP_SYS_PLL2_100M>, <&clk IMX8MP_SYS_PLL2_125M>; assigned-clock-rates = <0>, <100000000>, <125000000>; + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; intf_mode = <&gpr 0x4>; status = "disabled"; }; From 0de4ab81ab26f09d4dbf8142a881b4607070d01f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Mon, 22 Nov 2021 17:25:20 +0100 Subject: [PATCH 256/574] ARM: dts: imx6dl-yapp4: Add Y Soft IOTA Crux/Crux+ board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devicetrees for the new boards in the Y Soft IOTA family. These boards are based on Orion but use Quad/QuadPlus SoC instead of DualLite. Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6q-yapp4-crux.dts | 54 ++++++++++++++++++++ arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts | 54 ++++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-yapp4-crux.dts create mode 100644 arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e462dbe75f6a..51a6dd687191 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -632,6 +632,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-wandboard.dtb \ imx6q-wandboard-revb1.dtb \ imx6q-wandboard-revd1.dtb \ + imx6q-yapp4-crux.dtb \ imx6q-zii-rdu2.dtb \ imx6qp-mba6b.dtb \ imx6qp-nitrogen6_max.dtb \ @@ -646,6 +647,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6qp-tx6qp-8137-mb7.dtb \ imx6qp-vicutp.dtb \ imx6qp-wandboard-revd1.dtb \ + imx6qp-yapp4-crux-plus.dtb \ imx6qp-zii-rdu2.dtb \ imx6s-dhcom-drc02.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ diff --git a/arch/arm/boot/dts/imx6q-yapp4-crux.dts b/arch/arm/boot/dts/imx6q-yapp4-crux.dts new file mode 100644 index 000000000000..15f4824a5142 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-yapp4-crux.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Crux i.MX6Quad board"; + compatible = "ysoft,imx6q-yapp4-crux", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts b/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts new file mode 100644 index 000000000000..cea165f2161a --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6qp.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Crux+ i.MX6QuadPlus board"; + compatible = "ysoft,imx6qp-yapp4-crux-plus", "fsl,imx6qp"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; From 6d4518a086b2cce1f7935eb5a88a7f03e241f640 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Tue, 26 Oct 2021 16:20:34 +0300 Subject: [PATCH 257/574] ARM: dts: at91: sama5d2_xplained: remove PA11__SDMMC0_VDDSEL from pinctrl I/O voltage for eMMC is always 3.3V because PA11__SDMMC0_VDDSEL is tied with 10K resistor to GND. U13 switch S1 is always selected as voltage rail of 3.3V for VCCQ power pin from MPU controller and eMMC flash. Removing PA11 from pinctrl because it remains unused. Signed-off-by: Mihai Sain Reviewed-by: Eugen Hristev Signed-off-by: Eugen Hristev Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211026132034.678655-1-eugen.hristev@microchip.com --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index b1e854f658de..9bf2ec0ba3e2 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -66,7 +66,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc0_default>; non-removable; - mmc-ddr-1_8v; + mmc-ddr-3_3v; status = "okay"; }; @@ -619,10 +619,9 @@ bias-disable; }; - ck_cd_rstn_vddsel { + ck_cd_rstn { pinmux = , , - , ; bias-disable; }; From b3111fe15df5e420f5251bad612fcf6915392c92 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Thu, 11 Nov 2021 09:10:45 +0100 Subject: [PATCH 258/574] ARM: dts: at91: add Microchip EVB-KSZ9477 board Add KSZ9477 managed switch evaluation kit with SAMA5D36 MPU: https://www.microchip.com/en-us/development-tool/evb-ksz9477 Signed-off-by: Oleksij Rempel Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211111081045.711323-1-o.rempel@pengutronix.de --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/at91-sama5d3_ksz9477_evb.dts | 209 ++++++++++++++++++ 2 files changed, 210 insertions(+) create mode 100644 arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..f79585f6e80b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -61,6 +61,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d2_icp.dtb \ at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ + at91-sama5d3_ksz9477_evb.dtb \ at91-sama5d3_xplained.dtb \ at91-dvk_som60.dtb \ at91-gatwick.dtb \ diff --git a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts new file mode 100644 index 000000000000..443e8b022897 --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 Oleksij Rempel , Pengutronix + */ +/dts-v1/; +#include "sama5d36.dtsi" + +/ { + model = "EVB-KSZ9477"; + compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36", + "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = &dbgu; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vcc_mmc0: regulator-mmc0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcc0_vcc>; + regulator-name = "mmc0-vcc"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + }; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; +}; + +&macb0 { + phy-mode = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&mmc0 { + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <®_vcc_mmc0>; + vqmmc-supply = <®_3v3>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&spi0 { + cs-gpios = <&pioD 13 GPIO_ACTIVE_LOW>, <0>, <0>, + <&pioD 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&pinctrl_spi_ksz>; + cs-gpios = <&pioC 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + switch@0 { + compatible = "microchip,ksz9477"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpha; + spi-cpol; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "lan5"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&macb0>; + phy-mode = "rgmii-txid"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + board { + pinctrl_i2c0_pu: i2c0-pu { + atmel,pins = + , + ; + }; + + pinctrl_mmc0_cd: mmc0-cd { + atmel,pins = ; + }; + + pinctrl_mcc0_vcc: mmc0-vcc { + atmel,pins = ; + }; + + pinctrl_spi_ksz: spi-ksz { + atmel,pins = + < + /* SPI1_MISO */ + AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + /* SPI1_MOSI */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE + /* SPI1_SPCK */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE + + /* SPI CS */ + AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + /* switch IRQ */ + AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH + /* switch PME_N, SoC IN */ + AT91_PIOC 30 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP + /* switch RST */ + AT91_PIOC 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH + >; + }; + + pinctrl_usba_vbus: usba-vbus { + atmel,pins = + ; + }; + }; +}; From 36b88b209593f6e103fdc4df369fcdedc7f2f1c9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 20 Oct 2021 02:40:59 +0300 Subject: [PATCH 259/574] ARM: dts: elpida_ecb240abacn: Change Elpida compatible Vendor prefix shouldn't start with capital letter. The Elpida Memory compatible was never used in practice, hence just correct the compatible. Signed-off-by: Dmitry Osipenko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi index d87ee4794f83..9698801cbcfb 100644 --- a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi +++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi @@ -5,7 +5,7 @@ / { elpida_ECB240ABACN: lpddr2 { - compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; + compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4"; density = <2048>; io-width = <32>; From f3499b1329c9af605874df0664ee0e245687b72b Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 18 Oct 2021 15:00:19 -0700 Subject: [PATCH 260/574] ARM: dts: am335x-boneblack-common: move system-power-controller Move the rtc node system-power-controller property from am335x-boneblack-common.dtsi to am335x-bone-common.dtsi. am335x-boneblack-common.dtsi is included by am335x-boneblack.dts, am335x-boneblack-wireless.dts, am335x-sancloud-bbe.dts and am335x-sancloud-bbe-lite.dts. All of these dts files also include am335x-bone-common.dtsi and thus will retain the rtc node system-power-controller property. am335x-bone-common.dtsi is also included by am335x-bone.dts [1], am335x-bonegreen.dts [2] and am335x-bonegreen-wireless.dts [3]. These boards will now have the rtc node system-power-controller property too. This is valid as they also have PMIC_POWR_EN (ZCZ C6) connected to PWR_EN on the TPS65217B PMIC. Based on commit 15c7be47fb7c ("ARM: dts: am335x: Add rtc node as system-power-controller") by Keerthy in ti-linux-5.4.y branch [4]. [1] https://beagleboard.org/static/beaglebone/BEAGLEBONE_SCHEM_A3.pdf [2] https://github.com/SeeedDocument/BeagleBone_Green/blob/master/resources/BEAGLEBONE_GREEN_V1.pdf [3] https://github.com/SeeedDocument/BeagleBone_Green_Wireless/blob/master/resources/BeagleBone_Green%20Wireless_V1.0_SCH_20160314.pdf [4] git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git Cc: Jason Kridner Cc: Dave Gerlach Cc: Keerthy Link: https://lore.kernel.org/linux-omap/20211012191311.879838-1-dfustini@baylibre.com/ Suggested-by: Johan Hovold Reviewed-by: Johan Hovold Signed-off-by: Drew Fustini Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone-common.dtsi | 1 + arch/arm/boot/dts/am335x-boneblack-common.dtsi | 4 ---- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 0ccdc7cd463b..56ae5095a5b8 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -399,6 +399,7 @@ &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; + system-power-controller; }; &pruss_tm { diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/am335x-boneblack-common.dtsi index 10494c4431b9..a7a8c61ef9b2 100644 --- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi +++ b/arch/arm/boot/dts/am335x-boneblack-common.dtsi @@ -22,10 +22,6 @@ non-removable; }; -&rtc { - system-power-controller; -}; - / { memory@80000000 { device_type = "memory"; From 1e72c64eb75e99cfcd62c2678f4c465d1213170c Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 18 Oct 2021 15:00:20 -0700 Subject: [PATCH 261/574] ARM: dts: am335x-icev2: Add system-power-controller to RTC node On the am335x-icev2 board [1], AM3359 PMIC_PWR_EN (ZCZ ball C6) is connected to PWRHOLD (pin 1) on the TPS65910A3 PMIC. The addition of system-power-controller to the rtc node will enable the capability of the RTC driver to poweroff the board. Based on commit 15c7be47fb7c ("ARM: dts: am335x: Add rtc node as system-power-controller") by Keerthy in ti-linux-5.4.y branch [2]. [1] https://www.ti.com/tool/TMDSICE3359 [2] git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git Cc: Dave Gerlach Cc: Keerthy Link: https://lore.kernel.org/linux-omap/20211012191311.879838-1-dfustini@baylibre.com/ Suggested-by: Johan Hovold Signed-off-by: Drew Fustini Reviewed-by: Johan Hovold Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-icev2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index e5ce89c8f54d..5835c0cdda50 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -512,3 +512,7 @@ &pruss_tm { status = "okay"; }; + +&rtc { + system-power-controller; +}; From d2e8a6c43bbf61200e5fcb3199efc2680af32bc1 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 26 Nov 2021 15:24:11 +0100 Subject: [PATCH 262/574] ARM: dts: am437x-cm-t43: Use a correctly spelled DT property Back in 2014 a property got misspelled "ti,coordiante-readouts" instead of "ti,coordinate-readouts". The year after it got fixed but both are still supported, although this is not a reason to continue using this old deprecated property. Signed-off-by: Miquel Raynal Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-cm-t43.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index 5ce8e684e7d3..3e3354780db8 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -399,7 +399,7 @@ tsc { ti,wires = <4>; ti,x-plate-resistance = <200>; - ti,coordiante-readouts = <5>; + ti,coordinate-readouts = <5>; ti,wire-config = <0x00 0x11 0x22 0x33>; }; From 6c06a9f55b5fc9f48950bedfe8d5b74748a21e76 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 26 Nov 2021 15:24:12 +0100 Subject: [PATCH 263/574] ARM: dts: am43xx: Describe the magnetic reader/ADC1 hardware module This hardware module is close to the am33xx ADC module but instead of featuring a touchscreen it has a magnetic reader capability. Signed-off-by: Miquel Raynal Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 31 ++++++++++++++++++++++++++-- arch/arm/boot/dts/am43xx-clocks.dtsi | 7 +++++++ 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index ba58e6b0da1d..8f2268c02778 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -2378,11 +2378,38 @@ }; target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4c000 0x4>, + <0x4c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + clocks = <&l3s_clkctrl AM4_L3S_ADC1_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4c000 0x2000>; + + magadc: magadc@0 { + compatible = "ti,am4372-magadc"; + reg = <0x0 0x2000>; + interrupts = ; + clocks = <&adc_mag_fck>; + clock-names = "fck"; + dmas = <&edma 54 0>, <&edma 55 0>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + mag { + compatible = "ti,am4372-mag"; + }; + + adc { + #io-channel-cells = <1>; + compatible ="ti,am4372-adc"; + }; + }; }; target-module@80000 { /* 0x48380000, ap 123 42.0 */ diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 314fc5975acb..66e892fa3398 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -444,6 +444,13 @@ reg = <0x422c>; }; + adc_mag_fck: adc_mag_fck@424c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_per_m2_ck>; + reg = <0x424c>; + }; + l3_gclk: l3_gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; From 6fde719b19af7e82671c352c69981c75ca9909c2 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 26 Nov 2021 15:24:13 +0100 Subject: [PATCH 264/574] ARM: dts: am437x-gp-evm: enable ADC1 ADC0 and ADC1 pins are available on external connector J22. Enable ADC1 which was missing. Signed-off-by: Miquel Raynal Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index c2e4896076e7..4416ddb559e4 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -775,6 +775,14 @@ }; }; +&magadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + &ecap0 { status = "okay"; pinctrl-names = "default"; From 7ebe6e99f7702dad342486e5b30d989a0a6499af Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 3 Dec 2021 15:10:43 +0100 Subject: [PATCH 265/574] ARM: dts: motorola-mapphone: Drop second ti,wlcore compatible value The TI wlcore DT bindings specify using a single compatible value for each variant, and the Linux kernel driver matches against the first compatible value since commit 078b30da3f074f2e ("wlcore: add wl1285 compatible") in v4.13. Signed-off-by: Geert Uytterhoeven Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/motorola-mapphone-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index a4423ff0df39..c7a1f3ffc48c 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -310,7 +310,7 @@ #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { - compatible = "ti,wl1285", "ti,wl1283"; + compatible = "ti,wl1285"; reg = <2>; /* gpio_100 with gpmc_wait2 pad as wakeirq */ interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>, From fa0fdb78cb5d4cde00430ec481f09fbe7c029376 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 15:48:02 +0100 Subject: [PATCH 266/574] ARM: dts: am335x: Use correct vendor prefix for Asahi Kasei Corp. The old "ak" vendor prefix that was never officially accepted was still being used in some device trees. Convert to the correct vendor prefix (i.e. "asahi-kasei"). Signed-off-by: Thierry Reding Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblue.dts | 2 +- arch/arm/boot/dts/am335x-osd3358-sm-red.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index c6bb325ead33..147c00de3795 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -341,7 +341,7 @@ #address-cells = <1>; #size-cells = <0>; ax8975@c { - compatible = "ak,ak8975"; + compatible = "asahi-kasei,ak8975"; reg = <0x0c>; }; }; diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts index 605b2a436edf..b2846cd220f0 100644 --- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts +++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts @@ -84,7 +84,7 @@ #address-cells = <1>; #size-cells = <0>; ax8975@c { - compatible = "ak,ak8975"; + compatible = "asahi-kasei,ak8975"; reg = <0x0c>; }; }; From 2e4dbcf7177e5dd1f7cb53c59cb2f394e35fd7ba Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 8 Dec 2021 13:03:12 +0100 Subject: [PATCH 267/574] arm64: dts: rockchip: Change pwm pinctrl-name to "default" on rk356x The pinctrl state "active" is neither documented nor used by the PWM driver. Rename it to "default" Signed-off-by: Sascha Hauer Link: https://lore.kernel.org/r/20211208120312.3300390-1-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 46d9552f6028..29e8516ef0cb 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -269,7 +269,7 @@ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -280,7 +280,7 @@ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -291,7 +291,7 @@ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -302,7 +302,7 @@ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -951,7 +951,7 @@ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm4_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -962,7 +962,7 @@ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm5_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -973,7 +973,7 @@ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm6_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -984,7 +984,7 @@ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm7_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -995,7 +995,7 @@ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1006,7 +1006,7 @@ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1017,7 +1017,7 @@ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1028,7 +1028,7 @@ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1039,7 +1039,7 @@ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1050,7 +1050,7 @@ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1061,7 +1061,7 @@ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; @@ -1072,7 +1072,7 @@ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; clock-names = "pwm", "pclk"; pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "active"; + pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; From aaa552d84580e9213d0e2bf0f9243477d1227bdd Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Sat, 27 Nov 2021 15:19:08 +0100 Subject: [PATCH 268/574] arm64: dts: rockchip: Add spi nodes on rk356x This adds the four spi nodes (spi0, spi1, spi2, spi3) to the rk356x dtsi. These are from the downstream device tree, though I have double-checked that their interrupts and DMA numbers are correct. I have also tested spi1 with an SPI device. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20211127141910.12649-3-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 64 ++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 29e8516ef0cb..a68033a23975 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -39,6 +39,10 @@ serial7 = &uart7; serial8 = &uart8; serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; }; cpus { @@ -742,6 +746,66 @@ clock-names = "tclk", "pclk"; }; + spi0: spi@fe610000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe610000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 20>, <&dmac0 21>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@fe620000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe620000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 22>, <&dmac0 23>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@fe630000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe630000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 24>, <&dmac0 25>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@fe640000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe640000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 26>, <&dmac0 27>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart1: serial@fe650000 { compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; reg = <0x0 0xfe650000 0x0 0x100>; From ea1847c09c34234c2980b99b6bb732a55447c33f Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Sat, 27 Nov 2021 15:19:09 +0100 Subject: [PATCH 269/574] arm64: dts: rockchip: Add spi1 pins on Quartz64 A The Quartz64 Model A has the SPI pins broken out on its pin header. The actual pins being used though are not the m0 variant, but the m1 variant, which also lacks the cs1 pin. This commit overrides pinctrl-0 accordingly for this board. spi1 is intentionally left disabled, as anyone wishing to add SPI devices needs to edit the dts anyway, and the pins are more useful as GPIOs for the rest of the users. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20211127141910.12649-4-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 4d4b2a301b1a..166399b7f13f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -509,6 +509,11 @@ status = "okay"; }; +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; +}; + &tsadc { /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-mode = <1>; From d824dade33bfe464a5304f1772de8735a46eec7c Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 13:44:59 +0900 Subject: [PATCH 270/574] dt-bindings: power: apple,pmgr-pwrstate: Add apple,min-state prop A few devices (DCP/DCPEXT) need to have the minimum power state for auto-PM configured. Add a property that allows the DT to specify this value. Reviewed-by: Rob Herring Signed-off-by: Hector Martin --- .../devicetree/bindings/power/apple,pmgr-pwrstate.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index 5056d08b8261..19a194980142 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -61,6 +61,14 @@ properties: Forces this power domain to always be powered up. type: boolean + apple,min-state: + description: + Specifies the minimum power state for auto-PM. + 0 = power gated, 4 = clock gated, 15 = on. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + required: - compatible - reg From 34e5719e1c6bcdc585731cbe6af11497aafaa1a6 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 13:45:01 +0900 Subject: [PATCH 271/574] arm64: dts: apple: t8103: Add apple,min-state to DCP PMGR nodes This is required for DCP to boot successfully; it seems if power gating is allowed, they do not wake up properly. Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-pmgr.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi index 1310be74df1d..fc51bc872468 100644 --- a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -665,6 +665,7 @@ #reset-cells = <0>; label = "dispext_cpu0"; power-domains = <&ps_dispext_fe>; + apple,min-state = <4>; }; ps_jpg: power-controller@3c0 { @@ -1005,6 +1006,7 @@ label = "disp0_cpu0"; power-domains = <&ps_disp0_fe>; apple,always-on; /* TODO: figure out if we can enable PM here */ + apple,min-state = <4>; }; }; From e15b8c8563983c134869890d7a88aada33c52885 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 14:09:58 +0900 Subject: [PATCH 272/574] dt-bindings: arm: apple: Add t6000/t6001 MacBook Pro 14/16" compatibles This adds the initial apple,t6000 platforms: - apple,j314s - MacBook Pro (14-inch, M1 Pro, 2021) - apple,j316s - MacBook Pro (16-inch, M1 Pro, 2021) And the initial apple,t6001 platforms: - apple,j314c - MacBook Pro (14-inch, M1 Max, 2021) - apple,j316c - MacBook Pro (16-inch, M1 Max, 2021) Reviewed-by: Mark Kettenis Acked-by: Rob Herring Signed-off-by: Hector Martin --- .../devicetree/bindings/arm/apple.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index b23c8dc5a27d..8d93e8a6cc18 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -19,6 +19,13 @@ description: | - MacBook Air (M1, 2020) - iMac (24-inch, M1, 2021) + And devices based on the "M1 Pro" and "M1 Max" SoCs: + + - MacBook Pro (14-inch, M1 Pro, 2021) + - MacBook Pro (14-inch, M1 Max, 2021) + - MacBook Pro (16-inch, M1 Pro, 2021) + - MacBook Pro (16-inch, M1 Max, 2021) + The compatible property should follow this format: compatible = "apple,", "apple,", "apple,arm-platform"; @@ -60,6 +67,20 @@ properties: - apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021) - const: apple,t8103 - const: apple,arm-platform + - description: Apple M1 Pro SoC based platforms + items: + - enum: + - apple,j314s # MacBook Pro (14-inch, M1 Pro, 2021) + - apple,j316s # MacBook Pro (16-inch, M1 Pro, 2021) + - const: apple,t6000 + - const: apple,arm-platform + - description: Apple M1 Max SoC based platforms + items: + - enum: + - apple,j314c # MacBook Pro (14-inch, M1 Max, 2021) + - apple,j316c # MacBook Pro (16-inch, M1 Max, 2021) + - const: apple,t6001 + - const: apple,arm-platform additionalProperties: true From b66652c7517c80873258a00cccf56a2d133a5efe Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 14:09:59 +0900 Subject: [PATCH 273/574] dt-bindings: i2c: apple,i2c: Add apple,t6000-i2c compatible This block is compatible with t8103, so just add the new per-SoC compatible under apple,i2c. Reviewed-by: Mark Kettenis Reviewed-by: Sven Peter Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/i2c/apple,i2c.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml index 47dd6c107a6d..4ac61fec90e2 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -21,7 +21,9 @@ allOf: properties: compatible: items: - - const: apple,t8103-i2c + - enum: + - apple,t8103-i2c + - apple,t6000-i2c - const: apple,i2c reg: From 42c2366a9cbedc32921f0e53e14b7bef1d536514 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 14:10:00 +0900 Subject: [PATCH 274/574] dt-bindings: pci: apple,pcie: Add t6000 support This new SoC is compatible with the existing driver, but the block supports 4 downstream ports, so we need to adjust the binding to allow that. Reviewed-by: Mark Kettenis Acked-by: Rob Herring Signed-off-by: Hector Martin --- .../devicetree/bindings/pci/apple,pcie.yaml | 28 ++++++++++++++----- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml index ef1d424ec299..7f01e15fc81c 100644 --- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -28,19 +28,17 @@ description: | distributed over the root ports as the OS sees fit by programming the PCIe controller's port registers. -allOf: - - $ref: /schemas/pci/pci-bus.yaml# - - $ref: /schemas/interrupt-controller/msi-controller.yaml# - properties: compatible: items: - - const: apple,t8103-pcie + - enum: + - apple,t8103-pcie + - apple,t6000-pcie - const: apple,pcie reg: minItems: 3 - maxItems: 5 + maxItems: 6 reg-names: minItems: 3 @@ -50,6 +48,7 @@ properties: - const: port0 - const: port1 - const: port2 + - const: port3 ranges: minItems: 2 @@ -59,7 +58,7 @@ properties: description: Interrupt specifiers, one for each root port. minItems: 1 - maxItems: 3 + maxItems: 4 msi-parent: true @@ -81,6 +80,21 @@ required: unevaluatedProperties: false +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + - if: + properties: + compatible: + contains: + const: apple,t8103-pcie + then: + properties: + reg: + maxItems: 5 + interrupts: + maxItems: 3 + examples: - | #include From cba9c615bec18792c32cc95f478884e24de9d1a5 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 14:10:01 +0900 Subject: [PATCH 275/574] dt-bindings: pinctrl: apple,pinctrl: Add apple,t6000-pinctrl compatible This new SoC uses the same pinctrl hardware, so just add a new per-SoC compatible. Reviewed-by: Mark Kettenis Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 200d411621e7..572923d7023e 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -17,7 +17,9 @@ description: | properties: compatible: items: - - const: apple,t8103-pinctrl + - enum: + - apple,t8103-pinctrl + - apple,t6000-pinctrl - const: apple,pinctrl reg: From b4d11106d751a455154edf997891de0428f48a87 Mon Sep 17 00:00:00 2001 From: Sven Peter Date: Sat, 11 Dec 2021 13:40:44 +0100 Subject: [PATCH 276/574] arm64: dts: apple: t8103: Add watchdog node Add the watchdog node which also enables reboot support on the t8103. Signed-off-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 8d1628e0b0c7..8203c60d4819 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -324,6 +324,14 @@ ; }; + wdt: watchdog@23d2b0000 { + compatible = "apple,t8103-wdt", "apple,wdt"; + reg = <0x2 0x3d2b0000 0x0 0x4000>; + clocks = <&clk24>; + interrupt-parent = <&aic>; + interrupts = ; + }; + pinctrl_smc: pinctrl@23e820000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x3e820000 0x0 0x4000>; From a39891a6e420daeb55abc99cde4278511ac861d7 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 12 Dec 2021 00:38:17 +0100 Subject: [PATCH 277/574] arm64: dts: rockchip: Add missing secondary compatible for PX30 DSI Add second DSI compatible to comply with DT schema validation comming in the second patch. Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20211211233818.88482-1-david@ixit.cz Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 00f50b05d55a..f972704dfe7a 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1072,7 +1072,7 @@ }; dsi: dsi@ff450000 { - compatible = "rockchip,px30-mipi-dsi"; + compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff450000 0x0 0x10000>; interrupts = ; clocks = <&cru PCLK_MIPI_DSI>; From f471b1b2db0819917c54099ab68349ad6a7e9e19 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 12 Nov 2021 19:53:59 +0530 Subject: [PATCH 278/574] arm64: dts: rockchip: Fix Bluetooth on ROCK Pi 4 boards This patch fixes the Bluetooth on ROCK Pi 4 boards. ROCK Pi 4 boards has BCM4345C5 and now it is supported on Mainline Linux, brcm,bcm43438-bt still working but observed the BT Audio issues with latest test. So, use the BCM4345C5 compatible and its associated properties like clock-names as lpo and max-speed. Attach vbat and vddio supply rails as well. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20211112142359.320798-1-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts | 7 +++++-- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts | 7 +++++-- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts | 7 +++++-- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts index 81bea953c891..cec3b7b1b947 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts @@ -46,13 +46,16 @@ status = "okay"; bluetooth { - compatible = "brcm,bcm43438-bt"; + compatible = "brcm,bcm4345c5"; clocks = <&rk808 1>; - clock-names = "ext_clock"; + clock-names = "lpo"; device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts index 6c63e617063c..cf48746a3ad8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts @@ -34,13 +34,16 @@ status = "okay"; bluetooth { - compatible = "brcm,bcm43438-bt"; + compatible = "brcm,bcm4345c5"; clocks = <&rk808 1>; - clock-names = "ext_clock"; + clock-names = "lpo"; device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts index 0ad7b6e22f70..793d84833921 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts @@ -46,14 +46,17 @@ status = "okay"; bluetooth { - compatible = "brcm,bcm43438-bt"; + compatible = "brcm,bcm4345c5"; clocks = <&rk808 1>; - clock-names = "ext_clock"; + clock-names = "lpo"; device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; }; }; From 7b9eb6cfdb784ad713024a3f8f202620ad40ba70 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sun, 12 Dec 2021 18:49:40 +0100 Subject: [PATCH 279/574] ARM: dts: ixp4xx: Add devicetree for Gateway 7001 This adds a device tree for the Gateway 7001 AP, based on Intel IXP422. Cc: Imre Kaloz Signed-off-by: Zoltan HERPAI Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 3 +- .../boot/dts/intel-ixp42x-gateway-7001.dts | 111 ++++++++++++++++++ 2 files changed, 113 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4084535c6489..7dfda6be2916 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -269,7 +269,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp42x-gateworks-gw2348.dtb \ intel-ixp43x-gateworks-gw2358.dtb \ intel-ixp42x-netgear-wg302v2.dtb \ - intel-ixp42x-arcom-vulcan.dtb + intel-ixp42x-arcom-vulcan.dtb \ + intel-ixp42x-gateway-7001.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += \ keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ diff --git a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts new file mode 100644 index 000000000000..a1c03c965f17 --- /dev/null +++ b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Gateway 7001 AP + * Derived from boardfiles written by Imre Kaloz + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Gateway 7001 AP"; + compatible = "gateway,7001", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 32 MB SDRAM */ + device_type = "memory"; + reg = <0x00000000 0x2000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart1:115200n8"; + }; + + aliases { + /* second UART is the primary console */ + serial0 = &uart1; + serial1 = &uart0; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 8 MB of flash + */ + reg = <0 0x00000000 0x800000>; + + /* Configure expansion bus to allow writes */ + intel,ixp4xx-eb-write-enable = <1>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; + }; + }; + }; + + pci@c0000000 { + status = "ok"; + + /* + * Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c) + * We have slots (IDSEL) 1 and 2 with one assigned IRQ + * each handling all IRQs. + */ + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 11 */ + <0x0800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 11 */ + <0x0800 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 11 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */ + <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */ + <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */ + }; + + ethernet@c8009000 { + status = "ok"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + ethernet@c800a000 { + status = "ok"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy2>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + }; + }; + }; +}; From 7836149e155bd3c554571f135619f95932c841fc Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 8 Dec 2021 18:18:53 +0900 Subject: [PATCH 280/574] arm64: dts: exynos: convert serial_0 to USI on ExynosAutov9 According to USI v2 driver change[1], serial_0 node should be converted to use the USI node hierarchy. syscon_peric0 will be used as a syscon node to control the USI00_USI_SW_CONF register. This also changes the serial node name from uart@ to serial@. [1]: https://lore.kernel.org/linux-samsung-soc/20211204195757.8600-2-semen.protsenko@linaro.org/ Cc: Sam Protsenko Signed-off-by: Chanho Park Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20211208091853.8557-1-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/exynosautov9-sadk.dts | 4 +++ arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 36 ++++++++++++++----- 2 files changed, 32 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts index ef46d7aa6e28..57518cb5e8c4 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts @@ -54,3 +54,7 @@ vcc-supply = <&ufs_0_fixed_vcc_reg>; vcc-fixed-regulator; }; + +&usi_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 3e4727344b4a..0fab0aa4db3f 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -7,6 +7,7 @@ */ #include +#include / { compatible = "samsung,exynosautov9"; @@ -256,16 +257,35 @@ reg = <0x17c20000 0x1000>; }; - /* USI: UART */ - serial_0: uart@10300000 { - compatible = "samsung,exynos850-uart"; - reg = <0x10300000 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_bus_dual>; + syscon_peric0: syscon@10220000 { + compatible = "samsung,exynosautov9-sysreg", "syscon"; + reg = <0x10220000 0x2000>; + }; + + usi_0: usi@103000c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x103000c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x1000>; + samsung,mode = ; + samsung,clkreq-on; /* needed for UART mode */ + #address-cells = <1>; + #size-cells = <1>; + ranges; clocks = <&uart_clock>, <&uart_clock>; - clock-names = "uart", "clk_uart_baud0"; + clock-names = "pclk", "ipclk"; status = "disabled"; + + /* USI: UART */ + serial_0: serial@10300000 { + compatible = "samsung,exynos850-uart"; + reg = <0x10300000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus_dual>; + clocks = <&uart_clock>, <&uart_clock>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; }; ufs_0_phy: ufs0-phy@17e04000 { From 5e8c1bf1a0a5c728cee2b6c2162348a9dfddf1bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 30 Nov 2021 17:11:47 +0100 Subject: [PATCH 281/574] ARM: dts: bcm2711-rpi-4-b: Add gpio offsets to line name array MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this helps human readers considerably to determine the line name for a given offset or vice versa. Signed-off-by: Uwe Kleine-König [ nsaenz: corrected patch title ] Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/20211130161147.317653-1-u.kleine-koenig@pengutronix.de --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 28 +++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 631dd5baf68d..4432412044de 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -65,12 +65,12 @@ }; &expgpio { - gpio-line-names = "BT_ON", + gpio-line-names = "BT_ON", /* 0 */ "WL_ON", "PWR_LED_OFF", "GLOBAL_RESET", "VDD_SD_IO_SEL", - "CAM_GPIO", + "CAM_GPIO", /* 5 */ "SD_PWR_ON", ""; }; @@ -84,66 +84,66 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "ID_SDA", + gpio-line-names = "ID_SDA", /* 0 */ "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", - "GPIO5", + "GPIO5", /* 5 */ "GPIO6", "SPI_CE1_N", "SPI_CE0_N", "SPI_MISO", - "SPI_MOSI", + "SPI_MOSI", /* 10 */ "SPI_SCLK", "GPIO12", "GPIO13", /* Serial port */ "TXD1", - "RXD1", + "RXD1", /* 15 */ "GPIO16", "GPIO17", "GPIO18", "GPIO19", - "GPIO20", + "GPIO20", /* 20 */ "GPIO21", "GPIO22", "GPIO23", "GPIO24", - "GPIO25", + "GPIO25", /* 25 */ "GPIO26", "GPIO27", "RGMII_MDIO", "RGMIO_MDC", /* Used by BT module */ - "CTS0", + "CTS0", /* 30 */ "RTS0", "TXD0", "RXD0", /* Used by Wifi */ "SD1_CLK", - "SD1_CMD", + "SD1_CMD", /* 35 */ "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* Shared with SPI flash */ - "PWM0_MISO", + "PWM0_MISO", /* 40 */ "PWM1_MOSI", "STATUS_LED_G_CLK", "SPIFLASH_CE_N", "SDA0", - "SCL0", + "SCL0", /* 45 */ "RGMII_RXCLK", "RGMII_RXCTL", "RGMII_RXD0", "RGMII_RXD1", - "RGMII_RXD2", + "RGMII_RXD2", /* 50 */ "RGMII_RXD3", "RGMII_TXCLK", "RGMII_TXCTL", "RGMII_TXD0", - "RGMII_TXD1", + "RGMII_TXD1", /* 55 */ "RGMII_TXD2", "RGMII_TXD3"; }; From cf4060f1bb643495742f3630ab98a7b44fc5c0fd Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 12:25:42 +0200 Subject: [PATCH 282/574] ARM: dts: at91: sama5d2: Name the qspi clock Naming clocks is a good practice. The atmel-quadspi driver supports an unnamed clock for the peripheral clock in order to be backward compatible with old DTs, but it is recommended to name the clocks on new DTs. The driver's bindings file requires the clock-names property, so name the clock. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209102542.254153-1-tudor.ambarus@microchip.com --- arch/arm/boot/dts/sama5d2.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 801969c113d6..09c741e8ecb8 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -288,6 +288,7 @@ reg-names = "qspi_base", "qspi_mmap"; interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; + clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -299,6 +300,7 @@ reg-names = "qspi_base", "qspi_mmap"; interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; + clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From 0081a525ceef14e950172def4af14c3f652fb4a2 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 14:36:42 +0200 Subject: [PATCH 283/574] ARM: dts: at91: sama7g5: Add QSPI nodes sama7g5 embedds 2 instances of QSPI controller: 1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported. 2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209123643.341892-1-tudor.ambarus@microchip.com --- arch/arm/boot/dts/sama7g5.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 7039311bf678..eddcfbf4d223 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -181,6 +181,36 @@ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; + qspi0: spi@e080c000 { + compatible = "microchip,sama7g5-ospi"; + reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, + <&dma0 AT91_XDMAC_DT_PERID(40)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; + clock-names = "pclk", "gclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi1: spi@e0810000 { + compatible = "microchip,sama7g5-qspi"; + reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, + <&dma0 AT91_XDMAC_DT_PERID(42)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; + clock-names = "pclk", "gclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + adc: adc@e1000000 { compatible = "microchip,sama7g5-adc"; reg = <0xe1000000 0x200>; From 078c2a0e8e60bb3fe78cf50b5da1620a4e13e0cd Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 14:36:43 +0200 Subject: [PATCH 284/574] ARM: dts: at91: sama7g5ek: Add QSPI0 node QSPI0 comunicates with a MX66LM1G45G SPI NOR flash. Enable the controller and describe the flash. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209123643.341892-2-tudor.ambarus@microchip.com --- arch/arm/boot/dts/at91-sama7g5ek.dts | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 0e1975c6812e..ccf9e224da78 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -13,6 +13,7 @@ #include "sama7g5.dtsi" #include #include +#include / { model = "Microchip SAMA7G5-EK"; @@ -134,6 +135,59 @@ cpu-supply = <&vddcpu>; }; +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + m25p,fast-read; + + at91bootstrap@0 { + label = "ospi: at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "ospi: bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "ospi: bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "ospi: bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "ospi: device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "ospi: kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "ospi: rootfs"; + reg = <0x800000 0x7800000>; + }; + + }; +}; + &dma0 { status = "okay"; }; @@ -555,6 +609,25 @@ bias-disable; }; + pinctrl_qspi: qspi { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + slew-rate = <0>; + atmel,drive-strength = ; + }; + pinctrl_sdmmc0_default: sdmmc0_default { cmd_data { pinmux = , From 277ee96f89d806f110e3011ea324155dd69e798f Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Wed, 17 Nov 2021 11:08:06 +0530 Subject: [PATCH 285/574] arm64: dts: ti: iot2050: Disable mcasp nodes at dtsi level Disable mcasp nodes 0-2 because several required properties are not present in the dtsi file as they are board specific. These nodes can be enabled via an overlay whenever required. Signed-off-by: Jayesh Choudhary Signed-off-by: Vignesh Raghavendra Acked-by: Jan Kiszka Link: https://lore.kernel.org/r/20211117053806.10095-1-j-choudhary@ti.com --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 1e0112b90d9f..3079eaee01c0 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -739,3 +739,15 @@ &icssg2_mdio { status = "disabled"; }; + +&mcasp0 { + status = "disabled"; +}; + +&mcasp1 { + status = "disabled"; +}; + +&mcasp2 { + status = "disabled"; +}; From 5d7248e956e68f257b46cdfcee465792086e2c01 Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Thu, 2 Dec 2021 10:52:53 +0100 Subject: [PATCH 286/574] ARM: dts: spear3xx: Use plgpio regmap in SPEAr310 and SPEAr320 Resources used by plgpio and pinmux are conflicting on SPEAr310 and SPEAr320. Use the newly introduced regmap property in plgpio node to use pinmux resources from plgpio and so avoid the conflict. Signed-off-by: Herve Codina Link: https://lore.kernel.org/r/20211202095255.165797-5-herve.codina@bootlin.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/spear310.dtsi | 1 + arch/arm/boot/dts/spear320.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi index 8ce751a1376d..77570833d46b 100644 --- a/arch/arm/boot/dts/spear310.dtsi +++ b/arch/arm/boot/dts/spear310.dtsi @@ -92,6 +92,7 @@ gpiopinctrl: gpio@b4000000 { compatible = "st,spear-plgpio"; reg = <0xb4000000 0x1000>; + regmap = <&pinmux>; #interrupt-cells = <1>; interrupt-controller; gpio-controller; diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi index 3bc1e93a0a55..47ac4474ed96 100644 --- a/arch/arm/boot/dts/spear320.dtsi +++ b/arch/arm/boot/dts/spear320.dtsi @@ -120,6 +120,7 @@ gpiopinctrl: gpio@b3000000 { compatible = "st,spear-plgpio"; reg = <0xb3000000 0x1000>; + regmap = <&pinmux>; #interrupt-cells = <1>; interrupt-controller; gpio-controller; From 7cf4cc3e8524989f9f1619ba49726576a46ee32d Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Thu, 2 Dec 2021 10:52:55 +0100 Subject: [PATCH 287/574] ARM: dts: spear3xx: Add spear320s dtsi The SPEAr320s SOC is a SPEAr320 SOC variant. Mostly identical to the SPEAr320 SOC variant, it has a new interrupt routing for PL_PGIOs. Add spear320s.dtsi to handle SPEAr320s SOC Signed-off-by: Herve Codina Link: https://lore.kernel.org/r/20211202095255.165797-7-herve.codina@bootlin.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/spear320s.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 arch/arm/boot/dts/spear320s.dtsi diff --git a/arch/arm/boot/dts/spear320s.dtsi b/arch/arm/boot/dts/spear320s.dtsi new file mode 100644 index 000000000000..133236dc190d --- /dev/null +++ b/arch/arm/boot/dts/spear320s.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr320s SoC + * + * Copyright 2021 Herve Codina + */ + +/include/ "spear320.dtsi" + +/ { + ahb { + apb { + gpiopinctrl: gpio@b3000000 { + /* + * The "RM0321 SPEAr320s address and map + * registers" document mentions interrupt 6 + * (NPGIO_INTR) for the PL_GPIO interrupt. + */ + interrupts = <6>; + interrupt-parent = <&shirq>; + }; + }; + }; +}; From bd943653b10dc9df63ad6cb69f520c10f3f21372 Mon Sep 17 00:00:00 2001 From: Julian Ribbeck Date: Tue, 16 Nov 2021 21:07:34 +0100 Subject: [PATCH 288/574] arm64: dts: qcom: Add device tree for Samsung J5 2015 (samsung-j5) Samsung J5 2015 is a MSM8916 based Smartphone. It is similar to some of the other MSM8916 devices, especially the Samsung ones. With this patch initial support for the following is added: - eMMC/SD card - Buttons - USB (although no suiting MUIC driver currently) - UART (untested for lack of equipment) - WiFi/Bluetooth (WCNSS) It is worth noting that Samsung J5 with MSM8916 exists in different generations (e.g Samsung J5 2015 and Samsung J5 2016) which each have different models (e.g. samsung-j5nlte, samsung-j5xnlte, etc). This patch is only regarding the 2015 generation, but should work with all of it's models, as far as we could test. Co-developed-by: Stephan Gerhold Signed-off-by: Stephan Gerhold Signed-off-by: Julian Ribbeck Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211116200734.73920-1-julian.ribbeck@gmx.de --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8916-samsung-j5.dts | 209 ++++++++++++++++++ 2 files changed, 210 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7f26ec20d238..693b30c51e33 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts new file mode 100644 index 000000000000..687bea438a57 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include + +/ { + model = "Samsung Galaxy J5 (2015)"; + compatible = "samsung,j5", "qcom,msm8916"; + chassis-type = "handset"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home-key { + lable = "Home Key"; + gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + status = "okay"; + linux,code = ; +}; + +/* FIXME: Replace with SM5703 MUIC when driver is available */ +&pm8916_usbin { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; +}; + +&usb { + status = "okay"; + dr_mode = "peripheral"; + extcon = <&pm8916_usbin>; +}; + +&usb_hs_phy { + extcon = <&pm8916_usbin>; + qcom,init-seq = /bits/ 8 <0x1 0x19 0x2 0x0b>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + gpio_keys_default: gpio-keys-default { + pins = "gpio107", "gpio109"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; +}; From 6b1caf4dea3e0a961b7a11cff6757ff74c1c34ea Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 7 Dec 2021 13:39:00 +0530 Subject: [PATCH 289/574] dt-bindings: arm: ti: Add bindings for J721s2 SoC Add binding for J721S2 SoC Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Kishon Vijay Abraham I Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211207080904.14324-2-a-govindraju@ti.com --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index cf327230fc0e..b03c10fa2e7a 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -53,6 +53,12 @@ properties: - ti,am642-sk - const: ti,am642 + - description: K3 J721s2 SoC + items: + - enum: + - ti,j721s2-evm + - const: ti,j721s2 + additionalProperties: true ... From beba81faad86fc2bad567b1c029d6a000a43ca78 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 7 Dec 2021 13:39:01 +0530 Subject: [PATCH 290/574] dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2 Add pinctrl macros for J721S2 SoC. These macro definitions are similar to that of J721E, but adding new definitions to avoid any naming confusions in the soc dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Kishon Vijay Abraham I Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211207080904.14324-3-a-govindraju@ti.com --- include/dt-bindings/pinctrl/k3.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index e085f102b283..63e038e36ca3 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -38,4 +38,7 @@ #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif From b8545f9d3a5426a5f76814c8aaebc5cb46a3213a Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 7 Dec 2021 13:39:02 +0530 Subject: [PATCH 291/574] arm64: dts: ti: Add initial support for J721S2 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. * Chips and Media Wave521CL H.264/H.265 encode/decode engine See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20211207080904.14324-4-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 937 ++++++++++++++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 302 ++++++ arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 189 ++++ 3 files changed, 1428 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi new file mode 100644 index 000000000000..b04db1d3ab61 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -0,0 +1,937 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J721S2 SoC Family Main Domain peripherals + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + msmc_ram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x0 0x70000000 0x0 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x70000000 0x400000>; + + atf-sram@0 { + reg = <0x0 0x20000>; + }; + + tifs-sram@1f0000 { + reg = <0x1f0000 0x10000>; + }; + + l3cache-sram@200000 { + reg = <0x200000 0x200000>; + }; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ + <0x00 0x01900000 0x00 0x100000>; /* GICR */ + + /* vcpumntirq: virtual CPU interface maintenance interrupt */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&sms>; + ti,sci-dev-id = <148>; + ti,interrupt-ranges = <8 360 56>; + }; + + main_pmx0: pinctrl@11c000 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x0 0x11c000 0x0 0x120>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 146 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart1: serial@2810000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 350 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart2: serial@2820000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 351 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart3: serial@2830000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 352 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart4: serial@2840000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 353 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart5: serial@2850000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 354 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart6: serial@2860000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 355 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart7: serial@2870000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02870000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 356 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart8: serial@2880000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02880000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 357 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; + }; + + main_uart9: serial@2890000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02890000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 358 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <145>, <146>, <147>, <148>, <149>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <66>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 111 0>; + clock-names = "gpio"; + }; + + main_gpio2: gpio@610000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00610000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <154>, <155>, <156>, <157>, <158>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <66>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 112 0>; + clock-names = "gpio"; + }; + + main_gpio4: gpio@620000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00620000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <163>, <164>, <165>, <166>, <167>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <66>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 113 0>; + clock-names = "gpio"; + }; + + main_gpio6: gpio@630000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00630000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <172>, <173>, <174>, <175>, <176>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <66>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "gpio"; + }; + + main_i2c0: i2c@2000000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 214 1>; + clock-names = "fck"; + power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c1: i2c@2010000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 215 1>; + clock-names = "fck"; + power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c2: i2c@2020000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 216 1>; + clock-names = "fck"; + power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c3: i2c@2030000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 217 1>; + clock-names = "fck"; + power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c4: i2c@2040000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02040000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 218 1>; + clock-names = "fck"; + power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c5: i2c@2050000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02050000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 219 1>; + clock-names = "fck"; + power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; + }; + + main_i2c6: i2c@2060000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02060000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 220 1>; + clock-names = "fck"; + power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; + }; + + main_sdhci0: mmc@4f80000 { + compatible = "ti,j721e-sdhci-8bit"; + reg = <0x00 0x04f80000 0x00 0x1000>, + <0x00 0x04f88000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 98 1>; + assigned-clock-parents = <&k3_clks 98 2>; + bus-width = <8>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-ddr52 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,strobe-sel = <0x77>; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + dma-coherent; + }; + + main_sdhci1: mmc@4fb0000 { + compatible = "ti,j721e-sdhci-4bit"; + reg = <0x00 0x04fb0000 0x00 0x1000>, + <0x00 0x04fb8000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 99 1>; + assigned-clock-parents = <&k3_clks 99 2>; + bus-width = <4>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; + ti,otap-del-sel-ddr50 = <0xc>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; + dma-coherent; + /* Masking support for SDR104 capability */ + sdhci-caps-mask = <0x00000003 0x00000000>; + }; + + main_navss: bus@30000000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; + ti,sci-dev-id = <224>; + dma-coherent; + dma-ranges; + + main_navss_intr: interrupt-controller@310e0000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x310e0000 0x00 0x4000>; + ti,intr-trigger-type = <4>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&sms>; + ti,sci-dev-id = <227>; + ti,interrupt-ranges = <0 64 64>, + <64 448 64>, + <128 672 64>; + }; + + main_udmass_inta: msi-controller@33d00000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x33d00000 0x00 0x100000>; + interrupt-controller; + #interrupt-cells = <0>; + interrupt-parent = <&main_navss_intr>; + msi-controller; + ti,sci = <&sms>; + ti,sci-dev-id = <265>; + ti,interrupt-ranges = <0 0 256>; + }; + + secure_proxy_main: mailbox@32c00000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x32c00000 0x00 0x100000>, + <0x00 0x32400000 0x00 0x100000>, + <0x00 0x32800000 0x00 0x100000>; + interrupt-names = "rx_011"; + interrupts = ; + }; + + hwspinlock: spinlock@30e00000 { + compatible = "ti,am654-hwspinlock"; + reg = <0x00 0x30e00000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + + mailbox0_cluster0: mailbox@31f80000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f80000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster1: mailbox@31f81000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f81000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster2: mailbox@31f82000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f82000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster3: mailbox@31f83000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f83000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster4: mailbox@31f84000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f84000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster5: mailbox@31f85000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f85000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster6: mailbox@31f86000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f86000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster7: mailbox@31f87000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f87000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster8: mailbox@31f88000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f88000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster9: mailbox@31f89000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f89000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster10: mailbox@31f8a000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8a000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster11: mailbox@31f8b000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8b000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster0: mailbox@31f90000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f90000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster1: mailbox@31f91000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f91000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster2: mailbox@31f92000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f92000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster3: mailbox@31f93000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f93000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster4: mailbox@31f94000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f94000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster5: mailbox@31f95000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f95000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster6: mailbox@31f96000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f96000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster7: mailbox@31f97000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f97000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster8: mailbox@31f98000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f98000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster9: mailbox@31f99000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f99000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster10: mailbox@31f9a000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f9a000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox1_cluster11: mailbox@31f9b000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f9b000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + main_ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <1024>; + ti,sci-rm-range-gp-rings = <0x1>; + ti,sci = <&sms>; + ti,sci-dev-id = <259>; + msi-parent = <&main_udmass_inta>; + }; + + main_udmap: dma-controller@31150000 { + compatible = "ti,j721e-navss-main-udmap"; + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x80000>, + <0x0 0x35000000 0x0 0x200000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&sms>; + ti,sci-dev-id = <263>; + ti,ringacc = <&main_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>, /* TX_HCHAN */ + <0x10>; /* TX_UHCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>, /* RX_HCHAN */ + <0x0c>; /* RX_UHCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; + + cpts@310d0000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x310d0000 0x0 0x400>; + reg-names = "cpts"; + clocks = <&k3_clks 226 5>; + clock-names = "cpts"; + interrupts-extended = <&main_navss_intr 391>; + interrupt-names = "cpts"; + ti,cpts-periodic-outputs = <6>; + ti,cpts-ext-ts-inputs = <8>; + }; + }; + + main_mcan0: can@2701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02701000 0x00 0x200>, + <0x00 0x02708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan1: can@2711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02711000 0x00 0x200>, + <0x00 0x02718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan2: can@2721000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02721000 0x00 0x200>, + <0x00 0x02728000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan3: can@2731000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02731000 0x00 0x200>, + <0x00 0x02738000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan4: can@2741000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02741000 0x00 0x200>, + <0x00 0x02748000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan5: can@2751000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02751000 0x00 0x200>, + <0x00 0x02758000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan6: can@2761000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02761000 0x00 0x200>, + <0x00 0x02768000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan7: can@2771000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02771000 0x00 0x200>, + <0x00 0x02778000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan8: can@2781000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02781000 0x00 0x200>, + <0x00 0x02788000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan9: can@2791000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02791000 0x00 0x200>, + <0x00 0x02798000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan10: can@27a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027a1000 0x00 0x200>, + <0x00 0x027a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan11: can@27b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027b1000 0x00 0x200>, + <0x00 0x027b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan12: can@27c1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027c1000 0x00 0x200>, + <0x00 0x027c8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan13: can@27d1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027d1000 0x00 0x200>, + <0x00 0x027d8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan14: can@2681000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02681000 0x00 0x200>, + <0x00 0x02688000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan15: can@2691000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02691000 0x00 0x200>, + <0x00 0x02698000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan16: can@26a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026a1000 0x00 0x200>, + <0x00 0x026a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + main_mcan17: can@26b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026b1000 0x00 0x200>, + <0x00 0x026b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi new file mode 100644 index 000000000000..7521963719ff --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu_wakeup { + sms: system-controller@44083000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + + mbox-names = "rx", "tx"; + + mboxes= <&secure_proxy_main 11>, + <&secure_proxy_main 13>; + + reg-names = "debug_messages"; + reg = <0x00 0x44083000 0x00 0x1000>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + chipid@43000014 { + compatible = "ti,am654-chipid"; + reg = <0x00 0x43000014 0x00 0x4>; + }; + + mcu_ram: sram@41c00000 { + compatible = "mmio-sram"; + reg = <0x00 0x41c00000 0x00 0x100000>; + ranges = <0x00 0x00 0x41c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + wkup_pmx0: pinctrl@4301c000 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c000 0x00 0x178>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_gpio_intr: interrupt-controller@42200000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x42200000 0x00 0x400>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&sms>; + ti,sci-dev-id = <125>; + ti,interrupt-ranges = <16 928 16>; + }; + + mcu_conf: syscon@40f00000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x40f00000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x40f00000 0x20000>; + + phy_gmii_sel: phy@4040 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4040 0x4>; + #phy-cells = <1>; + }; + + }; + + wkup_uart0: serial@42300000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x42300000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 359 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; + }; + + mcu_uart0: serial@40a00000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x40a00000 0x00 0x200>; + interrupts = ; + current-speed = <115200>; + clocks = <&k3_clks 149 3>; + clock-names = "fclk"; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + }; + + wkup_gpio0: gpio@42110000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x42110000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <103>, <104>, <105>, <106>, <107>, <108>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <89>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 115 0>; + clock-names = "gpio"; + }; + + wkup_gpio1: gpio@42100000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x42100000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <112>, <113>, <114>, <115>, <116>, <117>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <89>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 116 0>; + clock-names = "gpio"; + }; + + wkup_i2c0: i2c@42120000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x42120000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 223 1>; + clock-names = "fck"; + power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; + }; + + mcu_i2c0: i2c@40b00000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x40b00000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 221 1>; + clock-names = "fck"; + power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; + }; + + mcu_i2c1: i2c@40b10000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x40b10000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 222 1>; + clock-names = "fck"; + power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; + }; + + mcu_mcan0: can@40528000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40528000 0x00 0x200>, + <0x00 0x40500000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + mcu_mcan1: can@40568000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40568000 0x00 0x200>, + <0x00 0x40540000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + + mcu_navss: bus@28380000{ + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; + dma-coherent; + dma-ranges; + + ti,sci-dev-id = <267>; + + mcu_ringacc: ringacc@2b800000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <286>; + ti,sci-rm-range-gp-rings = <0x1>; + ti,sci = <&sms>; + ti,sci-dev-id = <272>; + msi-parent = <&main_udmass_inta>; + }; + + mcu_udmap: dma-controller@285c0000 { + compatible = "ti,j721e-navss-mcu-udmap"; + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&sms>; + ti,sci-dev-id = <273>; + ti,ringacc = <&mcu_ringacc>; + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>; /* TX_HCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>; /* RX_HCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; + }; + + mcu_cpsw: ethernet@46000000 { + compatible = "ti,j721e-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x46000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; + dma-coherent; + clocks = <&k3_clks 29 28>; + clock-names = "fck"; + power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&mcu_udmap 0xf000>, + <&mcu_udmap 0xf001>, + <&mcu_udmap 0xf002>, + <&mcu_udmap 0xf003>, + <&mcu_udmap 0xf004>, + <&mcu_udmap 0xf005>, + <&mcu_udmap 0xf006>, + <&mcu_udmap 0xf007>, + <&mcu_udmap 0x7000>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + ti,syscon-efuse = <&mcu_conf 0x200>; + phys = <&phy_gmii_sel 1>; + }; + }; + + davinci_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 29 28>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 29 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi new file mode 100644 index 000000000000..80d3cae03e88 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J721S2 SoC Family + * + * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28 + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#include +#include +#include +#include + +/ { + + model = "Texas Instruments K3 J721S2 SoC"; + compatible = "ti,j721s2"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + serial5 = &main_uart3; + serial6 = &main_uart4; + serial7 = &main_uart5; + serial8 = &main_uart6; + serial9 = &main_uart7; + serial10 = &main_uart8; + serial11 = &main_uart9; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + can0 = &main_mcan16; + can1 = &mcu_mcan0; + can2 = &mcu_mcan1; + can3 = &main_mcan3; + can4 = &main_mcan5; + }; + + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a72"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a72"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + next-level-cache = <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a72_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + + }; + + pmu: pmu { + compatible = "arm,cortex-a72-pmu"; + /* Recommendation from GIC500 TRM Table A.3 */ + interrupts = ; + }; + + cbass_main: bus@100000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ + <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ + <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ + <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ + <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ + <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ + + /* MCUSS_WKUP Range */ + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + cbass_mcu_wakeup: bus@28380000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ + + }; + + }; +}; + +/* Now include peripherals from each bus segment */ +#include "k3-j721s2-main.dtsi" +#include "k3-j721s2-mcu-wakeup.dtsi" From d502f852d22af1ca33e7a2fedd7426831f6dbaef Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 7 Dec 2021 13:39:03 +0530 Subject: [PATCH 292/574] arm64: dts: ti: Add initial support for J721S2 System on Module A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Therefore, add support for the components present on the SoM. SoM: https://www.ti.com/lit/zip/sprr439 Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20211207080904.14324-5-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 175 +++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi new file mode 100644 index 000000000000..76f0ceacb6d4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SoM: https://www.ti.com/lit/zip/sprr439 + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j721s2.dtsi" +#include + +/ { + memory@80000000 { + device_type = "memory"; + /* 16 GB RAM */ + reg = <0x00 0x80000000 0x00 0x80000000>, + <0x08 0x80000000 0x03 0x80000000>; + }; + + /* Reserving memory regions still pending */ + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + alignment = <0x1000>; + no-map; + }; + }; + + transceiver0: can-phy0 { + /* standby pin has been grounded by default */ + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&main_pmx0 { + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ + J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ + >; + }; + + main_mcan16_pins_default: main-mcan16-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ + J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ + >; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + exp_som: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", + "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", + "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE", + "GPIO_LIN_EN", "CAN_STB"; + }; +}; + +&main_mcan16 { + pinctrl-0 = <&main_mcan16_pins_default>; + pinctrl-names = "default"; + phys = <&transceiver0>; +}; + +&mailbox0_cluster0 { + status = "disabled"; +}; + +&mailbox0_cluster1 { + status = "disabled"; +}; + +&mailbox0_cluster2 { + status = "disabled"; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + status = "disabled"; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +}; + +&mailbox1_cluster0 { + status = "disabled"; +}; + +&mailbox1_cluster1 { + status = "disabled"; +}; + +&mailbox1_cluster2 { + status = "disabled"; +}; + +&mailbox1_cluster3 { + status = "disabled"; +}; + +&mailbox1_cluster4 { + status = "disabled"; +}; + +&mailbox1_cluster5 { + status = "disabled"; +}; + +&mailbox1_cluster6 { + status = "disabled"; +}; + +&mailbox1_cluster7 { + status = "disabled"; +}; + +&mailbox1_cluster8 { + status = "disabled"; +}; + +&mailbox1_cluster9 { + status = "disabled"; +}; + +&mailbox1_cluster10 { + status = "disabled"; +}; + +&mailbox1_cluster11 { + status = "disabled"; +}; From effb32e931dd4feb8aa3cee7b5b4ddda43c8b701 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 7 Dec 2021 13:39:04 +0530 Subject: [PATCH 293/574] arch: arm64: ti: Add support J721S2 Common Processor Board The EVM architecture for J721S2 is similar to that of J721E and J7200. It is as follows, +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that contains most of the actual connectors, power supply etc. The System on Module (SoM) is plugged on to the common processor baord. Therefore, add support for peripherals brought out in the common processor board. Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20211207080904.14324-6-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/Makefile | 2 + .../dts/ti/k3-j721s2-common-proc-board.dts | 421 ++++++++++++++++++ 2 files changed, 423 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 71f6097d4621..90be511bc4d0 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -17,5 +17,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb + dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts new file mode 100644 index 000000000000..a5a24f9f46c5 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * + * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM + */ + +/dts-v1/; + +#include "k3-j721s2-som-p0.dtsi" +#include + +/ { + compatible = "ti,j721s2-evm", "ti,j721s2"; + model = "Texas Instruments J721S2 EVM"; + + chosen { + stdout-path = "serial10:115200n8"; + bootargs = "console=ttyS10,115200n8 earlycon=ns16550a,mmio32,2880000"; + }; + + evm_12v0: fixedregulator-evm12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: fixedregulator-vsys3v3 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: fixedregulator-vsys5v0 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: fixedregulator-sd { + /* Output of TPS22918 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: gpio-regulator-TLV71033 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + transceiver1: can-phy1 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>; + enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + +}; + +&main_pmx0 { + main_uart8_pins_default: main-uart8-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ + J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ + J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ + J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ + >; + }; + + main_i2c3_pins_default: main-i2c3-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */ + J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ + J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ + J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ + J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ + J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ + J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ + J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ + >; + }; +}; + +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ + J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ + >; + }; +}; + +&main_gpio2 { + status = "disabled"; +}; + +&main_gpio4 { + status = "disabled"; +}; + +&main_gpio6 { + status = "disabled"; +}; + +&wkup_gpio1 { + status = "disabled"; +}; + +&wkup_uart0 { + status = "reserved"; +}; + +&main_uart0 { + status = "disabled"; +}; + +&main_uart1 { + status = "disabled"; +}; + +&main_uart2 { + status = "disabled"; +}; + +&main_uart3 { + status = "disabled"; +}; + +&main_uart4 { + status = "disabled"; +}; + +&main_uart5 { + status = "disabled"; +}; + +&main_uart6 { + status = "disabled"; +}; + +&main_uart7 { + status = "disabled"; +}; + +&main_uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart8_pins_default>; + /* Shared with TFA on this platform */ + power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; +}; + +&main_uart9 { + status = "disabled"; +}; + +&main_i2c0 { + clock-frequency = <400000>; + + exp1: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ", + "PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ", + "PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#", + "PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1", + "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz"; + }; + + exp2: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN", + "USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#", + "MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1", + "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL", + "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL", + "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2"; + }; +}; + +&main_i2c1 { + status = "disabled"; +}; + +&main_i2c2 { + status = "disabled"; +}; + +&main_i2c3 { + status = "disabled"; +}; + +&main_i2c4 { + status = "disabled"; +}; + +&main_i2c5 { + status = "disabled"; +}; + +&main_i2c6 { + status = "disabled"; +}; + +&main_sdhci0 { + /* eMMC */ + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_sdhci1 { + /* SD card */ + pinctrl-0 = <&main_mmc1_pins_default>; + pinctrl-names = "default"; + disable-wp; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; +}; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +}; + +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan0 { + status = "disabled"; +}; + +&main_mcan1 { + status = "disabled"; +}; + +&main_mcan2 { + status = "disabled"; +}; + +&main_mcan3 { + status = "disabled"; +}; + +&main_mcan4 { + status = "disabled"; +}; + +&main_mcan5 { + status = "disabled"; +}; + +&main_mcan6 { + status = "disabled"; +}; + +&main_mcan7 { + status = "disabled"; +}; + +&main_mcan8 { + status = "disabled"; +}; + +&main_mcan9 { + status = "disabled"; +}; + +&main_mcan10 { + status = "disabled"; +}; + +&main_mcan11 { + status = "disabled"; +}; + +&main_mcan12 { + status = "disabled"; +}; + +&main_mcan13 { + status = "disabled"; +}; + +&main_mcan14 { + status = "disabled"; +}; + +&main_mcan15 { + status = "disabled"; +}; + +&main_mcan17 { + status = "disabled"; +}; From 4754eab7e5a78bdefe7a960c5c260c95ebbb5fa6 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Mon, 6 Dec 2021 01:43:34 +0100 Subject: [PATCH 294/574] ARM: dts: gemini: NAS4220-B: fis-index-block with 128 KiB sectors Steven Maddox reported in the OpenWrt bugzilla, that his RaidSonic IB-NAS4220-B was no longer booting with the new OpenWrt 21.02 (uses linux 5.10's device-tree). However, it was working with the previous OpenWrt 19.07 series (uses 4.14). |[ 5.548038] No RedBoot partition table detected in 30000000.flash |[ 5.618553] Searching for RedBoot partition table in 30000000.flash at offset 0x0 |[ 5.739093] No RedBoot partition table detected in 30000000.flash |... |[ 7.039504] Waiting for root device /dev/mtdblock3... The provided bootlog shows that the RedBoot partition parser was looking for the partition table "at offset 0x0". Which is strange since the comment in the device-tree says it should be at 0xfe0000. Further digging on the internet led to a review site that took some useful PCB pictures of their review unit back in February 2009. Their picture shows a Spansion S29GL128N11TFI01 flash chip. >From Spansion's Datasheet: "S29GL128N: One hundred twenty-eight 64 Kword (128 Kbyte) sectors" Steven also provided a "cat /sys/class/mtd/mtd0/erasesize" from his unit: "131072". With the 128 KiB Sector/Erasesize in mind. This patch changes the fis-index-block property to (0xfe0000 / 0x20000) = 0x7f. Fixes: b5a923f8c739 ("ARM: dts: gemini: Switch to redboot partition parsing") Reported-by: Steven Maddox Signed-off-by: Christian Lamparter Signed-off-by: Linus Walleij Tested-by: Steven Maddox Link: https://lore.kernel.org/r/20211206004334.4169408-1-linus.walleij@linaro.org' Bugzilla: https://bugs.openwrt.org/index.php?do=details&task_id=4137 Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/gemini-nas4220b.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts index 13112a8a5dd8..6544c730340f 100644 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini-nas4220b.dts @@ -84,7 +84,7 @@ partitions { compatible = "redboot-fis"; /* Eraseblock at 0xfe0000 */ - fis-index-block = <0x1fc>; + fis-index-block = <0x7f>; }; }; From a6839c42fe7c21173eb6f5db67d944e0f076be2a Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 13 Dec 2021 12:32:49 +0100 Subject: [PATCH 295/574] ARM: dts: qcom: Build apq8016-sbc/DragonBoard 410c DTB on ARM32 The DragonBoard 410c is a convenient device for testing and debugging. Since there is support for using ARM32 kernels on MSM8916 now, also build the DB410c DTB on ARM32 so it can be used for testing. ARM64 is still the main supported architecture for DB410c but it actually works great on ARM32 as well. The "apq8016-sbc.dts" is simply included as-is from ARM64 similar to the approach used for Raspberry Pi (e.g. bcm2711-rpi-4-b.dts). Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213113250.4249-1-stephan@gerhold.net --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-apq8016-sbc.dts | 2 ++ 2 files changed, 3 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-apq8016-sbc.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..bba17ee51e29 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -954,6 +954,7 @@ dtb-$(CONFIG_ARCH_OXNAS) += \ ox810se-wd-mbwe.dtb \ ox820-cloudengines-pogoplug-series-3.dtb dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8016-sbc.dtb \ qcom-apq8026-lg-lenok.dtb \ qcom-apq8060-dragonboard.dtb \ qcom-apq8064-cm-qs600.dtb \ diff --git a/arch/arm/boot/dts/qcom-apq8016-sbc.dts b/arch/arm/boot/dts/qcom-apq8016-sbc.dts new file mode 100644 index 000000000000..4ccd2dca74a2 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8016-sbc.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/apq8016-sbc.dts" From f56498fc6a9364a35dd74af791bd1251467e9cc1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:26:11 +0100 Subject: [PATCH 296/574] arm64: dts: qcom: sm6350: Fix validation errors Sort clocks and interrupts as specified in the docs and remove the stray property #power-domain-cells from aoss_qmp to solve dtbs_check validation errors. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082614.22651-11-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index cd55797facf6..14e1071bcca4 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -531,10 +531,10 @@ ranges; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&xo_board>, <&rpmhcc RPMH_QLINK_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, - <&xo_board>; - clock-names = "aux", "ref", "com_aux", "cfg_ahb"; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; @@ -592,11 +592,12 @@ "sleep"; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 14 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -656,7 +657,6 @@ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; #clock-cells = <0>; - #power-domain-cells = <1>; }; spmi_bus: spmi@c440000 { From 489be59b635ba76ea16d6f820ddf037644b3415a Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:22:03 +0100 Subject: [PATCH 297/574] arm64: dts: qcom: sm6350: Add MPSS nodes Add the required nodes for booting the MPSS on sm6350. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082208.21492-4-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 ++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 14e1071bcca4..b0d70eafe148 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -361,6 +361,32 @@ hwlocks = <&tcsr_mutex 3>; }; + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -473,6 +499,46 @@ #hwlock-cells = <1>; }; + mpss: remoteproc@4080000 { + compatible = "qcom,sm6350-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM6350_CX>, + <&rpmhpd SM6350_MSS>; + power-domain-names = "cx", "mss"; + + memory-region = <&pil_modem_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + label = "modem"; + qcom,remote-pid = <1>; + }; + }; + sdhc_2: sdhci@8804000 { compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; From efc33c969f23cd6fe983e7e7bdcd8bbb1521f1de Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:22:05 +0100 Subject: [PATCH 298/574] arm64: dts: qcom: sm6350: Add ADSP nodes Add the required nodes for booting the ADSP on sm6350. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082208.21492-6-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 91 ++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index b0d70eafe148..fdd7d3b59533 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -361,6 +361,30 @@ hwlocks = <&tcsr_mutex 3>; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; @@ -499,6 +523,73 @@ #hwlock-cells = <1>; }; + adsp: remoteproc@3000000 { + compatible = "qcom,sm6350-adsp-pas"; + reg = <0 0x03000000 0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM6350_LCX>, + <&rpmhpd SM6350_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&pil_adsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x0>; + qcom,nsessions = <5>; + }; + }; + }; + }; + mpss: remoteproc@4080000 { compatible = "qcom,sm6350-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; From 8eb5287e8a425aa7b27cfbb92096550046a231f8 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:22:07 +0100 Subject: [PATCH 299/574] arm64: dts: qcom: sm6350: Add CDSP nodes Add the required nodes for booting the CDSP on sm6350. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082208.21492-8-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 122 +++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index fdd7d3b59533..d7c9edff19f7 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -385,6 +385,30 @@ }; }; + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; @@ -630,6 +654,104 @@ }; }; + cdsp: remoteproc@8300000 { + compatible = "qcom,sm6350-cdsp-pas"; + reg = <0 0x08300000 0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM6350_CX>, + <&rpmhpd SM6350_MX>; + power-domain-names = "cx", "mx"; + + memory-region = <&pil_cdsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1401 0x20>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1402 0x20>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1403 0x20>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1404 0x20>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1405 0x20>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1406 0x20>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1407 0x20>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1408 0x20>; + }; + + /* note: secure cb9 in downstream */ + }; + }; + }; + sdhc_2: sdhci@8804000 { compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; From bc279dc04e9ee23f6a22f6c7a6924edbd5fe0f6d Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:22:08 +0100 Subject: [PATCH 300/574] arm64: dts: qcom: sm7225-fairphone-fp4: Enable ADSP, CDSP & MPSS Enable the remoteprocs found on the SoC and add a qcom,rmtfs-mem node. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082208.21492-9-luca.weiss@fairphone.com --- .../boot/dts/qcom/sm7225-fairphone-fp4.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index a6937642736e..d4af9e0dad87 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -53,6 +53,27 @@ gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>; }; }; + + reserved-memory { + /* + * The rmtfs memory region in downstream is 'dynamically allocated' + * but given the same address every time. Hard code it as this address is + * where the modem firmware expects it to be. + */ + memory@efe01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xefe01000 0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + }; +}; + +&adsp { + status = "okay"; + firmware-name = "qcom/sm7225/fairphone4/adsp.mdt"; }; &apps_rsc { @@ -269,6 +290,16 @@ }; }; +&cdsp { + status = "okay"; + firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt"; +}; + +&mpss { + status = "okay"; + firmware-name = "qcom/sm7225/fairphone4/modem.mdt"; +}; + &pm6350_gpios { gpio_keys_pin: gpio-keys-pin { pins = "gpio2"; From ced795c2648aae44314aa8027e8e1d691ea6153f Mon Sep 17 00:00:00 2001 From: Ivan Bornyakov Date: Thu, 2 Dec 2021 08:57:24 +0300 Subject: [PATCH 301/574] dt-bindings: bus: imx-weim: add words about continuous bclk Document continuous Burst Clock option. With this option Burst Clock, if enabled, will output continuous clock, otherwise Burst Clock will output clock only when necessary. Signed-off-by: Ivan Bornyakov Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/bus/imx-weim.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt index 1b1d1c5c21ea..e7f502070d77 100644 --- a/Documentation/devicetree/bindings/bus/imx-weim.txt +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt @@ -48,6 +48,11 @@ Optional properties: devices, the presence of this property indicates that the weim bus should operate in Burst Clock Mode. + - fsl,continuous-burst-clk Make Burst Clock to output continuous clock. + Without this option Burst Clock will output clock + only when necessary. This takes effect only if + "fsl,burst-clk-enable" is set. + Timing property for child nodes. It is mandatory, not optional. - fsl,weim-cs-timing: The timing array, contains timing values for the From c4cacb5b80f4f1d83b8bcd6e16672d6732982414 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 2 Dec 2021 08:38:26 -0600 Subject: [PATCH 302/574] dt-bindings: soc: imx: Add binding doc for spba bus Add binding doc for fsl,spba-bus. Signed-off-by: Adam Ford Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/bus/fsl,spba-bus.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml new file mode 100644 index 000000000000..d42dbb0bbc2e --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Shared Peripherals Bus Interface + +maintainers: + - Shawn Guo + +description: | + A simple bus enabling access to shared peripherals. + + The "spba-bus" follows the "simple-bus" set of properties, as + specified in the Devicetree Specification. It is an extension of + "simple-bus" because the SDMA controller uses this compatible flag to + determine which peripherals are available to it and the range over which + the SDMA can access. There are no special clocks for the bus, because + the SDMA controller itself has its interrupt and clock assignments. + +select: + properties: + compatible: + contains: + const: fsl,spba-bus + required: + - compatible + +properties: + $nodename: + pattern: "^spba-bus(@[0-9a-f]+)?$" + + compatible: + items: + - const: fsl,spba-bus + - const: simple-bus + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + reg: + maxItems: 1 + + ranges: true + +required: + - compatible + - '#address-cells' + - '#size-cells' + - reg + - ranges + +additionalProperties: + type: object + +examples: + - | + spba-bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + }; From b357ffd8604ae45ec4bb1ebec072cd4ca4ce839c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 2 Dec 2021 08:38:27 -0600 Subject: [PATCH 303/574] ARM: dts: imx: Change spba to spba-bus With the updated dt-bindings for the spba-bus, rename spba@xxxx to spba-bus@xxxx. There are no functional changes. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 2 +- arch/arm/boot/dts/imx31.dtsi | 2 +- arch/arm/boot/dts/imx50.dtsi | 2 +- arch/arm/boot/dts/imx51.dtsi | 2 +- arch/arm/boot/dts/imx53.dtsi | 2 +- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index fdcca82c9986..83278b390c70 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -200,7 +200,7 @@ }; }; - spba@50000000 { + spba-bus@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 948d2a543f8d..2adb923c0b27 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -166,7 +166,7 @@ }; }; - spba@50000000 { + spba-bus@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index a969f335b240..a31e3694fa2b 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -108,7 +108,7 @@ reg = <0x50000000 0x10000000>; ranges; - spba@50000000 { + spba-bus@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 01cfcbe5928e..ba496fdfe8cb 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -178,7 +178,7 @@ reg = <0x70000000 0x10000000>; ranges; - spba@70000000 { + spba-bus@70000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 2cf3909cca2f..6082cd347124 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -229,7 +229,7 @@ reg = <0x50000000 0x10000000>; ranges; - spba@50000000 { + spba-bus@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index f5de5def876d..6dc1b970bcad 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -481,7 +481,7 @@ status = "okay"; }; - spba@203c000 { + spba-bus@203c000 { reg = <0x0203c000 0x4000>; }; }; From 74092acd6eab63b1f1e0c293400ef3b1bb7af6f8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 3 Dec 2021 00:19:01 +0200 Subject: [PATCH 304/574] ARM: dts: imx7s-warp: Drop undefined property in mipi_csi node The fsl,csis-hs-settle property isn't defined by the nxp,imx7-mipi-csi2.yaml binding, and isn't parsed by the corresponding driver. Drop it. Signed-off-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 569bbd84e371..614d252f029f 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -248,7 +248,6 @@ &mipi_csi { clock-frequency = <166000000>; - fsl,csis-hs-settle = <3>; status = "okay"; port@0 { From 473d06b9093ddc6b9fd2927893819f43e830bde5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 3 Dec 2021 00:19:02 +0200 Subject: [PATCH 305/574] ARM: dts: imx7: Drop reset-names property for mipi_csi node The reset-names property isn't defined by the nxp,imx7-mipi-csi2.yaml binding, and isn't used by the corresponding driver as it acquires the reset with a NULL ID. Drop it. Signed-off-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 1843fc053870..7e6b99ece7e9 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -819,7 +819,6 @@ power-domains = <&pgc_mipi_phy>; phy-supply = <®_1p0d>; resets = <&src IMX7_RESET_MIPI_PHY_MRST>; - reset-names = "mrst"; status = "disabled"; port@0 { From 3f8b6cf82088e0423b755f9a9dc79b8650bd1e25 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 3 Dec 2021 00:19:03 +0200 Subject: [PATCH 306/574] ARM: dts: imx7: Group mipi_csi 'port' children in a 'ports' node The nxp,imx7-mipi-csi2.yaml binding requires ports to be grouped in a ports node, as multiple ports are present. Fix imx7s.dtsi and the only board file that references the mipi_csi ports. Signed-off-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 13 +++++++------ arch/arm/boot/dts/imx7s.dtsi | 21 ++++++++++++--------- 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 614d252f029f..4f1edef06c92 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -250,14 +250,15 @@ clock-frequency = <166000000>; status = "okay"; - port@0 { - reg = <0>; + ports { + port@0 { + reg = <0>; - mipi_from_sensor: endpoint { - remote-endpoint = <&ov2680_to_mipi>; - data-lanes = <1>; + mipi_from_sensor: endpoint { + remote-endpoint = <&ov2680_to_mipi>; + data-lanes = <1>; + }; }; - }; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 7e6b99ece7e9..52a9aeecdbb2 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -809,8 +809,6 @@ mipi_csi: mipi-csi@30750000 { compatible = "fsl,imx7-mipi-csi2"; reg = <0x30750000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; interrupts = ; clocks = <&clks IMX7D_IPG_ROOT_CLK>, <&clks IMX7D_MIPI_CSI_ROOT_CLK>, @@ -821,15 +819,20 @@ resets = <&src IMX7_RESET_MIPI_PHY_MRST>; status = "disabled"; - port@0 { - reg = <0>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@1 { - reg = <1>; + port@0 { + reg = <0>; + }; - mipi_vc0_to_csi_mux: endpoint { - remote-endpoint = <&csi_mux_from_mipi_vc0>; + port@1 { + reg = <1>; + + mipi_vc0_to_csi_mux: endpoint { + remote-endpoint = <&csi_mux_from_mipi_vc0>; + }; }; }; }; From 05be8e7472cdce0b006aa5fc995ec199f91979f5 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:23 +0100 Subject: [PATCH 307/574] ARM: dts: imx1: drop "fsl,imx-clk32" "fsl,imx-clk32" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi index 9b940987864c..e312f1e74e2f 100644 --- a/arch/arm/boot/dts/imx1.dtsi +++ b/arch/arm/boot/dts/imx1.dtsi @@ -55,7 +55,7 @@ clocks { clk32 { - compatible = "fsl,imx-clk32", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32000>; }; From 9a68c8ec9ac9f097c75d6a02f12ddcd29379622d Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:24 +0100 Subject: [PATCH 308/574] ARM: dts: imx25: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 83278b390c70..fa8044c21cb8 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -62,7 +62,7 @@ clocks { osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; From 20adb4921cd6d8db90efd466a1547af047160a0a Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:25 +0100 Subject: [PATCH 309/574] ARM: dts: imx50: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index a31e3694fa2b..d61c24846eef 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -80,7 +80,7 @@ }; osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; From c5e526a9c3d5d8be8829ab2c4530a063a9aef983 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:26 +0100 Subject: [PATCH 310/574] ARM: dts: imx50: drop "fsl,imx-ckil" "fsl,imx-ckil" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index d61c24846eef..af748ea4c1a5 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -62,7 +62,7 @@ clocks { ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; From c522683be5b56a2366bbe896bae2180a6d22e95e Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:27 +0100 Subject: [PATCH 311/574] ARM: dts: imx50: drop "fsl,imx-ckih1" "fsl,imx-ckih1" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index af748ea4c1a5..682880e9e485 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -68,7 +68,7 @@ }; ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <22579200>; }; From f6bc4a7c037f07bb338dde5171c64d191e65dfff Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:28 +0100 Subject: [PATCH 312/574] ARM: dts: imx50: drop "fsl,imx-ckih2" "fsl,imx-ckih2" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 682880e9e485..be0de0fd31f9 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -74,7 +74,7 @@ }; ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; From 73cda7c63a59609fa53ab91c1167f55692140a1f Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:29 +0100 Subject: [PATCH 313/574] ARM: dts: imx51: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index ba496fdfe8cb..090223321b3b 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -66,7 +66,7 @@ }; osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; From 929bdb7b0afb19c6f640b96859554d0d0010c3b3 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:30 +0100 Subject: [PATCH 314/574] ARM: dts: imx51: drop "fsl,imx-ckil" "fsl,imx-ckil" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 090223321b3b..7840489fcd6c 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -48,7 +48,7 @@ clocks { ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; From 58cd720f3f5a19c8cacff81b652018358c0105ea Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:31 +0100 Subject: [PATCH 315/574] ARM: dts: imx51: drop "fsl,imx-ckih1" "fsl,imx-ckih1" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 7840489fcd6c..e973f3c58052 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -54,7 +54,7 @@ }; ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; From 0dee2e69efc250410f1c0d756117d6b4506f54ef Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:32 +0100 Subject: [PATCH 316/574] ARM: dts: imx51: drop "fsl,imx-ckih2" "fsl,imx-ckih2" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index e973f3c58052..56c8d87864c3 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -60,7 +60,7 @@ }; ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; From 39cd25fe2e1d10a5b319a73a6e2bf97ecba86a9c Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:33 +0100 Subject: [PATCH 317/574] ARM: dts: imx53: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 6082cd347124..9e51ea3dd739 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -104,7 +104,7 @@ }; osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; From ac0894359ecfd80f260aa42b283c88bf02387e4e Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:34 +0100 Subject: [PATCH 318/574] ARM: dts: imx53: drop "fsl,imx-ckil" "fsl,imx-ckil" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 9e51ea3dd739..dd5cf147a7a4 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -86,7 +86,7 @@ clocks { ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; From 917fee9c6f7b7d4110730c2ab5f5fe8cdd7df534 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:35 +0100 Subject: [PATCH 319/574] ARM: dts: imx53: drop "fsl,imx-ckih1" "fsl,imx-ckih1" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index dd5cf147a7a4..3efa3d6d87c5 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -92,7 +92,7 @@ }; ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <22579200>; }; From 4ce956128d43527c5c917309257f2c4e927425d6 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:36 +0100 Subject: [PATCH 320/574] ARM: dts: imx53: drop "fsl,imx-ckih2" "fsl,imx-ckih2" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 3efa3d6d87c5..67487f3caee1 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -98,7 +98,7 @@ }; ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; From 36b85fdaa36ac19ec6bd77ad5d44050747265c28 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:37 +0100 Subject: [PATCH 321/574] ARM: dts: imx6qdl: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 6dc1b970bcad..6dcb3756597b 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -67,7 +67,7 @@ }; osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; From 5368f930cc655d0906574e9841960ee380bf4351 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:38 +0100 Subject: [PATCH 322/574] ARM: dts: imx6qdl: drop "fsl,imx-ckil" "fsl,imx-ckil" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 6dcb3756597b..5d4557d15d03 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -55,7 +55,7 @@ clocks { ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; From bca46d8e5fede9cf4491be27dba9d09721b80f71 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:39 +0100 Subject: [PATCH 323/574] ARM: dts: imx6qdl: drop "fsl,imx-ckih1" "fsl,imx-ckih1" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 5d4557d15d03..d27beb47f9a3 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -61,7 +61,7 @@ }; ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; From e7ed6ba0239df1e2aca3f9b2d77da4de180cdbe0 Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Wed, 8 Dec 2021 16:05:43 +0100 Subject: [PATCH 324/574] ARM: dts: imx6qdl-dhcom: Align PHY reset timing with other DHCOM SoMs According to datasheet Microchip LAN8710A/LAN8710Ai DS00002164B [1] the reset should stay asserted for at least 100uS and software should wait at least 200nS. On other DHCOM SoMs with the SMSC LAN8710Ai PHY both reset delays are 500us. This should be plenty and for consistency, the i.MX6 SoM should also use these delays. [1] https://ww1.microchip.com/downloads/en/DeviceDoc/00002164B.pdf Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi index 5d10c40313cb..e71687061161 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi @@ -138,8 +138,8 @@ pinctrl-0 = <&pinctrl_ethphy0>; pinctrl-names = "default"; reg = <0>; - reset-assert-us = <1000>; - reset-deassert-us = <1000>; + reset-assert-us = <500>; + reset-deassert-us = <500>; reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; smsc,disable-energy-detect; /* Make plugin detection reliable */ }; From cbcf2b40a7cf40da02e08e4485118a3b4fce54ce Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Wed, 8 Dec 2021 16:07:26 +0100 Subject: [PATCH 325/574] ARM: dts: imx6qdl-dhcom: Identify the PHY by ethernet-phy-id0007.c0f0 Identify the PHY by its compatible ID value. In some cases during boot, the PHY needs to be reset to be accessible, but this is only possible if the PHY is recognized. In that case, the automatic detection of the PHY does not work and a static compatible ID value is need. Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi index e71687061161..b2b7daf43ede 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi @@ -132,7 +132,8 @@ #size-cells = <0>; ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ - compatible = "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0007.c0f0", + "ethernet-phy-ieee802.3-c22"; interrupt-parent = <&gpio4>; interrupts = <15 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pinctrl_ethphy0>; From 6c5d66cb28b0611350007204da1cd079b7b4bf41 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 2 Dec 2021 16:15:25 +0200 Subject: [PATCH 326/574] arm64: dts: ls1028a-rdb: sort nodes alphabetically by label In preparation for this board's device tree synchronization with U-Boot, we must find a common node ordering pattern. Alphabetical sounds about right. Signed-off-by: Vladimir Oltean Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1028a-rdb.dts | 84 +++++++++---------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 7719f44bcaed..a6f41aa9004a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -102,6 +102,48 @@ }; }; +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&enetc_mdio_pf3 { + sgmii_phy0: ethernet-phy@2 { + reg = <0x2>; + }; + + /* VSC8514 QSGMII quad PHY */ + qsgmii_phy0: ethernet-phy@10 { + reg = <0x10>; + }; + + qsgmii_phy1: ethernet-phy@11 { + reg = <0x11>; + }; + + qsgmii_phy2: ethernet-phy@12 { + reg = <0x12>; + }; + + qsgmii_phy3: ethernet-phy@13 { + reg = <0x13>; + }; +}; + +&enetc_port0 { + phy-handle = <&sgmii_phy0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&enetc_port2 { + status = "okay"; +}; + &esdhc { sd-uhs-sdr104; sd-uhs-sdr50; @@ -188,48 +230,6 @@ }; }; -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&enetc_mdio_pf3 { - sgmii_phy0: ethernet-phy@2 { - reg = <0x2>; - }; - - /* VSC8514 QSGMII quad PHY */ - qsgmii_phy0: ethernet-phy@10 { - reg = <0x10>; - }; - - qsgmii_phy1: ethernet-phy@11 { - reg = <0x11>; - }; - - qsgmii_phy2: ethernet-phy@12 { - reg = <0x12>; - }; - - qsgmii_phy3: ethernet-phy@13 { - reg = <0x13>; - }; -}; - -&enetc_port0 { - phy-handle = <&sgmii_phy0>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; -}; - -&enetc_port2 { - status = "okay"; -}; - &mscc_felix { status = "okay"; }; From d18c7980d4d7125b0c9fc002de301054c3667a82 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 2 Dec 2021 16:15:26 +0200 Subject: [PATCH 327/574] arm64: dts: ls1028a-rdb: add an alias for the FlexSPI controller This is used by U-Boot and is required for keeping the device trees in sync. Signed-off-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index a6f41aa9004a..7e3faa78c706 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -22,6 +22,7 @@ mmc0 = &esdhc; mmc1 = &esdhc1; rtc1 = &ftm_alarm0; + spi0 = &fspi; }; chosen { From 96ad273759e0176b5e00c7c7266421c26a7f4811 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 2 Dec 2021 16:15:27 +0200 Subject: [PATCH 328/574] arm64: dts: ls1028a-rdb: add aliases for the Ethernet ports These are used by U-Boot, and are required for keeping the device trees in sync. Signed-off-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 7e3faa78c706..79d7e7cf5403 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -23,6 +23,12 @@ mmc1 = &esdhc1; rtc1 = &ftm_alarm0; spi0 = &fspi; + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port2; + ethernet2 = &mscc_felix_port0; + ethernet3 = &mscc_felix_port1; + ethernet4 = &mscc_felix_port2; + ethernet5 = &mscc_felix_port3; }; chosen { From bd8a9cd624c6189c6ad6e0d08513e089775303a4 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 2 Dec 2021 16:15:28 +0200 Subject: [PATCH 329/574] arm64: dts: ls1028a-rdb: update copyright Company policy requires that copyright is updated when a file is touched. Keeping the copyright change separate to reduce the noise in other patches. Signed-off-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 79d7e7cf5403..639f40740d56 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -2,7 +2,7 @@ /* * Device Tree file for NXP LS1028A RDB Board. * - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * * Harninder Rai * From 22e9e261bfe85539d2a3ce8e2f8f5b8187082028 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Fri, 3 Dec 2021 19:15:36 -0600 Subject: [PATCH 330/574] arm64: dts: ls1088a: Add reboot nodes ls1088a has a separate reset register block. Define it in dts and use it for reboot. Signed-off-by: Ashish Kumar Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index f891ef6a3754..1eda080b497c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -206,6 +206,13 @@ clock-output-names = "sysclk"; }; + reboot { + compatible = "syscon-reboot"; + regmap = <&reset>; + offset = <0x0>; + mask = <0x02>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -226,6 +233,11 @@ little-endian; }; + reset: syscon@1e60000 { + compatible = "fsl,ls1088a-reset", "syscon"; + reg = <0x0 0x1e60000 0x0 0x10000>; + }; + isc: syscon@1f70000 { compatible = "fsl,ls1088a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; From a3d5b4e2af448afd0c8c843178380a8efbbaf8df Mon Sep 17 00:00:00 2001 From: Li Yang Date: Fri, 3 Dec 2021 19:15:37 -0600 Subject: [PATCH 331/574] arm64: dts: ls1088a: add snps incr burst type adjustment for usb1 This property could fix the defect that external usb device always prints this error log --- 'reset SuperSpeed USB device number n using xhci_hcd' when system power on. Signed-off-by: Pengbo Mu Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 1eda080b497c..3ed1f2c51cad 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -497,6 +497,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; }; From 1a42daaa3c7e0749f212c6bf9a8176d59833da71 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 5 Dec 2021 15:01:43 -0600 Subject: [PATCH 332/574] arm64: dts: imx8mq-evk: link regulator to VPU domain The SW1C regulator powers the VPU and the state isn't guaranteed to always be on. Link the VPU power-domain to the regulator to ensure it is turned on before using the power domain. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index c96d23fe3010..a1b7582f3ecf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -331,6 +331,10 @@ power-supply = <&sw1a_reg>; }; +&pgc_vpu { + power-supply = <&sw1c_reg>; +}; + &qspi0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; From 057ccd9db760fc2c336b1138dab345bc2d3cdd35 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 8 Dec 2021 21:17:53 +0800 Subject: [PATCH 333/574] dt-bindings: power: imx8ulp: add power domain header file Add i.MX8ULP power domain header file Acked-by: Rob Herring Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- include/dt-bindings/power/imx8ulp-power.h | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 include/dt-bindings/power/imx8ulp-power.h diff --git a/include/dt-bindings/power/imx8ulp-power.h b/include/dt-bindings/power/imx8ulp-power.h new file mode 100644 index 000000000000..a556b2e96df1 --- /dev/null +++ b/include/dt-bindings/power/imx8ulp-power.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2021 NXP + */ + +#ifndef __DT_BINDINGS_IMX8ULP_POWER_H__ +#define __DT_BINDINGS_IMX8ULP_POWER_H__ + +#define IMX8ULP_PD_DMA1 0 +#define IMX8ULP_PD_FLEXSPI2 1 +#define IMX8ULP_PD_USB0 2 +#define IMX8ULP_PD_USDHC0 3 +#define IMX8ULP_PD_USDHC1 4 +#define IMX8ULP_PD_USDHC2_USB1 5 +#define IMX8ULP_PD_DCNANO 6 +#define IMX8ULP_PD_EPDC 7 +#define IMX8ULP_PD_DMA2 8 +#define IMX8ULP_PD_GPU2D 9 +#define IMX8ULP_PD_GPU3D 10 +#define IMX8ULP_PD_HIFI4 11 +#define IMX8ULP_PD_ISI 12 +#define IMX8ULP_PD_MIPI_CSI 13 +#define IMX8ULP_PD_MIPI_DSI 14 +#define IMX8ULP_PD_PXP 15 + +#endif From a38771d7a49baf682fffd5cb8e1c6aea45ae5d26 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 8 Dec 2021 21:17:54 +0800 Subject: [PATCH 334/574] arm64: dts: imx8ulp: add scmi firmware node i.MX8ULP use scmi firmware based power domain and sensor support. So add the firmware node and the sram it uses. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index fb8714379026..8ee040e3cbae 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include "imx8ulp-pinfunc.h" @@ -102,6 +103,40 @@ #clock-cells = <0>; }; + sram@2201f000 { + compatible = "mmio-sram"; + reg = <0x0 0x2201f000 0x0 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x2201f000 0x1000>; + + scmi_buf: scmi-buf@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x400>; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0xc20000fe>; + #address-cells = <1>; + #size-cells = <0>; + shmem = <&scmi_buf>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <0>; + }; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; From 03eb813dac25d478151892e959055a80b9eb7dbe Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 8 Dec 2021 21:17:55 +0800 Subject: [PATCH 335/574] arm64: dts: imx8ulp: add power domain entry for usdhc Add power domain for USDHC node. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 8ee040e3cbae..a987ff7156bd 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -329,6 +329,7 @@ <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, <&pcc4 IMX8ULP_CLK_USDHC0>; clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; @@ -343,6 +344,7 @@ <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, <&pcc4 IMX8ULP_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; @@ -357,6 +359,7 @@ <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, <&pcc4 IMX8ULP_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; From aafac22d6b232a2a4f496f7ac3f98a32ff1fb29f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 8 Dec 2021 16:52:45 -0300 Subject: [PATCH 336/574] arm64: dts: imx8mm/n: Remove the 'pm-ignore-notify' property The 'pm-ignore-notify' property is not a valid property and there is no documentation for it. Drop such invalid property. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 1 - arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts | 1 - arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 1 - arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 1 - 4 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 40f5e7a3b064..cf07987ccc10 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -263,7 +263,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - pm-ignore-notify; keep-power-in-suspend; mmc-pwrseq = <&usdhc1_pwrseq>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts index 5389d6f2beba..502745402847 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts @@ -91,7 +91,6 @@ max-frequency = <50000000>; bus-width = <4>; no-1-8-v; - pm-ignore-notify; keep-power-in-suspend; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts index a4a2ada14835..ddac8bc7ae65 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts @@ -91,7 +91,6 @@ max-frequency = <50000000>; bus-width = <4>; no-1-8-v; - pm-ignore-notify; keep-power-in-suspend; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index 3b2d627a0342..1133cded9be2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -274,7 +274,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - pm-ignore-notify; keep-power-in-suspend; mmc-pwrseq = <&usdhc1_pwrseq>; status = "okay"; From 63aca69c224fd2a38e02598a8ce48b984c7e9c76 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Fri, 10 Dec 2021 10:23:15 -0300 Subject: [PATCH 337/574] dt-bindings: Add vendor prefix for BSH Hausgeraete GmbH Document vendor prefix for BSH Hausgeraete GmbH ('BSH Home Appliances', B/S/H/) manufacturer. Signed-off-by: Ariel D'Alessandro Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 6414f5fdcb91..b491666ba620 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -187,6 +187,8 @@ patternProperties: description: Shanghai Broadmobi Communication Technology Co.,Ltd. "^brcm,.*": description: Broadcom Corporation + "^bsh,.*": + description: BSH Hausgeraete GmbH "^buffalo,.*": description: Buffalo, Inc. "^bur,.*": From 50cee5eb406b9557f30a2824691b26d2a74f1a8a Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Fri, 10 Dec 2021 10:23:16 -0300 Subject: [PATCH 338/574] dt-bindings: arm: fsl: Add iMX8MN BSH SMM S2 boards Add bindings for BSH SystemMaster (SMM) S2 board family, which consists of: iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. Signed-off-by: Ariel D'Alessandro Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index c35076cc551d..d065721d65e9 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -807,6 +807,8 @@ properties: items: - enum: - beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit + - bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2 + - bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board - gw,imx8mn-gw7902 # i.MX8MM Gateworks Board From 8802266a103343da81fc99f7977273713e0e1980 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Fri, 10 Dec 2021 10:23:18 -0300 Subject: [PATCH 339/574] dt-bindings: arm: fsl: Add BSH SMM-M2 IMX6ULZ SystemMaster board Add bindings for BSH SystemMaster (SMM) M2 IMX6ULZ board. Signed-off-by: Ariel D'Alessandro Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d065721d65e9..97f6eebad76a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -670,6 +670,7 @@ properties: - description: i.MX6ULZ based Boards items: - enum: + - bsh,imx6ulz-bsh-smm-m2 # i.MX6 ULZ BSH SystemMaster - fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board - const: fsl,imx6ull # This seems odd. Should be last? - const: fsl,imx6ulz From bd4372f056a2cf1a8b47afafc565b1fa7eb54323 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Fri, 10 Dec 2021 10:23:17 -0300 Subject: [PATCH 340/574] arm64: dts: imx8mn-bsh-smm-s2/pro: Add iMX8MN BSH SMM S2 boards Introduce BSH SystemMaster (SMM) S2 board family, which consists of: iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. Add support for iMX8MN BSH SMM S2 board: - 256 MiB DDR3 RAM - 512 MiB NAND - Megabit Ethernet PHY - Wi-Fi 802.11 a/b/g/n/ac with Bluetooth 5.0 - USB-OTG (peripheral mode) Add support for iMX8MN BSH SMM S2 PRO board: - 512 MiB DDR3 RAM - 8 GiB eMMC - Megabit Ethernet PHY - Wi-Fi 802.11 a/b/g/n/ac with Bluetooth 5.0 - USB-OTG (peripheral mode) Signed-off-by: Ariel D'Alessandro Signed-off-by: Michael Trimarchi Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../freescale/imx8mn-bsh-smm-s2-common.dtsi | 426 ++++++++++++++++++ .../boot/dts/freescale/imx8mn-bsh-smm-s2.dts | 48 ++ .../dts/freescale/imx8mn-bsh-smm-s2pro.dts | 80 ++++ 4 files changed, 556 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 58971bd89901..5018b8b1e5f2 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -48,6 +48,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi new file mode 100644 index 000000000000..c11895d9d582 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Collabora Ltd. + * Copyright 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include "imx8mn.dtsi" + +/ { + chosen { + stdout-path = &uart4; + }; + + fec_supply: fec-supply-en { + compatible = "regulator-fixed"; + vin-supply = <&buck4_reg>; + regulator-name = "tja1101_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_pwrseq: usdhc2-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwrseq>; + reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_espi2>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <&fec_supply>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + reset-assert-us = <20>; + reset-deassert-us = <2000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + bd71847: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + + regulators { + buck1_reg: BUCK1 { + /* PMIC_BUCK1 - VDD_SOC */ + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + /* PMIC_BUCK2 - VDD_ARM */ + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: BUCK3 { + /* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */ + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + /* PMIC_BUCK6 - VDD_3V3 */ + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + /* PMIC_BUCK7 - VDD_1V8 */ + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + /* PMIC_BUCK8 - NVCC_DRAM */ + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + /* PMIC_LDO1 - NVCC_SNVS_1V8 */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + /* PMIC_LDO2 - VDD_SNVS_0V8 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + /* PMIC_LDO3 - VDDA_1V8 */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + /* PMIC_LDO4 - VDD_MIPI_0V9 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + /* PMIC_LDO6 - VDD_MIPI_1V2 */ + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bluetooth>; + shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + }; +}; + +/* Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + mmc-pwrseq = <&usdhc2_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: bcrmf@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */ + MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */ + MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */ + >; + }; + + pinctrl_espi2: espi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082 + MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090 + MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090 + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016 + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016 + MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090 + MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016 + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */ + MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */ + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */ + MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040 + MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6 + >; + }; + + pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */ + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */ + MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */ + MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts new file mode 100644 index 000000000000..33f98582eace --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Collabora Ltd. + * Copyright 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include "imx8mn-bsh-smm-s2-common.dtsi" + +/ { + model = "BSH SMM S2"; + compatible = "bsh,imx8mn-bsh-smm-s2", "fsl,imx8mn"; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x10000000>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts new file mode 100644 index 000000000000..c6a8ed6745c1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Collabora Ltd. + * Copyright 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include "imx8mn-bsh-smm-s2-common.dtsi" + +/ { + model = "BSH SMM S2 PRO"; + compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn"; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x20000000>; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0 + MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0 + MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0 + MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0 + MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0 + MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4 + MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4 + MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4 + MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4 + MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4 + MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6 + MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6 + MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6 + MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6 + MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6 + MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096 + >; + }; +}; From b2db714bc9a6dcf3636d2c5b1053cf43c0a700d9 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Tue, 30 Nov 2021 16:43:10 +0000 Subject: [PATCH 341/574] arm64: dts: renesas: r8a779a0: Add DSI encoders Provide the two MIPI DSI encoders on the V3U and connect them to the DU accordingly. Reviewed-by: Laurent Pinchart Signed-off-by: Kieran Bingham Link: https://lore.kernel.org/r/20211130164311.2909616-2-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 58 +++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 8ac1a31e4146..f89bcc698420 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2290,12 +2290,14 @@ port@0 { reg = <0>; du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; }; }; port@1 { reg = <1>; du_out_dsi1: endpoint { + remote-endpoint = <&dsi1_in>; }; }; }; @@ -2633,6 +2635,62 @@ }; }; + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779a0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>, + <&cpg CPG_CORE R8A779A0_CLK_CL16MCK>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 415>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + dsi1: dsi-encoder@fed90000 { + compatible = "renesas,r8a779a0-dsi-csi2-tx"; + reg = <0 0xfed90000 0 0x10000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>, + <&cpg CPG_CORE R8A779A0_CLK_CL16MCK>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 416>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From 5a6bca1ff7a50d2613c3074f00d2768af1aff120 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Tue, 30 Nov 2021 16:43:11 +0000 Subject: [PATCH 342/574] arm64: dts: renesas: falcon-cpu: Add DSI display output Provide the display output using the sn65dsi86 MIPI DSI bridge. Reviewed-by: Laurent Pinchart Signed-off-by: Kieran Bingham Link: https://lore.kernel.org/r/20211130164311.2909616-3-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index cd2f0d60f21a..6af3f4f4f268 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -98,6 +98,27 @@ reg = <0x7 0x00000000 0x0 0x80000000>; }; + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -115,6 +136,29 @@ regulator-boot-on; regulator-always-on; }; + + sn65dsi86_refclk: clk-x6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; +}; + +&dsi0 { + status = "okay"; + + ports { + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; }; &extal_clk { @@ -146,6 +190,41 @@ status = "okay"; clock-frequency = <400000>; + + bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; }; &i2c6 { From 844dd4378453ad8234498ebc330887209e8ad346 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 8 Dec 2021 14:27:28 +0000 Subject: [PATCH 343/574] arm64: dts: renesas: r9a07g044: Add TSU node Add TSU node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211208142729.2456-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 439870930fb3..ea528580f306 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -539,6 +539,16 @@ }; }; + tsu: thermal@10059400 { + compatible = "renesas,r9a07g044-tsu", + "renesas,rzg2l-tsu"; + reg = <0 0x10059400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>; + resets = <&cpg R9A07G044_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <1>; + }; + sbc: spi@10060000 { compatible = "renesas,r9a07g044-rpc-if", "renesas,rzg2l-rpc-if"; @@ -902,6 +912,22 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu 0>; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, From 88404c56fde05eb741552a33fdfe6d7d20c1c986 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 8 Dec 2021 14:27:29 +0000 Subject: [PATCH 344/574] arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. Based on the work done by Dien Pham and others for r8a77990 SoC. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211208142729.2456-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index ea528580f306..2639fd383010 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -88,6 +88,7 @@ compatible = "arm,cortex-a55"; reg = <0>; device_type = "cpu"; + #cooling-cells = <2>; next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; @@ -917,6 +918,15 @@ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsu 0>; + sustainable-power = <717>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; trips { sensor_crit: sensor-crit { @@ -924,6 +934,12 @@ hysteresis = <1000>; type = "critical"; }; + + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; }; From 0714ccb54c38826f942848813cb06bc50d148e37 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 18 Dec 2019 13:49:14 +0100 Subject: [PATCH 345/574] ARM: tegra: Clean up external memory controller nodes The external memory controller should be sorted after the memory controller to keep the ordering by unit-address intact. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 432 ++-- .../arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 648 +++--- arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 1774 +++++++++-------- .../arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 596 +++--- 4 files changed, 1754 insertions(+), 1696 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index a7ac805eeed5..25c1006a2c5a 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -15,66 +15,77 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-924000000 { clock-frequency = <924000000>; nvidia,parent-clock-frequency = <924000000>; @@ -84,6 +95,216 @@ }; }; + memory-controller@70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 0x8000000a + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x77e30303 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 0x80000012 + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x76230303 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 0x80000017 + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x74a30303 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 0x8000001e + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x74230403 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 0x80000026 + 0x00000001 0x00000001 + 0x00000003 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0503 + 0x73c30504 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 0x80000040 + 0x00000001 0x00000001 + 0x00000004 0x00000002 + 0x00000003 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000004 0x00000006 + 0x06040203 0x000a0504 + 0x73840a05 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 0x80000040 + 0x00000001 0x00000002 + 0x00000007 0x00000004 + 0x00000004 0x00000001 + 0x00000002 0x00000007 + 0x00000002 0x00000002 + 0x00000004 0x00000006 + 0x06040202 0x000b0607 + 0x77450e08 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 0x80000040 + 0x00000001 0x00000002 + 0x00000009 0x00000005 + 0x00000006 0x00000001 + 0x00000002 0x00000008 + 0x00000002 0x00000002 + 0x00000004 0x00000006 + 0x06040202 0x000d0709 + 0x7586120a 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 0x80000040 + 0x00000002 0x00000003 + 0x0000000c 0x00000007 + 0x00000008 0x00000001 + 0x00000002 0x00000009 + 0x00000002 0x00000002 + 0x00000005 0x00000006 + 0x06050202 0x0010090c + 0x7428180d 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 0x80000040 + 0x00000003 0x00000004 + 0x0000000e 0x00000009 + 0x0000000a 0x00000001 + 0x00000003 0x0000000b + 0x00000002 0x00000002 + 0x00000005 0x00000007 + 0x07050202 0x00130b0e + 0x73a91b0f 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b 0x80000040 + 0x00000004 0x00000005 + 0x00000013 0x0000000c + 0x0000000d 0x00000002 + 0x00000003 0x0000000c + 0x00000002 0x00000002 + 0x00000006 0x00000008 + 0x08060202 0x00170e13 + 0x736c2414 0x70000f02 + 0x001f0000 + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < + 0x0e00000d 0x80000040 + 0x00000005 0x00000006 + 0x00000016 0x0000000e + 0x0000000f 0x00000002 + 0x00000004 0x0000000e + 0x00000002 0x00000002 + 0x00000006 0x00000009 + 0x09060202 0x001a1016 + 0x734e2a17 0x70000f02 + 0x001f0000 + >; + }; + }; + }; + external-memory-controller@7001b000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -1251,217 +1472,6 @@ 0x00000011 >; }; - - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 0x8000000a - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x77e30303 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 0x80000012 - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x76230303 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 0x80000017 - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x74a30303 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 0x8000001e - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x74230403 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 0x80000026 - 0x00000001 0x00000001 - 0x00000003 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0503 - 0x73c30504 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 0x80000040 - 0x00000001 0x00000001 - 0x00000004 0x00000002 - 0x00000003 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000004 0x00000006 - 0x06040203 0x000a0504 - 0x73840a05 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 0x80000040 - 0x00000001 0x00000002 - 0x00000007 0x00000004 - 0x00000004 0x00000001 - 0x00000002 0x00000007 - 0x00000002 0x00000002 - 0x00000004 0x00000006 - 0x06040202 0x000b0607 - 0x77450e08 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 0x80000040 - 0x00000001 0x00000002 - 0x00000009 0x00000005 - 0x00000006 0x00000001 - 0x00000002 0x00000008 - 0x00000002 0x00000002 - 0x00000004 0x00000006 - 0x06040202 0x000d0709 - 0x7586120a 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 0x80000040 - 0x00000002 0x00000003 - 0x0000000c 0x00000007 - 0x00000008 0x00000001 - 0x00000002 0x00000009 - 0x00000002 0x00000002 - 0x00000005 0x00000006 - 0x06050202 0x0010090c - 0x7428180d 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 0x80000040 - 0x00000003 0x00000004 - 0x0000000e 0x00000009 - 0x0000000a 0x00000001 - 0x00000003 0x0000000b - 0x00000002 0x00000002 - 0x00000005 0x00000007 - 0x07050202 0x00130b0e - 0x73a91b0f 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b 0x80000040 - 0x00000004 0x00000005 - 0x00000013 0x0000000c - 0x0000000d 0x00000002 - 0x00000003 0x0000000c - 0x00000002 0x00000002 - 0x00000006 0x00000008 - 0x08060202 0x00170e13 - 0x736c2414 0x70000f02 - 0x001f0000 - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emem-configuration = < - 0x0e00000d 0x80000040 - 0x00000005 0x00000006 - 0x00000016 0x0000000e - 0x0000000f 0x00000002 - 0x00000004 0x0000000e - 0x00000002 0x00000002 - 0x00000006 0x00000009 - 0x09060202 0x001a1016 - 0x734e2a17 0x70000f02 - 0x001f0000 - >; - }; }; }; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index df4e463afbd1..3ad2e02c7d3a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -10,66 +10,77 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-924000000 { clock-frequency = <924000000>; nvidia,parent-clock-frequency = <924000000>; @@ -79,6 +90,324 @@ }; }; + memory-controller@70019000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0503 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000004 + 0x00000002 + 0x00000003 + 0x00000001 + 0x00000003 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0504 + 0x73840a05 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000004 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000006 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000007 + 0x00000008 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090c + 0x7428180d + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000a + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000d + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00170e13 + 0x736c2414 + 0x70000f02 + 0x001f0000 + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < + 0x0e00000d + 0x80000040 + 0x00000005 + 0x00000006 + 0x00000016 + 0x0000000e + 0x0000000f + 0x00000002 + 0x00000004 + 0x0000000e + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000009 + 0x09060202 + 0x001a1016 + 0x734e2a17 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; + external-memory-controller@7001b000 { emc-timings-3 { nvidia,ram-code = <3>; @@ -2098,325 +2427,6 @@ 0x00000011 >; }; - - }; - }; - - memory-controller@70019000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0503 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000004 - 0x00000002 - 0x00000003 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040203 - 0x000a0504 - 0x73840a05 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000004 - 0x00000004 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 - 0x00000006 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 - 0x80000040 - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000007 - 0x00000008 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000006 - 0x06050202 - 0x0010090c - 0x7428180d - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000a - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000d - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000008 - 0x08060202 - 0x00170e13 - 0x736c2414 - 0x70000f02 - 0x001f0000 - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emem-configuration = < - 0x0e00000d - 0x80000040 - 0x00000005 - 0x00000006 - 0x00000016 - 0x0000000e - 0x0000000f - 0x00000002 - 0x00000004 - 0x0000000e - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000009 - 0x09060202 - 0x001a1016 - 0x734e2a17 - 0x70000f02 - 0x001f0000 - >; - }; }; }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index a0f56cc9da5c..49a6d6afc633 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -14,60 +14,70 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; @@ -85,60 +95,70 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; @@ -156,60 +176,70 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; @@ -219,6 +249,878 @@ }; }; + memory-controller@70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x76230303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74230403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ + 0x7428180e /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x734c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-4 { + nvidia,ram-code = <4>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x77430303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75430403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x74e30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0504 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a40a05 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RC */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090c /* MC_EMEM_ARB_DA_COVERS */ + 0x7488180d /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x74691b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00170e13 /* MC_EMEM_ARB_DA_COVERS */ + 0x746c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-6 { + nvidia,ram-code = <6>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x76230303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74230403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ + 0x7428180e /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x734c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + }; + external-memory-controller@7001b000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -5776,878 +6678,6 @@ }; }; }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ - 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180e /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - - emc-timings-4 { - nvidia,ram-code = <4>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x77430303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75430403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x74e30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0504 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a40a05 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090c /* MC_EMEM_ARB_DA_COVERS */ - 0x7488180d /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x74691b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00170e13 /* MC_EMEM_ARB_DA_COVERS */ - 0x746c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - - emc-timings-6 { - nvidia,ram-code = <6>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ - 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180e /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - }; }; &emc_icc_dvfs_opp_table { diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index 35c98734d35f..7360a1f35389 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -10,55 +10,65 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + /* TODO: Add 528MHz frequency */ + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; @@ -68,6 +78,298 @@ }; }; + memory-controller@70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 + 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0403 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000005 + 0x00000002 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0405 + 0x73840a06 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000004 + 0x00000005 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000007 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 + 0x00000003 + 0x0000000d + 0x00000008 + 0x0000000a + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090d + 0x7428180e + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000b + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000f + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00160d13 + 0x734c2414 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; + external-memory-controller@7001b000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -1751,300 +2053,6 @@ 0x0000000f >; }; - - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0403 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000005 - 0x00000002 - 0x00000004 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040203 - 0x000a0405 - 0x73840a06 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000004 - 0x00000005 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 - 0x00000007 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 - 0x80000040 - 0x00000002 - 0x00000003 - 0x0000000d - 0x00000008 - 0x0000000a - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000006 - 0x06050202 - 0x0010090d - 0x7428180e - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000b - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000f - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000008 - 0x08060202 - 0x00160d13 - 0x734c2414 - 0x70000f02 - 0x001f0000 - >; - }; }; }; }; From 0a6a64f904c6fda33f4b7d50abcae3b8302e89f1 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 17:08:42 +0100 Subject: [PATCH 346/574] ARM: tegra: Specify correct PMIC compatible on Tegra114 boards The PMIC found on Dalmore, TN7 and Roth is a TPS65913, so add the specific compatible string in addition to the generic Palmas series compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 2 +- arch/arm/boot/dts/tegra114-roth.dts | 2 +- arch/arm/boot/dts/tegra114-tn7.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 7fd901f8d39a..82caefe5928c 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -894,7 +894,7 @@ }; palmas: tps65913@58 { - compatible = "ti,palmas"; + compatible = "ti,tps65913", "ti,palmas"; reg = <0x58>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 07960171fabe..71a2806c0f59 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -801,7 +801,7 @@ }; palmas: pmic@58 { - compatible = "ti,palmas"; + compatible = "ti,tps65913", "ti,palmas"; reg = <0x58>; interrupts = ; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 745d234b105b..753130b1e37b 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -62,7 +62,7 @@ clock-frequency = <400000>; palmas: pmic@58 { - compatible = "ti,palmas"; + compatible = "ti,tps65913", "ti,palmas"; reg = <0x58>; interrupts = ; From 0b9f3940d6305dd0fc059f7ffaa8334d2e2dd8b6 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 17:19:28 +0100 Subject: [PATCH 347/574] ARM: tegra: Rename SPI flash chip nodes SPI flash chip nodes should be named "flash" instead of "spi-flash". Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 3 ++- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 3 ++- arch/arm/boot/dts/tegra124-venice2.dts | 3 ++- arch/arm/boot/dts/tegra20-trimslice.dts | 3 ++- arch/arm/boot/dts/tegra30-beaver.dts | 3 ++- arch/arm/boot/dts/tegra30-cardhu.dtsi | 3 ++- 6 files changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 82caefe5928c..e64199ba82cb 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1084,7 +1084,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@0 { + + flash@0 { compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 35ab296408e1..b2b3eea81232 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1655,7 +1655,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@0 { + + flash@0 { compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index e6b54ac1ebd1..02cf986c7567 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -881,7 +881,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@0 { + + flash@0 { compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 4bc87bc0c2a4..beae368f827a 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -287,7 +287,8 @@ spi@7000c380 { status = "okay"; spi-max-frequency = <48000000>; - spi-flash@0 { + + flash@0 { compatible = "winbond,w25q80bl", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <48000000>; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index e159feeedef7..f724abcdb1a5 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1898,7 +1898,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@1 { + + flash@1 { compatible = "winbond,w25q32", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 448f1397e64a..e7bfe0e5ee06 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -374,7 +374,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@1 { + + flash@1 { compatible = "winbond,w25q32", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <20000000>; From 4f74ed817ef8d8aa2ef5049537f329fde2f9fca7 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 12 Dec 2021 00:14:03 +0300 Subject: [PATCH 348/574] ARM: tegra: Rename top-level clocks Clocks defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the clock to the node name. [treding@nvidia.com: factored out patch and wrote commit message] Signed-off-by: David Heidelberg Co-developed-by: Thierry Reding Signed-off-by: Thierry Reding Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 2 +- arch/arm/boot/dts/tegra114-roth.dts | 2 +- arch/arm/boot/dts/tegra114-tn7.dts | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +- arch/arm/boot/dts/tegra124-venice2.dts | 2 +- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++-- arch/arm/boot/dts/tegra20-harmony.dts | 2 +- arch/arm/boot/dts/tegra20-paz00.dts | 2 +- arch/arm/boot/dts/tegra20-seaboard.dts | 2 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +- arch/arm/boot/dts/tegra20-trimslice.dts | 2 +- arch/arm/boot/dts/tegra20-ventana.dts | 2 +- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 2 +- arch/arm/boot/dts/tegra30-beaver.dts | 2 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- 16 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index e64199ba82cb..ad8116780dc9 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1152,7 +1152,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 71a2806c0f59..ed6ebbf008e1 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1016,7 +1016,7 @@ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 753130b1e37b..36717331101e 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -273,7 +273,7 @@ power-supply = <&lcd_bl_en>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index b2b3eea81232..f59135b93cb0 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1869,7 +1869,7 @@ vbus-supply = <&vdd_usb3_vbus>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 63a81270300a..f15623f83893 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -582,7 +582,7 @@ 256>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 02cf986c7567..14eeb1242b15 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1062,7 +1062,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 23d3f8daab23..1aaee6f09fd8 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -827,7 +827,7 @@ }; /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock@0 { + clk32k_in: clock-32k-in { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -839,7 +839,7 @@ * oscillator is used as a reference clock-source by the * Azurewave WiFi/BT module. */ - rtc_32k_wifi: clock@1 { + rtc_32k_wifi: clock-32k-wifi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index ae4312eedcbd..4d137461f3c4 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -640,7 +640,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 5b38b0606f99..d3d24523553e 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -575,7 +575,7 @@ default-brightness-level = <10>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 92d494b8c3d2..ffeae5da22e7 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -792,7 +792,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index dd4d506683de..d5f1a46da0bc 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -502,7 +502,7 @@ status = "okay"; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index beae368f827a..49c3b3bfac51 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -380,7 +380,7 @@ bus-width = <4>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 5a2578b3707f..ef97457f1334 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -606,7 +606,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 07d4ea130964..72159eb55a3d 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1069,7 +1069,7 @@ }; /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index f724abcdb1a5..91ecca0be5a2 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1967,7 +1967,7 @@ status = "okay"; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index e7bfe0e5ee06..6074885280fc 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -434,7 +434,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; From c629196d04c8cdb0624a0763cec78fa18ba8ab1f Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:04 +0300 Subject: [PATCH 349/574] ARM: tegra: Rename top-level regulators Regulators defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the regulator to the node name. [treding@nvidia.com: factored out patch and wrote commit message] Signed-off-by: David Heidelberg Co-developed-by: Thierry Reding Signed-off-by: Thierry Reding Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 14 +++++----- arch/arm/boot/dts/tegra114-roth.dts | 12 ++++----- arch/arm/boot/dts/tegra114-tn7.dts | 6 ++--- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 24 ++++++++--------- arch/arm/boot/dts/tegra124-nyan.dtsi | 26 +++++++++---------- arch/arm/boot/dts/tegra124-venice2.dts | 26 +++++++++---------- .../boot/dts/tegra20-acer-a500-picasso.dts | 8 +++--- arch/arm/boot/dts/tegra20-harmony.dts | 14 +++++----- arch/arm/boot/dts/tegra20-medcom-wide.dts | 8 +++--- arch/arm/boot/dts/tegra20-paz00.dts | 4 +-- arch/arm/boot/dts/tegra20-plutux.dts | 8 +++--- arch/arm/boot/dts/tegra20-seaboard.dts | 14 +++++----- arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +- arch/arm/boot/dts/tegra20-tec.dts | 8 +++--- arch/arm/boot/dts/tegra20-trimslice.dts | 10 +++---- arch/arm/boot/dts/tegra20-ventana.dts | 10 +++---- .../tegra30-asus-nexus7-grouper-common.dtsi | 8 +++--- ...egra30-asus-nexus7-grouper-maxim-pmic.dtsi | 4 +-- .../tegra30-asus-nexus7-grouper-ti-pmic.dtsi | 2 +- arch/arm/boot/dts/tegra30-beaver.dts | 18 ++++++------- arch/arm/boot/dts/tegra30-cardhu-a02.dts | 12 ++++----- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 14 +++++----- arch/arm/boot/dts/tegra30-cardhu.dtsi | 26 +++++++++---------- 23 files changed, 139 insertions(+), 139 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index ad8116780dc9..658edfb8d7fa 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1187,7 +1187,7 @@ }; }; - vdd_ac_bat_reg: regulator@0 { + vdd_ac_bat_reg: regulator-acbat { compatible = "regulator-fixed"; regulator-name = "vdd_ac_bat"; regulator-min-microvolt = <5000000>; @@ -1195,7 +1195,7 @@ regulator-always-on; }; - dvdd_ts_reg: regulator@1 { + dvdd_ts_reg: regulator-ts { compatible = "regulator-fixed"; regulator-name = "dvdd_ts"; regulator-min-microvolt = <1800000>; @@ -1204,7 +1204,7 @@ gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; }; - usb1_vbus_reg: regulator@3 { + usb1_vbus_reg: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -1215,7 +1215,7 @@ vin-supply = <&tps65090_dcdc1_reg>; }; - usb3_vbus_reg: regulator@4 { + usb3_vbus_reg: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "usb2_vbus"; regulator-min-microvolt = <5000000>; @@ -1226,7 +1226,7 @@ vin-supply = <&tps65090_dcdc1_reg>; }; - vdd_hdmi_reg: regulator@5 { + vdd_hdmi_reg: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "vdd_hdmi_5v0"; regulator-min-microvolt = <5000000>; @@ -1234,7 +1234,7 @@ vin-supply = <&tps65090_dcdc1_reg>; }; - vdd_cam_1v8_reg: regulator@6 { + vdd_cam_1v8_reg: regulator-cam { compatible = "regulator-fixed"; regulator-name = "vdd_cam_1v8_reg"; regulator-min-microvolt = <1800000>; @@ -1243,7 +1243,7 @@ gpio = <&palmas_gpio 6 0>; }; - vdd_5v0_hdmi: regulator@7 { + vdd_5v0_hdmi: regulator-hdmicon { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index ed6ebbf008e1..2498cf18fd39 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1045,7 +1045,7 @@ }; }; - lcd_bl_en: regulator@0 { + lcd_bl_en: regulator-lcden { compatible = "regulator-fixed"; regulator-name = "lcd_bl_en"; regulator-min-microvolt = <5000000>; @@ -1053,7 +1053,7 @@ regulator-boot-on; }; - vdd_lcd: regulator@1 { + vdd_lcd: regulator-lcd { compatible = "regulator-fixed"; regulator-name = "vdd_lcd_1v8"; regulator-min-microvolt = <1800000>; @@ -1064,7 +1064,7 @@ regulator-boot-on; }; - regulator@2 { + regulator-1v8ts { compatible = "regulator-fixed"; regulator-name = "vdd_1v8_ts"; regulator-min-microvolt = <1800000>; @@ -1073,7 +1073,7 @@ regulator-boot-on; }; - regulator@3 { + regulator-3v3ts { compatible = "regulator-fixed"; regulator-name = "vdd_3v3_ts"; regulator-min-microvolt = <3300000>; @@ -1083,7 +1083,7 @@ regulator-boot-on; }; - regulator@4 { + regulator-1v8com { compatible = "regulator-fixed"; regulator-name = "vdd_1v8_com"; regulator-min-microvolt = <1800000>; @@ -1094,7 +1094,7 @@ regulator-boot-on; }; - regulator@5 { + regulator-3v3com { compatible = "regulator-fixed"; regulator-name = "vdd_3v3_com"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 36717331101e..ef8f722dd9cb 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -303,7 +303,7 @@ }; /* FIXME: output of BQ24192 */ - vs_sys: regulator@0 { + vs_sys: regulator-vs { compatible = "regulator-fixed"; regulator-name = "VS_SYS"; regulator-min-microvolt = <4200000>; @@ -312,7 +312,7 @@ regulator-boot-on; }; - lcd_bl_en: regulator@1 { + lcd_bl_en: regulator-lcden { compatible = "regulator-fixed"; regulator-name = "VDD_LCD_BL"; regulator-min-microvolt = <16500000>; @@ -323,7 +323,7 @@ regulator-boot-on; }; - vdd_lcd: regulator@2 { + vdd_lcd: regulator-lcd { compatible = "regulator-fixed"; regulator-name = "VD_LCD_1V8"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index f59135b93cb0..c3edb332187a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1893,7 +1893,7 @@ }; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <12000000>; @@ -1902,7 +1902,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-5v0sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -1912,7 +1912,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-3v3sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -1922,7 +1922,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-3v3run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -1934,7 +1934,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-3v3hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -1942,7 +1942,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_usb1_vbus: regulator@5 { + vdd_usb1_vbus: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "+USB0_VBUS_SW"; regulator-min-microvolt = <5000000>; @@ -1953,7 +1953,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@6 { + vdd_usb3_vbus: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -1964,7 +1964,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_lp0: regulator@7 { + vdd_3v3_lp0: regulator-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; @@ -1976,7 +1976,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@8 { + vdd_hdmi_pll: regulator-hdmipll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; regulator-min-microvolt = <1050000>; @@ -1985,7 +1985,7 @@ vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@9 { + vdd_5v0_hdmi: regulator-hdmicon { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; @@ -1996,7 +1996,7 @@ }; /* Molex power connector */ - vdd_5v0_sata: regulator@10 { + vdd_5v0_sata: regulator-5v0sata { compatible = "regulator-fixed"; regulator-name = "+5V_SATA"; regulator-min-microvolt = <5000000>; @@ -2006,7 +2006,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_12v0_sata: regulator@11 { + vdd_12v0_sata: regulator-12v0sata { compatible = "regulator-fixed"; regulator-name = "+12V_SATA"; regulator-min-microvolt = <12000000>; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index f15623f83893..2d045d1a9bcf 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -615,7 +615,7 @@ }; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <12000000>; @@ -624,7 +624,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-5v0sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -634,7 +634,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-3v3sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -644,7 +644,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-3v3run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -656,7 +656,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-3v3hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -664,7 +664,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_led: regulator@5 { + vdd_led: regulator-led { compatible = "regulator-fixed"; regulator-name = "+VDD_LED"; gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; @@ -672,7 +672,7 @@ vin-supply = <&vdd_mux>; }; - vdd_5v0_ts: regulator@6 { + vdd_5v0_ts: regulator-ts { compatible = "regulator-fixed"; regulator-name = "+5V_VDD_TS_SW"; regulator-min-microvolt = <5000000>; @@ -683,7 +683,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb1_vbus: regulator@7 { + vdd_usb1_vbus: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -694,7 +694,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@8 { + vdd_usb3_vbus: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_SS"; regulator-min-microvolt = <5000000>; @@ -705,7 +705,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_panel: regulator@9 { + vdd_3v3_panel: regulator-panel { compatible = "regulator-fixed"; regulator-name = "+3.3V_PANEL"; regulator-min-microvolt = <3300000>; @@ -715,7 +715,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_3v3_lp0: regulator@10 { + vdd_3v3_lp0: regulator-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; @@ -730,7 +730,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@11 { + vdd_hdmi_pll: regulator-hdmipll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; regulator-min-microvolt = <1050000>; @@ -739,7 +739,7 @@ vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@12 { + vdd_5v0_hdmi: regulator-hdmicon { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 14eeb1242b15..5f17a2f7d270 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1087,7 +1087,7 @@ ddc-i2c-bus = <&dpaux>; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <12000000>; @@ -1096,7 +1096,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-5v0sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -1106,7 +1106,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-3v3sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -1116,7 +1116,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-3v3run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -1128,7 +1128,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -1136,7 +1136,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_led: regulator@5 { + vdd_led: regulator-led { compatible = "regulator-fixed"; regulator-name = "+VDD_LED"; regulator-min-microvolt = <3300000>; @@ -1146,7 +1146,7 @@ vin-supply = <&vdd_mux>; }; - vdd_5v0_ts: regulator@6 { + vdd_5v0_ts: regulator-ts { compatible = "regulator-fixed"; regulator-name = "+5V_VDD_TS_SW"; regulator-min-microvolt = <5000000>; @@ -1157,7 +1157,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb1_vbus: regulator@7 { + vdd_usb1_vbus: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -1168,7 +1168,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@8 { + vdd_usb3_vbus: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_SS"; regulator-min-microvolt = <5000000>; @@ -1179,7 +1179,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_panel: regulator@9 { + vdd_3v3_panel: regulator-panel { compatible = "regulator-fixed"; regulator-name = "+3.3V_PANEL"; regulator-min-microvolt = <3300000>; @@ -1189,7 +1189,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_3v3_lp0: regulator@10 { + vdd_3v3_lp0: regulator-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; @@ -1204,7 +1204,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@11 { + vdd_hdmi_pll: regulator-hdmipll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; regulator-min-microvolt = <1050000>; @@ -1213,7 +1213,7 @@ vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@12 { + vdd_5v0_hdmi: regulator-hdmicon { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 1aaee6f09fd8..2e6340e92fe1 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -964,7 +964,7 @@ }; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -972,7 +972,7 @@ regulator-always-on; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3_vs"; regulator-min-microvolt = <3300000>; @@ -981,7 +981,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_1v8_sys: regulator@2 { + vdd_1v8_sys: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd_1v8_vs"; regulator-min-microvolt = <1800000>; @@ -990,7 +990,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_pnl: regulator@3 { + vdd_pnl: regulator-panel { compatible = "regulator-fixed"; regulator-name = "vdd_panel"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 4d137461f3c4..a8494378c382 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -666,7 +666,7 @@ backlight = <&backlight>; }; - vdd_5v0_reg: regulator@0 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -674,7 +674,7 @@ regulator-always-on; }; - regulator@1 { + regulator-1v5 { compatible = "regulator-fixed"; regulator-name = "vdd_1v5"; regulator-min-microvolt = <1500000>; @@ -682,7 +682,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - regulator@2 { + regulator-1v2 { compatible = "regulator-fixed"; regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; @@ -691,7 +691,7 @@ enable-active-high; }; - pci_vdd_reg: regulator@3 { + pci_vdd_reg: regulator-1v05 { compatible = "regulator-fixed"; regulator-name = "vdd_1v05"; regulator-min-microvolt = <1050000>; @@ -700,7 +700,7 @@ enable-active-high; }; - vdd_pnl_reg: regulator@4 { + vdd_pnl_reg: regulator-pn1 { compatible = "regulator-fixed"; regulator-name = "vdd_pnl"; regulator-min-microvolt = <2800000>; @@ -709,7 +709,7 @@ enable-active-high; }; - vdd_bl_reg: regulator@5 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <2800000>; @@ -718,7 +718,7 @@ enable-active-high; }; - vdd_5v0_hdmi: regulator@6 { + vdd_5v0_hdmi: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "VDDIO_HDMI"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index b31c9bca16e6..cb6199d7d224 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -92,7 +92,7 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - vcc_24v_reg: regulator@100 { + vcc_24v_reg: regulator-24v0 { compatible = "regulator-fixed"; regulator-name = "vcc_24v"; regulator-min-microvolt = <24000000>; @@ -100,7 +100,7 @@ regulator-always-on; }; - vdd_5v0_reg: regulator@101 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; vin-supply = <&vcc_24v_reg>; @@ -109,7 +109,7 @@ regulator-always-on; }; - vdd_3v3_reg: regulator@102 { + vdd_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; vin-supply = <&vcc_24v_reg>; @@ -118,7 +118,7 @@ regulator-always-on; }; - vdd_1v8_reg: regulator@103 { + vdd_1v8_reg: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd_1v8"; vin-supply = <&vdd_3v3_reg>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index d3d24523553e..46d81d703548 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -612,7 +612,7 @@ backlight = <&backlight>; }; - p5valw_reg: regulator@0 { + p5valw_reg: regulator-5v0alw { compatible = "regulator-fixed"; regulator-name = "+5valw"; regulator-min-microvolt = <5000000>; @@ -620,7 +620,7 @@ regulator-always-on; }; - vdd_pnl_reg: regulator@1 { + vdd_pnl_reg: regulator-3v0 { compatible = "regulator-fixed"; regulator-name = "+3VS,vdd_pnl"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index 5811b7006a9b..71a8236491df 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -60,7 +60,7 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - vcc_24v_reg: regulator@100 { + vcc_24v_reg: regulator-24v0 { compatible = "regulator-fixed"; regulator-name = "vcc_24v"; regulator-min-microvolt = <24000000>; @@ -68,7 +68,7 @@ regulator-always-on; }; - vdd_5v0_reg: regulator@101 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; vin-supply = <&vcc_24v_reg>; @@ -77,7 +77,7 @@ regulator-always-on; }; - vdd_3v3_reg: regulator@102 { + vdd_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; vin-supply = <&vcc_24v_reg>; @@ -86,7 +86,7 @@ regulator-always-on; }; - vdd_1v8_reg: regulator@103 { + vdd_1v8_reg: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd_1v8"; vin-supply = <&vdd_3v3_reg>; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index ffeae5da22e7..ca7adeb1fdd9 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -828,7 +828,7 @@ ddc-i2c-bus = <&lvds_ddc>; }; - vdd_5v0_reg: regulator@0 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -836,7 +836,7 @@ regulator-always-on; }; - regulator@1 { + regulator-1v5 { compatible = "regulator-fixed"; regulator-name = "vdd_1v5"; regulator-min-microvolt = <1500000>; @@ -844,7 +844,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - regulator@2 { + regulator-1v2 { compatible = "regulator-fixed"; regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; @@ -853,7 +853,7 @@ enable-active-high; }; - vbus_reg: regulator@3 { + vbus_reg: regulator-vbus { compatible = "regulator-fixed"; regulator-name = "vdd_vbus_wup1"; regulator-min-microvolt = <5000000>; @@ -864,7 +864,7 @@ regulator-boot-on; }; - vdd_pnl_reg: regulator@4 { + vdd_pnl_reg: regulator-pnl { compatible = "regulator-fixed"; regulator-name = "vdd_pnl"; regulator-min-microvolt = <2800000>; @@ -873,7 +873,7 @@ enable-active-high; }; - vdd_bl_reg: regulator@5 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <2800000>; @@ -882,7 +882,7 @@ enable-active-high; }; - vdd_hdmi: regulator@6 { + vdd_hdmi: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "VDDIO_HDMI"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index d5f1a46da0bc..2ad56f84bb62 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -508,7 +508,7 @@ #clock-cells = <0>; }; - pci_vdd_reg: regulator@1 { + pci_vdd_reg: regulator-1v05 { compatible = "regulator-fixed"; regulator-name = "vdd_1v05"; regulator-min-microvolt = <1050000>; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 10ff09d86efa..4f41c74384b2 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -69,7 +69,7 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - vcc_24v_reg: regulator@100 { + vcc_24v_reg: regulator-24v { compatible = "regulator-fixed"; regulator-name = "vcc_24v"; regulator-min-microvolt = <24000000>; @@ -77,7 +77,7 @@ regulator-always-on; }; - vdd_5v0_reg: regulator@101 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; vin-supply = <&vcc_24v_reg>; @@ -86,7 +86,7 @@ regulator-always-on; }; - vdd_3v3_reg: regulator@102 { + vdd_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; vin-supply = <&vcc_24v_reg>; @@ -95,7 +95,7 @@ regulator-always-on; }; - vdd_1v8_reg: regulator@103 { + vdd_1v8_reg: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd_1v8"; vin-supply = <&vdd_3v3_reg>; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 49c3b3bfac51..dd05e2c87c29 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -402,7 +402,7 @@ gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; - hdmi_vdd_reg: regulator@0 { + hdmi_vdd_reg: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "avdd_hdmi"; regulator-min-microvolt = <3300000>; @@ -410,7 +410,7 @@ regulator-always-on; }; - hdmi_pll_reg: regulator@1 { + hdmi_pll_reg: regulator-hdmipll { compatible = "regulator-fixed"; regulator-name = "avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; @@ -418,7 +418,7 @@ regulator-always-on; }; - vbus_reg: regulator@2 { + vbus_reg: regulator-vbus { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -429,7 +429,7 @@ regulator-boot-on; }; - pci_clk_reg: regulator@3 { + pci_clk_reg: regulator-pciclk { compatible = "regulator-fixed"; regulator-name = "pci_clk"; regulator-min-microvolt = <3300000>; @@ -437,7 +437,7 @@ regulator-always-on; }; - pci_vdd_reg: regulator@4 { + pci_vdd_reg: regulator-pcivdd { compatible = "regulator-fixed"; regulator-name = "pci_vdd"; regulator-min-microvolt = <1050000>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index ef97457f1334..4284054ebd2c 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -647,7 +647,7 @@ ddc-i2c-bus = <&lvds_ddc>; }; - vdd_5v0_reg: regulator@0 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -655,7 +655,7 @@ regulator-always-on; }; - regulator@1 { + regulator-1v5 { compatible = "regulator-fixed"; regulator-name = "vdd_1v5"; regulator-min-microvolt = <1500000>; @@ -663,7 +663,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - regulator@2 { + regulator-1v2 { compatible = "regulator-fixed"; regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; @@ -672,7 +672,7 @@ enable-active-high; }; - vdd_pnl_reg: regulator@3 { + vdd_pnl_reg: regulator-pnl { compatible = "regulator-fixed"; regulator-name = "vdd_pnl"; regulator-min-microvolt = <2800000>; @@ -681,7 +681,7 @@ enable-active-high; }; - vdd_bl_reg: regulator@4 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <2800000>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 72159eb55a3d..e6aed19a5f3b 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1207,7 +1207,7 @@ }; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -1216,7 +1216,7 @@ regulator-boot-on; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; regulator-min-microvolt = <3300000>; @@ -1226,7 +1226,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_pnl: regulator@2 { + vdd_pnl: regulator-panel { compatible = "regulator-fixed"; regulator-name = "vdd_panel"; regulator-min-microvolt = <3300000>; @@ -1237,7 +1237,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vcc_3v3_ts: regulator@3 { + vcc_3v3_ts: regulator-ts { compatible = "regulator-fixed"; regulator-name = "ldo_s-1167_3v3"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi index 53966fa4eef2..cd28e8782f7d 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -166,12 +166,12 @@ }; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-3v3 { gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; enable-active-high; }; - regulator@4 { + regulator-usb { compatible = "regulator-fixed"; regulator-name = "avdd_usb"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi index 9365ae607239..ee4a3f482769 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi @@ -143,7 +143,7 @@ }; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-3v3 { gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; enable-active-high; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 91ecca0be5a2..7c2b70b13cc4 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1986,7 +1986,7 @@ }; }; - vdd_5v_in_reg: regulator@0 { + vdd_5v_in_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v_in"; regulator-min-microvolt = <5000000>; @@ -1994,7 +1994,7 @@ regulator-always-on; }; - chargepump_5v_reg: regulator@1 { + chargepump_5v_reg: regulator-chargepump { compatible = "regulator-fixed"; regulator-name = "chargepump_5v"; regulator-min-microvolt = <5000000>; @@ -2005,7 +2005,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - ddr_reg: regulator@2 { + ddr_reg: regulator-ddr { compatible = "regulator-fixed"; regulator-name = "vdd_ddr"; regulator-min-microvolt = <1500000>; @@ -2017,7 +2017,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - vdd_5v_sata_reg: regulator@3 { + vdd_5v_sata_reg: regulator-sata { compatible = "regulator-fixed"; regulator-name = "vdd_5v_sata"; regulator-min-microvolt = <5000000>; @@ -2029,7 +2029,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - usb1_vbus_reg: regulator@4 { + usb1_vbus_reg: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -2040,7 +2040,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - usb3_vbus_reg: regulator@5 { + usb3_vbus_reg: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "usb3_vbus"; regulator-min-microvolt = <5000000>; @@ -2051,7 +2051,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - sys_3v3_reg: regulator@6 { + sys_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "sys_3v3,vdd_3v3_alw"; regulator-min-microvolt = <3300000>; @@ -2063,7 +2063,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - sys_3v3_pexs_reg: regulator@7 { + sys_3v3_pexs_reg: regulator-pexs { compatible = "regulator-fixed"; regulator-name = "sys_3v3_pexs"; regulator-min-microvolt = <3300000>; @@ -2075,7 +2075,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_5v0_hdmi: regulator@8 { + vdd_5v0_hdmi: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "+VDD_5V_HDMI"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts index 4899e05a0d9c..247185314f46 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -16,7 +16,7 @@ keep-power-in-suspend; }; - ddr_reg: regulator@100 { + ddr_reg: regulator-ddr { compatible = "regulator-fixed"; regulator-name = "vdd_ddr"; regulator-min-microvolt = <1500000>; @@ -27,7 +27,7 @@ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; }; - sys_3v3_reg: regulator@101 { + sys_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "sys_3v3"; regulator-min-microvolt = <3300000>; @@ -38,7 +38,7 @@ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; }; - usb1_vbus_reg: regulator@102 { + usb1_vbus_reg: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -49,7 +49,7 @@ vin-supply = <&vdd_5v0_reg>; }; - usb3_vbus_reg: regulator@103 { + usb3_vbus_reg: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "usb3_vbus"; regulator-min-microvolt = <5000000>; @@ -60,7 +60,7 @@ vin-supply = <&vdd_5v0_reg>; }; - vdd_5v0_reg: regulator@104 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "5v0"; regulator-min-microvolt = <5000000>; @@ -69,7 +69,7 @@ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; }; - vdd_bl_reg: regulator@105 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index a11028b8b67b..2911f08863a0 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -16,7 +16,7 @@ keep-power-in-suspend; }; - ddr_reg: regulator@100 { + ddr_reg: regulator-ddr { compatible = "regulator-fixed"; regulator-name = "ddr"; regulator-min-microvolt = <1500000>; @@ -27,7 +27,7 @@ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; }; - sys_3v3_reg: regulator@101 { + sys_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "sys_3v3"; regulator-min-microvolt = <3300000>; @@ -38,7 +38,7 @@ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; }; - usb1_vbus_reg: regulator@102 { + usb1_vbus_reg: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -49,7 +49,7 @@ vin-supply = <&vdd_5v0_reg>; }; - usb3_vbus_reg: regulator@103 { + usb3_vbus_reg: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "usb3_vbus"; regulator-min-microvolt = <5000000>; @@ -60,7 +60,7 @@ vin-supply = <&vdd_5v0_reg>; }; - vdd_5v0_reg: regulator@104 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "5v0"; regulator-min-microvolt = <5000000>; @@ -69,7 +69,7 @@ gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; }; - vdd_bl_reg: regulator@105 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <5000000>; @@ -80,7 +80,7 @@ gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; }; - vdd_bl2_reg: regulator@106 { + vdd_bl2_reg: regulator-bl2 { compatible = "regulator-fixed"; regulator-name = "vdd_bl2"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 6074885280fc..886d4bb2d82c 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -476,7 +476,7 @@ backlight = <&backlight>; }; - vdd_ac_bat_reg: regulator@0 { + vdd_ac_bat_reg: regulator-acbat { compatible = "regulator-fixed"; regulator-name = "vdd_ac_bat"; regulator-min-microvolt = <5000000>; @@ -484,7 +484,7 @@ regulator-always-on; }; - cam_1v8_reg: regulator@1 { + cam_1v8_reg: regulator-cam { compatible = "regulator-fixed"; regulator-name = "cam_1v8"; regulator-min-microvolt = <1800000>; @@ -494,7 +494,7 @@ vin-supply = <&vio_reg>; }; - cp_5v_reg: regulator@2 { + cp_5v_reg: regulator-5v0cp { compatible = "regulator-fixed"; regulator-name = "cp_5v"; regulator-min-microvolt = <5000000>; @@ -505,7 +505,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - emmc_3v3_reg: regulator@3 { + emmc_3v3_reg: regulator-emmc { compatible = "regulator-fixed"; regulator-name = "emmc_3v3"; regulator-min-microvolt = <3300000>; @@ -517,7 +517,7 @@ vin-supply = <&sys_3v3_reg>; }; - modem_3v3_reg: regulator@4 { + modem_3v3_reg: regulator-modem { compatible = "regulator-fixed"; regulator-name = "modem_3v3"; regulator-min-microvolt = <3300000>; @@ -526,7 +526,7 @@ gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; }; - pex_hvdd_3v3_reg: regulator@5 { + pex_hvdd_3v3_reg: regulator-pex { compatible = "regulator-fixed"; regulator-name = "pex_hvdd_3v3"; regulator-min-microvolt = <3300000>; @@ -536,7 +536,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_cam1_ldo_reg: regulator@6 { + vdd_cam1_ldo_reg: regulator-cam1 { compatible = "regulator-fixed"; regulator-name = "vdd_cam1_ldo"; regulator-min-microvolt = <2800000>; @@ -546,7 +546,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_cam2_ldo_reg: regulator@7 { + vdd_cam2_ldo_reg: regulator-cam2 { compatible = "regulator-fixed"; regulator-name = "vdd_cam2_ldo"; regulator-min-microvolt = <2800000>; @@ -556,7 +556,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_cam3_ldo_reg: regulator@8 { + vdd_cam3_ldo_reg: regulator-cam3 { compatible = "regulator-fixed"; regulator-name = "vdd_cam3_ldo"; regulator-min-microvolt = <3300000>; @@ -566,7 +566,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_com_reg: regulator@9 { + vdd_com_reg: regulator-com { compatible = "regulator-fixed"; regulator-name = "vdd_com"; regulator-min-microvolt = <3300000>; @@ -578,7 +578,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_fuse_3v3_reg: regulator@10 { + vdd_fuse_3v3_reg: regulator-fuse { compatible = "regulator-fixed"; regulator-name = "vdd_fuse_3v3"; regulator-min-microvolt = <3300000>; @@ -588,7 +588,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_pnl1_reg: regulator@11 { + vdd_pnl1_reg: regulator-pnl1 { compatible = "regulator-fixed"; regulator-name = "vdd_pnl1"; regulator-min-microvolt = <3300000>; @@ -600,7 +600,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_vid_reg: regulator@12 { + vdd_vid_reg: regulator-vid { compatible = "regulator-fixed"; regulator-name = "vddio_vid"; regulator-min-microvolt = <5000000>; From f8d5db7e27b389825b7c61255f14f81d6104061b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 10:55:06 +0100 Subject: [PATCH 350/574] ARM: tegra: Fix compatible string for Tegra114+ timer The TKE (time-keeping engine) found on Tegra114 and later is no longer backwards compatible with the version found on Tegra20, so update the compatible string list accordingly. Note that while the hardware block is strictly backwards-compatible, an architectural timer exists on those newer SoCs that is more reliable, so that should always be preferred. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 2 +- arch/arm/boot/dts/tegra124.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 546272e396b4..328425dba023 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -164,7 +164,7 @@ }; timer@60005000 { - compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; reg = <0x60005000 0x400>; interrupts = , , diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 63a64171b422..f4ac0c327c2e 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -259,7 +259,7 @@ }; timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; reg = <0x0 0x60005000 0x0 0x400>; interrupts = , , From 82d03bec4e97f01d982b1663d438c55b100de7e3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 10:56:21 +0100 Subject: [PATCH 351/574] ARM: tegra: Add #reset-cells for Tegra114 MC The Tegra memory controller provides reset controls for hotflush reset, so the #reset-cells property must be specified. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 328425dba023..ce7410ee08b8 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -542,6 +542,7 @@ interrupts = ; + #reset-cells = <1>; #iommu-cells = <1>; }; From 63658cbc66a27b5fcb683623d299e59cc2771964 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 10:59:24 +0100 Subject: [PATCH 352/574] ARM: tegra: Rename GPIO hog nodes to match schema GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to the DT schema. Rename all such nodes to allow validation to pass. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 4 ++-- arch/arm/boot/dts/tegra124-apalis.dtsi | 4 ++-- arch/arm/boot/dts/tegra20-colibri.dtsi | 6 +++--- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 2 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 +- 8 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index 28c29b6813a7..3209554ec7e6 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -246,7 +246,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + pex-perst-n-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index f3afde410615..814257c79bf1 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -248,7 +248,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + pex-perst-n-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index cde9ae8fa04b..4ba4d5229fcf 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -2055,7 +2055,7 @@ &gpio { /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n { + lan-reset-n-hog { gpio-hog; gpios = ; output-high; @@ -2063,7 +2063,7 @@ }; /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl { + reset-moci-ctrl-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index a46d9ba9bb7a..3760744cc1b0 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -2047,7 +2047,7 @@ &gpio { /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n { + lan-reset-n-hog { gpio-hog; gpios = ; output-high; @@ -2055,7 +2055,7 @@ }; /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl { + reset-moci-ctrl-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 585a5b441cf6..80e439003a6d 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -747,7 +747,7 @@ }; &gpio { - lan-reset-n { + lan-reset-n-hog { gpio-hog; gpios = ; output-high; @@ -755,7 +755,7 @@ }; /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ - npwe { + npwe-hog { gpio-hog; gpios = ; output-high; @@ -763,7 +763,7 @@ }; /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ - rdnwr { + rdnwr-hog { gpio-hog; gpios = ; output-low; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 9f653ef41da4..93b83b3c5655 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -239,7 +239,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + pex-perst-n-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index 86e138e8c7f0..fbfa75e53f32 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -257,7 +257,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + pex-perst-n-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 413e35215804..fcd3d26bef2d 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -1044,7 +1044,7 @@ }; &gpio { - lan-reset-n { + lan-reset-n-hog { gpio-hog; gpios = ; output-high; From 1b5bad01abdcefd1bbf58590d5a78e15741f6a34 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:03:12 +0100 Subject: [PATCH 353/574] ARM: tegra: Rename GPU node on Tegra124 In order to be able to pass DT schema validation, change the GPU nodes' unit-address to the standard notation. Previously this was using a "0," prefix that originated from a time when the top-level device tree node contained #address-cells = <2>. Note that this technically breaks backwards-compatibility with certain older versions of the U-Boot bootloader because early versions used a hard-coded DT path lookup to find the GPU node and perform some fixups on it. However, this was changed to a compatible string based lookup in April 2016, so it's reasonable to expect people to update U-Boot on the systems that they want to use this updated kernel DTB with. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +- arch/arm/boot/dts/tegra124-venice2.dts | 2 +- arch/arm/boot/dts/tegra124.dtsi | 7 +------ 6 files changed, 6 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 4ba4d5229fcf..f00ef4d08fd4 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -57,7 +57,7 @@ }; }; - gpu@0,57000000 { + gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 3760744cc1b0..e6d25813b416 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -56,7 +56,7 @@ }; }; - gpu@0,57000000 { + gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index c3edb332187a..f42191f22c19 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -72,7 +72,7 @@ status = "okay"; }; - gpu@0,57000000 { + gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 2d045d1a9bcf..998b129321f8 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -61,7 +61,7 @@ }; }; - gpu@0,57000000 { + gpu@57000000 { status = "okay"; vdd-supply = <&vdd_gpu>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 5f17a2f7d270..7985d1cbc1c0 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -51,7 +51,7 @@ }; }; - gpu@0,57000000 { + gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index f4ac0c327c2e..d0ec1a30ff54 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -223,12 +223,7 @@ interrupt-parent = <&gic>; }; - /* - * Please keep the following 0, notation in place as a former mainline - * U-Boot version was looking for that particular notation in order to - * perform required fix-ups on that GPU node. - */ - gpu@0,57000000 { + gpu@57000000 { compatible = "nvidia,gk20a"; reg = <0x0 0x57000000 0x0 0x01000000>, <0x0 0x58000000 0x0 0x01000000>; From 9ab9ecd83a3ecf269e8cda08233652203347f5f1 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:11:33 +0100 Subject: [PATCH 354/574] ARM: tegra: Drop reg-shift for Tegra HS UART When the Tegra High-Speed UART is used instead of the regular UART, the reg-shift property is implied from the compatible string and should not be explicitly listed. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 3 +++ arch/arm/boot/dts/tegra124-apalis.dtsi | 3 +++ arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 ++ arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 2 ++ arch/arm/boot/dts/tegra20-colibri.dtsi | 2 ++ arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 3 +++ arch/arm/boot/dts/tegra30-apalis.dtsi | 3 +++ arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 2 ++ arch/arm/boot/dts/tegra30-cardhu.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 2 ++ arch/arm/boot/dts/tegra30-ouya.dts | 3 ++- 11 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index f00ef4d08fd4..b952b272afc0 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1539,14 +1539,17 @@ serial@70006040 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c700 { diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index e6d25813b416..2b1bb4382b42 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1532,14 +1532,17 @@ serial@70006040 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c400 { diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index f42191f22c19..e805cb2e20f4 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1389,6 +1389,7 @@ */ serial@70006000 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; }; @@ -1401,6 +1402,7 @@ */ serial@70006040 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 2e6340e92fe1..f973df0158c9 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -382,11 +382,13 @@ uartb: serial@70006040 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; /* GPS BCM4751 */ }; uartc: serial@70006200 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; status = "okay"; /* Azurewave AW-NH665 BCM4329B1 */ diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 80e439003a6d..6fed5706da79 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -428,10 +428,12 @@ serial@70006040 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; }; nand-controller@70008000 { diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 6a3a72f81c44..6fe775b2b38d 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -829,14 +829,17 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c700 { diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index b2ac51fb15b1..7df2841690d7 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -820,14 +820,17 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c700 { diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index e6aed19a5f3b..ab33ceb63fff 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -804,11 +804,13 @@ uartb: serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; /* GPS BCM4751 */ }; uartc: serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; nvidia,adjust-baud-rates = <0 9600 100>, diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 886d4bb2d82c..12e185846dcb 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -175,6 +175,7 @@ serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index fcd3d26bef2d..b585831e3212 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -701,10 +701,12 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c700 { diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 4259871b76c9..2a6dc423b9fc 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -82,8 +82,9 @@ }; uartc: serial@70006200 { - status = "okay"; compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; nvidia,adjust-baud-rates = <0 9600 100>, <9600 115200 200>, From 272c5c3a3792366dfd441182f1bd94aa4b6e346f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:14:33 +0100 Subject: [PATCH 355/574] ARM: tegra: Rename thermal zone nodes The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 6 +++--- arch/arm/boot/dts/tegra124-apalis.dtsi | 6 +++--- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 +++--- arch/arm/boot/dts/tegra124.dtsi | 8 ++++---- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index b952b272afc0..f5440ae14cb4 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -2024,7 +2024,7 @@ }; thermal-zones { - cpu { + cpu-thermal { trips { cpu-shutdown-trip { temperature = <101000>; @@ -2034,7 +2034,7 @@ }; }; - mem { + mem-thermal { trips { mem-shutdown-trip { temperature = <101000>; @@ -2044,7 +2044,7 @@ }; }; - gpu { + gpu-thermal { trips { gpu-shutdown-trip { temperature = <101000>; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 2b1bb4382b42..1d83f2e254c5 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -2016,7 +2016,7 @@ }; thermal-zones { - cpu { + cpu-thermal { trips { cpu-shutdown-trip { temperature = <101000>; @@ -2026,7 +2026,7 @@ }; }; - mem { + mem-thermal { trips { mem-shutdown-trip { temperature = <101000>; @@ -2036,7 +2036,7 @@ }; }; - gpu { + gpu-thermal { trips { gpu-shutdown-trip { temperature = <101000>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index e805cb2e20f4..28b889e4e33b 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -2047,7 +2047,7 @@ }; thermal-zones { - cpu { + cpu-thermal { trips { cpu-shutdown-trip { temperature = <101000>; @@ -2057,7 +2057,7 @@ }; }; - mem { + mem-thermal { trips { mem-shutdown-trip { temperature = <101000>; @@ -2067,7 +2067,7 @@ }; }; - gpu { + gpu-thermal { trips { gpu-shutdown-trip { temperature = <101000>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index d0ec1a30ff54..752a28268024 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1242,7 +1242,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -1270,7 +1270,7 @@ }; }; - mem { + mem-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -1298,7 +1298,7 @@ }; }; - gpu { + gpu-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -1326,7 +1326,7 @@ }; }; - pllx { + pllx-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; From c6d4a8977598c022355521fcf29d706dd95c7a83 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:41 +0300 Subject: [PATCH 356/574] ARM: tegra: Rename CPU and EMC OPP table device-tree nodes OPP table name now should start with "opp-table" and OPP entries shouldn't contain commas and @ signs in accordance to the new schema requirement. Reorganize CPU and EMC OPP table device-tree nodes. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 4 +- .../arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 4 +- arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 8 +- .../arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 8 +- .../boot/dts/tegra124-peripherals-opp.dtsi | 140 ++++++++--------- .../boot/dts/tegra20-acer-a500-picasso.dts | 4 +- arch/arm/boot/dts/tegra20-colibri.dtsi | 2 +- .../boot/dts/tegra20-cpu-opp-microvolt.dtsi | 82 +++++----- arch/arm/boot/dts/tegra20-cpu-opp.dtsi | 82 +++++----- arch/arm/boot/dts/tegra20-paz00.dts | 2 +- .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 36 ++--- ...30-asus-nexus7-grouper-memory-timings.dtsi | 12 +- .../boot/dts/tegra30-cpu-opp-microvolt.dtsi | 144 +++++++++--------- arch/arm/boot/dts/tegra30-cpu-opp.dtsi | 144 +++++++++--------- arch/arm/boot/dts/tegra30-ouya.dts | 4 +- .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 128 ++++++++-------- 16 files changed, 402 insertions(+), 402 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index 25c1006a2c5a..7143c6b2ec3e 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -1477,9 +1477,9 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@1200000000,1100; + /delete-node/ opp-1200000000-1100; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@1200000000; + /delete-node/ opp-1200000000; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index 3ad2e02c7d3a..79e776db5f37 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -2432,9 +2432,9 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@1200000000,1100; + /delete-node/ opp-1200000000-1100; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@1200000000; + /delete-node/ opp-1200000000; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index 49a6d6afc633..31b2e26c69d4 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -6681,11 +6681,11 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@924000000,1100; - /delete-node/ opp@1200000000,1100; + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@924000000; - /delete-node/ opp@1200000000; + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index 7360a1f35389..2ce1b12be44d 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -2058,11 +2058,11 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@924000000,1100; - /delete-node/ opp@1200000000,1100; + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@924000000; - /delete-node/ opp@1200000000; + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; }; diff --git a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi index 781ac8601030..b262c1289da5 100644 --- a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi @@ -1,421 +1,421 @@ // SPDX-License-Identifier: GPL-2.0 / { - emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; - opp@12750000,800 { + opp-12750000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0003>; }; - opp@12750000,950 { + opp-12750000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0008>; }; - opp@12750000,1050 { + opp-12750000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0010>; }; - opp@12750000,1110 { + opp-12750000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0004>; }; - opp@20400000,800 { + opp-20400000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x0003>; }; - opp@20400000,950 { + opp-20400000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x0008>; }; - opp@20400000,1050 { + opp-20400000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x0010>; }; - opp@20400000,1110 { + opp-20400000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x0004>; }; - opp@40800000,800 { + opp-40800000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x0003>; }; - opp@40800000,950 { + opp-40800000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x0008>; }; - opp@40800000,1050 { + opp-40800000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x0010>; }; - opp@40800000,1110 { + opp-40800000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x0004>; }; - opp@68000000,800 { + opp-68000000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x0003>; }; - opp@68000000,950 { + opp-68000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x0008>; }; - opp@68000000,1050 { + opp-68000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x0010>; }; - opp@68000000,1110 { + opp-68000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x0004>; }; - opp@102000000,800 { + opp-102000000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0003>; }; - opp@102000000,950 { + opp-102000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0008>; }; - opp@102000000,1050 { + opp-102000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0010>; }; - opp@102000000,1110 { + opp-102000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0004>; }; - opp@204000000,800 { + opp-204000000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0003>; opp-suspend; }; - opp@204000000,950 { + opp-204000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0008>; opp-suspend; }; - opp@204000000,1050 { + opp-204000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0010>; opp-suspend; }; - opp@204000000,1110 { + opp-204000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0004>; opp-suspend; }; - opp@264000000,800 { + opp-264000000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x0003>; }; - opp@264000000,950 { + opp-264000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x0008>; }; - opp@264000000,1050 { + opp-264000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x0010>; }; - opp@264000000,1110 { + opp-264000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x0004>; }; - opp@300000000,850 { + opp-300000000-850 { opp-microvolt = <850000 850000 1150000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x0003>; }; - opp@300000000,950 { + opp-300000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x0008>; }; - opp@300000000,1050 { + opp-300000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x0010>; }; - opp@300000000,1110 { + opp-300000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x0004>; }; - opp@348000000,850 { + opp-348000000-850 { opp-microvolt = <850000 850000 1150000>; opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x0003>; }; - opp@348000000,950 { + opp-348000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x0008>; }; - opp@348000000,1050 { + opp-348000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x0010>; }; - opp@348000000,1110 { + opp-348000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x0004>; }; - opp@396000000,950 { + opp-396000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x0008>; }; - opp@396000000,1000 { + opp-396000000-1000 { opp-microvolt = <1000000 1000000 1150000>; opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x0003>; }; - opp@396000000,1050 { + opp-396000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x0010>; }; - opp@396000000,1110 { + opp-396000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x0004>; }; - opp@528000000,950 { + opp-528000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x0008>; }; - opp@528000000,1000 { + opp-528000000-1000 { opp-microvolt = <1000000 1000000 1150000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x0003>; }; - opp@528000000,1050 { + opp-528000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x0010>; }; - opp@528000000,1110 { + opp-528000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x0004>; }; - opp@600000000,950 { + opp-600000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x0008>; }; - opp@600000000,1000 { + opp-600000000-1000 { opp-microvolt = <1000000 1000000 1150000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x0003>; }; - opp@600000000,1050 { + opp-600000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x0010>; }; - opp@600000000,1110 { + opp-600000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x0004>; }; - opp@792000000,1000 { + opp-792000000-1000 { opp-microvolt = <1000000 1000000 1150000>; opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x000B>; }; - opp@792000000,1050 { + opp-792000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x0010>; }; - opp@792000000,1110 { + opp-792000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x0004>; }; - opp@924000000,1100 { + opp-924000000-1100 { opp-microvolt = <1100000 1100000 1150000>; opp-hz = /bits/ 64 <924000000>; opp-supported-hw = <0x0013>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { opp-microvolt = <1100000 1100000 1150000>; opp-hz = /bits/ 64 <1200000000>; opp-supported-hw = <0x0003>; }; }; - emc_bw_dfs_opp_table: emc-bandwidth-opp-table { + emc_bw_dfs_opp_table: opp-table-actmon { compatible = "operating-points-v2"; - opp@12750000 { + opp-12750000 { opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <204000>; }; - opp@20400000 { + opp-20400000 { opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <326400>; }; - opp@40800000 { + opp-40800000 { opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <652800>; }; - opp@68000000 { + opp-68000000 { opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <1088000>; }; - opp@102000000 { + opp-102000000 { opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <1632000>; }; - opp@204000000 { + opp-204000000 { opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <3264000>; opp-suspend; }; - opp@264000000 { + opp-264000000 { opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <4224000>; }; - opp@300000000 { + opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <4800000>; }; - opp@348000000 { + opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <5568000>; }; - opp@396000000 { + opp-396000000 { opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <6336000>; }; - opp@528000000 { + opp-528000000 { opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <8448000>; }; - opp@600000000 { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <9600000>; }; - opp@792000000 { + opp-792000000 { opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <12672000>; }; - opp@924000000 { + opp-924000000 { opp-hz = /bits/ 64 <924000000>; opp-supported-hw = <0x0013>; opp-peak-kBps = <14784000>; }; - opp@1200000000 { + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-supported-hw = <0x0003>; opp-peak-kBps = <19200000>; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index f973df0158c9..2d5fead9de6b 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -1508,6 +1508,6 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@666000000; - /delete-node/ opp@760000000; + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 6fed5706da79..e36b258c82df 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -745,7 +745,7 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@760000000; + /delete-node/ opp-760000000; }; &gpio { diff --git a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi index 6f3e8c5fc5f0..7330c1b13d93 100644 --- a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi +++ b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi @@ -1,164 +1,164 @@ // SPDX-License-Identifier: GPL-2.0 / { - cpu0_opp_table: cpu_opp_table0 { - opp@216000000,750 { + cpu0_opp_table: opp-table-cpu0 { + opp-216000000-750 { opp-microvolt = <750000 750000 1125000>; }; - opp@216000000,800 { + opp-216000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@312000000,750 { + opp-312000000-750 { opp-microvolt = <750000 750000 1125000>; }; - opp@312000000,800 { + opp-312000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000,750 { + opp-456000000-750 { opp-microvolt = <750000 750000 1125000>; }; - opp@456000000,800 { + opp-456000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000,825 { + opp-456000000-825 { opp-microvolt = <825000 825000 1125000>; }; - opp@608000000,750 { + opp-608000000-750 { opp-microvolt = <750000 750000 1125000>; }; - opp@608000000,800 { + opp-608000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@608000000,825 { + opp-608000000-825 { opp-microvolt = <825000 825000 1125000>; }; - opp@608000000,850 { + opp-608000000-850 { opp-microvolt = <850000 850000 1125000>; }; - opp@608000000,900 { + opp-608000000-900 { opp-microvolt = <900000 900000 1125000>; }; - opp@760000000,775 { + opp-760000000-775 { opp-microvolt = <775000 775000 1125000>; }; - opp@760000000,800 { + opp-760000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@760000000,850 { + opp-760000000-850 { opp-microvolt = <850000 850000 1125000>; }; - opp@760000000,875 { + opp-760000000-875 { opp-microvolt = <875000 875000 1125000>; }; - opp@760000000,900 { + opp-760000000-900 { opp-microvolt = <900000 900000 1125000>; }; - opp@760000000,975 { + opp-760000000-975 { opp-microvolt = <975000 975000 1125000>; }; - opp@816000000,800 { + opp-816000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@816000000,850 { + opp-816000000-850 { opp-microvolt = <850000 850000 1125000>; }; - opp@816000000,875 { + opp-816000000-875 { opp-microvolt = <875000 875000 1125000>; }; - opp@816000000,950 { + opp-816000000-950 { opp-microvolt = <950000 950000 1125000>; }; - opp@816000000,1000 { + opp-816000000-1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@912000000,850 { + opp-912000000-850 { opp-microvolt = <850000 850000 1125000>; }; - opp@912000000,900 { + opp-912000000-900 { opp-microvolt = <900000 900000 1125000>; }; - opp@912000000,925 { + opp-912000000-925 { opp-microvolt = <925000 925000 1125000>; }; - opp@912000000,950 { + opp-912000000-950 { opp-microvolt = <950000 950000 1125000>; }; - opp@912000000,1000 { + opp-912000000-1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@912000000,1050 { + opp-912000000-1050 { opp-microvolt = <1050000 1050000 1125000>; }; - opp@1000000000,875 { + opp-1000000000-875 { opp-microvolt = <875000 875000 1125000>; }; - opp@1000000000,900 { + opp-1000000000-900 { opp-microvolt = <900000 900000 1125000>; }; - opp@1000000000,950 { + opp-1000000000-950 { opp-microvolt = <950000 950000 1125000>; }; - opp@1000000000,975 { + opp-1000000000-975 { opp-microvolt = <975000 975000 1125000>; }; - opp@1000000000,1000 { + opp-1000000000-1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@1000000000,1025 { + opp-1000000000-1025 { opp-microvolt = <1025000 1025000 1125000>; }; - opp@1000000000,1100 { + opp-1000000000-1100 { opp-microvolt = <1100000 1100000 1125000>; }; - opp@1200000000,1000 { + opp-1200000000-1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@1200000000,1050 { + opp-1200000000-1050 { opp-microvolt = <1050000 1050000 1125000>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { opp-microvolt = <1100000 1100000 1125000>; }; - opp@1200000000,1125 { + opp-1200000000-1125 { opp-microvolt = <1125000 1125000 1125000>; }; }; diff --git a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi index 135de316383b..47c8e78ca958 100644 --- a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi @@ -1,250 +1,250 @@ // SPDX-License-Identifier: GPL-2.0 / { - cpu0_opp_table: cpu_opp_table0 { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; - opp@216000000,750 { + opp-216000000-750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0003>; opp-hz = /bits/ 64 <216000000>; opp-suspend; }; - opp@216000000,800 { + opp-216000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0004>; opp-hz = /bits/ 64 <216000000>; opp-suspend; }; - opp@312000000,750 { + opp-312000000-750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0003>; opp-hz = /bits/ 64 <312000000>; }; - opp@312000000,800 { + opp-312000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0004>; opp-hz = /bits/ 64 <312000000>; }; - opp@456000000,750 { + opp-456000000-750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0C 0x0003>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000,800 { + opp-456000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>, <0x04 0x0004>, <0x08 0x0004>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000,825 { + opp-456000000-825 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <456000000>; }; - opp@608000000,750 { + opp-608000000-750 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0003>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,800 { + opp-608000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0006>, <0x08 0x0004>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,825 { + opp-608000000-825 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,850 { + opp-608000000-850 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,900 { + opp-608000000-900 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <608000000>; }; - opp@760000000,775 { + opp-760000000-775 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0003>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,800 { + opp-760000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,850 { + opp-760000000-850 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0006>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,875 { + opp-760000000-875 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>, <0x02 0x0002>, <0x01 0x0004>, <0x02 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,900 { + opp-760000000-900 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,975 { + opp-760000000-975 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <760000000>; }; - opp@816000000,800 { + opp-816000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,850 { + opp-816000000-850 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,875 { + opp-816000000-875 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0005>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,950 { + opp-816000000-950 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,1000 { + opp-816000000-1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <816000000>; }; - opp@912000000,850 { + opp-912000000-850 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,900 { + opp-912000000-900 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,925 { + opp-912000000-925 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,950 { + opp-912000000-950 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>, <0x04 0x0004>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,1000 { + opp-912000000-1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,1050 { + opp-912000000-1050 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <912000000>; }; - opp@1000000000,875 { + opp-1000000000-875 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,900 { + opp-1000000000-900 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,950 { + opp-1000000000-950 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,975 { + opp-1000000000-975 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1000 { + opp-1000000000-1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1025 { + opp-1000000000-1025 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1100 { + opp-1000000000-1100 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1200000000,1000 { + opp-1200000000-1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1050 { + opp-1200000000-1050 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1125 { + opp-1200000000-1125 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0004>; opp-hz = /bits/ 64 <1200000000>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 46d81d703548..1fd5a7458c7a 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -705,5 +705,5 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@760000000; + /delete-node/ opp-760000000; }; diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi index ef3ad2e5f270..d4d0a5fa7015 100644 --- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi @@ -1,107 +1,107 @@ // SPDX-License-Identifier: GPL-2.0 / { - emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; - opp@36000000 { + opp-36000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <36000000>; opp-supported-hw = <0x000F>; }; - opp@47500000 { + opp-47500000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <47500000>; opp-supported-hw = <0x000F>; }; - opp@50000000 { + opp-50000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <50000000>; opp-supported-hw = <0x000F>; }; - opp@54000000 { + opp-54000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x000F>; }; - opp@57000000 { + opp-57000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <57000000>; opp-supported-hw = <0x000F>; }; - opp@100000000 { + opp-100000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <100000000>; opp-supported-hw = <0x000F>; }; - opp@108000000 { + opp-108000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x000F>; }; - opp@126666000 { + opp-126666000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <126666000>; opp-supported-hw = <0x000F>; }; - opp@150000000 { + opp-150000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <150000000>; opp-supported-hw = <0x000F>; }; - opp@190000000 { + opp-190000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <190000000>; opp-supported-hw = <0x000F>; }; - opp@216000000 { + opp-216000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <216000000>; opp-supported-hw = <0x000F>; opp-suspend; }; - opp@300000000 { + opp-300000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x000F>; }; - opp@333000000 { + opp-333000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <333000000>; opp-supported-hw = <0x000F>; }; - opp@380000000 { + opp-380000000 { opp-microvolt = <1100000 1100000 1300000>; opp-hz = /bits/ 64 <380000000>; opp-supported-hw = <0x000F>; }; - opp@600000000 { + opp-600000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x000F>; }; - opp@666000000 { + opp-666000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <666000000>; opp-supported-hw = <0x000F>; }; - opp@760000000 { + opp-760000000 { opp-microvolt = <1300000 1300000 1300000>; opp-hz = /bits/ 64 <760000000>; opp-supported-hw = <0x000F>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi index bcff0997ee51..6c229e1d67e7 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi @@ -1565,13 +1565,13 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@750000000,1300; - /delete-node/ opp@800000000,1300; - /delete-node/ opp@900000000,1350; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@750000000; - /delete-node/ opp@800000000; - /delete-node/ opp@900000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; }; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi index 1be715d2a442..b8e0e9117021 100644 --- a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi +++ b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi @@ -1,288 +1,288 @@ // SPDX-License-Identifier: GPL-2.0 / { - cpu0_opp_table: cpu_opp_table0 { - opp@51000000,800 { + cpu0_opp_table: opp-table-cpu0 { + opp-51000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@51000000,850 { + opp-51000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@51000000,912 { + opp-51000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@102000000,800 { + opp-102000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@102000000,850 { + opp-102000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@102000000,912 { + opp-102000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@204000000,800 { + opp-204000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@204000000,850 { + opp-204000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@204000000,912 { + opp-204000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@312000000,850 { + opp-312000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@312000000,912 { + opp-312000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@340000000,800 { + opp-340000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@340000000,850 { + opp-340000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@370000000,800 { + opp-370000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@456000000,850 { + opp-456000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@456000000,912 { + opp-456000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@475000000,800 { + opp-475000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@475000000,850 { + opp-475000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@608000000,850 { + opp-608000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@608000000,912 { + opp-608000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@620000000,850 { + opp-620000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000,850 { + opp-640000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000,900 { + opp-640000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000,850 { + opp-760000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000,900 { + opp-760000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000,912 { + opp-760000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@760000000,975 { + opp-760000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@816000000,850 { + opp-816000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@816000000,912 { + opp-816000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@860000000,850 { + opp-860000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@860000000,900 { + opp-860000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000,975 { + opp-860000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000,1000 { + opp-860000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@910000000,900 { + opp-910000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1000000000,900 { + opp-1000000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1000000000,975 { + opp-1000000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000,1000 { + opp-1000000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1000000000,1025 { + opp-1000000000-1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1100000000,900 { + opp-1100000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1100000000,975 { + opp-1100000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000,1000 { + opp-1100000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000,1025 { + opp-1100000000-1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1100000000,1075 { + opp-1100000000-1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1150000000,975 { + opp-1150000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1200000000,975 { + opp-1200000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1200000000,1000 { + opp-1200000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000,1025 { + opp-1200000000-1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000,1050 { + opp-1200000000-1050 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1200000000,1075 { + opp-1200000000-1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1300000000,1000 { + opp-1300000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1300000000,1025 { + opp-1300000000-1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1300000000,1050 { + opp-1300000000-1050 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000,1075 { + opp-1300000000-1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1300000000,1100 { + opp-1300000000-1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1300000000,1125 { + opp-1300000000-1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1300000000,1150 { + opp-1300000000-1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1300000000,1175 { + opp-1300000000-1175 { opp-microvolt = <1175000 1175000 1250000>; }; - opp@1400000000,1100 { + opp-1400000000-1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1400000000,1125 { + opp-1400000000-1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1400000000,1150 { + opp-1400000000-1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1400000000,1175 { + opp-1400000000-1175 { opp-microvolt = <1175000 1175000 1250000>; }; - opp@1400000000,1237 { + opp-1400000000-1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1500000000,1125 { + opp-1500000000-1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000,1150 { + opp-1500000000-1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000,1200 { + opp-1500000000-1200 { opp-microvolt = <1200000 1200000 1250000>; }; - opp@1500000000,1237 { + opp-1500000000-1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1600000000,1212 { + opp-1600000000-1212 { opp-microvolt = <1212000 1212000 1250000>; }; - opp@1600000000,1237 { + opp-1600000000-1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1700000000,1212 { + opp-1700000000-1212 { opp-microvolt = <1212000 1212000 1250000>; }; - opp@1700000000,1237 { + opp-1700000000-1237 { opp-microvolt = <1237000 1237000 1250000>; }; }; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi index 72f2fe26cc0e..5b9ebb75a09f 100644 --- a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi @@ -1,116 +1,116 @@ // SPDX-License-Identifier: GPL-2.0 / { - cpu0_opp_table: cpu_opp_table0 { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; - opp@51000000,800 { + opp-51000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <51000000>; }; - opp@51000000,850 { + opp-51000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <51000000>; }; - opp@51000000,912 { + opp-51000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <51000000>; }; - opp@102000000,800 { + opp-102000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <102000000>; }; - opp@102000000,850 { + opp-102000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <102000000>; }; - opp@102000000,912 { + opp-102000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <102000000>; }; - opp@204000000,800 { + opp-204000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <204000000>; opp-suspend; }; - opp@204000000,850 { + opp-204000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <204000000>; opp-suspend; }; - opp@204000000,912 { + opp-204000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <204000000>; opp-suspend; }; - opp@312000000,850 { + opp-312000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C00>; opp-hz = /bits/ 64 <312000000>; }; - opp@312000000,912 { + opp-312000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <312000000>; }; - opp@340000000,800 { + opp-340000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0192>; opp-hz = /bits/ 64 <340000000>; }; - opp@340000000,850 { + opp-340000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>; opp-hz = /bits/ 64 <340000000>; }; - opp@370000000,800 { + opp-370000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x306C>; opp-hz = /bits/ 64 <370000000>; }; - opp@456000000,850 { + opp-456000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C00>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000,912 { + opp-456000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <456000000>; }; - opp@475000000,800 { + opp-475000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x31FE>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000,850 { + opp-475000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>, <0x01 0x0002>, <0x01 0x0010>, <0x01 0x0080>, @@ -118,25 +118,25 @@ opp-hz = /bits/ 64 <475000000>; }; - opp@608000000,850 { + opp-608000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0400>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,912 { + opp-608000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <608000000>; }; - opp@620000000,850 { + opp-620000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x306C>; opp-hz = /bits/ 64 <620000000>; }; - opp@640000000,850 { + opp-640000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>, <0x02 0x0002>, <0x04 0x0002>, <0x08 0x0002>, @@ -149,13 +149,13 @@ opp-hz = /bits/ 64 <640000000>; }; - opp@640000000,900 { + opp-640000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <640000000>; }; - opp@760000000,850 { + opp-760000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x3461>, <0x08 0x0002>, <0x08 0x0004>, <0x08 0x0008>, @@ -165,7 +165,7 @@ opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,900 { + opp-760000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>, <0x04 0x0002>, <0x02 0x0004>, @@ -177,37 +177,37 @@ opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,912 { + opp-760000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,975 { + opp-760000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <760000000>; }; - opp@816000000,850 { + opp-816000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0400>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,912 { + opp-816000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <816000000>; }; - opp@860000000,850 { + opp-860000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0C 0x0001>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000,900 { + opp-860000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>, <0x08 0x0002>, <0x04 0x0004>, @@ -220,7 +220,7 @@ opp-hz = /bits/ 64 <860000000>; }; - opp@860000000,975 { + opp-860000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>, <0x02 0x0004>, <0x02 0x0008>, @@ -229,25 +229,25 @@ opp-hz = /bits/ 64 <860000000>; }; - opp@860000000,1000 { + opp-860000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <860000000>; }; - opp@910000000,900 { + opp-910000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x3060>; opp-hz = /bits/ 64 <910000000>; }; - opp@1000000000,900 { + opp-1000000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x0C 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,975 { + opp-1000000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x03 0x0001>, <0x04 0x0002>, <0x08 0x0002>, <0x04 0x0004>, @@ -260,25 +260,25 @@ opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1000 { + opp-1000000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1025 { + opp-1000000000-1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1100000000,900 { + opp-1100000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000,975 { + opp-1100000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x06 0x0001>, <0x08 0x0002>, <0x08 0x0004>, <0x08 0x0008>, @@ -288,7 +288,7 @@ opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000,1000 { + opp-1100000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>, <0x04 0x0002>, <0x04 0x0004>, <0x04 0x0008>, @@ -297,31 +297,31 @@ opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000,1025 { + opp-1100000000-1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000,1075 { + opp-1100000000-1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1150000000,975 { + opp-1150000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x3060>; opp-hz = /bits/ 64 <1150000000>; }; - opp@1200000000,975 { + opp-1200000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1000 { + opp-1200000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>, <0x08 0x0004>, <0x08 0x0008>, @@ -331,7 +331,7 @@ opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1025 { + opp-1200000000-1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>, <0x04 0x0004>, <0x04 0x0008>, @@ -340,39 +340,39 @@ opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1050 { + opp-1200000000-1050 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1075 { + opp-1200000000-1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1300000000,1000 { + opp-1300000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>, <0x10 0x0080>, <0x10 0x0100>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1025 { + opp-1300000000-1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>, <0x08 0x0080>, <0x08 0x0100>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1050 { + opp-1300000000-1050 { clock-latency-ns = <100000>; opp-supported-hw = <0x12 0x3061>, <0x04 0x0002>, <0x08 0x0004>, <0x08 0x0008>, @@ -383,68 +383,68 @@ opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1075 { + opp-1300000000-1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0182>, <0x04 0x0004>, <0x04 0x0008>, <0x04 0x0010>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1100 { + opp-1300000000-1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x001C>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1125 { + opp-1300000000-1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1150 { + opp-1300000000-1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0182>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1175 { + opp-1300000000-1175 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1400000000,1100 { + opp-1400000000-1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x307C>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000,1125 { + opp-1400000000-1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x000C>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000,1150 { + opp-1400000000-1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x000C>, <0x04 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000,1175 { + opp-1400000000-1175 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000,1237 { + opp-1400000000-1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1500000000,1125 { + opp-1500000000-1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>, <0x10 0x0020>, <0x10 0x0040>, <0x10 0x1000>, @@ -452,7 +452,7 @@ opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000,1150 { + opp-1500000000-1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>, <0x08 0x0020>, <0x08 0x0040>, <0x08 0x1000>, @@ -460,37 +460,37 @@ opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000,1200 { + opp-1500000000-1200 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000,1237 { + opp-1500000000-1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1600000000,1212 { + opp-1600000000-1212 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x3060>; opp-hz = /bits/ 64 <1600000000>; }; - opp@1600000000,1237 { + opp-1600000000-1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x3060>; opp-hz = /bits/ 64 <1600000000>; }; - opp@1700000000,1212 { + opp-1700000000-1212 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x3060>; opp-hz = /bits/ 64 <1700000000>; }; - opp@1700000000,1237 { + opp-1700000000-1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x3060>; opp-hz = /bits/ 64 <1700000000>; diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 2a6dc423b9fc..9e59d9bd6b35 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -4524,9 +4524,9 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@900000000,1350; + /delete-node/ opp-900000000-1350; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@900000000; + /delete-node/ opp-900000000; }; diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi index 2c9780319725..ff25350869b3 100644 --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -1,383 +1,383 @@ // SPDX-License-Identifier: GPL-2.0 / { - emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; - opp@12750000,950 { + opp-12750000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0006>; }; - opp@12750000,1000 { + opp-12750000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0001>; }; - opp@12750000,1250 { + opp-12750000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0008>; }; - opp@25500000,950 { + opp-25500000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0006>; }; - opp@25500000,1000 { + opp-25500000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0001>; }; - opp@25500000,1250 { + opp-25500000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0008>; }; - opp@27000000,950 { + opp-27000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0006>; }; - opp@27000000,1000 { + opp-27000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0001>; }; - opp@27000000,1250 { + opp-27000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0008>; }; - opp@51000000,950 { + opp-51000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0006>; }; - opp@51000000,1000 { + opp-51000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0001>; }; - opp@51000000,1250 { + opp-51000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0008>; }; - opp@54000000,950 { + opp-54000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0006>; }; - opp@54000000,1000 { + opp-54000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0001>; }; - opp@54000000,1250 { + opp-54000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0008>; }; - opp@102000000,950 { + opp-102000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0006>; }; - opp@102000000,1000 { + opp-102000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0001>; }; - opp@102000000,1250 { + opp-102000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0008>; }; - opp@108000000,1000 { + opp-108000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x0007>; }; - opp@108000000,1250 { + opp-108000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x0008>; }; - opp@204000000,1000 { + opp-204000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0007>; opp-suspend; }; - opp@204000000,1250 { + opp-204000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0008>; opp-suspend; }; - opp@333500000,1000 { + opp-333500000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0006>; }; - opp@333500000,1200 { + opp-333500000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0001>; }; - opp@333500000,1250 { + opp-333500000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0008>; }; - opp@375000000,1000 { + opp-375000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0006>; }; - opp@375000000,1200 { + opp-375000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0001>; }; - opp@375000000,1250 { + opp-375000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0008>; }; - opp@400000000,1000 { + opp-400000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0006>; }; - opp@400000000,1200 { + opp-400000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0001>; }; - opp@400000000,1250 { + opp-400000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0008>; }; - opp@416000000,1200 { + opp-416000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x0007>; }; - opp@416000000,1250 { + opp-416000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x0008>; }; - opp@450000000,1200 { + opp-450000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x0007>; }; - opp@450000000,1250 { + opp-450000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x0008>; }; - opp@533000000,1200 { + opp-533000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x0007>; }; - opp@533000000,1250 { + opp-533000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x0008>; }; - opp@625000000,1200 { + opp-625000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x0006>; }; - opp@625000000,1250 { + opp-625000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x0008>; }; - opp@667000000,1200 { + opp-667000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <667000000>; opp-supported-hw = <0x0006>; }; - opp@750000000,1300 { + opp-750000000-1300 { opp-microvolt = <1300000 1300000 1350000>; opp-hz = /bits/ 64 <750000000>; opp-supported-hw = <0x0004>; }; - opp@800000000,1300 { + opp-800000000-1300 { opp-microvolt = <1300000 1300000 1350000>; opp-hz = /bits/ 64 <800000000>; opp-supported-hw = <0x0004>; }; - opp@900000000,1350 { + opp-900000000-1350 { opp-microvolt = <1350000 1350000 1350000>; opp-hz = /bits/ 64 <900000000>; opp-supported-hw = <0x0004>; }; }; - emc_bw_dfs_opp_table: emc-bandwidth-opp-table { + emc_bw_dfs_opp_table: opp-table-actmon { compatible = "operating-points-v2"; - opp@12750000 { + opp-12750000 { opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <102000>; }; - opp@25500000 { + opp-25500000 { opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <204000>; }; - opp@27000000 { + opp-27000000 { opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <216000>; }; - opp@51000000 { + opp-51000000 { opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <408000>; }; - opp@54000000 { + opp-54000000 { opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <432000>; }; - opp@102000000 { + opp-102000000 { opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <816000>; }; - opp@108000000 { + opp-108000000 { opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <864000>; }; - opp@204000000 { + opp-204000000 { opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <1632000>; opp-suspend; }; - opp@333500000 { + opp-333500000 { opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <2668000>; }; - opp@375000000 { + opp-375000000 { opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <3000000>; }; - opp@400000000 { + opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <3200000>; }; - opp@416000000 { + opp-416000000 { opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <3328000>; }; - opp@450000000 { + opp-450000000 { opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <3600000>; }; - opp@533000000 { + opp-533000000 { opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <4264000>; }; - opp@625000000 { + opp-625000000 { opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x000E>; opp-peak-kBps = <5000000>; }; - opp@667000000 { + opp-667000000 { opp-hz = /bits/ 64 <667000000>; opp-supported-hw = <0x0006>; opp-peak-kBps = <5336000>; }; - opp@750000000 { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; opp-supported-hw = <0x0004>; opp-peak-kBps = <6000000>; }; - opp@800000000 { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-supported-hw = <0x0004>; opp-peak-kBps = <6400000>; }; - opp@900000000 { + opp-900000000 { opp-hz = /bits/ 64 <900000000>; opp-supported-hw = <0x0004>; opp-peak-kBps = <7200000>; From 9b07cfe27647639e52a411d07413608cb5cda7dc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:22:26 +0100 Subject: [PATCH 357/574] ARM: tegra: Fix Tegra124 I2C compatible string list The I2C controller found on Tegra124 is not fully compatible with the Tegra114 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 752a28268024..0e0a769fb30f 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -438,7 +438,7 @@ }; i2c@7000c000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -453,7 +453,7 @@ }; i2c@7000c400 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c400 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -468,7 +468,7 @@ }; i2c@7000c500 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c500 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -483,7 +483,7 @@ }; i2c@7000c700 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c700 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -498,7 +498,7 @@ }; i2c@7000d000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -513,7 +513,7 @@ }; i2c@7000d100 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d100 0x0 0x100>; interrupts = ; #address-cells = <1>; From e51c87b7cb1a41d99e059ca3a9c8edf41656ce1f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:23:43 +0100 Subject: [PATCH 358/574] ARM: tegra: Drop unused AHCI clocks on Tegra124 The CML1 and PLL_E clocks are never explicitly used by the AHCI controller found on Tegra124, so drop them from the corresponding device tree node. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 0e0a769fb30f..36566a777e49 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -672,10 +672,8 @@ <0x0 0x70020000 0x0 0x7000>; /* SATA */ interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SATA>, - <&tegra_car TEGRA124_CLK_SATA_OOB>, - <&tegra_car TEGRA124_CLK_CML1>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "sata", "sata-oob", "cml1", "pll_e"; + <&tegra_car TEGRA124_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; resets = <&tegra_car 124>, <&tegra_car 129>, <&tegra_car 123>; From 4b7f222d832364e17363e4232d5110c7e7660932 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:25:49 +0100 Subject: [PATCH 359/574] ARM: tegra: Sort Tegra124 XUSB clocks correctly Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 36566a777e49..e87da6c24f7c 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -710,8 +710,8 @@ <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA124_CLK_PLL_U_480M>, @@ -719,7 +719,7 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, From 959fddf537c8d3f305df135881976318d7e13b93 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:27:46 +0100 Subject: [PATCH 360/574] ARM: tegra: Avoid pwm- prefix in pinmux nodes The "pwm-" prefix currently matches the DT schema for PWM controllers and throws an error in that case. This is something that should be fixed in the PWM DT schema, but in this case we can also preempt any such conflict by naming the nodes after the pins like we do for many others of these nodes. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-eval-v3.dts | 4 ++-- arch/arm/boot/dts/tegra20-colibri-iris.dts | 4 ++-- arch/arm/boot/dts/tegra20-colibri.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts index a05fb3853da8..d2a3bf9d28bd 100644 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -70,11 +70,11 @@ nvidia,tristate = ; }; - pwm-a-b { + sdc { nvidia,tristate = ; }; - pwm-c-d { + sdb_sdd { nvidia,tristate = ; }; diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 425494b9ed54..00ecbbd5e9e1 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -70,11 +70,11 @@ nvidia,tristate = ; }; - pwm-a-b { + sdc { nvidia,tristate = ; }; - pwm-c-d { + sdb_sdd { nvidia,tristate = ; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index e36b258c82df..28e22097578d 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -113,7 +113,7 @@ }; /* Colibri Backlight PWM, PWM */ - pwm-a-b { + sdc { nvidia,pins = "sdc"; nvidia,function = "pwm"; nvidia,tristate = ; @@ -242,7 +242,7 @@ }; /* Colibri PWM, PWM */ - pwm-c-d { + sdb_sdd { nvidia,pins = "sdb", "sdd"; nvidia,function = "pwm"; nvidia,tristate = ; From 8f8ef3860d4403d1bf0887380f9e3376be092c40 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Mon, 6 Dec 2021 23:32:49 -0800 Subject: [PATCH 361/574] dt-bindings: clock: Add SDX65 GCC clock bindings Add device tree bindings for global clock controller on SDX65 SOCs. Signed-off-by: Vamsi Krishna Lanka Reviewed-by: Rob Herring Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/e15509b2b7c9b600ab38c5269d4fac609c077b5b.1638861860.git.quic_vamslank@quicinc.com --- .../bindings/clock/qcom,gcc-sdx65.yaml | 80 ++++++++++++ include/dt-bindings/clock/qcom,gcc-sdx65.h | 122 ++++++++++++++++++ 2 files changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml create mode 100644 include/dt-bindings/clock/qcom,gcc-sdx65.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml new file mode 100644 index 000000000000..16c4cdc7b4d6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SDX65 + +maintainers: + - Vamsi krishna Lanka + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SDX65 + + See also: + - dt-bindings/clock/qcom,gcc-sdx65.h + +properties: + compatible: + const: qcom,gcc-sdx65 + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + - description: PLL test clock source (Optional clock) + minItems: 5 + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: pcie_pipe_clk + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk + - const: core_bi_pll_test_se # Optional clock + minItems: 5 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,gcc-sdx65"; + reg = <0x100000 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, + <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", + "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,gcc-sdx65.h b/include/dt-bindings/clock/qcom,gcc-sdx65.h new file mode 100644 index 000000000000..75ecc9237d8f --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sdx65.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GCC_AHB_PCIE_LINK_CLK 2 +#define GCC_BLSP1_AHB_CLK 3 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 4 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 5 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 6 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 7 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 8 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 9 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 10 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 11 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 12 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 13 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 14 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 15 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 16 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 17 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 18 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 19 +#define GCC_BLSP1_SLEEP_CLK 20 +#define GCC_BLSP1_UART1_APPS_CLK 21 +#define GCC_BLSP1_UART1_APPS_CLK_SRC 22 +#define GCC_BLSP1_UART2_APPS_CLK 23 +#define GCC_BLSP1_UART2_APPS_CLK_SRC 24 +#define GCC_BLSP1_UART3_APPS_CLK 25 +#define GCC_BLSP1_UART3_APPS_CLK_SRC 26 +#define GCC_BLSP1_UART4_APPS_CLK 27 +#define GCC_BLSP1_UART4_APPS_CLK_SRC 28 +#define GCC_BOOT_ROM_AHB_CLK 29 +#define GCC_CPUSS_AHB_CLK 30 +#define GCC_CPUSS_AHB_CLK_SRC 31 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 32 +#define GCC_CPUSS_GNOC_CLK 33 +#define GCC_GP1_CLK 34 +#define GCC_GP1_CLK_SRC 35 +#define GCC_GP2_CLK 36 +#define GCC_GP2_CLK_SRC 37 +#define GCC_GP3_CLK 38 +#define GCC_GP3_CLK_SRC 39 +#define GCC_PCIE_0_CLKREF_EN 40 +#define GCC_PCIE_AUX_CLK 41 +#define GCC_PCIE_AUX_CLK_SRC 42 +#define GCC_PCIE_AUX_PHY_CLK_SRC 43 +#define GCC_PCIE_CFG_AHB_CLK 44 +#define GCC_PCIE_MSTR_AXI_CLK 45 +#define GCC_PCIE_PIPE_CLK 46 +#define GCC_PCIE_PIPE_CLK_SRC 47 +#define GCC_PCIE_RCHNG_PHY_CLK 48 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 49 +#define GCC_PCIE_SLEEP_CLK 50 +#define GCC_PCIE_SLV_AXI_CLK 51 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 52 +#define GCC_PDM2_CLK 53 +#define GCC_PDM2_CLK_SRC 54 +#define GCC_PDM_AHB_CLK 55 +#define GCC_PDM_XO4_CLK 56 +#define GCC_RX1_USB2_CLKREF_EN 57 +#define GCC_SDCC1_AHB_CLK 58 +#define GCC_SDCC1_APPS_CLK 59 +#define GCC_SDCC1_APPS_CLK_SRC 60 +#define GCC_SPMI_FETCHER_AHB_CLK 61 +#define GCC_SPMI_FETCHER_CLK 62 +#define GCC_SPMI_FETCHER_CLK_SRC 63 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 64 +#define GCC_USB30_MASTER_CLK 65 +#define GCC_USB30_MASTER_CLK_SRC 66 +#define GCC_USB30_MOCK_UTMI_CLK 67 +#define GCC_USB30_MOCK_UTMI_CLK_SRC 68 +#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 69 +#define GCC_USB30_MSTR_AXI_CLK 70 +#define GCC_USB30_SLEEP_CLK 71 +#define GCC_USB30_SLV_AHB_CLK 72 +#define GCC_USB3_PHY_AUX_CLK 73 +#define GCC_USB3_PHY_AUX_CLK_SRC 74 +#define GCC_USB3_PHY_PIPE_CLK 75 +#define GCC_USB3_PHY_PIPE_CLK_SRC 76 +#define GCC_USB3_PRIM_CLKREF_EN 77 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 78 +#define GCC_XO_DIV4_CLK 79 +#define GCC_XO_PCIE_LINK_CLK 80 + +/* GCC resets */ +#define GCC_BLSP1_QUP1_BCR 0 +#define GCC_BLSP1_QUP2_BCR 1 +#define GCC_BLSP1_QUP3_BCR 2 +#define GCC_BLSP1_QUP4_BCR 3 +#define GCC_BLSP1_UART1_BCR 4 +#define GCC_BLSP1_UART2_BCR 5 +#define GCC_BLSP1_UART3_BCR 6 +#define GCC_BLSP1_UART4_BCR 7 +#define GCC_PCIE_BCR 8 +#define GCC_PCIE_LINK_DOWN_BCR 9 +#define GCC_PCIE_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_PHY_BCR 11 +#define GCC_PCIE_PHY_CFG_AHB_BCR 12 +#define GCC_PCIE_PHY_COM_BCR 13 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 14 +#define GCC_PDM_BCR 15 +#define GCC_QUSB2PHY_BCR 16 +#define GCC_SDCC1_BCR 17 +#define GCC_SPMI_FETCHER_BCR 18 +#define GCC_TCSR_PCIE_BCR 19 +#define GCC_USB30_BCR 20 +#define GCC_USB3_PHY_BCR 21 +#define GCC_USB3PHY_PHY_BCR 22 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 + +/* GCC power domains */ +#define USB30_GDSC 0 +#define PCIE_GDSC 1 + +#endif From 3b338c9a6a2afd6db46d5d8e39ae4f5eef420bf8 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Fri, 29 Oct 2021 17:02:03 -0700 Subject: [PATCH 362/574] dt-bindings: arm: qcom: Document SDX65 platform and boards Document the SDX65 platform binding and also the boards using it. Signed-off-by: Vamsi Krishna Lanka Reviewed-by: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1635552125-16407-2-git-send-email-quic_vamslank@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c8808e0f9e64..2d613282816a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -48,6 +48,7 @@ description: | sdx65 sm7225 sm8150 + sdx65 sm8250 sm8350 @@ -224,6 +225,11 @@ properties: - qcom,sdx65-mtp - const: qcom,sdx65 + - items: + - enum: + - qcom,sdx65-mtp + - const: qcom,sdx65 + - items: - enum: - qcom,ipq6018-cp01 From bae2f5979c6e537334c9099013b5407019e88c44 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Fri, 29 Oct 2021 17:02:04 -0700 Subject: [PATCH 363/574] ARM: dts: qcom: Add SDX65 platform and MTP board support Add basic devicetree support for SDX65 platform and MTP board from Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. This commit adds basic devicetree support that includes GCC, RPMh clock, INTC and Debug UART. Signed-off-by: Vamsi Krishna Lanka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 25 ++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 210 +++++++++++++++++++++++++++ 3 files changed, 237 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/qcom-sdx65-mtp.dts create mode 100644 arch/arm/boot/dts/qcom-sdx65.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bba17ee51e29..3497c08c1afc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -987,7 +987,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-mdm9615-wp8548-mangoh-green.dtb \ qcom-sdx55-mtp.dtb \ qcom-sdx55-t55.dtb \ - qcom-sdx55-telit-fn980-tlb.dtb + qcom-sdx55-telit-fn980-tlb.dtb \ + qcom-sdx65-mtp.dtb dtb-$(CONFIG_ARCH_RDA) += \ rda8810pl-orangepi-2g-iot.dtb \ rda8810pl-orangepi-i96.dtb diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts new file mode 100644 index 000000000000..59457da8e5f1 --- /dev/null +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; + +#include "qcom-sdx65.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX65 MTP"; + compatible = "qcom,sdx65-mtp", "qcom,sdx65"; + qcom,board-id = <0x2010008 0x302>; + + aliases { + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart3 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi new file mode 100644 index 000000000000..5aecb004e953 --- /dev/null +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SDX65 SoC device tree source + * + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; + interrupt-parent = <&intc>; + + memory { + device_type = "memory"; + reg = <0 0>; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cmd_db: reserved-memory@8fee0000 { + compatible = "qcom,cmd-db"; + reg = <0x8fee0000 0x20000>; + no-map; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdx65"; + reg = <0x00100000 0x001f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + blsp1_uart3: serial@831000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x00831000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + pdc: interrupt-controller@b210000 { + compatible = "qcom,sdx65-pdc", "qcom,pdc"; + reg = <0xb210000 0x10000>; + qcom,pdc-ranges = <0 147 52>, <52 266 32>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17800000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x17800000 0x1000>, + <0x17802000 0x1000>; + }; + + timer@17820000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17820000 0x1000>; + clock-frequency = <19200000>; + + frame@17821000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17821000 0x1000>, + <0x17822000 0x1000>; + }; + + frame@17823000 { + frame-number = <1>; + interrupts = ; + reg = <0x17823000 0x1000>; + status = "disabled"; + }; + + frame@17824000 { + frame-number = <2>; + interrupts = ; + reg = <0x17824000 0x1000>; + status = "disabled"; + }; + + frame@17825000 { + frame-number = <3>; + interrupts = ; + reg = <0x17825000 0x1000>; + status = "disabled"; + }; + + frame@17826000 { + frame-number = <4>; + interrupts = ; + reg = <0x17826000 0x1000>; + status = "disabled"; + }; + + frame@17827000 { + frame-number = <5>; + interrupts = ; + reg = <0x17827000 0x1000>; + status = "disabled"; + }; + + frame@17828000 { + frame-number = <6>; + interrupts = ; + reg = <0x17828000 0x1000>; + status = "disabled"; + }; + + frame@17829000 { + frame-number = <7>; + interrupts = ; + reg = <0x17829000 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17830000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x17830000 0x10000>, + <0x17840000 0x10000>; + reg-names = "drv-0", "drv-1"; + interrupts = , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <1>; + qcom,tcs-config = , + , + , + ; + + rpmhcc: clock-controller@1 { + compatible = "qcom,sdx65-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 12 0xf08>, + <1 10 0xf08>, + <1 11 0xf08>; + clock-frequency = <19200000>; + }; +}; From ff8b573a6ccf4deba10285abef072c577099e038 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Fri, 29 Oct 2021 17:02:05 -0700 Subject: [PATCH 364/574] ARM: dts: qcom: sdx65: Add pincontrol node This commit adds pincontrol node to SDX65 dts. Signed-off-by: Vamsi Krishna Lanka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1635552125-16407-4-git-send-email-quic_vamslank@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 5aecb004e953..796641d30e06 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -91,6 +91,18 @@ status = "disabled"; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sdx65-tlmm"; + reg = <0xf100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 109>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx65-pdc", "qcom,pdc"; reg = <0xb210000 0x10000>; From 72a0ca203ca7fae34fe61668906fe483b97d9039 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 7 Dec 2021 17:10:02 +0530 Subject: [PATCH 365/574] dt-bindings: clock: Add SM8450 GCC clock bindings Add device tree bindings for global clock controller on SM8450 SoCs. Signed-off-by: Vinod Koul Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211207114003.100693-2-vkoul@kernel.org --- .../bindings/clock/qcom,gcc-sm8450.yaml | 85 ++++++ include/dt-bindings/clock/qcom,gcc-sm8450.h | 244 ++++++++++++++++++ 2 files changed, 329 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8450.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml new file mode 100644 index 000000000000..58d98a766de6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SM8450 + +maintainers: + - Vinod Koul + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SM8450 + + See also: + - dt-bindings/clock/qcom,gcc-sm8450.h + +properties: + compatible: + const: qcom,gcc-sm8450 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source (Optional clock) + - description: PCIE 1 Pipe clock source (Optional clock) + - description: PCIE 1 Phy Auxillary clock source (Optional clock) + - description: UFS Phy Rx symbol 0 clock source (Optional clock) + - description: UFS Phy Rx symbol 1 clock source (Optional clock) + - description: UFS Phy Tx symbol 0 clock source (Optional clock) + - description: USB3 Phy wrapper pipe clock source (Optional clock) + minItems: 2 + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + - const: pcie_0_pipe_clk # Optional clock + - const: pcie_1_pipe_clk # Optional clock + - const: pcie_1_phy_aux_clk # Optional clock + - const: ufs_phy_rx_symbol_0_clk # Optional clock + - const: ufs_phy_rx_symbol_1_clk # Optional clock + - const: ufs_phy_tx_symbol_0_clk # Optional clock + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock + minItems: 2 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,gcc-sm8450"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,gcc-sm8450.h b/include/dt-bindings/clock/qcom,gcc-sm8450.h new file mode 100644 index 000000000000..cf1469312c4c --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sm8450.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H + +/* GCC HW clocks */ +#define CORE_BI_PLL_TEST_SE 0 +#define PCIE_0_PIPE_CLK 1 +#define PCIE_1_PHY_AUX_CLK 2 +#define PCIE_1_PIPE_CLK 3 +#define UFS_PHY_RX_SYMBOL_0_CLK 4 +#define UFS_PHY_RX_SYMBOL_1_CLK 5 +#define UFS_PHY_TX_SYMBOL_0_CLK 6 +#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 7 + +/* GCC clocks */ +#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 8 +#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 9 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 10 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 11 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12 +#define GCC_ANOC_PCIE_PWRCTL_CLK 13 +#define GCC_BOOT_ROM_AHB_CLK 14 +#define GCC_CAMERA_AHB_CLK 15 +#define GCC_CAMERA_HF_AXI_CLK 16 +#define GCC_CAMERA_SF_AXI_CLK 17 +#define GCC_CAMERA_XO_CLK 18 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 19 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 20 +#define GCC_CPUSS_AHB_CLK 21 +#define GCC_CPUSS_AHB_CLK_SRC 22 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 23 +#define GCC_CPUSS_CONFIG_NOC_SF_CLK 24 +#define GCC_DDRSS_GPU_AXI_CLK 25 +#define GCC_DDRSS_PCIE_SF_TBU_CLK 26 +#define GCC_DISP_AHB_CLK 27 +#define GCC_DISP_HF_AXI_CLK 28 +#define GCC_DISP_SF_AXI_CLK 29 +#define GCC_DISP_XO_CLK 30 +#define GCC_EUSB3_0_CLKREF_EN 31 +#define GCC_GP1_CLK 32 +#define GCC_GP1_CLK_SRC 33 +#define GCC_GP2_CLK 34 +#define GCC_GP2_CLK_SRC 35 +#define GCC_GP3_CLK 36 +#define GCC_GP3_CLK_SRC 37 +#define GCC_GPLL0 38 +#define GCC_GPLL0_OUT_EVEN 39 +#define GCC_GPLL4 40 +#define GCC_GPLL9 41 +#define GCC_GPU_CFG_AHB_CLK 42 +#define GCC_GPU_GPLL0_CLK_SRC 43 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 44 +#define GCC_GPU_MEMNOC_GFX_CLK 45 +#define GCC_GPU_SNOC_DVM_GFX_CLK 46 +#define GCC_PCIE_0_AUX_CLK 47 +#define GCC_PCIE_0_AUX_CLK_SRC 48 +#define GCC_PCIE_0_CFG_AHB_CLK 49 +#define GCC_PCIE_0_CLKREF_EN 50 +#define GCC_PCIE_0_MSTR_AXI_CLK 51 +#define GCC_PCIE_0_PHY_RCHNG_CLK 52 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 53 +#define GCC_PCIE_0_PIPE_CLK 54 +#define GCC_PCIE_0_PIPE_CLK_SRC 55 +#define GCC_PCIE_0_SLV_AXI_CLK 56 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57 +#define GCC_PCIE_1_AUX_CLK 58 +#define GCC_PCIE_1_AUX_CLK_SRC 59 +#define GCC_PCIE_1_CFG_AHB_CLK 60 +#define GCC_PCIE_1_CLKREF_EN 61 +#define GCC_PCIE_1_MSTR_AXI_CLK 62 +#define GCC_PCIE_1_PHY_AUX_CLK 63 +#define GCC_PCIE_1_PHY_AUX_CLK_SRC 64 +#define GCC_PCIE_1_PHY_RCHNG_CLK 65 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 66 +#define GCC_PCIE_1_PIPE_CLK 67 +#define GCC_PCIE_1_PIPE_CLK_SRC 68 +#define GCC_PCIE_1_SLV_AXI_CLK 69 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 70 +#define GCC_PDM2_CLK 71 +#define GCC_PDM2_CLK_SRC 72 +#define GCC_PDM_AHB_CLK 73 +#define GCC_PDM_XO4_CLK 74 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 75 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 76 +#define GCC_QMIP_DISP_AHB_CLK 77 +#define GCC_QMIP_GPU_AHB_CLK 78 +#define GCC_QMIP_PCIE_AHB_CLK 79 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 80 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 81 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 82 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 83 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 84 +#define GCC_QUPV3_WRAP0_CORE_CLK 85 +#define GCC_QUPV3_WRAP0_S0_CLK 86 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 87 +#define GCC_QUPV3_WRAP0_S1_CLK 88 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 89 +#define GCC_QUPV3_WRAP0_S2_CLK 90 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 91 +#define GCC_QUPV3_WRAP0_S3_CLK 92 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 93 +#define GCC_QUPV3_WRAP0_S4_CLK 94 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 95 +#define GCC_QUPV3_WRAP0_S5_CLK 96 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 97 +#define GCC_QUPV3_WRAP0_S6_CLK 98 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 99 +#define GCC_QUPV3_WRAP0_S7_CLK 100 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 101 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 102 +#define GCC_QUPV3_WRAP1_CORE_CLK 103 +#define GCC_QUPV3_WRAP1_S0_CLK 104 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 105 +#define GCC_QUPV3_WRAP1_S1_CLK 106 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 107 +#define GCC_QUPV3_WRAP1_S2_CLK 108 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 109 +#define GCC_QUPV3_WRAP1_S3_CLK 110 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 111 +#define GCC_QUPV3_WRAP1_S4_CLK 112 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 113 +#define GCC_QUPV3_WRAP1_S5_CLK 114 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 115 +#define GCC_QUPV3_WRAP1_S6_CLK 116 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 117 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 118 +#define GCC_QUPV3_WRAP2_CORE_CLK 119 +#define GCC_QUPV3_WRAP2_S0_CLK 120 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 121 +#define GCC_QUPV3_WRAP2_S1_CLK 122 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 123 +#define GCC_QUPV3_WRAP2_S2_CLK 124 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 125 +#define GCC_QUPV3_WRAP2_S3_CLK 126 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 127 +#define GCC_QUPV3_WRAP2_S4_CLK 128 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 129 +#define GCC_QUPV3_WRAP2_S5_CLK 130 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 131 +#define GCC_QUPV3_WRAP2_S6_CLK 132 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 133 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 134 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 135 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 136 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 137 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 138 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 139 +#define GCC_SDCC2_AHB_CLK 140 +#define GCC_SDCC2_APPS_CLK 141 +#define GCC_SDCC2_APPS_CLK_SRC 142 +#define GCC_SDCC2_AT_CLK 143 +#define GCC_SDCC4_AHB_CLK 144 +#define GCC_SDCC4_APPS_CLK 145 +#define GCC_SDCC4_APPS_CLK_SRC 146 +#define GCC_SDCC4_AT_CLK 147 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 148 +#define GCC_UFS_0_CLKREF_EN 149 +#define GCC_UFS_PHY_AHB_CLK 150 +#define GCC_UFS_PHY_AXI_CLK 151 +#define GCC_UFS_PHY_AXI_CLK_SRC 152 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 153 +#define GCC_UFS_PHY_ICE_CORE_CLK 154 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 155 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 156 +#define GCC_UFS_PHY_PHY_AUX_CLK 157 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 158 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 159 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 160 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 161 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 162 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 163 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 164 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 165 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 166 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 167 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 168 +#define GCC_USB30_PRIM_MASTER_CLK 169 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 170 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 171 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 172 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 173 +#define GCC_USB30_PRIM_SLEEP_CLK 174 +#define GCC_USB3_0_CLKREF_EN 175 +#define GCC_USB3_PRIM_PHY_AUX_CLK 176 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 177 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 178 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 179 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 180 +#define GCC_VIDEO_AHB_CLK 181 +#define GCC_VIDEO_AXI0_CLK 182 +#define GCC_VIDEO_AXI1_CLK 183 +#define GCC_VIDEO_XO_CLK 184 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_MMSS_BCR 3 +#define GCC_PCIE_0_BCR 4 +#define GCC_PCIE_0_LINK_DOWN_BCR 5 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_0_PHY_BCR 7 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_1_BCR 9 +#define GCC_PCIE_1_LINK_DOWN_BCR 10 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 +#define GCC_PCIE_1_PHY_BCR 12 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_PHY_BCR 14 +#define GCC_PCIE_PHY_CFG_AHB_BCR 15 +#define GCC_PCIE_PHY_COM_BCR 16 +#define GCC_PDM_BCR 17 +#define GCC_QUPV3_WRAPPER_0_BCR 18 +#define GCC_QUPV3_WRAPPER_1_BCR 19 +#define GCC_QUPV3_WRAPPER_2_BCR 20 +#define GCC_QUSB2PHY_PRIM_BCR 21 +#define GCC_QUSB2PHY_SEC_BCR 22 +#define GCC_SDCC2_BCR 23 +#define GCC_SDCC4_BCR 24 +#define GCC_UFS_PHY_BCR 25 +#define GCC_USB30_PRIM_BCR 26 +#define GCC_USB3_DP_PHY_PRIM_BCR 27 +#define GCC_USB3_DP_PHY_SEC_BCR 28 +#define GCC_USB3_PHY_PRIM_BCR 29 +#define GCC_USB3_PHY_SEC_BCR 30 +#define GCC_USB3PHY_PHY_PRIM_BCR 31 +#define GCC_USB3PHY_PHY_SEC_BCR 32 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 33 +#define GCC_VIDEO_AXI0_CLK_ARES 34 +#define GCC_VIDEO_AXI1_CLK_ARES 35 +#define GCC_VIDEO_BCR 36 + +/* GCC power domains */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define UFS_PHY_GDSC 2 +#define USB30_PRIM_GDSC 3 + +#endif From 8e6de09c716f37dbdc8181e803455603c89c4bd2 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Thu, 9 Dec 2021 22:59:38 +0000 Subject: [PATCH 366/574] arm64: dts: qcom: sdm845-oneplus-*: add msm-id and board-id The msm-id and board-id can be used to select the correct dtb when multiple are provided to the bootloader. Multiple DTBs can be provided on sdm845 devices using boot image header v1 by appending them all to the kernel image before creating the boot image. The bootloader then selects them like this: Best match DTB tags 321/00000008/0x00000000/20001/20014/20115/20018/0/(offset)0x79998E27/(size)0x000173CD Using pmic info 0x20014/0x20115/0x20018/0x0 for device 0x20014/0x20115/0x20018/0x0 Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211209225938.2427342-1-caleb.connolly@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts | 2 ++ arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 73493079d13e..5936b47dee5f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -11,6 +11,8 @@ model = "OnePlus 6"; compatible = "oneplus,enchilada", "qcom,sdm845"; chassis-type = "handset"; + qcom,msm-id = <0x141 0x20001>; + qcom,board-id = <8 0 17819 22>; }; &display_panel { diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index b63ebc48f62f..78a0b99144e6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -11,6 +11,8 @@ model = "OnePlus 6T"; compatible = "oneplus,fajita", "qcom,sdm845"; chassis-type = "handset"; + qcom,msm-id = <0x141 0x20001>; + qcom,board-id = <8 0 18801 41>; }; &display_panel { From c16160cfa5651039f886d5cc6a6d9129e1fe789d Mon Sep 17 00:00:00 2001 From: Katherine Perez Date: Thu, 9 Dec 2021 10:32:46 -0800 Subject: [PATCH 367/574] arm64: dts: qcom: add minimal DTS for Microsoft Surface Duo 2 This is a minimal devicetree for Microsoft Surface Duo 2 with SM8350 Chipset Signed-off-by: Katherine Perez Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211209183246.842880-2-kaperez@linux.microsoft.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/sm8350-microsoft-surface-duo2.dts | 369 ++++++++++++++++++ 2 files changed, 370 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 693b30c51e33..a3eedb8b33ee 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts new file mode 100644 index 000000000000..9cb1d8455fd0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (C) 2021, Microsoft Corporation + */ + +/dts-v1/; + +#include +#include "sm8350.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" +#include "pmr735b.dtsi" + +/ { + model = "Microsoft Surface Duo 2"; + compatible = "microsoft,surface-duo2", "qcom,sm8350"; + chassis-type = "handset"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&adsp { + status = "okay"; + firmware-name = "qcom/sm8350/microsoft/adsp.mbn"; +}; + +&apps_rsc { + pm8350-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&vreg_s11b_0p95>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&vreg_s11b_0p95>; + vdd-l8-supply = <&vreg_s2c_0p8>; + + vreg_s10b_1p8: smps10 { + regulator-name = "vreg_s10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s11b_0p95: smps11 { + regulator-name = "vreg_s11b_0p95"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_s12b_1p25: smps12 { + regulator-name = "vreg_s12b_1p25"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1360000>; + }; + + vreg_l1b_0p88: ldo1 { + regulator-name = "vreg_l1b_0p88"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p07: ldo2 { + regulator-name = "vreg_l2b_3p07"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p9: ldo3 { + regulator-name = "vreg_l3b_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l5b_0p88: ldo5 { + regulator-name = "vreg_l3b_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1208000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-name = "vreg_l7b_2p96"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_s1c_1p86>; + vdd-l2-l8-supply = <&vreg_s1c_1p86>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&vreg_s12b_1p25>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_1p86: smps1 { + regulator-name = "vreg_s1c_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_s2c_0p8: smps2 { + regulator-name = "vreg_s2c_0p8"; + regulator-min-microvolt = <640000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_s10c_1p05: smps10 { + regulator-name = "vreg_s10c_1p05"; + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p8: ldo2 { + regulator-name = "vreg_l2c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-name = "vreg_l3c_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l4c_uim1: ldo4 { + regulator-name = "vreg_l4c_uim1"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l5c_uim2: ldo5 { + regulator-name = "vreg_l5c_uim2"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6c_1p8: ldo6 { + regulator-name = "vreg_l6c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l10c_1p2: ldo10 { + regulator-name = "vreg_l10c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l11c_2p96: ldo11 { + regulator-name = "vreg_l11c_2p96"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-name = "vreg_l13c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + }; +}; + +&cdsp { + status = "okay"; + firmware-name = "qcom/sm8350/microsoft/cdsp.mbn"; +}; + +&ipa { + status = "okay"; + + memory-region = <&pil_ipa_fw_mem>; +}; + +&mpss { + status = "okay"; + firmware-name = "qcom/sm8350/microsoft/modem.mbn"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&slpi { + status = "okay"; + firmware-name = "qcom/sm8350/microsoft/slpi.mbn"; +}; + +&tlmm { + gpio-reserved-ranges = <4 4>, <12 4>, <56 4>, <76 4>; +}; + +&uart2 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 203 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p96>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-max-microamp = <91600>; + vdda-pll-supply = <&vreg_l6b_1p2>; + vdda-pll-max-microamp = <19000>; +}; + +&usb_1 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5b_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p07>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p88>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5b_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p07>; +}; + +&usb_2_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l5b_0p88>; +}; From d56a8e9c7af835a4f3f88b2ae34f4ba6f7085b7c Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Tue, 14 Dec 2021 19:09:24 +0200 Subject: [PATCH 368/574] dt-bindings: soc: samsung: Fix I2C clocks order in USI binding example Now that HSI2C binding [1] is converted to dt-schema format, it reveals incorrect HSI2C clocks order in USI binding example: .../exynos-usi.example.dt.yaml: i2c@13820000: clock-names:0: 'hsi2c' was expected From schema: .../i2c-exynos5.yaml .../exynos-usi.example.dt.yaml: i2c@13820000: clock-names:1: 'hsi2c_pclk' was expected From schema: .../i2c-exynos5.yaml Change HSI2C clock order in USI binding example to satisfy HSI2C binding requirements and fix above warnings. [1] Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211214170924.27998-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index 0af4821fae5e..273f2d95a043 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -152,8 +152,8 @@ examples: interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&cmu_peri 32>, <&cmu_peri 31>; - clock-names = "hsi2c_pclk", "hsi2c"; + clocks = <&cmu_peri 31>, <&cmu_peri 32>; + clock-names = "hsi2c", "hsi2c_pclk"; status = "disabled"; }; }; From 57337b252442128605f89a3e96df128c2e5404bf Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Tue, 5 Oct 2021 23:24:21 +0900 Subject: [PATCH 369/574] arm64: dts: apple: t8103: Rename clk24 to clkref We now know that this frequency comes from the external reference oscillator and is used for various SoC blocks, and isn't just a random 24MHz clock, so let's call it something more appropriate. Reviewed-by: Mark Kettenis Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 8203c60d4819..33c9ea6c7c63 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -96,11 +96,11 @@ ; }; - clk24: clock-24m { + clkref: clock-ref { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; - clock-output-names = "clk24"; + clock-output-names = "clkref"; }; soc { @@ -114,7 +114,7 @@ i2c0: i2c@235010000 { compatible = "apple,t8103-i2c", "apple,i2c"; reg = <0x2 0x35010000 0x0 0x4000>; - clocks = <&clk24>; + clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = ; pinctrl-0 = <&i2c0_pins>; @@ -127,7 +127,7 @@ i2c1: i2c@235014000 { compatible = "apple,t8103-i2c", "apple,i2c"; reg = <0x2 0x35014000 0x0 0x4000>; - clocks = <&clk24>; + clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = ; pinctrl-0 = <&i2c1_pins>; @@ -140,7 +140,7 @@ i2c2: i2c@235018000 { compatible = "apple,t8103-i2c", "apple,i2c"; reg = <0x2 0x35018000 0x0 0x4000>; - clocks = <&clk24>; + clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = ; pinctrl-0 = <&i2c2_pins>; @@ -154,7 +154,7 @@ i2c3: i2c@23501c000 { compatible = "apple,t8103-i2c", "apple,i2c"; reg = <0x2 0x3501c000 0x0 0x4000>; - clocks = <&clk24>; + clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = ; pinctrl-0 = <&i2c3_pins>; @@ -167,7 +167,7 @@ i2c4: i2c@235020000 { compatible = "apple,t8103-i2c", "apple,i2c"; reg = <0x2 0x35020000 0x0 0x4000>; - clocks = <&clk24>; + clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = ; pinctrl-0 = <&i2c4_pins>; @@ -188,7 +188,7 @@ * TODO: figure out the clocking properly, there may * be a third selectable clock. */ - clocks = <&clk24>, <&clk24>; + clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; power-domains = <&ps_uart0>; status = "disabled"; @@ -200,7 +200,7 @@ reg-io-width = <4>; interrupt-parent = <&aic>; interrupts = ; - clocks = <&clk24>, <&clk24>; + clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; power-domains = <&ps_uart2>; status = "disabled"; @@ -327,7 +327,7 @@ wdt: watchdog@23d2b0000 { compatible = "apple,t8103-wdt", "apple,wdt"; reg = <0x2 0x3d2b0000 0x0 0x4000>; - clocks = <&clk24>; + clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = ; }; From 8adf987ce08275433a7b2eb281a19785b5d30c30 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Sun, 12 Dec 2021 10:40:16 +0900 Subject: [PATCH 370/574] arm64: dts: apple: t8103: Sort nodes by address We decided to keep SoC nodes sorted by address for sanity; fix a couple that slipped into the wrong place. Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103.dtsi | 56 ++++++++++++++-------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 33c9ea6c7c63..4950e6340995 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -274,34 +274,6 @@ }; }; - pmgr_mini: power-management@23d280000 { - compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2 0x3d280000 0 0x4000>; - }; - - pinctrl_aop: pinctrl@24a820000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x4a820000 0x0 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aop 0 0 42>; - apple,npins = <42>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = , - , - , - , - , - , - ; - }; - pinctrl_nub: pinctrl@23d1f0000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x3d1f0000 0x0 0x4000>; @@ -324,6 +296,13 @@ ; }; + pmgr_mini: power-management@23d280000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3d280000 0 0x4000>; + }; + wdt: watchdog@23d2b0000 { compatible = "apple,t8103-wdt", "apple,wdt"; reg = <0x2 0x3d2b0000 0x0 0x4000>; @@ -353,6 +332,27 @@ ; }; + pinctrl_aop: pinctrl@24a820000 { + compatible = "apple,t8103-pinctrl", "apple,pinctrl"; + reg = <0x2 0x4a820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aop 0 0 42>; + apple,npins = <42>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + pcie0_dart_0: dart@681008000 { compatible = "apple,t8103-dart"; reg = <0x6 0x81008000 0x0 0x4000>; From 301f651614c3396d711a8cc3f92f6fb95b12f5c5 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 13:50:42 +0900 Subject: [PATCH 371/574] dt-bindings: mailbox: apple,mailbox: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The mailbox driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Reviewed-by: Sven Peter Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml index 2c1704b34e7a..c4255f42e801 100644 --- a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml @@ -56,6 +56,9 @@ properties: "#mbox-cells": const: 0 + power-domains: + maxItems: 1 + required: - compatible - reg From c96ebc5fde274edcc02543dcfb6a1ee097f98070 Mon Sep 17 00:00:00 2001 From: David Virag Date: Mon, 6 Dec 2021 16:31:17 +0100 Subject: [PATCH 372/574] dt-bindings: arm: samsung: document jackpotlte board binding Add binding for the jackpotlte board (Samsung Galaxy A8 (2018)). Signed-off-by: David Virag Reviewed-by: Rob Herring Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20211206153124.427102-4-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index ef6dc14be4b5..d88571202713 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -199,6 +199,12 @@ properties: - samsung,exynos7-espresso # Samsung Exynos7 Espresso - const: samsung,exynos7 + - description: Exynos7885 based boards + items: + - enum: + - samsung,jackpotlte # Samsung Galaxy A8 (2018) + - const: samsung,exynos7885 + - description: Exynos Auto v9 based boards items: - enum: From 86a3a7f8a42bcdda6281b949d7e78e6e20ddc8ff Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 13:51:33 +0100 Subject: [PATCH 373/574] ARM: tegra: Add compatible string for built-in ASIX on Colibri boards The device tree node for the built-in ASIX Ethernet device on Colibri boards needs a compatible string in order to pass DT schema validation. Add the USB VID,PID compatible string as required by the DT schema for USB devices. Reviewed-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 28e22097578d..b1f2f7f82928 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -691,6 +691,7 @@ #size-cells = <0>; asix@1 { + compatible = "usbb95,772b"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index b585831e3212..febcb403412c 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -953,6 +953,7 @@ #size-cells = <0>; asix@1 { + compatible = "usbb95,772b"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; }; From e1808b09df868135240b6b489b692e105d0b17a7 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 13:57:40 +0100 Subject: [PATCH 374/574] ARM: tegra: Remove PHY reset GPIO references from USB controller node The PHY reset GPIO references belong in the USB PHY nodes, where they already exist. There is no need to keep them in the USB controller's device tree node as well. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-harmony.dts | 2 -- arch/arm/boot/dts/tegra20-paz00.dts | 2 -- arch/arm/boot/dts/tegra20-seaboard.dts | 2 -- arch/arm/boot/dts/tegra20-trimslice.dts | 2 -- arch/arm/boot/dts/tegra20-ventana.dts | 2 -- 5 files changed, 10 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index a8494378c382..f560bf743a19 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -595,8 +595,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 1fd5a7458c7a..12c245869a74 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -533,8 +533,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index ca7adeb1fdd9..98e61068b981 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -742,8 +742,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index dd05e2c87c29..8bb0eaa610f2 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -349,8 +349,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 4284054ebd2c..b1c92ba789be 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -556,8 +556,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { From c98167bbe865591351df10fd88f759f41006d060 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 13:59:59 +0100 Subject: [PATCH 375/574] ARM: tegra: Add dummy backlight power supplies The Medcom Wide and PAZ00 boards don't specify the power supply for the backlight, which means that the Linux driver will provide a dummy one. Wire up an explicit dummy to also make the DT schema validation succeed. Unfortunately I don't have access to the schematics for the Medcom Wide, so I don't know if a more accurate description is possible. The AC100 (PAZ00) schematics from here: https://www.s-manuals.com/pdf/motherboard/compal/compal_la-6352p_r1.0a_schematics.pdf aren't entirely clear which one of the supplies powers backlight, but the panel supply is probably close enough. Based on work by David Heidelberg . Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-medcom-wide.dts | 3 +++ arch/arm/boot/dts/tegra20-paz00.dts | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index cb6199d7d224..f144487c5da3 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -54,6 +54,9 @@ brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; + + /* close enough */ + power-supply = <&vdd_3v3_reg>; }; panel: panel { diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 12c245869a74..5ce6a1ff93de 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -571,6 +571,9 @@ brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; default-brightness-level = <10>; + + /* close enough */ + power-supply = <&vdd_pnl_reg>; }; clk32k_in: clock-32k { From 9b34a2a1bc6e29562d0a2a2f77934d8829daedb4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:01:53 +0100 Subject: [PATCH 376/574] ARM: tegra: Use correct vendor prefix for Invensense The correct vendor prefix for Invensense is "invensense," rather than "invn,". Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-seaboard.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 98e61068b981..f9309c07a9f2 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -358,7 +358,7 @@ }; gyrometer@68 { - compatible = "invn,mpu3050"; + compatible = "invensense,mpu3050"; reg = <0x68>; interrupt-parent = <&gpio>; interrupts = ; From fe3c94e8e7e458dca28024e39fdaad537b2ea28c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:03:00 +0100 Subject: [PATCH 377/574] ARM: tegra: Remove unsupported properties on Apalis The +V1.2_VDD_CORE regulator on Apalis and Colibri boards uses the unsupported ti,vsel{0,1}-state-low properties. It turns out that these are in fact the default and can be overridden by ti,vsel{0,1}-state-high properties if needed. Drop them since they are not needed. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 3 --- arch/arm/boot/dts/tegra30-apalis.dtsi | 3 --- arch/arm/boot/dts/tegra30-colibri.dtsi | 3 --- 3 files changed, 9 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 6fe775b2b38d..380f22a35821 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -1050,9 +1050,6 @@ regulator-max-microvolt = <1400000>; regulator-boot-on; regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; }; }; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 7df2841690d7..9bdc4cb71449 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1033,9 +1033,6 @@ regulator-max-microvolt = <1400000>; regulator-boot-on; regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; }; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index febcb403412c..9bf8170fee79 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -901,9 +901,6 @@ regulator-max-microvolt = <1400000>; regulator-boot-on; regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; }; }; From e6cc64655480de215993cabec45d1f32bb1f5857 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Wed, 8 Dec 2021 20:36:05 +0300 Subject: [PATCH 378/574] ARM: tegra: nexus7: Drop clock-frequency from NFC node The clock-frequency property was never used and is deprecated now. Remove it from Nexus 7 device-tree. Signed-off-by: David Heidelberg Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi | 1 - arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi | 2 -- 2 files changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi index a044dbd200a9..564cfcde21a9 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi @@ -137,7 +137,6 @@ nfc@28 { compatible = "nxp,pn544-i2c"; reg = <0x28>; - clock-frequency = <100000>; interrupt-parent = <&gpio>; interrupts = ; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi index a681ad51fddd..cd63e0ef7445 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi @@ -223,8 +223,6 @@ compatible = "nxp,pn544-i2c"; reg = <0x2a>; - clock-frequency = <100000>; - interrupt-parent = <&gpio>; interrupts = ; From e3cc9c1c51f872629e860ef3b780ddf07f515123 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:06:16 +0100 Subject: [PATCH 379/574] ARM: tegra: Remove stray #reset-cells property The Ouya board specifies the #reset-cells property for the GPIO controller. Since the GPIO controller doesn't provide reset controls this is not needed, so they can be dropped. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-ouya.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 9e59d9bd6b35..9a774500cb88 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -70,7 +70,6 @@ gpio: gpio@6000d000 { gpio-ranges = <&pinmux 0 0 248>; - #reset-cells = <1>; }; pinmux@70000868 { From 695494bb969a6070663c20425608c7b72f22887f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:07:30 +0100 Subject: [PATCH 380/574] ARM: tegra: Fix SLINK compatible string on Tegra30 The SLINK controller found on Tegra30 is not compatible with its predecessor found on Tegra20. Drop the fallback compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index ae3df73c20a7..46befba0bc72 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -666,7 +666,7 @@ }; spi@7000d400 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000d400 0x200>; interrupts = ; #address-cells = <1>; @@ -680,7 +680,7 @@ }; spi@7000d600 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000d600 0x200>; interrupts = ; #address-cells = <1>; @@ -694,7 +694,7 @@ }; spi@7000d800 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000d800 0x200>; interrupts = ; #address-cells = <1>; @@ -708,7 +708,7 @@ }; spi@7000da00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000da00 0x200>; interrupts = ; #address-cells = <1>; @@ -722,7 +722,7 @@ }; spi@7000dc00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000dc00 0x200>; interrupts = ; #address-cells = <1>; @@ -736,7 +736,7 @@ }; spi@7000de00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000de00 0x200>; interrupts = ; #address-cells = <1>; From b716d046041e19af9ba188bd2865e141f749a76a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:08:32 +0100 Subject: [PATCH 381/574] ARM: tegra: Fix I2C mux reset GPIO reference on Cardhu Use the correct "reset-gpios" property for the I2C mux reset GPIO reference instead of the deprecated "reset-gpio" property. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 12e185846dcb..c2a56eb0b9fa 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -210,7 +210,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; - reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; }; }; From c6e331a2bb0696075d28810e1afd5c35658c240e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Dec 2021 13:49:02 +0100 Subject: [PATCH 382/574] ARM: tegra: Avoid phandle indirection on Ouya Move the default state pinmux definition into the pinmux node. There's no need for the indirection via the phandle. Note that the phandle indirection is kept for the EMC operating performance point tables because they reference nodes that are defined in an external file. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-ouya.dts | 8136 ++++++++++++++-------------- 1 file changed, 4202 insertions(+), 3934 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 9a774500cb88..b28c5504e1b1 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -75,8 +75,1926 @@ pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; + state_default: pinmux { - /* located at $state_default below */ + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pwr1_pc1 { + nvidia,pins = "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat4_pd1 { + nvidia,pins = "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat7_pd4 { + nvidia,pins = "sdmmc3_dat7_pd4"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_hsync_pd7 { + nvidia,pins = "vi_hsync_pd7"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d0_pe0 { + nvidia,pins = "lcd_d0_pe0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d1_pe1 { + nvidia,pins = "lcd_d1_pe1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d2_pe2 { + nvidia,pins = "lcd_d2_pe2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d3_pe3 { + nvidia,pins = "lcd_d3_pe3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d4_pe4 { + nvidia,pins = "lcd_d4_pe4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d5_pe5 { + nvidia,pins = "lcd_d5_pe5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d6_pe6 { + nvidia,pins = "lcd_d6_pe6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d7_pe7 { + nvidia,pins = "lcd_d7_pe7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d8_pf0 { + nvidia,pins = "lcd_d8_pf0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d9_pf1 { + nvidia,pins = "lcd_d9_pf1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d10_pf2 { + nvidia,pins = "lcd_d10_pf2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d11_pf3 { + nvidia,pins = "lcd_d11_pf3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d12_pf4 { + nvidia,pins = "lcd_d12_pf4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d13_pf5 { + nvidia,pins = "lcd_d13_pf5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d14_pf6 { + nvidia,pins = "lcd_d14_pf6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d15_pf7 { + nvidia,pins = "lcd_d15_pf7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad1_pg1 { + nvidia,pins = "gmi_ad1_pg1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad3_pg3 { + nvidia,pins = "gmi_ad3_pg3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad7_pg7 { + nvidia,pins = "gmi_ad7_pg7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad14_ph6 { + nvidia,pins = "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wr_n_pi0 { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_oe_n_pi1 { + nvidia,pins = "gmi_oe_n_pi1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_de_pj1 { + nvidia,pins = "lcd_de_pj1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs1_n_pj2 { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_hsync_pj3 { + nvidia,pins = "lcd_hsync_pj3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_vsync_pj4 { + nvidia,pins = "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d2_pl0 { + nvidia,pins = "vi_d2_pl0"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d3_pl1 { + nvidia,pins = "vi_d3_pl1"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d5_pl3 { + nvidia,pins = "vi_d5_pl3"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d7_pl5 { + nvidia,pins = "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d9_pl7 { + nvidia,pins = "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d16_pm0 { + nvidia,pins = "lcd_d16_pm0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d17_pm1 { + nvidia,pins = "lcd_d17_pm1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d18_pm2 { + nvidia,pins = "lcd_d18_pm2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d19_pm3 { + nvidia,pins = "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d20_pm4 { + nvidia,pins = "lcd_d20_pm4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d21_pm5 { + nvidia,pins = "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d22_pm6 { + nvidia,pins = "lcd_d22_pm6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d23_pm7 { + nvidia,pins = "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sdout_pn5 { + nvidia,pins = "lcd_sdout_pn5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_dc0_pn6 { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d0_pt4 { + nvidia,pins = "vi_d0_pt4"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "clk_12m_out"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs1_n_pw0 { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_m1_pw1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_cs0_n_px6 { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sdin_pz2 { + nvidia,pins = "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sck_pz4 { + nvidia,pins = "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_prsnt_n_pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_prsnt_n_pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_groups { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; }; }; @@ -279,12 +2197,2291 @@ nvidia,sys-clock-req-active-high; }; - mc_timings: memory-controller@7000f000 { - /* timings located at &mc_timings below */ + memory-controller@7000f000 { + emc-timings-0 { + nvidia,ram-code = <0>; /* Samsung RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix M RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-2 { + nvidia,ram-code = <2>; /* Hynix A RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75e30303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74e30303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x74430504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x74040a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; }; - emc_timings: memory-controller@7000f400 { - /* timings located at &emc_timings below */ + memory-controller@7000f400 { + emc-timings-0 { + nvidia,ram-code = <0>; /* Samsung RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000006 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000007 /* EMC_TXSR */ + 0x00000007 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000d /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000e /* EMC_TXSR */ + 0x0000000e /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000066 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ce /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix M RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000006 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000007 /* EMC_TXSR */ + 0x00000007 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000d /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000e /* EMC_TXSR */ + 0x0000000e /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000066 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ce /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + + emc-timings-2 { + nvidia,ram-code = <2>; /* Hynix A RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000007 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000008 /* EMC_TXSR */ + 0x00000008 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000f /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000010 /* EMC_TXSR */ + 0x00000010 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001e /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000020 /* EMC_TXSR */ + 0x00000020 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x0000003d /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000040 /* EMC_TXSR */ + 0x00000040 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000076 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000007c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00044000 /* EMC_DLL_XFORM_DQS0 */ + 0x00044000 /* EMC_DLL_XFORM_DQS1 */ + 0x00044000 /* EMC_DLL_XFORM_DQS2 */ + 0x00044000 /* EMC_DLL_XFORM_DQS3 */ + 0x00044000 /* EMC_DLL_XFORM_DQS4 */ + 0x00044000 /* EMC_DLL_XFORM_DQS5 */ + 0x00044000 /* EMC_DLL_XFORM_DQS6 */ + 0x00044000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00058000 /* EMC_DLL_XFORM_DQ0 */ + 0x00058000 /* EMC_DLL_XFORM_DQ1 */ + 0x00058000 /* EMC_DLL_XFORM_DQ2 */ + 0x00058000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0148000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ee /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000f8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000c /* EMC_DLL_XFORM_DQS0 */ + 0x007fc00a /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00d0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; }; hda@70030000 { @@ -592,3935 +4789,6 @@ }; }; }; -&mc_timings { - emc-timings-0 { - nvidia,ram-code = <0>; /* Samsung RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emem-configuration = < - 0x00030003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75830303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emem-configuration = < - 0x00010003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74630303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x00000006 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emem-configuration = < - 0x0000000c /* MC_EMEM_ARB_CFG */ - 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7086120a /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emem-configuration = < - 0x00000018 /* MC_EMEM_ARB_CFG */ - 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x712c2414 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - emc-timings-1 { - nvidia,ram-code = <1>; /* Hynix M RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emem-configuration = < - 0x00030003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75830303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emem-configuration = < - 0x00010003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74630303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x00000006 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emem-configuration = < - 0x0000000c /* MC_EMEM_ARB_CFG */ - 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7086120a /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emem-configuration = < - 0x00000018 /* MC_EMEM_ARB_CFG */ - 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x712c2414 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - emc-timings-2 { - nvidia,ram-code = <2>; /* Hynix A RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emem-configuration = < - 0x00030003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75e30303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emem-configuration = < - 0x00010003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74e30303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x74430504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x00000006 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x74040a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emem-configuration = < - 0x0000000c /* MC_EMEM_ARB_CFG */ - 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7086120a /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emem-configuration = < - 0x00000018 /* MC_EMEM_ARB_CFG */ - 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x712c2414 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; -}; -&emc_timings { - emc-timings-0 { - nvidia,ram-code = <0>; /* Samsung RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000006 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000007 /* EMC_TXSR */ - 0x00000007 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x0000000d /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000e /* EMC_TXSR */ - 0x0000000e /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000066 /* EMC_RFC */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x00000bf0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000010 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c30 /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x001d0084 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000ce /* EMC_RFC */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000004 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001820 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000012 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000020 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000007 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001860 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf0070191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000800a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f0000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; - }; - }; - emc-timings-1 { - nvidia,ram-code = <1>; /* Hynix M RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000006 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000007 /* EMC_TXSR */ - 0x00000007 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x0000000d /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000e /* EMC_TXSR */ - 0x0000000e /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000066 /* EMC_RFC */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x00000bf0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000010 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c30 /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x001d0084 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000ce /* EMC_RFC */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000004 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001820 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000012 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000020 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000007 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001860 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf0070191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000800a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f0000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; - }; - }; - emc-timings-2 { - nvidia,ram-code = <2>; /* Hynix A RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000007 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000008 /* EMC_TXSR */ - 0x00000008 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x0000000f /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000010 /* EMC_TXSR */ - 0x00000010 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001e /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000020 /* EMC_TXSR */ - 0x00000020 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x0000003d /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000040 /* EMC_TXSR */ - 0x00000040 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000076 /* EMC_RFC */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x00000bf0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000007c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000010 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c30 /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x001d0084 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00044000 /* EMC_DLL_XFORM_DQS0 */ - 0x00044000 /* EMC_DLL_XFORM_DQS1 */ - 0x00044000 /* EMC_DLL_XFORM_DQS2 */ - 0x00044000 /* EMC_DLL_XFORM_DQS3 */ - 0x00044000 /* EMC_DLL_XFORM_DQS4 */ - 0x00044000 /* EMC_DLL_XFORM_DQS5 */ - 0x00044000 /* EMC_DLL_XFORM_DQS6 */ - 0x00044000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00058000 /* EMC_DLL_XFORM_DQ0 */ - 0x00058000 /* EMC_DLL_XFORM_DQ1 */ - 0x00058000 /* EMC_DLL_XFORM_DQ2 */ - 0x00058000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0148000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000ee /* EMC_RFC */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001820 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000012 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000f8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000020 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000007 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001860 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf0070191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000c /* EMC_DLL_XFORM_DQS0 */ - 0x007fc00a /* EMC_DLL_XFORM_DQS1 */ - 0x00000008 /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000c /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00d0000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; - }; - }; -}; -&state_default { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr0_pb2 { - nvidia,pins = "lcd_pwr0_pb2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pclk_pb3 { - nvidia,pins = "lcd_pclk_pb3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr1_pc1 { - nvidia,pins = "lcd_pwr1_pc1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat5_pd0 { - nvidia,pins = "sdmmc3_dat5_pd0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat4_pd1 { - nvidia,pins = "sdmmc3_dat4_pd1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_dc1_pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat6_pd3 { - nvidia,pins = "sdmmc3_dat6_pd3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat7_pd4 { - nvidia,pins = "sdmmc3_dat7_pd4"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d1_pd5 { - nvidia,pins = "vi_d1_pd5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_vsync_pd6 { - nvidia,pins = "vi_vsync_pd6"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_hsync_pd7 { - nvidia,pins = "vi_hsync_pd7"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d0_pe0 { - nvidia,pins = "lcd_d0_pe0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d1_pe1 { - nvidia,pins = "lcd_d1_pe1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d2_pe2 { - nvidia,pins = "lcd_d2_pe2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d3_pe3 { - nvidia,pins = "lcd_d3_pe3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d4_pe4 { - nvidia,pins = "lcd_d4_pe4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d5_pe5 { - nvidia,pins = "lcd_d5_pe5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d6_pe6 { - nvidia,pins = "lcd_d6_pe6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d7_pe7 { - nvidia,pins = "lcd_d7_pe7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d8_pf0 { - nvidia,pins = "lcd_d8_pf0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d9_pf1 { - nvidia,pins = "lcd_d9_pf1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d10_pf2 { - nvidia,pins = "lcd_d10_pf2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d11_pf3 { - nvidia,pins = "lcd_d11_pf3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d12_pf4 { - nvidia,pins = "lcd_d12_pf4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d13_pf5 { - nvidia,pins = "lcd_d13_pf5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d14_pf6 { - nvidia,pins = "lcd_d14_pf6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d15_pf7 { - nvidia,pins = "lcd_d15_pf7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad1_pg1 { - nvidia,pins = "gmi_ad1_pg1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad3_pg3 { - nvidia,pins = "gmi_ad3_pg3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad4_pg4 { - nvidia,pins = "gmi_ad4_pg4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_dqs_pi2 { - nvidia,pins = "gmi_dqs_pi2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wait_pi7 { - nvidia,pins = "gmi_wait_pi7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_de_pj1 { - nvidia,pins = "lcd_de_pj1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_hsync_pj3 { - nvidia,pins = "lcd_hsync_pj3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_vsync_pj4 { - nvidia,pins = "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d2_pl0 { - nvidia,pins = "vi_d2_pl0"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d3_pl1 { - nvidia,pins = "vi_d3_pl1"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d4_pl2 { - nvidia,pins = "vi_d4_pl2"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d5_pl3 { - nvidia,pins = "vi_d5_pl3"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d6_pl4 { - nvidia,pins = "vi_d6_pl4"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d7_pl5 { - nvidia,pins = "vi_d7_pl5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d8_pl6 { - nvidia,pins = "vi_d8_pl6"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d9_pl7 { - nvidia,pins = "vi_d9_pl7"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d16_pm0 { - nvidia,pins = "lcd_d16_pm0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d17_pm1 { - nvidia,pins = "lcd_d17_pm1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d18_pm2 { - nvidia,pins = "lcd_d18_pm2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d19_pm3 { - nvidia,pins = "lcd_d19_pm3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d20_pm4 { - nvidia,pins = "lcd_d20_pm4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d21_pm5 { - nvidia,pins = "lcd_d21_pm5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d22_pm6 { - nvidia,pins = "lcd_d22_pm6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d23_pm7 { - nvidia,pins = "lcd_d23_pm7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_cs0_n_pn4 { - nvidia,pins = "lcd_cs0_n_pn4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sdout_pn5 { - nvidia,pins = "lcd_sdout_pn5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_dc0_pn6 { - nvidia,pins = "lcd_dc0_pn6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_pclk_pt0 { - nvidia,pins = "vi_pclk_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_mclk_pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d10_pt2 { - nvidia,pins = "vi_d10_pt2"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d11_pt3 { - nvidia,pins = "vi_d11_pt3"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d0_pt4 { - nvidia,pins = "vi_d0_pt4"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck_pu7 { - nvidia,pins = "jtag_rtck_pu7"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "clk_12m_out"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_hsync_pv6 { - nvidia,pins = "crt_hsync_pv6"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_vsync_pv7 { - nvidia,pins = "crt_vsync_pv7"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_cs1_n_pw0 { - nvidia,pins = "lcd_cs1_n_pw0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_m1_pw1 { - nvidia,pins = "lcd_m1_pw1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_cs1_n_pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_sck_px2 { - nvidia,pins = "spi2_sck_px2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_mosi_px4 { - nvidia,pins = "spi1_mosi_px4"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_sck_px5 { - nvidia,pins = "spi1_sck_px5"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_cs0_n_px6 { - nvidia,pins = "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_miso_px7 { - nvidia,pins = "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sdin_pz2 { - nvidia,pins = "lcd_sdin_pz2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_wr_n_pz3 { - nvidia,pins = "lcd_wr_n_pz3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sck_pz4 { - nvidia,pins = "lcd_sck_pz4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_rst_n_pcc3 { - nvidia,pins = "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_rst_n_pcc6 { - nvidia,pins = "pex_l2_rst_n_pcc6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_clkreq_n_pcc7 { - nvidia,pins = "pex_l2_clkreq_n_pcc7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_prsnt_n_pdd0 { - nvidia,pins = "pex_l0_prsnt_n_pdd0"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_prsnt_n_pdd4 { - nvidia,pins = "pex_l1_prsnt_n_pdd4"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_prsnt_n_pdd7 { - nvidia,pins = "pex_l2_prsnt_n_pdd7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "dev3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - drive_groups { - nvidia,pins = "drive_gma", - "drive_gmb", - "drive_gmc", - "drive_gmd"; - nvidia,pull-down-strength = <9>; - nvidia,pull-up-strength = <9>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; -}; &emc_icc_dvfs_opp_table { /delete-node/ opp-900000000-1350; From b405066bd3e04e9d0c34a25db85adf19c08274ef Mon Sep 17 00:00:00 2001 From: Nikola Milosavljevic Date: Sun, 12 Dec 2021 00:13:49 +0300 Subject: [PATCH 383/574] ARM: tegra: Add device-tree for ASUS Transformer EeePad TF101 Add device-tree for Tegra20-based ASUS Transformer EeePad TF101. Link: https://wiki.postmarketos.org/wiki/ASUS_Eee_Pad_Transformer_(asus-tf101) Co-developed-by: David Heidelberg Signed-off-by: David Heidelberg Co-developed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel Co-developed-by: Antoni Aloy Torrens Signed-off-by: Antoni Aloy Torrens Signed-off-by: Nikola Milosavljevic Co-developed-by: Dmitry Osipenko Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra20-asus-tf101.dts | 1280 ++++++++++++++++++++++ arch/arm/boot/dts/tegra20.dtsi | 2 +- 3 files changed, 1282 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/tegra20-asus-tf101.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..f51edce19a60 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1304,6 +1304,7 @@ dtb-$(CONFIG_MACH_SUNIV) += \ suniv-f1c100s-licheepi-nano.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-acer-a500-picasso.dtb \ + tegra20-asus-tf101.dtb \ tegra20-harmony.dtb \ tegra20-colibri-eval-v3.dtb \ tegra20-colibri-iris.dtb \ diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts new file mode 100644 index 000000000000..020172ee7340 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts @@ -0,0 +1,1280 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include +#include + +#include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" +#include "tegra20-cpu-opp-microvolt.dtsi" + +/ { + model = "ASUS EeePad Transformer TF101"; + compatible = "asus,tf101", "nvidia,tegra20"; + chassis-type = "convertible"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* MicroSD */ + mmc2 = &sdmmc1; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@0 { + reg = <0x00000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@2ffe0000 { + compatible = "ramoops"; + reg = <0x2ffe0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + linux,cma@30000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x30000000 0x10000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port@0 { + lcd_output: endpoint { + remote-endpoint = <&lvds_encoder_input>; + bus-width = <18>; + }; + }; + }; + }; + + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + hdmi-supply = <&vdd_hdmi_en>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + gpio@6000d000 { + charging-enable-hog { + gpio-hog; + gpios = ; + output-low; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + + lm1 { + nvidia,pins = "lm1"; + nvidia,function = "rsvd3"; + }; + + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + + gpv { + nvidia,pins = "gpv", "slxa"; + nvidia,function = "pcie"; + }; + + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lpw0", + "lpw2", "lsc0", "lsc1", "lsck", "lsda", + "lspi", "lvp1", "lvs"; + nvidia,function = "displaya"; + }; + + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; + nvidia,function = "sdio3"; + }; + + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + + slxd { + nvidia,pins = "slxd"; + nvidia,function = "spdif"; + }; + + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "dap1", "dap4", + "dte", "ddc", "dtf", "gma", "gmc", + "gme", "gpu", "gpu7", "gpv", "i2cp", + "irrx", "irtx", "pta", "rm", "sdc", + "sdd", "slxc", "slxd", "slxk", "spdi", + "spdo", "uac", "uad", + "uda", "csus"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_ate { + nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd", + "owc", "spia", "spib", "spic", + "spid", "spie", "spig", "slxa"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + + conf_crtp { + nvidia,pins = "crtp", "spih"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_spif { + nvidia,pins = "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsck", "lsda", "lsdi", "lvp0"; + nvidia,tristate = ; + }; + + conf_kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "uaa", "uab", + "uca", "ucb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lsc1", "lspi", + "lvp1", "lvs", "pmc", "sdb"; + nvidia,tristate = ; + }; + + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_csus { + nvidia,pins = "drive_csus"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006040 { + compatible = "nvidia,tegra20-hsuart"; + /* GPS BCM4751 */ + }; + + serial@70006200 { + compatible = "nvidia,tegra20-hsuart"; + status = "okay"; + + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + /* PLLP 216MHz / 16 / 4 */ + max-speed = <3375000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_sys>; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + }; + }; + + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* Aichi AMI306 digital compass */ + magnetometer@e { + compatible = "asahi-kasei,ak8974"; + reg = <0xe>; + + avdd-supply = <&vdd_3v3_sys>; + dvdd-supply = <&vdd_1v8_sys>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0x83>; + micdet-delay = <100>; + + gpio-cfg = < + 0xffffffff /* don't touch */ + 0xffffffff /* don't touch */ + 0x00000000 /* Speaker-enable GPIO, output, low */ + 0x00000400 /* Mic bias current detect */ + 0xffffffff /* don't touch */ + >; + + AVDD-supply = <&vdd_1v8_sys>; + CPVDD-supply = <&vdd_1v8_sys>; + DBVDD-supply = <&vdd_1v8_sys>; + DCVDD-supply = <&vdd_1v8_sys>; + }; + + /* Atmel MXT1386 Touchscreen */ + touchscreen@5b { + compatible = "atmel,maxtouch"; + reg = <0x5b>; + + interrupt-parent = <&gpio>; + interrupts = ; + + reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + + atmel,wakeup-method = ; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + vlogic-supply = <&vdd_1v8_sys>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0xf>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_sys>; + vddio-supply = <&vdd_1v8_sys>; + + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c2: i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_sys>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + vdd_core: sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + }; + + vdd_cpu: sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; + regulator-coupled-with = <&vdd_core &rtc_vdd>; + regulator-coupled-max-spread = <550000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + rtc_vdd: ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&vdd_core &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-rtc-regulator; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + nct1008: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&vdd_3v3_sys>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <100>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + memory-controller@7000f400 { + nvidia,use-ram-code; + + emc-tables@3 { + reg = <0x3>; + + #address-cells = <1>; + #size-cells = <0>; + + lpddr2 { + compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; + revision-id1 = <1>; + density = <2048>; + io-width = <16>; + }; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dc010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e0 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; + + /* Peripheral USB via ASUS connector */ + usb@c5000000 { + compatible = "nvidia,tegra20-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@c5000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + /* Dock's USB port */ + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + vbus-supply = <&vdd_5v0_sys>; + }; + + sdmmc1: mmc@c8000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <40000000>; + + max-frequency = <40000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + + /* Azurewave AW-NH615 BCM4329B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc3: mmc@c8000400 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + sdmmc4: mmc@c8000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_3v3_sys>; + non-removable; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_3v3_sys>; + pwms = <&pwm 2 4000000>; + + brightness-levels = <7 255>; + num-interpolated-steps = <248>; + default-brightness-level = <20>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + dock-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; + wakeup-source; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + display-panel { + compatible = "panel-lvds"; + + /* AUO B101EW05 using custom timings */ + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; + power-supply = <&vdd_pnl_reg>; + + width-mm = <218>; + height-mm = <135>; + + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <71200000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <8>; + hback-porch = <18>; + hsync-len = <184>; + vsync-len = <3>; + vfront-porch = <4>; + vback-porch = <8>; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&lvds_encoder_output>; + }; + }; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&i2c2>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + smart-battery@b { + compatible = "ti,bq20z75", "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&mains>; + }; + }; + }; + + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + remote-endpoint = <&lcd_output>; + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + vdd_5v0_sys: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "pcie_vdd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + vdd_pnl_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_1v8_sys: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_vs"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_hdmi_en: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_hdmi_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "asus,tegra-audio-wm8903-tf101", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Asus EeePad Transformer WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,headset; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + thermal-zones { + /* + * NCT1008 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone is a simpler solution which prevents TF101 from + * getting too hot from a user's tactile perspective. + * The CPU zone is intended to protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 0>; + + trips { + trip0: skin-alert { + /* start throttling at 60C */ + temperature = <60000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 70C */ + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 1>; + + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + power-off-delay-us = <200>; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; +}; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9508248fd166..6f493a8a8a9f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -523,7 +523,7 @@ status = "disabled"; }; - i2c@7000c400 { + i2c2: i2c@7000c400 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c400 0x100>; interrupts = ; From 91ead34f47c907d931a1f6d396d7dfbbc068263a Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:50 +0300 Subject: [PATCH 384/574] ARM: tegra: Add common device-tree base for Tegra30 ASUS Transformers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add common DTSI for Tegra30 ASUS Transformers. It will be used by multiple device-trees of ASUS devices. The common part initially was born out of the ASUS TF300T tablet's device-tree that was created by Michał Mirosław. It was heavily reworked and improved by Svyatoslav Ryhel, Maxim Schwalm, Ion Agorria et al. [digetx@gmail.com: factored out common part into separate patch and wrote commit message] Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Co-developed-by: Michał Mirosław Signed-off-by: Michał Mirosław Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- .../dts/tegra30-asus-transformer-common.dtsi | 1787 +++++++++++++++++ 1 file changed, 1787 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi new file mode 100644 index 000000000000..85b43a86a26d --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi @@ -0,0 +1,1787 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + chassis-type = "convertible"; + + aliases { + mmc0 = "/mmc@78000600"; /* eMMC */ + mmc1 = "/mmc@78000000"; /* uSD slot */ + mmc2 = "/mmc@78000400"; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + display0 = &lcd; + display1 = &hdmi; + + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@beb00000 { + compatible = "ramoops"; + reg = <0xbeb00000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; /* 2MB */ + no-map; + }; + }; + + host1x@50000000 { + hdmi: hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&hdmi_5v0_sys>; + pll-supply = <&vdd_1v8_vio>; + vdd-supply = <&vdd_3v3_sys>; + + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + }; + }; + + gpio@6000d000 { + init-lpm-in-hog { + gpio-hog; + gpios = , + ; + input; + }; + + init-lpm-out-hog { + gpio-hog; + gpios = , + ; + output-low; + }; + + usb-charge-limit-hog { + gpio-hog; + gpios = ; + output-high; + }; + }; + + vde@6001a000 { + assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; + assigned-clock-rates = <408000000>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cmd { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cd { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_wp { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_rst_n { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + /* I2C pinmux */ + gen1_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + gen2_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + ddc_i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + }; + + pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + hotplug_i2c { + nvidia,pins = "pu4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI pinmux */ + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + hdmi_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-B */ + uartb_txd_rts { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartb_rxd_cts { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-C */ + uartc_rxd_cts { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartc_txd_rts { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-D */ + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2S pinmux */ + dap_i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap_i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_dout { + nvidia,pins = "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap_i2s3 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Sensors pinmux */ + nct_irq { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Asus EC pinmux */ + ec_irqs { + nvidia,pins = "kb_row10_ps2", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ec_reqs { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Memory type bootstrap */ + mem_boostraps { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_wake_n_pdd3", + "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_dc0_pn6", + "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + blink { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC keys */ + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col1_pq1 { + nvidia,pins = "kb_row1_pr1", + "kb_row3_pr3", + "kb_row8_ps0", + "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row12_ps4", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs0_n_pj0 { + nvidia,pins = "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* GPIO keys pinmux */ + power_key { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vol_keys { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Bluetooth */ + bt_shutdown { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + bt_dev_wake { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + bt_host_wake { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_rst_n_pi4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Vibrator control */ + vibrator { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PWM pimnmux */ + pwm_0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pwm_2 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Spdif pinmux */ + spdif_out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5", + "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + /* Broadcom GPS BCM47511 */ + }; + + serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + bluetooth { + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_com>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + pwm@7000a000 { + status = "okay"; + }; + + lcd_ddc: i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000c500 { + status = "okay"; + + /* Aichi AMI306 digital compass */ + magnetometer@e { + compatible = "asahi-kasei,ak8974"; + reg = <0x0e>; + + avdd-supply = <&vdd_3v3_sys>; + dvdd-supply = <&vdd_1v8_vio>; + }; + + /* Dynaimage ambient light sensor */ + light-sensor@1c { + compatible = "dynaimage,al3010"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + vlogic-supply = <&vdd_1v8_vio>; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_vio>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <93750>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + + /* Texas Instruments TPS659110 PMIC */ + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_bat>; + vcc2-supply = <&vdd_5v0_bat>; + vcc3-supply = <&vdd_1v8_vio>; + vcc4-supply = <&vdd_5v0_sys>; + vcc5-supply = <&vdd_5v0_bat>; + vcc6-supply = <&vdd_3v3_sys>; + vcc7-supply = <&vdd_5v0_bat>; + vccio-supply = <&vdd_5v0_bat>; + + pmic-sleep-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + }; + + regulators { + /* VDD1 is not used by Transformers */ + + vddio_ddr: vdd2 { + regulator-name = "vddio_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <1>; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8_vio: vio { + regulator-name = "vdd_1v8_gen"; + /* FIXME: eMMC won't work, if set to 1.8 V */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + /* FIXME: Without this, voltage switching fails */ + regulator-always-on; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3100000>; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* LDO5 is not used by Transformers */ + + ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + ti,regulator-ext-sleep-control = <8>; + }; + }; + }; + + vdd_core: core-regulator@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,enable-vout-discharge; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + /* FIXME: LP1 doesn't work at the moment */ + nvidia,suspend-mode = <2>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x81>; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + i2s@70080400 { /* i2s1 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70080600 { /* i2s3 */ + status = "okay"; + }; + }; + + mmc@78000000 { + status = "okay"; + + /* FIXME: Full 208Mhz clock rate doesn't work reliably */ + max-frequency = <104000000>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + bus-width = <4>; + + vmmc-supply = <&vdd_usd>; /* ldo2 */ + vqmmc-supply = <&vddio_usd>; /* ldo3 */ + }; + + mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_com>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* Azurewave AW-NH615 BCM4329B1 or AW-NH665 BCM4330B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + mmc@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + mmc-ddr-3_3v; + non-removable; + }; + + /* USB via ASUS connector */ + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + /* Dock's USB port */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_5v0_bat>; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 4000000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <40>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu2: cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu3: cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + extcon-keys { + compatible = "gpio-keys"; + interrupt-parent = <&gpio>; + + dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; + wakeup-source; + }; + + lineout-detect { + label = "Audio dock line-out detect"; + gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + interrupt-parent = <&gpio>; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + vdd_5v0_bat: regulator-bat { + compatible = "regulator-fixed"; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_cp: regulator-sby { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_sby"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_5v0_sys: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_1v5_ddr: regulator-ddr { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_3v3_sys: regulator-3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_com: regulator-com { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + hdmi_5v0_sys: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + sound { + nvidia,i2s-controller = <&tegra_i2s1>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,hp-mute-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * Transformers from getting too hot from a user's + * tactile perspective. The CPU zone is intended to + * protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 57C until temperature drops to 56.8C */ + temperature = <57000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 65C */ + temperature = <65000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 75C until temperature drops to 74.8C */ + temperature = <75000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; +}; From a0d7dba8c3c125692405ac3e2db0e9414952c14f Mon Sep 17 00:00:00 2001 From: Maxim Schwalm Date: Sun, 12 Dec 2021 00:13:51 +0300 Subject: [PATCH 385/574] ARM: tegra: Add common device-tree for LVDS display panels of Tegra30 ASUS tablets All Tegra30 ASUS tablets have a similar design pattern in terms of hardware integration of LVDS display panels, like exactly the same GPIOs are used for power and reset, etc. Add a common device-tree for LVDS display panels of Tegra30 ASUS tablets to avoid replicating the boilerplate panel description. [digetx@gmail.com: factored out common part into separate patch and wrote commit message] Co-developed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel Signed-off-by: Maxim Schwalm Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../boot/dts/tegra30-asus-lvds-display.dtsi | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi new file mode 100644 index 000000000000..a047abfa6369 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */ + +/ { + host1x@50000000 { + lcd: dc@54200000 { + rgb { + status = "okay"; + + port@0 { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + display-panel { + power-supply = <&vdd_pnl>; + ddc-i2c-bus = <&lcd_ddc>; + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + + /* Texas Instruments SN75LVDS83B LVDS Transmitter */ + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; +}; From 9b66bd835dfd85efaf5f590f34230d1d75b446f9 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:52 +0300 Subject: [PATCH 386/574] ARM: tegra: Add device-tree for ASUS Transformer Prime TF201 Add device-tree for ASUS Transformer Prime TF201, which is a NVIDIA Tegra30-based 2-in-1 detachable, orignally running Android. Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Prime_(asus-tf201) Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-asus-tf201.dts | 627 +++++++++++++++++++++++ 2 files changed, 628 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-tf201.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f51edce19a60..fcc48f8aa3b4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1321,6 +1321,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-nexus7-grouper-PM269.dtb \ tegra30-asus-nexus7-grouper-E1565.dtb \ tegra30-asus-nexus7-tilapia-E1565.dtb \ + tegra30-asus-tf201.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-asus-tf201.dts b/arch/arm/boot/dts/tegra30-asus-tf201.dts new file mode 100644 index 000000000000..315c6dc068c5 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-tf201.dts @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Prime TF201"; + compatible = "asus,tf201", "nvidia,tegra30"; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Atmel MXT768E touchscreen */ + touchscreen@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + }; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + + magnetometer@e { + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0x80000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0x80000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0x80000048 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000006 + 0x00000001 0x00000000 0x00000004 0x00000004 + 0x04040001 0x000d090c 0x71c6120d 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* TF201 Unknown 1GB LPDDR2 500MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0x80000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0x80000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-500000000 { + clock-frequency = <500000000>; + + nvidia,emem-configuration = < 0x00000007 0x8000005a + 0x00000003 0x00000004 0x0000000e 0x00000009 + 0x0000000c 0x00000002 0x00000002 0x00000008 + 0x00000001 0x00000000 0x00000004 0x00000005 + 0x05040001 0x00100a0e 0x71c8170f 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x00098000 0x00098000 0x00098000 + 0x00098000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x00098000 0x00098000 0x00098000 + 0x00098000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000018 0x00000018 0x00000018 + 0x00000018 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000a0000 0x000a0000 0x000a0000 + 0x000a0000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00120220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x00440084 + 0x00008000 0x00074000 0x00074000 0x00074000 + 0x00074000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000018 0x00000018 0x00000018 + 0x00000018 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00078000 0x00078000 0x00078000 + 0x00078000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010082>; + nvidia,emc-mode-2 = <0x00020004>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000024>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000017 + 0x00000033 0x00000010 0x00000007 0x00000007 + 0x00000007 0x00000002 0x0000000a 0x00000007 + 0x00000007 0x00000003 0x00000002 0x00000000 + 0x00000003 0x00000007 0x00000004 0x0000000d + 0x0000000e 0x000005e9 0x00000000 0x0000017a + 0x00000002 0x00000002 0x00000007 0x00000000 + 0x00000001 0x0000000c 0x00000038 0x00000038 + 0x00000006 0x00000014 0x00000009 0x00000004 + 0x00000002 0x00000680 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0x001d0084 + 0x00008000 0x0002c000 0x0002c000 0x0002c000 + 0x0002c000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000c0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000024 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; + }; + }; + + emc-timings-1 { + /* TF201 Unknown 1GB LPDDR2 500MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x00440084 + 0x00008000 0x00060000 0x00060000 0x00060000 + 0x00060000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000d0000 0x000d0000 0x000d0000 + 0x000d0000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-500000000 { + clock-frequency = <500000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020005>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000002d>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001d + 0x00000040 0x00000014 0x00000008 0x00000007 + 0x00000009 0x00000003 0x0000000d 0x00000008 + 0x00000008 0x00000004 0x00000002 0x00000000 + 0x00000004 0x00000008 0x00000005 0x0000000d + 0x0000000f 0x00000763 0x00000000 0x000001d8 + 0x00000003 0x00000003 0x00000008 0x00000000 + 0x00000001 0x0000000e 0x00000046 0x00000046 + 0x00000008 0x00000019 0x0000000b 0x00000004 + 0x00000002 0x00000820 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0xf0140091 + 0x00008000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x00080220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000b4 0x000d000d 0xa0f10404 0x00000000 + 0x00000000 0x80000fde 0xe0000000 0xff00ff88 >; + }; + }; + }; + + usb-phy@7d000000 { + /delete-property/ nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ + }; + + usb-phy@7d008000 { + /delete-property/ nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ + }; + + display-panel { + compatible = "hannstar,hsd101pww2"; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-533000000-1200; + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-533000000; + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; From 65fce832a97cb7ed3e4896475baabeb7f506de3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Date: Sun, 12 Dec 2021 00:13:53 +0300 Subject: [PATCH 387/574] ARM: tegra: Add device-tree for ASUS Transformer Pad TF300T MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device-tree for ASUS Transformer Pad TF300T, which is a NVIDIA Tegra30-based 2-in-1 detachable, originally running Android. Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(asus-tf300t) Tested-by: Ihor Didenko Tested-by: Andreas Westman Dorcsak Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Co-developed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel Signed-off-by: Michał Mirosław Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-asus-tf300t.dts | 1034 +++++++++++++++++++++ 2 files changed, 1035 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-tf300t.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index fcc48f8aa3b4..71ec43e72380 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1322,6 +1322,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-nexus7-grouper-E1565.dtb \ tegra30-asus-nexus7-tilapia-E1565.dtb \ tegra30-asus-tf201.dtb \ + tegra30-asus-tf300t.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/tegra30-asus-tf300t.dts new file mode 100644 index 000000000000..f47434871a5c --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-tf300t.dts @@ -0,0 +1,1034 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Pad TF300T"; + compatible = "asus,tf300t", "nvidia,tegra30"; + + gpio@6000d000 { + tf300t-init-hog { + gpio-hog; + gpios = ; + output-low; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech EKTH1036 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2240>; + touchscreen-size-y = <1408>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + + magnetometer@e { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Wolfson Microelectronics WM8903 audio codec */ + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + + gpio-cfg = < + 0xffffffff /* don't touch */ + 0xffffffff /* don't touch */ + 0x00000000 /* Speaker-enable GPIO, output, low */ + 0xffffffff /* don't touch */ + 0xffffffff /* don't touch */ + >; + + AVDD-supply = <&vdd_1v8_vio>; + CPVDD-supply = <&vdd_1v8_vio>; + DBVDD-supply = <&vdd_1v8_vio>; + DCVDD-supply = <&vdd_1v8_vio>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00030003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x0000000a 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x00000014 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00030003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0605 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x0000000a 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000005 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x00000014 0xc0000079 + 0x00000003 0x00000004 0x00000011 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00140b11 0x70ea1f12 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00140b10 0x70ea1f11 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x0f000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000003 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000b 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000020 + 0x0000006a 0x00000018 0x00000008 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0155000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xd8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xd8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000016 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000008 + 0x00000008 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xf8000000 0xff00ff49 >; + }; + }; + }; + + display-panel { + compatible = "innolux,g101ice-l01"; + }; + + sound { + compatible = "asus,tegra-audio-wm8903-tf300t", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Asus Transformer Pad TF300T WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "IN1L", "Mic Jack", + "IN2L", "Mic Jack", + "DMICDAT", "Int Mic"; + + nvidia,audio-codec = <&wm8903>; + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,headset; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; From 2602de4800e6058f811b467b40e1cd16a21d0a30 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:54 +0300 Subject: [PATCH 388/574] ARM: tegra: Add device-tree for ASUS Transformer Pad TF300TG Add device-tree for ASUS Transformer Pad TF300TG, which is a NVIDIA Tegra30-based 2-in-1 detachable, originally running Android. It's a variant of the TF300T that has a 3G modem. Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(asus-tf300t) Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-asus-tf300tg.dts | 1087 ++++++++++++++++++++ 2 files changed, 1088 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-tf300tg.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 71ec43e72380..c957986f023c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1323,6 +1323,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-nexus7-tilapia-E1565.dtb \ tegra30-asus-tf201.dtb \ tegra30-asus-tf300t.dtb \ + tegra30-asus-tf300tg.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts new file mode 100644 index 000000000000..96345f821c3d --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts @@ -0,0 +1,1087 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Pad 3G TF300TG"; + compatible = "asus,tf300tg", "nvidia,tegra30"; + + gpio@6000d000 { + tf300tg-init-hog { + gpio-hog; + gpios = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + output-low; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,tristate = ; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech EKTH1036 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2240>; + touchscreen-size-y = <1408>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + + magnetometer@e { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0x8000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0x80000079 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00050000 0x00050000 0x00050000 + 0x00050000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0a00013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x0a000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000020 + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00040000 0x00040000 0x00040000 + 0x00040000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000016 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0600013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + }; + + display-panel { + compatible = "innolux,g101ice-l01"; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; From e6d391a0b29bd083dabc620534892f0d05707501 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:55 +0300 Subject: [PATCH 389/574] ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T Add device-tree for ASUS Transformer Infinity TF700T, which is a NVIDIA Tegra30-based 2-in-1 detachable, originally running Android. Link: https://wiki.postmarketos.org/wiki/Asus_Transformer_Pad_Infinity_TF700T_(asus-tf700t) Tested-by: Andreas Westman Dorcsak Tested-by: Jasper Korten Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Co-developed-by: Dmitry Osipenko Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-asus-tf700t.dts | 823 ++++++++++++++++++++++ 2 files changed, 824 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-tf700t.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c957986f023c..47cd157496f9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1324,6 +1324,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-tf201.dtb \ tegra30-asus-tf300t.dtb \ tegra30-asus-tf300tg.dtb \ + tegra30-asus-tf700t.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/tegra30-asus-tf700t.dts new file mode 100644 index 000000000000..18a9bfa5e97b --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-tf700t.dts @@ -0,0 +1,823 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" + +/ { + model = "Asus Transformer Infinity TF700T"; + compatible = "asus,tf700t", "nvidia,tegra30"; + + host1x@50000000 { + lcd: dc@54200000 { + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + + rgb { + status = "okay"; + + port@0 { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH665 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech ELAN-3024-7053 or 5184N FPC-1 REV: 2/3 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2944>; + touchscreen-size-y = <1856>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + + magnetometer@e { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Micron 1GB 800MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x75830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74630303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000002 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x73c30504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000004 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x73840a06 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000007 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000d0709 0x7086120a 0x001f0000 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emem-configuration = < 0x0000000c 0xc0000090 + 0x00000004 0x00000005 0x00000013 0x0000000c + 0x0000000f 0x00000002 0x00000003 0x0000000c + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00160d13 0x712c2414 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Elpida 1GB 800MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x75830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74630303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000002 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x73c30504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000004 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x73840a06 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000007 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000d0709 0x7086120a 0x001f0000 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emem-configuration = < 0x0000000c 0xc0000090 + 0x00000004 0x00000005 0x00000013 0x0000000c + 0x0000000f 0x00000002 0x00000003 0x0000000c + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00160d13 0x712c2414 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Micron 1GB 800MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000006 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000007 0x00000007 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x0000000d 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000000e 0x0000000e + 0x00000004 0x00000003 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x0000001a 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000001c 0x0000001c + 0x00000004 0x00000005 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000035 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000038 0x00000038 + 0x00000004 0x00000009 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x00000012 + 0x00000066 0x0000000c 0x00000004 0x00000003 + 0x00000008 0x00000002 0x0000000a 0x00000004 + 0x00000004 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x00000bf0 0x00000000 0x000002fc + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000008 0x0000000f 0x0000006c 0x00000200 + 0x00000004 0x00000010 0x00000000 0x00000004 + 0x00000005 0x00000c30 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x001d0084 + 0x00008000 0x00044000 0x00044000 0x00044000 + 0x00044000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0600013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0158000c 0xa0f10000 0x00000000 + 0x00000000 0x800018c8 0xe8000000 0xff00ff89 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000025 + 0x000000ce 0x0000001a 0x00000009 0x00000005 + 0x0000000d 0x00000004 0x00000013 0x00000009 + 0x00000009 0x00000004 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001820 0x00000000 0x00000608 + 0x00000003 0x00000012 0x00000001 0x00000000 + 0x0000000f 0x00000018 0x000000d8 0x00000200 + 0x00000005 0x00000020 0x00000000 0x00000007 + 0x00000008 0x00001860 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf0070191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x00f0000c 0xa0f10000 0x00000000 + 0x00000000 0x8000308c 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Elpida 1GB 800MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000006 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000007 0x00000007 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x0000000d 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000000e 0x0000000e + 0x00000004 0x00000003 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x0000001a 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000001c 0x0000001c + 0x00000004 0x00000005 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000035 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000038 0x00000038 + 0x00000004 0x00000009 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x00000012 + 0x00000066 0x0000000c 0x00000004 0x00000003 + 0x00000008 0x00000002 0x0000000a 0x00000004 + 0x00000004 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x00000bf0 0x00000000 0x000002fc + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000008 0x0000000f 0x0000006c 0x00000200 + 0x00000004 0x00000010 0x00000000 0x00000004 + 0x00000005 0x00000c30 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x001d0084 + 0x00008000 0x00044000 0x00044000 0x00044000 + 0x00044000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0600013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0158000c 0xa0f10000 0x00000000 + 0x00000000 0x800018c8 0xe8000000 0xff00ff89 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000025 + 0x000000ce 0x0000001a 0x00000009 0x00000005 + 0x0000000d 0x00000004 0x00000013 0x00000009 + 0x00000009 0x00000004 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001820 0x00000000 0x00000608 + 0x00000003 0x00000012 0x00000001 0x00000000 + 0x0000000f 0x00000018 0x000000d8 0x00000200 + 0x00000005 0x00000020 0x00000000 0x00000007 + 0x00000008 0x00001860 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf0070191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0a00013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x00f0000c 0xa0f10000 0x00000000 + 0x00000000 0x8000308c 0xe8000000 0xff00ff49 >; + }; + }; + }; + + tc358768_refclk: clock-tc358768 { + compatible = "fixed-clock"; + clock-frequency = <23100000>; + clock-accuracy = <100>; + #clock-cells = <0>; + }; + + tc358768_osc: clock-tc358768-osc-gate { + compatible = "gpio-gate-clock"; + enable-gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>; + clocks = <&tc358768_refclk>; + #clock-cells = <0>; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; + + i2c-mux { + compatible = "i2c-mux-gpio"; + + mux-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; + i2c-parent = <&lcd_ddc>; + idle-state = <0x0>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dsi-bridge@7 { + compatible = "toshiba,tc358768"; + reg = <0x7>; + + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&tc358768_osc>; + clock-names = "refclk"; + + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + + vddc-supply = <&vdd_1v2_mipi>; + vddio-supply = <&vdd_1v8_vio>; + vddmipi-supply = <&vdd_1v2_mipi>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + data-lines = <24>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + + /* + * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1 + * LCD SuperIPS+ Full HD panel. + */ + panel@1 { + compatible = "panasonic,vvx10f004b00"; + reg = <1>; + + power-supply = <&vdd_pnl>; + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + }; + }; + }; + + vdd_1v2_mipi: regulator-mipi { + compatible = "regulator-fixed"; + regulator-name = "tc358768_1v2_vdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <10000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-900000000; +}; From 2b69c7b5fd350754b524c3410563a8d0fc452f99 Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sun, 12 Dec 2021 00:13:56 +0300 Subject: [PATCH 390/574] ARM: tegra: Add device-tree for ASUS Transformer Pad TF701T Add device-tree for Tegra114-based ASUS Transformer Pad TF701T (K00C) tablet. Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(TF701T)_(asus-tf701t) Signed-off-by: Anton Bambura Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra114-asus-tf701t.dts | 807 +++++++++++++++++++++ arch/arm/boot/dts/tegra114.dtsi | 4 +- 3 files changed, 810 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/tegra114-asus-tf701t.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 47cd157496f9..faaeae1f2a58 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1331,6 +1331,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-colibri-eval-v3.dtb \ tegra30-ouya.dtb dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ + tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ tegra114-roth.dtb \ tegra114-tn7.dtb diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/tegra114-asus-tf701t.dts new file mode 100644 index 000000000000..b791ce97424b --- /dev/null +++ b/arch/arm/boot/dts/tegra114-asus-tf701t.dts @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include +#include + +#include "tegra114.dtsi" + +/ { + model = "Asus Transformer Pad TF701T"; + compatible = "asus,tf701t", "nvidia,tegra114"; + chassis-type = "convertible"; + + aliases { + mmc0 = "/mmc@78000600"; /* eMMC */ + mmc1 = "/mmc@78000400"; /* uSD slot */ + mmc2 = "/mmc@78000000"; /* WiFi */ + + rtc0 = &palmas; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; /* Console */ + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + memory@80000000 { + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; + linux,cma-default; + reusable; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; + no-map; + }; + }; + + host1x@50000000 { + dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&tps65913_ldo2>; + + nvidia,ganged-mode = <&dsib>; + + panel_primary: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + + link2 = <&panel_secondary>; + + power-supply = <&vdd_lcd>; + backlight = <&backlight>; + }; + }; + + dsi@54400000 { + status = "okay"; + + avdd-dsi-csi-supply = <&tps65913_ldo2>; + + panel_secondary: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + }; + }; + }; + + pinmux@70000868 { + asus_pad_ec_default: asus-pad-ec-default { + ec-interrupt { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ec-request { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + backlight_default: backlight-default { + backlight-enable { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + codec_default: codec-default { + ldo1-en { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + interrupt { + nvidia,pins = "gpio_w2_aud_pw2", + "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + gpio_keys_default: gpio-keys-default { + power { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + volume { + nvidia,pins = "kb_row1_pr1", + "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + gpio_hall_sensor_default: gpio-hall-sensor-default { + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + hp_det_default: hp-det-default { + gmi_iordy_pi5 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + imu_default: imu-default { + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + pwm_default: pwm-default { + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + /* XXX make this something more sensible */ + pwm_sleep: pwm-sleep { + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + sdmmc3_default: sdmmc3-default { + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "kb_col4_pq4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5", + "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + + sdmmc3_vdd_default: sdmmc3-vdd-default { + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + vdd_lcd_default: vdd-lcd-default { + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006040 { + /* GPS */ + }; + + serial@70006200 { + /* Bluetooth */ + }; + + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm_default>; + pinctrl-1 = <&pwm_sleep>; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + magnetometer@c { + compatible = "asahi-kasei,ak09911"; + reg = <0xc>; + + vdd-supply = <&vdd_3v3_sys>; + }; + + rt5639: audio-codec@1c { + compatible = "realtek,rt5639"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&codec_default>; + }; + + motion-tracker@68 { + compatible = "invensense,mpu6500"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + + pinctrl-names = "default"; + pinctrl-0 = <&imu_default>; + }; + + temp_sensor: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + }; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + light-sensor@1c { + compatible = "dynaimage,al3320a"; + reg = <0x1c>; + + vdd-supply = <&vdd_3v3_sys>; + }; + }; + + i2c@7000c700 { + /* HDMI DDC */ + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + palmas: pmic@58 { + compatible = "ti,tps65913", "ti,palmas"; + reg = <0x58>; + interrupts = ; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + + ldo1-in-supply = <&tps65913_smps7>; + ldo2-in-supply = <&tps65913_smps7>; + ldo4-in-supply = <&tps65913_smps8>; + ldo5-in-supply = <&tps65913_smps9>; + ldo6-in-supply = <&tps65913_smps9>; + ldo7-in-supply = <&tps65913_smps9>; + ldo9-in-supply = <&tps65913_smps9>; + + regulators { + tps65913_smps123: smps123 { + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <1>; + ti,mode-sleep = <3>; + }; + + tps65913_smps45: smps45 { + regulator-name = "vdd-core"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <3>; + }; + + smps6 { + regulator-name = "va-lcd-hv"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps7: smps7 { + regulator-name = "vdd-ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps8: smps8 { + regulator-name = "vdd-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps9: smps9 { + regulator-name = "vdd-sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + + tps65913_smps10_out1: smps10_out1 { + regulator-name = "vd-smps10-out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps10_out2: smps10_out2 { + regulator-name = "vd-smps10-out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_ldo1: ldo1 { + regulator-name = "vdd-hdmi-pll"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + ti,roof-floor = <3>; + }; + + tps65913_ldo2: ldo2 { + regulator-name = "vdd-2v8-dsi-csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + ldo3 { + regulator-name = "vpp-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo4 { + regulator-name = "vdd-1v2-cam"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo5 { + regulator-name = "vdd-cam"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo6 { + regulator-name = "vdd-dev"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-boot-on; + }; + + ldo7 { + regulator-name = "vdd-2v8-cam"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + tps65913_ldo8: ldo8 { + regulator-name = "vdd-rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + ti,enable-ldo8-tracking; + }; + + tps65913_ldo9: ldo9 { + regulator-name = "vdd-sdmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + }; + + tps65913_ldoln: ldoln { + regulator-name = "vdd-hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldousb { + regulator-name = "vdd-usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 0>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_powergood { + pins = "powergood"; + function = "powergood"; + }; + + pin_vac { + pins = "vac"; + function = "vac"; + }; + + pin_gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "gpio"; + }; + + pin_gpio2 { + pins = "gpio2"; + function = "gpio"; + }; + + pin_gpio3 { + pins = "gpio3"; + function = "gpio"; + }; + + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + + pin_gpio5 { + pins = "gpio5"; + function = "gpio"; + }; + + pin_gpio6 { + pins = "gpio6"; + function = "gpio"; + }; + + pin_gpio7 { + pins = "gpio7"; + function = "gpio"; + }; + }; + }; + }; + }; + + ahub@70080000 { + i2s@70080300 { + status = "okay"; + }; + }; + + mmc@78000000 { + /* WiFi */ + }; + + /* MicroSD card */ + mmc@78000400 { + status = "okay"; + + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&tps65913_ldo9>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc3_default>; + }; + + mmc@78000600 { + /* eMMC */ + }; + + usb@7d000000 { + compatible = "nvidia,tegra114-udc"; + status = "okay"; + dr_mode = "peripheral"; + + /* Peripheral USB via ASUS connector */ + }; + + usb-phy@7d000000 { + status = "okay"; + }; + + usb@7d008000 { + status = "okay"; + + /* Host USB via dock */ + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_5v0_sys>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_sys>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <224>; + + pinctrl-names = "default"; + pinctrl-0 = <&backlight_default>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + label = "GPIO Buttons"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + label = "GPIO Hall Effect Sensor"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_hall_sensor_default>; + + hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + }; + + sound { + compatible = "asus,tegra-audio-rt5639-tf701t", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "Asus Transformer Pad TF701T RT5639"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL", + "Speakers", "SPORP", + "Speakers", "SPORN", + "Speakers", "SPOLP", + "Speakers", "SPOLN", + "Mic Jack", "MICBIAS1", + "IN2P", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s0>; + nvidia,audio-codec = <&rt5639>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA114_CLK_PLL_A>, + <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA114_CLK_EXTERN1>; + + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_default>; + }; + + vdd_5v0_sys: regulator-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: regulator-3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_lcd: regulator-vdd-lcd { + compatible = "regulator-fixed"; + regulator-name = "vdd_lcd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&tps65913_smps8>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + + pinctrl-names = "default"; + pinctrl-0 = <&vdd_lcd_default>; + }; + + vdd_usd: regulator-vdd-usd { + compatible = "regulator-fixed"; + regulator-name = "vdd_sd_slot"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + vin-supply = <&tps65913_smps9>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc3_vdd_default>; + }; +}; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index ce7410ee08b8..8b45f4617b2f 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -105,7 +105,7 @@ status = "disabled"; }; - dsi@54300000 { + dsia: dsi@54300000 { compatible = "nvidia,tegra114-dsi"; reg = <0x54300000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_DSIA>, @@ -121,7 +121,7 @@ #size-cells = <0>; }; - dsi@54400000 { + dsib: dsi@54400000 { compatible = "nvidia,tegra114-dsi"; reg = <0x54400000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_DSIB>, From 87d9cf2e846968c7ca8e2a3299e4fb93899bd7fc Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:57 +0300 Subject: [PATCH 391/574] ARM: tegra: Add device-tree for Pegatron Chagall Add device-tree for Pegatron Chagall, which is a NVIDIA Tegra30-based Android tablet. Link: https://wiki.postmarketos.org/wiki/Pegatron_Chagall_(pegatron-chagall) Co-developed-by: Raffaele Tranquillini Signed-off-by: Raffaele Tranquillini Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 3 +- .../arm/boot/dts/tegra30-pegatron-chagall.dts | 2859 +++++++++++++++++ 2 files changed, 2861 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/tegra30-pegatron-chagall.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faaeae1f2a58..8f93e9e65a7c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1329,7 +1329,8 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ tegra30-colibri-eval-v3.dtb \ - tegra30-ouya.dtb + tegra30-ouya.dtb \ + tegra30-pegatron-chagall.dtb dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts new file mode 100644 index 000000000000..f4b2d4218849 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts @@ -0,0 +1,2859 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Pegatron Chagall"; + compatible = "pegatron,chagall", "nvidia,tegra30"; + chassis-type = "tablet"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* uSD slot */ + mmc2 = &sdmmc3; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + display0 = &lcd; + display1 = &hdmi; + + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@beb00000 { + compatible = "ramoops"; + reg = <0xbeb00000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; /* 2MB */ + no-map; + }; + }; + + host1x@50000000 { + hdmi: hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&hdmi_5v0_sys>; + pll-supply = <&vdd_1v8_vio>; + vdd-supply = <&vdd_3v3_sys>; + + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + }; + }; + + vde@6001a000 { + assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; + assigned-clock-rates = <408000000>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_dat5_pd0", + "sdmmc3_dat4_pd1", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2C pinmux */ + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + }; + + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + /* HDMI-CEC pinmux */ + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-B */ + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-C */ + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-D */ + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2S pinmux */ + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2", + "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_pwr2_pc6", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_dc0_pn6", + "lcd_sdin_pz2", + "lcd_wr_n_pz3", + "lcd_sck_pz4", + "lcd_cs1_n_pw0", + "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC keys */ + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row3_pr3", + "kb_row8_ps0", + "kb_col0_pq0", + "kb_col1_pq1", + "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4", + "kb_row7_pr7", + "kb_row10_ps2", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs4_n_pk2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5", + "gmi_ad12_ph4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "sata"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI hot-plug-detect */ + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2", + "kb_row5_pr5"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,pull-down-strength = <5>; + nvidia,pull-up-strength = <5>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_gma { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_lcd2 { + nvidia,pins = "drive_lcd2"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + /* Broadcom GPS BCM47511 */ + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* Azurewave AW-AH663 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + lcd_ddc: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* Wolfson Microelectronics WM8903 audio codec */ + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + + AVDD-supply = <&vdd_1v8_vio>; + CPVDD-supply = <&vdd_1v8_vio>; + DBVDD-supply = <&vdd_1v8_vio>; + DCVDD-supply = <&vdd_1v8_vio>; + }; + }; + + i2c2: i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + + /* Atmel touchscreen */ + touchscreen@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + }; + }; + + i2c3: i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sen>; + }; + + /* AsahiKASEI AK8975 magnetometer sensor */ + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + + vdd-supply = <&vdd_3v3_sen>; + vid-supply = <&vdd_1v8_vio>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sen>; + vlogic-supply = <&vdd_1v8_vio>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_vio>; + vddio-supply = <&vdd_1v8_vio>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "1"; + }; + }; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <93750>; + }; + + i2c5: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + + /* Texas Instruments TPS659110 PMIC */ + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_sys>; + vcc2-supply = <&vdd_5v0_sys>; + vcc3-supply = <&vdd_1v8_vio>; + vcc4-supply = <&vdd_1v8_vio>; + vcc5-supply = <&vdd_5v0_sys>; + vcc6-supply = <&vddio_1v2_ddr>; + vcc7-supply = <&vdd_5v0_sys>; + vccio-supply = <&vdd_5v0_sys>; + + pmic-sleep-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>, + <2 GPIO_ACTIVE_HIGH>, + <6 GPIO_ACTIVE_HIGH>, + <8 GPIO_ACTIVE_HIGH>; + output-high; + }; + + regulators { + /* VDD1 is not used by Chagall */ + + vddio_1v2_ddr: vdd2 { + regulator-name = "vddio_1v2_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <1>; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8_vio: vio { + regulator-name = "vdd_1v8_gen"; + /* FIXME: eMMC won't work, if set to 1.8 V */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <3200000>; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_1v3_cam_isp"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + ti,regulator-ext-sleep-control = <8>; + }; + }; + }; + + vdd_core: core-regulator@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,enable-vout-discharge; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + vdd_5v0_sys: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: regulator-3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <300000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_sen: regulator-sensors { + compatible = "regulator-fixed"; + regulator-name = "sen_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + hdmi_5v0_sys: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_vbus_usb1: regulator-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus_micro_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_vbus_usb3: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus_typea_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <2>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x81>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* SAMSUNG K4P8G304EB FGC1 */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000006 + 0x00000001 0x00000000 0x00000004 0x00000004 + 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* ELPIDA EDB8132B2MA 8D_F */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000006 + 0x00000001 0x00000000 0x00000004 0x00000004 + 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* SAMSUNG K4P8G304EB FGC2 */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x00000008 0xc0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + + emc-timings-3 { + /* HYNIX H9TCNNN8JDMMPR NGM */ + nvidia,ram-code = <3>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x00000008 0xc0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* SAMSUNG K4P8G304EB FGC1 */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010082>; + nvidia,emc-mode-2 = <0x00020004>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000024>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000017 + 0x00000033 0x00000010 0x00000007 0x00000007 + 0x00000007 0x00000002 0x0000000a 0x00000007 + 0x00000007 0x00000003 0x00000002 0x00000000 + 0x00000003 0x00000007 0x00000004 0x0000000d + 0x0000000e 0x000005e9 0x00000000 0x0000017a + 0x00000002 0x00000002 0x00000007 0x00000000 + 0x00000001 0x0000000c 0x00000038 0x00000038 + 0x00000006 0x00000014 0x00000009 0x00000004 + 0x00000002 0x00000680 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0x001d0084 + 0x00008000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00038000 0x00038000 0x00038000 + 0x00038000 0x00080220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000090 0x000c000c 0xa0f10404 0x00000000 + 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; + }; + }; + + emc-timings-1 { + /* ELPIDA EDB8132B2MA 8D_F */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010082>; + nvidia,emc-mode-2 = <0x00020004>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000024>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000017 + 0x00000033 0x00000010 0x00000007 0x00000007 + 0x00000007 0x00000002 0x0000000a 0x00000007 + 0x00000007 0x00000003 0x00000002 0x00000000 + 0x00000003 0x00000007 0x00000004 0x0000000d + 0x0000000e 0x000005e9 0x00000000 0x0000017a + 0x00000002 0x00000002 0x00000007 0x00000000 + 0x00000001 0x0000000c 0x00000038 0x00000038 + 0x00000006 0x00000014 0x00000009 0x00000004 + 0x00000002 0x00000680 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0x001d0084 + 0x00008000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x00060220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000090 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; + }; + }; + + emc-timings-2 { + /* SAMSUNG K4P8G304EB FGC2 */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000004 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000005 0x00000004 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x0000000a 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000004 + 0x00000002 0x000008aa 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x007f8008 0x007f8008 0x007f8008 + 0x007f8008 0x007f8008 0x007f8008 0x007f8008 + 0x007f8008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x00080220 0x0200003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xf0000000 0xff00ff88 >; + }; + }; + + emc-timings-3 { + /* HYNIX H9TCNNN8JDMMPR NGM */ + nvidia,ram-code = <3>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xd0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x00000009 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000004 + 0x00000002 0x000008aa 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000a0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; + }; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + i2s@70080400 { /* i2s1 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70080600 { /* i2s3 */ + status = "okay"; + }; + }; + + sdmmc1: mmc@78000000 { + status = "okay"; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + bus-width = <4>; + + vmmc-supply = <&vdd_usd>; /* ldo2 */ + vqmmc-supply = <&vddio_usd>; /* ldo3 */ + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + sdmmc3: mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* Azurewave AW-AH663 BCM4330B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc4: mmc@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + non-removable; + }; + + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "otg"; + vbus-supply = <&vdd_vbus_usb1>; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_vbus_usb3>; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <15>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu2: cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu3: cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + display-panel { + compatible = "panel-lvds"; + + width-mm = <217>; + height-mm = <136>; + + data-mapping = "jeida-24"; + + panel-timing { + /* 1280x800@60Hz */ + clock-frequency = <68000000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <48>; + hback-porch = <18>; + hsync-len = <30>; + vsync-len = <5>; + vfront-porch = <3>; + vback-porch = <12>; + }; + }; + + extcon-keys { + compatible = "gpio-keys"; + interrupt-parent = <&gpio>; + + dock-insert { + label = "Chagall Dock"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + lineout-detect { + label = "Audio dock line-out detect"; + gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + interrupt-parent = <&gpio>; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; + + sound { + compatible = "pegatron,tegra-audio-wm8903-chagall", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Pegatron Chagall WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "IN1R", "Mic Jack", + "DMICDAT", "Int Mic"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,headset; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * Chagall from getting too hot from a user's tactile + * perspective. The CPU zone is intended to protect + * silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 57C until temperature drops to 56.8C */ + temperature = <57000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 65C */ + temperature = <65000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; From ef6fb9875ce0f495115ebb22a635a1aaafc0f467 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:13:58 +0300 Subject: [PATCH 392/574] ARM: tegra: Add device-tree for 1080p version of Nyan Big Add dedicated device-tree for 1080p version of Nyan Big in order to describe display panel properly. FHD panel doesn't support modes other than 1080p, hence it's wrong to use incompatible lower resolution panel in device-tree. Tested-by: Thomas Graichen Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra124-nyan-big-fhd.dts | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 arch/arm/boot/dts/tegra124-nyan-big-fhd.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8f93e9e65a7c..a8763a75b3b2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1341,6 +1341,7 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ tegra124-apalis-v1.2-eval.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ + tegra124-nyan-big-fhd.dtb \ tegra124-nyan-blaze.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ARCH_U8500) += \ diff --git a/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts b/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts new file mode 100644 index 000000000000..d35fb79d2f51 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra124-nyan-big.dts" + +/ { + /* Version of Nyan Big with 1080p panel */ + panel { + compatible = "auo,b133htn01"; + }; +}; From e6fd5c1e9fc5b35ad855cf748cc18b86776b6389 Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Sun, 12 Dec 2021 00:13:59 +0300 Subject: [PATCH 393/574] ARM: tegra: Add usb-role-switch property to USB OTG ports If an USB port is an OTG port, then we should add the usb-role-switch property. Otherwise XUSB setup fails and therefore padctl is unable to set up the ports. This leads to broken USB and PCIe ports. Add the usb-role-switch properties to Tegra124 device-trees to fix the problem. The error message shown without this patch is e.g: usb2-0: usb-role-switch not found for otg mode [digetx@gmail.com: improved commit message] Tested-by: Thomas Graichen # T124 Nyan Big Signed-off-by: Stefan Eichenberger Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 + arch/arm/boot/dts/tegra124-apalis.dtsi | 1 + arch/arm/boot/dts/tegra124-nyan.dtsi | 1 + arch/arm/boot/dts/tegra124-venice2.dts | 2 +- 4 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index f5440ae14cb4..dbb0da08cb95 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1888,6 +1888,7 @@ usb2-0 { status = "okay"; mode = "otg"; + usb-role-switch; vbus-supply = <®_usbo1_vbus>; }; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 1d83f2e254c5..d3f16c117b0c 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1880,6 +1880,7 @@ usb2-0 { status = "okay"; mode = "otg"; + usb-role-switch; vbus-supply = <®_usbo1_vbus>; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 998b129321f8..cab0a6e95b7e 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -466,6 +466,7 @@ vbus-supply = <&vdd_usb1_vbus>; status = "okay"; mode = "otg"; + usb-role-switch; }; usb2-1 { diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 7985d1cbc1c0..232c90604df9 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -973,7 +973,7 @@ usb2-0 { status = "okay"; mode = "otg"; - + usb-role-switch; vbus-supply = <&vdd_usb1_vbus>; }; From 770586291f9a99c0abb6edee7d709a189355ac7e Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:00 +0300 Subject: [PATCH 394/574] ARM: tegra: Enable HDMI CEC on Nyan Enable HDMI CEC on Nyan Chromebooks. It allows to control TV over HDMI. Suggested-by: Thomas Graichen Tested-by: Thomas Graichen # T124 Nyan Big Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-nyan.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index cab0a6e95b7e..e702f91e0707 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -390,6 +390,10 @@ nvidia,sys-clock-req-active-high; }; + cec@70015000 { + status = "okay"; + }; + hda@70030000 { status = "okay"; }; From 894ea1121b29713c5da17e1032d1049f31e11d19 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:01 +0300 Subject: [PATCH 395/574] ARM: tegra: Enable CPU DFLL on Nyan Enable CPU DFLL node on Nyan Chromebooks. DFLL was previously disabled due to Linux kernel CPUFreq driver which didn't support suspend-resume. That problem was fixed years ago, but DFLL was never re-enabled. Tested-by: Thomas Graichen # T124 Nyan Big Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index e702f91e0707..f693daad68d8 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -532,7 +532,7 @@ /* CPU DFLL clock */ clock@70110000 { - status = "disabled"; + status = "okay"; vdd-cpu-supply = <&vdd_cpu>; nvidia,i2c-fs-rate = <400000>; }; From 7525c2a354e083a33f8775f810edd544f11ec108 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:02 +0300 Subject: [PATCH 396/574] ARM: tegra: Add CPU thermal zones to Nyan device-tree CPU of Nyan Chromebooks is overheating badly because apparently hardware soctherm controller doesn't work well. Add CPU thermal zones to enable software thermal control over CPU and fix the overheat trouble. Tested-by: Thomas Graichen # T124 Nyan Big Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-nyan.dtsi | 49 +++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index f693daad68d8..a93cfb492ba1 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include "tegra124.dtsi" / { @@ -87,7 +88,7 @@ interrupts = ; }; - temperature-sensor@4c { + tmp451: temperature-sensor@4c { compatible = "ti,tmp451"; reg = <0x4c>; interrupt-parent = <&gpio>; @@ -789,6 +790,52 @@ gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; priority = <200>; }; + + cpus { + cpu0: cpu@0 { + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + #cooling-cells = <2>; + }; + }; + + thermal-zones { + cpu-skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tmp451 0>; + + trips { + cpu_passive_trip: cpu-alert0 { + /* throttle at 70C until temperature drops to 69.8C */ + temperature = <70000>; + hysteresis = <200>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_passive_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; }; #include "cros-ec-keyboard.dtsi" From a28c1b4f11fc201103faf51902bb207edba76c73 Mon Sep 17 00:00:00 2001 From: Maxim Schwalm Date: Sun, 12 Dec 2021 00:14:06 +0300 Subject: [PATCH 397/574] ARM: tegra: nexus7: Use common LVDS display device-tree Make Nexus 7 device-tree to use common LVDS bridge description. This makes device-trees more consistent. [digetx@gmail.com: factored Nexus7 change into separate patch and wrote commit message] Signed-off-by: Maxim Schwalm Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../tegra30-asus-nexus7-grouper-common.dtsi | 54 ++----------------- 1 file changed, 3 insertions(+), 51 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index ab33ceb63fff..d79a99470ac2 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -8,6 +8,7 @@ #include "tegra30.dtsi" #include "tegra30-cpu-opp.dtsi" #include "tegra30-cpu-opp-microvolt.dtsi" +#include "tegra30-asus-lvds-display.dtsi" / { aliases { @@ -59,21 +60,6 @@ }; }; - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - port@0 { - lcd_output: endpoint { - remote-endpoint = <&lvds_encoder_input>; - bus-width = <24>; - }; - }; - }; - }; - }; - gpio@6000d000 { init-mode-hog { gpio-hog; @@ -1116,20 +1102,14 @@ */ compatible = "panel-lvds"; - power-supply = <&vdd_pnl>; - backlight = <&backlight>; - width-mm = <94>; height-mm = <150>; rotation = <180>; data-mapping = "jeida-24"; - port { - panel_input: endpoint { - remote-endpoint = <&lvds_encoder_output>; - }; - }; + /* DDC unconnected on Nexus 7 */ + /delete-property/ ddc-i2c-bus; }; firmware { @@ -1181,34 +1161,6 @@ }; }; - lvds-encoder { - compatible = "ti,sn75lvds83", "lvds-encoder"; - - powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; - power-supply = <&vdd_3v3_sys>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_encoder_input: endpoint { - remote-endpoint = <&lcd_output>; - }; - }; - - port@1 { - reg = <1>; - - lvds_encoder_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; From e6e395578a6e92307c54232bc695bb08b32b0f86 Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sun, 12 Dec 2021 00:14:08 +0300 Subject: [PATCH 398/574] ARM: tegra: Enable video decoder on Tegra114 Add Video Decoder Engine node to Tegra114 device-tree. Signed-off-by: Anton Bambura Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 8b45f4617b2f..ae1be90a9385 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -17,6 +17,19 @@ reg = <0x80000000 0x0>; }; + sram@40000000 { + compatible = "mmio-sram"; + reg = <0x40000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x40000>; + + vde_pool: sram@400 { + reg = <0x400 0x3fc00>; + pool; + }; + }; + host1x@50000000 { compatible = "nvidia,tegra114-host1x"; reg = <0x50000000 0x00028000>; @@ -253,6 +266,30 @@ */ }; + vde@6001a000 { + compatible = "nvidia,tegra114-vde"; + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x400>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&vde_pool>; /* IRAM region */ + interrupts = , /* Sync token interrupt */ + , /* BSE-V interrupt */ + ; /* SXE interrupt */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&tegra_car TEGRA114_CLK_VDE>; + reset-names = "vde", "mc"; + resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; + iommus = <&mc TEGRA_SWGROUP_VDE>; + }; + apbmisc@70000800 { compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; reg = <0x70000800 0x64>, /* Chip revision */ From 19ebf10e8d837c0a296274b571a681b0c2885e4e Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Mon, 22 Nov 2021 20:32:21 +0800 Subject: [PATCH 399/574] dt-bindings: arm64: dts: mediatek: Add mt7986 series MT7986 series is Mediatek's new 4-core SoC, which is mainly for wifi-router application. The difference between mt7986a and mt7986b is that some pins do not exist on mt7986b. Signed-off-by: Sam Shih Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211122123222.8016-2-sam.shih@mediatek.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 723810cffce2..0ffe1acf1344 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -77,6 +77,14 @@ properties: - enum: - mediatek,mt7629-rfb - const: mediatek,mt7629 + - items: + - enum: + - mediatek,mt7986a-rfb + - const: mediatek,mt7986a + - items: + - enum: + - mediatek,mt7986b-rfb + - const: mediatek,mt7986b - items: - enum: - mediatek,mt8127-moose From 50137c150f5f478e083b0b24b650de49f55ebfa2 Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Mon, 22 Nov 2021 20:32:22 +0800 Subject: [PATCH 400/574] arm64: dts: mediatek: add basic mt7986 support Add basic chip support for Mediatek mt7986, include basic uart nodes, rng node and watchdog node. Add cpu node, timer node, gic node, psci and reserved-memory node for ARM Trusted Firmware. Signed-off-by: Sam Shih Link: https://lore.kernel.org/r/20211122123222.8016-3-sam.shih@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 37 +++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 148 +++++++++++++++++++ 3 files changed, 186 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 1613259b6865..0127284dbc2d 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts new file mode 100644 index 000000000000..6911862390d7 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7986a.dtsi" + +/ { + model = "MediaTek MT7986a RFB"; + compatible = "mediatek,mt7986a-rfb"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi new file mode 100644 index 000000000000..77906839cc85 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + system_clk: dummy40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + enable-method = "psci"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + #cooling-cells = <2>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x10000>, /* GICD */ + <0 0x0c080000 0 0x80000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + interrupts = ; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + status = "disabled"; + }; + + trng: trng@1020f000 { + compatible = "mediatek,mt7986-rng", + "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x100>; + clocks = <&system_clk>; + clock-names = "rng"; + status = "disabled"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&system_clk>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&system_clk>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&system_clk>; + status = "disabled"; + }; + + }; + +}; From fd31f778da81fec188f3ac8e03da4338642a8f08 Mon Sep 17 00:00:00 2001 From: Prashant Malani Date: Thu, 9 Dec 2021 11:51:12 -0800 Subject: [PATCH 401/574] arm64: dts: mt8183: kukui: Add Type C node Add a node describing the USB Type C connector, in order to utilize the Chromium OS USB Type-C driver that enumerates Type-C ports and connected cables/peripherals and makes them visible to userspace. Cc: Alexandru M Stan Cc: Benson Leung Signed-off-by: Prashant Malani Reviewed-by: Alexandru M Stan Reviewed-by: Benson Leung Link: https://lore.kernel.org/r/20211209195112.366176-1-pmalani@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 94c13c459194..0f9480f91261 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -886,6 +886,20 @@ cbas { compatible = "google,cros-cbas"; }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + try-power-role = "sink"; + }; + }; }; }; From c3a064a32ed98437dd62ff30e07a4ea3c659852f Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Mon, 22 Nov 2021 20:35:51 +0800 Subject: [PATCH 402/574] arm64: dts: mediatek: add pinctrl support for mt7986a Add mt7986a pinctrl node, and update pinmux setting for mt7986a Signed-off-by: Sam Shih Link: https://lore.kernel.org/r/20211122123552.8218-2-sam.shih@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 20 +++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 ++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 6911862390d7..5cd760abff51 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -29,9 +29,29 @@ }; &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; status = "okay"; }; &uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; status = "okay"; }; + +&pio { + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 77906839cc85..b8da76b6ba47 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -107,6 +107,27 @@ status = "disabled"; }; + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7986a-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c30000 0 0x1000>, + <0 0x11c40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", + "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 100>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + trng: trng@1020f000 { compatible = "mediatek,mt7986-rng", "mediatek,mt7623-rng"; From f40c0f800f15e9e3566cb39a9eee2855c634eb5f Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Mon, 22 Nov 2021 20:35:52 +0800 Subject: [PATCH 403/574] arm64: dts: mediatek: add pinctrl support for mt7986b Add mt7986b pinctrl node Signed-off-by: Sam Shih Link: https://lore.kernel.org/r/20211122123552.8218-3-sam.shih@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 29 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 12 ++++++++ 3 files changed, 42 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7986b.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 0127284dbc2d..8c1e18032f9f 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts new file mode 100644 index 000000000000..5fb752edd754 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7986b.dtsi" + +/ { + model = "MediaTek MT7986b RFB"; + compatible = "mediatek,mt7986b-rfb"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi new file mode 100644 index 000000000000..23923b9f8944 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +#include "mt7986a.dtsi" + +&pio { + compatible = "mediatek,mt7986b-pinctrl"; + gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>; +}; From c02b360ca67ebeb9de07b47b2fe53f964c2561d1 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 9 Dec 2021 17:53:41 +0000 Subject: [PATCH 404/574] arm64: dts: qcom: c630: Fix soundcard setup Currently Soundcard has 1 rx device for headset and SoundWire Speaker Playback. This setup has issues, ex if we try to play on headset the audio stream is also sent to SoundWire Speakers and we will hear sound in both headsets and speakers. Make a separate device for Speakers and Headset so that the streams are different and handled properly. Fixes: 45021d35fcb2 ("arm64: dts: qcom: c630: Enable audio support") Signed-off-by: Srinivas Kandagatla Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211209175342.20386-2-srinivas.kandagatla@linaro.org --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index d6b2ba4396f6..2e882a977e2c 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -523,6 +523,10 @@ dai@1 { reg = <1>; }; + + dai@2 { + reg = <2>; + }; }; &sound { @@ -535,6 +539,7 @@ "SpkrLeft IN", "SPK1 OUT", "SpkrRight IN", "SPK2 OUT", "MM_DL1", "MultiMedia1 Playback", + "MM_DL3", "MultiMedia3 Playback", "MultiMedia2 Capture", "MM_UL2"; mm1-dai-link { @@ -551,6 +556,13 @@ }; }; + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + slim-dai-link { link-name = "SLIM Playback"; cpu { @@ -580,6 +592,21 @@ sound-dai = <&wcd9340 1>; }; }; + + slim-wcd-dai-link { + link-name = "SLIM WCD Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_1_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 2>; + }; + }; }; &tlmm { From ef10e1b89508d3315e47e23098fec60b33b1f6b3 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 9 Dec 2021 17:53:42 +0000 Subject: [PATCH 405/574] arm64: dts: qcom: c630: add headset jack and button detection support Add MBHC support available in WCD934X codec. Signed-off-by: Srinivas Kandagatla Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211209175342.20386-3-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 2e882a977e2c..58845a14805f 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -771,6 +771,9 @@ vdd-tx-supply = <&vreg_s4a_1p8>; vdd-rx-supply = <&vreg_s4a_1p8>; vdd-io-supply = <&vreg_s4a_1p8>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; swm: swm@c85 { left_spkr: wsa8810-left{ From 202f69cd4e1dad6c86a35d8b29fc693877c6c91d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 2 Dec 2021 01:43:28 +0100 Subject: [PATCH 406/574] Revert "arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer" This reverts commit ed9500c1df59437856d43e657f185fb1eb5d817d. The clock-frequency property was meant to aid platforms with broken firmwares that don't set up the timer properly on their own. Don't include it where it is not the case. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211202004328.459899-1-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 7323ed74f41a..53b39e718fb6 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3193,6 +3193,5 @@ , , ; - clock-frequency = <19200000>; }; }; From 409fd3f10c0b71dabff735d5f290096d6bb6b4df Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Wed, 8 Dec 2021 19:47:06 +0100 Subject: [PATCH 407/574] arm64: qcom: dts: drop legacy property #stream-id-cells Property #stream-id-cells is legacy leftover and isn't currently documented nor used. Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211208184707.100716-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8998.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm630.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 - 8 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 1ac78d9909ab..91bc974aeb0a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -962,7 +962,6 @@ gpu: gpu@b00000 { compatible = "qcom,adreno-530.2", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0x00b00000 0x3f000>; reg-names = "kgsl_3d0_reg_memory"; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 408f265e277b..f273bc1ff629 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1446,7 +1446,6 @@ iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; power-domains = <&rpmpd MSM8998_VDDMX>; - #stream-id-cells = <16>; status = "disabled"; gpu_opp_table: opp-table { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index faf8b807d0ff..2151cd8c8c7a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1952,7 +1952,6 @@ gpu: gpu@5000000 { compatible = "qcom,adreno-618.0", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, <0 0x05061000 0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 40b409f279f5..937c2e0e93eb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1753,7 +1753,6 @@ gpu: gpu@3d00000 { compatible = "qcom,adreno-635.0", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0 0x03d00000 0 0x40000>, <0 0x03d9e000 0 0x1000>, <0 0x03d61000 0 0x800>; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index b75bb87ed290..9217c3a51f79 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1019,7 +1019,6 @@ adreno_gpu: gpu@5000000 { compatible = "qcom,adreno-508.0", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0x05000000 0x40000>; reg-names = "kgsl_3d0_reg_memory"; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 526087586ba4..ff344a9a81a6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4415,7 +4415,6 @@ gpu: gpu@5000000 { compatible = "qcom,adreno-630.2", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; reg-names = "kgsl_3d0_reg_memory", "cx_mem"; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 81b4ff2cc4cd..6012322a5984 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1785,7 +1785,6 @@ compatible = "qcom,adreno-640.1", "qcom,adreno", "amd,imageon"; - #stream-id-cells = <16>; reg = <0 0x02c00000 0 0x40000>; reg-names = "kgsl_3d0_reg_memory"; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 40f18d539d80..5617a46e5ccd 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2399,7 +2399,6 @@ gpu: gpu@3d00000 { compatible = "qcom,adreno-650.2", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0 0x03d00000 0 0x40000>; reg-names = "kgsl_3d0_reg_memory"; From 4cc7c85cccc87e436a86b4281ddcd886eb0bf58f Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 4 Oct 2021 20:25:30 -0700 Subject: [PATCH 408/574] arm64: dts: qcom: pm8998: Add ADC Thermal Monitor node Add a node for the ADC Thermal Monitor found in the PM8998 PMIC. This is used to connect thermal zones with ADC channels. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20211005032531.2251928-4-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/pm8998.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 6f5bb6b37ec2..d09f2954b6f9 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -84,6 +84,16 @@ }; }; + pm8998_adc_tm: adc-tm@3400 { + compatible = "qcom,spmi-adc-tm-hc"; + reg = <0x3400>; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>, <0x6100>; From d5e12f3823aed1e35ee2411bdf0ab61dc1011387 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 4 Oct 2021 20:25:31 -0700 Subject: [PATCH 409/574] arm64: dts: qcom: sdm845: mtp: Add vadc channels and thermal zones Downstream defines four ADC channels related to thermal sensors external to the PM8998 and two channels for internal voltage measurements. Add these to the upstream SDM845 MTP, describe the thermal monitor channels and add thermal_zones for these. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20211005032531.2251928-5-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 140 ++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 5e6e8f4fb5be..7713e8060c5b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -9,6 +9,8 @@ #include #include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" / { model = "Qualcomm Technologies, Inc. SDM845 MTP"; @@ -45,6 +47,68 @@ vin-supply = <&vph_pwr>; }; + + thermal-zones { + xo_thermal: xo-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm8998_adc_tm 1>; + + trips { + trip-point { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + msm_thermal: msm-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm8998_adc_tm 2>; + + trips { + trip-point { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + pa_thermal: pa-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm8998_adc_tm 3>; + + trips { + trip-point { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + quiet_thermal: quiet-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm8998_adc_tm 4>; + + trips { + trip-point { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + }; }; &adsp_pas { @@ -467,6 +531,82 @@ firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; }; +&pm8998_adc { + adc-chan@4c { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + adc-chan@4d { + reg = ; + label = "msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + adc-chan@4f { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + adc-chan@51 { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + adc-chan@83 { + reg = ; + label = "vph_pwr"; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + adc-chan@85 { + reg = ; + label = "vcoin"; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8998_adc_tm { + status = "okay"; + + xo-thermistor@1 { + reg = <1>; + io-channels = <&pm8998_adc ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + msm-thermistor@2 { + reg = <2>; + io-channels = <&pm8998_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pa-thermistor@3 { + reg = <3>; + io-channels = <&pm8998_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-thermistor@4 { + reg = <4>; + io-channels = <&pm8998_adc ADC5_AMUX_THM5_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &qupv3_id_1 { status = "okay"; }; From c8b9d64bb262033775ff64dde6ca7cf18899651b Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 13 Dec 2021 20:02:28 +0100 Subject: [PATCH 410/574] arm64: dts: qcom: sdm845: add QFPROM chipset specific compatible Use correct compatible according to dt-binding. Fixes + few other lines of `make qcom/sdm845-oneplus-fajita.dtb`: arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: qfprom@784000: compatible: ['qcom,qfprom'] is too short From schema: Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213190228.106924-1-david@ixit.cz --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index ff344a9a81a6..cfdeaa81f1bb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1078,7 +1078,7 @@ }; qfprom@784000 { - compatible = "qcom,qfprom"; + compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; reg = <0 0x00784000 0 0x8ff>; #address-cells = <1>; #size-cells = <1>; From 72cb4c48a46a7cfa58eb5842c0d3672ddd5bd9ad Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Tue, 7 Dec 2021 09:27:10 +0200 Subject: [PATCH 411/574] arm64: dts: qcom: ipq6018: Fix gpio-ranges property There must be three parameters in gpio-ranges property. Fixes this not very helpful error message: OF: /soc/pinctrl@1000000: (null) = 3 found 3 Fixes: 1e8277854b49 ("arm64: dts: Add ipq6018 SoC and CP01 board support") Cc: Sricharan R Signed-off-by: Baruch Siach Tested-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/8a744cfd96aff5754bfdcf7298d208ddca5b319a.1638862030.git.baruch@tkos.co.il --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 933b56103a46..66ec5615651d 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -220,7 +220,7 @@ interrupts = ; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 80>; + gpio-ranges = <&tlmm 0 0 80>; interrupt-controller; #interrupt-cells = <2>; From 5188049c9b36d718124e2cce91803a26a34a0ad6 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:30 +0530 Subject: [PATCH 412/574] arm64: dts: qcom: Add base SM8450 DTSI This add based DTSI for SM8450 SoC and includes base description of CPUs, GCC, RPMHCC, UART, interuupt-controller which helps to boot to shell with console on boards with this SoC Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-2-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 476 +++++++++++++++++++++++++++ 1 file changed, 476 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8450.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi new file mode 100644 index 000000000000..96fbf4be3f89 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <76800000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <274>; + exit-latency-us = <480>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <327>; + exit-latency-us = <1502>; + min-residency-us = <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-l3-off"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <584>; + exit-latency-us = <2332>; + min-residency-us = <6118>; + local-timer-stop; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <2893>; + exit-latency-us = <4023>; + min-residency-us = <9987>; + local-timer-stop; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm8450", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sm8450"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart7: serial@99c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8450-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, + <94 609 31>, <125 63 1>, <126 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ + <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ + interrupts = ; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + reg = <0x0 0x17420000 0x0 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0 0x17421000 0x0 0x1000>, + <0x0 0x17422000 0x0 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x0 0x17423000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x0 0x17425000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x0 0x17427000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x0 0x17429000 0x0 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x0 0x1742b000 0x0 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x0 0x1742d000 0x0 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>, + <0x0 0x17a30000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sm8450-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; +}; From ec950d55728459248e78f5c70ab3e3c2f7c22e38 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:31 +0530 Subject: [PATCH 413/574] arm64: dts: qcom: sm8450: Add tlmm nodes Add tlmm node found in SM8450 SoC and uart pin configuration Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-3-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 96fbf4be3f89..fb93d53d3433 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -343,6 +343,8 @@ reg = <0 0x0099c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -366,6 +368,32 @@ interrupt-controller; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8450-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + wakeup-parent = <&pdc>; + + qup_uart7_rx: qup-uart7-rx { + pins = "gpio26"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart7_tx: qup-uart7-tx { + pins = "gpio27"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + }; + intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From 285f97bc4b017b013d273a69ba3ee12252990812 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:32 +0530 Subject: [PATCH 414/574] arm64: dts: qcom: sm8450: Add reserved memory nodes Add the reserved memory nodes for SM8450. This is based on the downstream documentation. Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-4-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 221 +++++++++++++++++++++++++++ 1 file changed, 221 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index fb93d53d3433..d9439c6ebfa2 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -310,6 +310,227 @@ }; }; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_dt_log_mem: memory@80600000 { + reg = <0x0 0x80600000 0x0 0x40000>; + no-map; + }; + + xbl_ramdump_mem: memory@80640000 { + reg = <0x0 0x80640000 0x0 0x180000>; + no-map; + }; + + xbl_sc_mem: memory@807c0000 { + reg = <0x0 0x807c0000 0x0 0x40000>; + no-map; + }; + + aop_image_mem: memory@80800000 { + reg = <0x0 0x80800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: memory@80860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x80860000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: memory@80880000 { + reg = <0x0 0x80880000 0x0 0x20000>; + no-map; + }; + + tme_crash_dump_mem: memory@808a0000 { + reg = <0x0 0x808a0000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: memory@808e0000 { + reg = <0x0 0x808e0000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: memory@808e4000 { + reg = <0x0 0x808e4000 0x0 0x10000>; + no-map; + }; + + /* secdata region can be reused by apps */ + smem: memory@80900000 { + compatible = "qcom,smem"; + reg = <0x0 0x80900000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + cpucp_fw_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap: memory@80c00000 { + reg = <0x0 0x80c00000 0x0 0x4600000>; + no-map; + }; + + camera_mem: memory@85200000 { + reg = <0x0 0x85200000 0x0 0x500000>; + no-map; + }; + + video_mem: memory@85700000 { + reg = <0x0 0x85700000 0x0 0x700000>; + no-map; + }; + + adsp_mem: memory@85e00000 { + reg = <0x0 0x85e00000 0x0 0x2100000>; + no-map; + }; + + slpi_mem: memory@88000000 { + reg = <0x0 0x88000000 0x0 0x1900000>; + no-map; + }; + + cdsp_mem: memory@89900000 { + reg = <0x0 0x89900000 0x0 0x2000000>; + no-map; + }; + + ipa_fw_mem: memory@8b900000 { + reg = <0x0 0x8b900000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: memory@8b910000 { + reg = <0x0 0x8b910000 0x0 0xa000>; + no-map; + }; + + gpu_micro_code_mem: memory@8b91a000 { + reg = <0x0 0x8b91a000 0x0 0x2000>; + no-map; + }; + + spss_region_mem: memory@8ba00000 { + reg = <0x0 0x8ba00000 0x0 0x180000>; + no-map; + }; + + /* First part of the "SPU secure shared memory" region */ + spu_tz_shared_mem: memory@8bb80000 { + reg = <0x0 0x8bb80000 0x0 0x60000>; + no-map; + }; + + /* Second part of the "SPU secure shared memory" region */ + spu_modem_shared_mem: memory@8bbe0000 { + reg = <0x0 0x8bbe0000 0x0 0x20000>; + no-map; + }; + + mpss_mem: memory@8bc00000 { + reg = <0x0 0x8bc00000 0x0 0x13200000>; + no-map; + }; + + cvp_mem: memory@9ee00000 { + reg = <0x0 0x9ee00000 0x0 0x700000>; + no-map; + }; + + global_sync_mem: memory@a6f00000 { + reg = <0x0 0xa6f00000 0x0 0x100000>; + no-map; + }; + + /* uefi region can be reused by APPS */ + + /* Linux kernel image is loaded at 0xa0000000 */ + + oem_vm_mem: memory@bb000000 { + reg = <0x0 0xbb000000 0x0 0x5000000>; + no-map; + }; + + mte_mem: memory@c0000000 { + reg = <0x0 0xc0000000 0x0 0x20000000>; + no-map; + }; + + qheebsp_reserved_mem: memory@e0000000 { + reg = <0x0 0xe0000000 0x0 0x600000>; + no-map; + }; + + cpusys_vm_mem: memory@e0600000 { + reg = <0x0 0xe0600000 0x0 0x400000>; + no-map; + }; + + hyp_reserved_mem: memory@e0a00000 { + reg = <0x0 0xe0a00000 0x0 0x100000>; + no-map; + }; + + trust_ui_vm_mem: memory@e0b00000 { + reg = <0x0 0xe0b00000 0x0 0x4af3000>; + no-map; + }; + + trust_ui_vm_qrtr: memory@e55f3000 { + reg = <0x0 0xe55f3000 0x0 0x9000>; + no-map; + }; + + trust_ui_vm_vblk0_ring: memory@e55fc000 { + reg = <0x0 0xe55fc000 0x0 0x4000>; + no-map; + }; + + trust_ui_vm_swiotlb: memory@e5600000 { + reg = <0x0 0xe5600000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: memory@e8800000 { + reg = <0x0 0xe8800000 0x0 0x100000>; + no-map; + }; + + tags_mem: memory@e8900000 { + reg = <0x0 0xe8900000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: memory@e9b00000 { + reg = <0x0 0xe9b00000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: memory@ea000000 { + reg = <0x0 0xea000000 0x0 0x3900000>; + no-map; + }; + + trusted_apps_ext_mem: memory@ed900000 { + reg = <0x0 0xed900000 0x0 0x3b00000>; + no-map; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; From 892d5395396d5515c42e502810884225776b3b10 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:33 +0530 Subject: [PATCH 415/574] arm64: dts: qcom: sm8450: add smmu nodes Add the apps smmu node as found in the SM8450 SoC Signed-off-by: Vinod Koul Acked-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-5-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 103 +++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d9439c6ebfa2..d29680c405bf 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -615,6 +615,109 @@ }; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From 24de05c38e6bfe80fccc3b632c142accfaa7232d Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:34 +0530 Subject: [PATCH 416/574] arm64: dts: qcom: Add base SM8450 QRD DTS Add DTS for Qualcomm QRD platform which uses SM8450 SoC and mark the reserved nodes. Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-6-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 33 +++++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8450-qrd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index a3eedb8b33ee..f7232052d286 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -121,3 +121,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts new file mode 100644 index 000000000000..8dcd41c4e5ab --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +/dts-v1/; + +#include "sm8450.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8450 QRD"; + compatible = "qcom,sm8450-qrd", "qcom,sm8450"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <28 4>, <36 4>; +}; + +&uart7 { + status = "okay"; +}; From 128914ad230354ab4af9c3b86fdce2147f467553 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:35 +0530 Subject: [PATCH 417/574] arm64: dts: qcom: sm8450-qrd: Add rpmh regulator nodes Add the RPMH regulators found in QRD-SM8450 platform Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-7-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 322 ++++++++++++++++++++++++ 1 file changed, 322 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 8dcd41c4e5ab..2ab19608a455 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "sm8450.dtsi" / { @@ -18,6 +19,327 @@ chosen { stdout-path = "serial0:115200n8"; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + pm8350-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&vreg_s11b_0p95>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&vreg_s12b_1p25>; + vdd-l8-supply = <&vreg_s2h_0p95>; + + vreg_s10b_1p8: smps10 { + regulator-name = "vreg_s10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s11b_0p95: smps11 { + regulator-name = "vreg_s11b_0p95"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s12b_1p25: smps12 { + regulator-name = "vreg_s12b_1p25"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_l1b_0p91: ldo1 { + regulator-name = "vreg_l1b_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p07: ldo2 { + regulator-name = "vreg_l2b_3p07"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p9: ldo3 { + regulator-name = "vreg_l3b_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l5b_0p88: ldo5 { + regulator-name = "vreg_l5b_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p5: ldo7 { + regulator-name = "vreg_l7b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_bob>; + vdd-l2-l8-supply = <&vreg_bob>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_1p86: smps1 { + regulator-name = "vreg_s1c_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + }; + + vreg_s10c_1p05: smps10 { + regulator-name = "vreg_s10c_1p05"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-name = "vreg_l3c_3p0"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-name = "vreg_l4c_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6c_1p8: ldo6 { + regulator-name = "vreg_l6c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1968000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-name = "vreg_l13c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + }; + + pm8450-rpmh-regulators { + compatible = "qcom,pm8450-rpmh-regulators"; + qcom,pmic-id = "h"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-l2-supply = <&vreg_bob>; + vdd-l3-supply = <&vreg_bob>; + vdd-l4-supply = <&vreg_bob>; + + vreg_s2h_0p95: smps2 { + regulator-name = "vreg_s2h_0p95"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s3h_0p5: smps3 { + regulator-name = "vreg_s3h_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + }; + + vreg_l2h_0p91: ldo2 { + regulator-name = "vreg_l2h_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3h_0p91: ldo3 { + regulator-name = "vreg_l3h_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + }; + + pmr735a-rpmh-regulators { + compatible = "qcom,pmr735a-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + + vdd-l1-l2-supply = <&vreg_s2e_0p85>; + vdd-l3-supply = <&vreg_s1e_1p25>; + vdd-l4-supply = <&vreg_s1c_1p86>; + vdd-l5-l6-supply = <&vreg_s1c_1p86>; + vdd-l7-bob-supply = <&vreg_bob>; + + vreg_s1e_1p25: smps1 { + regulator-name = "vreg_s1e_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1296000>; + }; + + vreg_s2e_0p85: smps2 { + regulator-name = "vreg_s2e_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_l1e_0p8: ldo1 { + regulator-name = "vreg_l1e_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l4e_1p7: ldo4 { + regulator-name = "vreg_l4e_1p7"; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + }; + + vreg_l5e_0p88: ldo5 { + regulator-name = "vreg_l5e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + }; + + vreg_l6e_1p2: ldo6 { + regulator-name = "vreg_l6e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; }; &qupv3_id_0 { From 07fa917a335e139a108e94085c6beac3098e3874 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:36 +0530 Subject: [PATCH 418/574] arm64: dts: qcom: sm8450: add ufs nodes Add the UFS and QMP PHY node for SM8450 SoC Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-8-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 72 ++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d29680c405bf..9556d2fc46e0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -815,6 +815,78 @@ clocks = <&xo_board>; }; }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sm8450-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0xe0 0x0>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm8450-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0xe10>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", "ref_aux", "qref"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_0_CLKREF_EN>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: lanes@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells = <0>; + #clock-cells = <0>; + }; + }; }; timer { From 8f8f98c881686d21fc937f469d3a198f2f9bb9ba Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 15 Dec 2021 10:04:37 +0530 Subject: [PATCH 419/574] arm64: dts: qcom: sm8450-qrd: enable ufs nodes Enable the UFS and phy node and add the regulators used by them. Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-9-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 2ab19608a455..4b7ad190d538 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -353,3 +353,23 @@ &uart7 { status = "okay"; }; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p5>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <1200000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + vdda-max-microamp = <173000>; + vdda-pll-max-microamp = <24900>; +}; From 61eba74e473ed4cd64ec17440092f4a98913cda3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 15 Dec 2021 10:04:38 +0530 Subject: [PATCH 420/574] arm64: dts: qcom: sm8450: Add rpmhpd node This adds RPMH power domain found in SM8450 SoC Signed-off-by: Dmitry Baryshkov Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-10-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9556d2fc46e0..8fff4d54933f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include / { @@ -814,6 +815,56 @@ clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sm8450-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; }; ufs_mem_hc: ufshc@1d84000 { From 015a89f0d317dce4d2174059155c2fc39db7cbc8 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 15 Dec 2021 10:04:39 +0530 Subject: [PATCH 421/574] arm64: dts: qcom: sm8450: add cpufreq support The change adds a description of a SM8450 cpufreq-epss controller and references to it from CPU nodes. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-11-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 8fff4d54933f..56e3e8f771bd 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -44,6 +44,7 @@ next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -61,6 +62,7 @@ next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -75,6 +77,7 @@ next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -89,6 +92,7 @@ next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -103,6 +107,7 @@ next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -117,6 +122,7 @@ next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -132,6 +138,7 @@ next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -146,6 +153,7 @@ next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -867,6 +875,21 @@ }; }; + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x17d91000 0 0x1000>, + <0 0x17d92000 0 0x1000>, + <0 0x17d93000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; + #freq-domain-cells = <1>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; From bf0a257a9418ebcbe6ab2a73728f76969942e52a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 15 Dec 2021 10:04:40 +0530 Subject: [PATCH 422/574] arm64: dts: qcom: sm8450: add i2c13 and i2c14 device nodes Add device tree nodes for two i2c blocks: i2c13 and i2c14. Signed-off-by: Dmitry Baryshkov Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211215043440.605624-12-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 52 ++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 56e3e8f771bd..62082ed5335d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -582,6 +582,44 @@ }; }; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -609,6 +647,20 @@ gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + qup_i2c13_data_clk: qup-i2c13-data-clk { + pins = "gpio48", "gpio49"; + function = "qup13"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk { + pins = "gpio52", "gpio53"; + function = "qup14"; + drive-strength = <2>; + bias-pull-up; + }; + qup_uart7_rx: qup-uart7-rx { pins = "gpio26"; function = "qup7"; From ef5ad2608511596b8bd28f1e2b4fa8fadfd2f536 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Tue, 23 Nov 2021 23:19:22 +0700 Subject: [PATCH 423/574] ARM: dts: qcom: Drop input-name property This property doesn't seem to exist in the documentation nor in source code, but for some reason it is defined in a bunch of device trees. Signed-off-by: Dang Huynh Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211123161919.1506755-1-danct12@riseup.net --- arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts | 1 - arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts | 1 - arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 1 - arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 1 - arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts | 1 - arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts | 1 - arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts | 1 - 7 files changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts index f8c97efc61fc..0cee62c7b8b0 100644 --- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts +++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts @@ -19,7 +19,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts index ea15b645b229..6d77e0f8ca4d 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -20,7 +20,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 30ee913faae6..069136170198 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -450,7 +450,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 003f0fa9c857..96e1c978b878 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -349,7 +349,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts index 398a3eaf306b..79e2cfbbb1ba 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts @@ -20,7 +20,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts index b4dd85bd4faf..e66937e3f7dd 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts @@ -20,7 +20,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts index 9743beebd84d..a62e5c25b23c 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -20,7 +20,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; From eb197dfe389a35566c8e27c537355aaed04fed67 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Fri, 10 Dec 2021 10:23:19 -0300 Subject: [PATCH 424/574] ARM: dts: imx6ulz-bsh-smm-m2: Add BSH SMM-M2 IMX6ULZ SystemMaster Add DTS of BSH SMM-M2 SystemMaster. This version comes with: - 128 MiB DDR3 RAM - 256 MiB Nand - wifi - bluetooth Signed-off-by: Ariel D'Alessandro Signed-off-by: Michael Trimarchi Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts | 146 +++++++++++++++++++++++ 2 files changed, 148 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 51a6dd687191..ab965ad2d6a9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -701,7 +701,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ - imx6ulz-14x14-evk.dtb + imx6ulz-14x14-evk.dtb \ + imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-aster.dtb \ diff --git a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts new file mode 100644 index 000000000000..59bcfc9a6b10 --- /dev/null +++ b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include +#include "imx6ulz.dtsi" + +/ { + model = "BSH SMM M2"; + compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz"; + + chosen { + stdout-path = &uart4; + }; + + usdhc2_pwrseq: usdhc2-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + bus-width = <4>; + no-1-8-v; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + cap-sdio-irq; + mmc-pwrseq = <&usdhc2_pwrseq>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&wdog1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b099 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b099 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 /* BT_REG_ON */ + MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x100b1 /* BT_DEV_WAKE out */ + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BT_HOST_WAKE in */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x79 /* WL_REG_ON */ + MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x100b1 /* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 /* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */ + MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */ + >; + }; +}; From 538e5f7106f61e6b8404b0509f71f518123968cd Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Wed, 8 Dec 2021 22:40:45 +1000 Subject: [PATCH 425/574] ARM: dts: imx7d-remarkable2: add wacom digitizer device Add Wacom I2C support for the reMarkable 2 eInk tablet using the generic I2C HID framework. Signed-off-by: Alistair Francis Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-remarkable2.dts | 59 +++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-remarkable2.dts b/arch/arm/boot/dts/imx7d-remarkable2.dts index 89cbf13097a4..a2a91bfdd98e 100644 --- a/arch/arm/boot/dts/imx7d-remarkable2.dts +++ b/arch/arm/boot/dts/imx7d-remarkable2.dts @@ -34,6 +34,19 @@ startup-delay-us = <150>; }; + reg_digitizer: regulator-digitizer { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_DIGITIZER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_digitizer_reg>; + pinctrl-1 = <&pinctrl_digitizer_reg>; + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; /* 100 ms */ + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -51,6 +64,26 @@ assigned-clock-rates = <0>, <32768>; }; +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + wacom_digitizer: digitizer@9 { + compatible = "hid-over-i2c"; + reg = <0x09>; + hid-descr-addr = <0x01>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wacom>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + touchscreen-inverted-x; + touchscreen-inverted-y; + vdd-supply = <®_digitizer>; + }; +}; + &snvs_pwrkey { status = "okay"; }; @@ -117,6 +150,25 @@ fsl,ext-reset-output; }; +&iomuxc_lpsr { + pinctrl_digitizer_reg: digitizerreggrp { + fsl,pins = < + /* DIGITIZER_PWR_EN */ + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 + >; + }; + + pinctrl_wacom: wacomgrp { + fsl,pins = < + /*MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x00000014 FWE */ + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x00000074 /* PDCTB */ + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x00000034 /* WACOM INT */ + /*MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x00000014 WACOM PWR ENABLE */ + /*MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x00000074 WACOM RESET */ + >; + }; +}; + &iomuxc { pinctrl_brcm_reg: brcmreggrp { fsl,pins = < @@ -125,6 +177,13 @@ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 From ee47d510b4d2a771ff42b2dca637195ec5e24d0b Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 11 Dec 2021 23:17:43 +0100 Subject: [PATCH 426/574] arm64: dts: nitrogen8-som: correct network PHY reset Add the missing reset-gpios property to allow Linux to fully reset the network PHY and fix the pinmux to add the neccessary pull-ups for the PHY strap configuration. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi index 36fc428ebe30..5f27d3a17ddb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi @@ -69,6 +69,9 @@ reg = <4>; interrupt-parent = <&gpio1>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; }; @@ -191,13 +194,13 @@ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1 + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1 + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41 >; }; From 92d2c17edb2a796ed548b3b50da46c8a29e28e0f Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sun, 12 Dec 2021 14:49:12 +0100 Subject: [PATCH 427/574] arm64: dts: nitrogen8-som: correct i2c1 pad-ctrl The slew rate and drive-strength of the i2c1 pads were much too high. Bring them down to avoid signal quality issues. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi index 5f27d3a17ddb..395f77b5aca7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi @@ -206,8 +206,8 @@ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022 + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000022 >; }; From 0baddea60e8d536fd240008882128fc32eda74d6 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 29 Nov 2021 19:26:33 +0100 Subject: [PATCH 428/574] arm64: dts: allwinner: h6: Add Hantro G2 node H6 SoC has a second VPU, dedicated to VP9 decoding. It's a slightly older design, though. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211129182633.480021-10-jernej.skrabec@gmail.com --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 46ed529a4dc2..fbe94abbb1f9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -153,6 +153,15 @@ }; }; + video-codec-g2@1c00000 { + compatible = "allwinner,sun50i-h6-vpu-g2"; + reg = <0x01c00000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_VP9>; + }; + video-codec@1c0e000 { compatible = "allwinner,sun50i-h6-video-engine"; reg = <0x01c0e000 0x2000>; From 842912c42e88748648901e22c238834f7a6ccb26 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 13 Dec 2021 21:40:47 +0100 Subject: [PATCH 429/574] arm64: dts: imx8mm: don't assign PLL2 in SoC dtsi The base i.MX8MM dtsi changes the audio PLL2 rate, which gets in the way if it should be used for anything else than audio. As this PLL doesn't seem to be used by any upstream supported board, just remove the rate configuration to allow boards to set it up as they wish. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c84d76860441..f77f90ed416f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -619,8 +619,7 @@ <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MM_SYS_PLL3>, <&clk IMX8MM_VIDEO_PLL1>, - <&clk IMX8MM_AUDIO_PLL1>, - <&clk IMX8MM_AUDIO_PLL2>; + <&clk IMX8MM_AUDIO_PLL1>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, <&clk IMX8MM_ARM_PLL_OUT>, <&clk IMX8MM_SYS_PLL3_OUT>, @@ -630,8 +629,7 @@ <400000000>, <750000000>, <594000000>, - <393216000>, - <361267200>; + <393216000>; }; src: reset-controller@30390000 { From 674d63dfadb5da1e28678574e5bce4793b9f65f3 Mon Sep 17 00:00:00 2001 From: Ioana Radulescu Date: Tue, 14 Dec 2021 01:23:34 -0600 Subject: [PATCH 430/574] arm64: dts: lx2160a-rdb: Add Inphi PHY node DPMAC5 and DPMAC6 are connected to 25G Inphi PHY Signed-off-by: Vicentiu Galanopulo Signed-off-by: Florin Chiculita Signed-off-by: Ioana Radulescu Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-lx2160a-rdb.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 028ff8074b9d..0ec41838e54e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -49,6 +49,14 @@ managed = "in-band-status"; }; +&dpmac5 { + phy-handle = <&inphi_phy>; +}; + +&dpmac6 { + phy-handle = <&inphi_phy>; +}; + &dpmac17 { phy-handle = <&rgmii_phy1>; phy-connection-type = "rgmii-id"; @@ -109,6 +117,15 @@ }; }; +&emdio2 { + status = "okay"; + + inphi_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; +}; + &esdhc0 { sd-uhs-sdr104; sd-uhs-sdr50; From 519bace37b2d160a7a1cb4199f9828d12c28ba12 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Tue, 14 Dec 2021 01:23:35 -0600 Subject: [PATCH 431/574] arm64: dts: lx2160a: add optee-tz node Disabled by default in SoC dtsi and enables in board dts files. Signed-off-by: Pankaj Gupta Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 4 ++++ arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++ arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++ arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 4 ++++ 4 files changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts index d858d9c8b583..8354af0b31e3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts @@ -156,6 +156,10 @@ }; }; +&optee { + status = "okay"; +}; + &sata0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 0ec41838e54e..0c44b3cbef77 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -219,6 +219,10 @@ }; }; +&optee { + status = "okay"; +}; + &pcs_mdio3 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index dc8661ebd1f6..3123dea573f6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1751,4 +1751,12 @@ }; }; }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index 67e07a8a42bd..5b7c51c1e3c2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -315,6 +315,10 @@ }; }; +&optee { + status = "okay"; +}; + &sata0 { status = "okay"; }; From eb70c4a3b1aa2a9d6195ce8bb6ff09b40bc6451e Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Tue, 14 Dec 2021 01:23:36 -0600 Subject: [PATCH 432/574] arm64: dts: lx2160a-qds: Add mdio mux nodes The two external MDIO buses used to communicate with phy devices that are external to SOC are muxed in LX2160AQDS board. These buses can be routed to any one of the eight IO slots on LX2160AQDS board depending on value in fpga register 0x54. Additionally the external MDIO1 is used to communicate to the onboard RGMII phy devices. The mdio1 is controlled by bits 4-7 of fpga register and mdio2 is controlled by bits 4-7 of fpga register. Signed-off-by: Pankaj Bansal Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-lx2160a-qds.dts | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts index 8354af0b31e3..2ecfa90f5e28 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts @@ -31,6 +31,130 @@ regulator-boot-on; regulator-always-on; }; + + mdio-mux-1 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 0>; + mdio-parent-bus = <&emdio1>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* On-board PHY #1 RGMI1*/ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@8 { /* On-board PHY #2 RGMI2*/ + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@18 { /* Slot #1 */ + reg = <0x18>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@19 { /* Slot #2 */ + reg = <0x19>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1a { /* Slot #3 */ + reg = <0x1a>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1b { /* Slot #4 */ + reg = <0x1b>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1c { /* Slot #5 */ + reg = <0x1c>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1d { /* Slot #6 */ + reg = <0x1d>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1e { /* Slot #7 */ + reg = <0x1e>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1f { /* Slot #8 */ + reg = <0x1f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 1>; + mdio-parent-bus = <&emdio2>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* Slot #1 (secondary EMI) */ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1 { /* Slot #2 (secondary EMI) */ + reg = <0x01>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@2 { /* Slot #3 (secondary EMI) */ + reg = <0x02>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@3 { /* Slot #4 (secondary EMI) */ + reg = <0x03>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@4 { /* Slot #5 (secondary EMI) */ + reg = <0x04>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@5 { /* Slot #6 (secondary EMI) */ + reg = <0x05>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@6 { /* Slot #7 (secondary EMI) */ + reg = <0x06>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@7 { /* Slot #8 (secondary EMI) */ + reg = <0x07>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; &can0 { @@ -81,6 +205,14 @@ }; }; +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + &esdhc0 { status = "okay"; }; @@ -107,6 +239,19 @@ &i2c0 { status = "okay"; + fpga@66 { + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", + "simple-mfd"; + reg = <0x66>; + + mux: mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ + <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ + }; + }; + i2c-mux@77 { compatible = "nxp,pca9547"; reg = <0x77>; From a5b13770faf324e4cf25a9c0de323fca8dd789fa Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Tue, 14 Dec 2021 01:23:40 -0600 Subject: [PATCH 433/574] arm64: dts: lx2160a: enable usb3-lpm-capable for usb3 nodes Enable USB3 HW LPM feature for lx2160a. Signed-off-by: Ran Wang Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 3123dea573f6..6274bec3ec32 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1023,6 +1023,7 @@ interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + usb3-lpm-capable; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; @@ -1034,6 +1035,7 @@ interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + usb3-lpm-capable; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; From 23817c8396730371662f47f33c30c29e45649a01 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Tue, 14 Dec 2021 01:23:41 -0600 Subject: [PATCH 434/574] arm64: dts: lx2162a-qds: support SD UHS-I and eMMC HS400 modes The default NXP SDHC adapter cards for LX2162AQDS are SD 2.0/3.0 adapter card for eSDHC1, and eMMC 5.1 adapter card for eSDHC2. Add speed modes properties supported by the two adapters in device tree node. Signed-off-by: Yangbo Lu Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index 5b7c51c1e3c2..dcca026446d8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -234,10 +234,17 @@ }; &esdhc0 { + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; status = "okay"; }; &esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; status = "okay"; }; From cc03211c745a729d072a33133379c32411b5ce52 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Tue, 14 Dec 2021 01:23:42 -0600 Subject: [PATCH 435/574] arm64: dts: lx2162a-qds: add interrupt line for RTC node Add interrupt line for RTC node on lx2162a-qds Signed-off-by: Biwen Li Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index dcca026446d8..a1644ceed154 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -317,6 +317,8 @@ rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; + /* IRQ_RTC_B -> IRQ11_B(CPLD) -> IRQ11(CPU), active low */ + interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>; }; }; }; From 20c7b41d03d3c1d75cd652a45554b3594e513e3d Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Tue, 14 Dec 2021 10:03:53 +0100 Subject: [PATCH 436/574] ARM: dts: imx6qdl-dhcom: Add USB overcurrent pin on SoM layer Add USB overcurrent pin muxing on SoM layer. On DRC02 and PDK2 the USB overcurrent pin isn't connected, but a USB hub on the board takes care of the USB overcurrent instead. Therefore disable it there with the property disable-over-current. Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Marek Vasut Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi | 4 ++++ arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi | 4 ++++ arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi | 1 + 3 files changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi index 3d0a50a9ab21..702cd4a1b2e6 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi @@ -95,6 +95,10 @@ rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */ }; +&usbh1 { + disable-over-current; +}; + &usdhc2 { /* SD card */ status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi index dc21853706a5..dc89b554e694 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi @@ -260,6 +260,10 @@ status = "okay"; }; +&usbh1 { + disable-over-current; +}; + &usdhc2 { /* SD card */ status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi index b2b7daf43ede..5befbe13d1a3 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi @@ -729,6 +729,7 @@ pinctrl_usbh1: usbh1-grp { fsl,pins = < MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b1 >; }; From e84e22c0c3b34898269eb054c6366a75b331d395 Mon Sep 17 00:00:00 2001 From: Xiaowei Bao Date: Tue, 14 Dec 2021 03:32:33 -0600 Subject: [PATCH 437/574] arm64: dts: ls1028a: Add PCIe EP nodes Add PCIe EP nodes for ls1028a to support EP mode. Signed-off-by: Xiaowei Bao Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index fd3f3e8bb6ce..9010c535252a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -637,6 +637,18 @@ status = "disabled"; }; + pcie_ep1: pcie-ep@3400000 { + compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + interrupts = ; /* PME interrupt */ + interrupt-names = "pme"; + num-ib-windows = <6>; + num-ob-windows = <8>; + status = "disabled"; + }; + pcie2: pcie@3500000 { compatible = "fsl,ls1028a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ @@ -664,6 +676,18 @@ status = "disabled"; }; + pcie_ep2: pcie-ep@3500000 { + compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000 + 0x88 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + interrupts = ; /* PME interrupt */ + interrupt-names = "pme"; + num-ib-windows = <6>; + num-ob-windows = <8>; + status = "disabled"; + }; + smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; From dd3d936a1b17d2d63deb3347d8e8d1dad2a410a9 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Tue, 14 Dec 2021 03:32:34 -0600 Subject: [PATCH 438/574] arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source Add flextimer2 based ftm_alarm1 node and enable it to be the default rtc wakeup source for rdb and qds boards instead of the original flextimer1 which is used by PWM. The ftm_alarm0 node hence is disabled by default. Signed-off-by: Biwen Li Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 6 +++++- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 6 +++++- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 9 +++++++++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 6e2a1da662fb..00d5b81bdef3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -25,7 +25,7 @@ serial1 = &duart1; mmc0 = &esdhc; mmc1 = &esdhc1; - rtc1 = &ftm_alarm0; + rtc1 = &ftm_alarm1; }; chosen { @@ -234,6 +234,10 @@ }; }; +&ftm_alarm1 { + status = "okay"; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 639f40740d56..6d26b010187c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -21,7 +21,7 @@ serial1 = &duart1; mmc0 = &esdhc; mmc1 = &esdhc1; - rtc1 = &ftm_alarm0; + rtc1 = &ftm_alarm1; spi0 = &fspi; ethernet0 = &enetc_port0; ethernet1 = &enetc_port2; @@ -181,6 +181,10 @@ }; }; +&ftm_alarm1 { + status = "okay"; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 9010c535252a..f2564faf7067 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -1198,6 +1198,15 @@ reg = <0x0 0x2800000 0x0 0x10000>; fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; interrupts = ; + status = "disabled"; + }; + + ftm_alarm1: timer@2810000 { + compatible = "fsl,ls1028a-ftm-alarm"; + reg = <0x0 0x2810000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; + interrupts = ; + status = "disabled"; }; }; From 71799672ea24d2935322d655d2407c1ccd7db9ff Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Tue, 14 Dec 2021 03:32:35 -0600 Subject: [PATCH 439/574] arm64: dts: ls1028a: add flextimer based pwm nodes Add pwm nodes using flextimer controller. Signed-off-by: Biwen Li Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index f2564faf7067..5a7b26a1bad2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -66,6 +66,13 @@ }; }; + rtc_clk: rtc-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "rtc_clk"; + }; + sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -1186,6 +1193,94 @@ reg = <0x01 0xf0800000 0x0 0x10000>; }; + pwm0: pwm@2800000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2800000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm1: pwm@2810000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2810000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm2: pwm@2820000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2820000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm3: pwm@2830000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2830000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm4: pwm@2840000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2840000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm5: pwm@2850000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2850000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm6: pwm@2860000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2860000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm7: pwm@2870000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2870000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + rcpm: power-controller@1e34040 { compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; reg = <0x0 0x1e34040 0x0 0x1c>; From b2e2d3e02fb60f4d45843ceebef0465c59c8d392 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Tue, 14 Dec 2021 03:32:37 -0600 Subject: [PATCH 440/574] arm64: dts: ls1028a-rdb: enable pwm0 Enable pwm0 on ls1028a-rdb board which uses flextimer1. Signed-off-by: Biwen Li Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 6d26b010187c..68c31cb8eead 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -286,6 +286,10 @@ status = "okay"; }; +&pwm0 { + status = "okay"; +}; + &sai4 { status = "okay"; }; From cbe9d948eadfe352ad45495a7cc5bf20a1b29d90 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Tue, 14 Dec 2021 03:32:38 -0600 Subject: [PATCH 441/574] arm64: dts: ls1028a-qds: move rtc node to the correct i2c bus The i2c rtc is on i2c2 bus not i2c1 bus, so fix it in dts. Signed-off-by: Biwen Li Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 00d5b81bdef3..baa1cc9b9835 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -276,11 +276,6 @@ vcc-supply = <&sb_3v3>; }; - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; - eeprom@56 { compatible = "atmel,24c512"; reg = <0x56>; @@ -322,6 +317,15 @@ }; +&i2c1 { + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; +}; + &enetc_port1 { phy-handle = <&qds_phy1>; phy-mode = "rgmii-id"; From 52b98481171eee3fa5abbedd57f9e64cbfb727e1 Mon Sep 17 00:00:00 2001 From: Vabhav Sharma Date: Tue, 14 Dec 2021 03:32:39 -0600 Subject: [PATCH 442/574] arm64: dts: ls1028a-qds: enable lpuart1 LPUART nodes by default are disabled in LS1028A device tree, Enabling LPUART1 node. Signed-off-by: Vabhav Sharma Acked-by: Fugang Duan Signed-off-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index baa1cc9b9835..782853a449cc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -336,6 +336,10 @@ status = "okay"; }; +&lpuart1 { + status = "okay"; +}; + &sai1 { status = "okay"; }; From e426d63e752bdbe7d5ba2d872319dde9ab844a07 Mon Sep 17 00:00:00 2001 From: Alex Marginean Date: Tue, 14 Dec 2021 03:32:40 -0600 Subject: [PATCH 443/574] arm64: dts: ls1028a-qds: add overlays for various serdes protocols Add overlays for various serdes protocols on LS1028A QDS board using different PHY cards. These should be applied at boot, based on serdes configuration. If no overlay is applied, only the RGMII interface on the QDS is available in Linux. Building device tree fragments requires passing the "-@" argument to dtc, which increases the base dtb size and might cause some platforms to fail to store the new binary. To avoid that, it would be nice to only pass "-@" for the platforms where fragments will be used, aka LS1028A-QDS. One approach suggested by Rob Herring is used here: https://lore.kernel.org/patchwork/patch/821645/ Also moved the enet* override nodes in dts file to be in alphabetic order. Signed-off-by: Alex Marginean Signed-off-by: Ioana Ciornei Signed-off-by: Dong Aisheng Signed-off-by: Jason Liu Signed-off-by: Vladimir Oltean Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 16 +++ .../dts/freescale/fsl-ls1028a-qds-13bb.dts | 113 ++++++++++++++++++ .../dts/freescale/fsl-ls1028a-qds-65bb.dts | 108 +++++++++++++++++ .../dts/freescale/fsl-ls1028a-qds-7777.dts | 82 +++++++++++++ .../dts/freescale/fsl-ls1028a-qds-85bb.dts | 107 +++++++++++++++++ .../dts/freescale/fsl-ls1028a-qds-899b.dts | 75 ++++++++++++ .../dts/freescale/fsl-ls1028a-qds-9999.dts | 79 ++++++++++++ .../boot/dts/freescale/fsl-ls1028a-qds.dts | 21 +++- .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +- 9 files changed, 596 insertions(+), 7 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 5018b8b1e5f2..6d8f0a532587 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -1,4 +1,14 @@ # SPDX-License-Identifier: GPL-2.0 + +# required for overlay support +DTC_FLAGS_fsl-ls1028a-qds := -@ +DTC_FLAGS_fsl-ls1028a-qds-13bb := -@ +DTC_FLAGS_fsl-ls1028a-qds-65bb := -@ +DTC_FLAGS_fsl-ls1028a-qds-7777 := -@ +DTC_FLAGS_fsl-ls1028a-qds-85bb := -@ +DTC_FLAGS_fsl-ls1028a-qds-899b := -@ +DTC_FLAGS_fsl-ls1028a-qds-9999 := -@ + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb @@ -11,6 +21,12 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts new file mode 100644 index 000000000000..f748a2c12a70 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 13bb + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C. + * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot2_qxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qxgmii0>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qxgmii1>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qxgmii2>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qxgmii3>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@4 { + target = <&mscc_felix>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts new file mode 100644 index 000000000000..8ffb707a1576 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 69xx + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "2500base-x"; + managed = "in-band-status"; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@4 { + target = <&mscc_felix>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts new file mode 100644 index 000000000000..eb6a1e674f10 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 7777 + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing + * disabled, plugged in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot1_sxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&mscc_felix_ports>; + + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot1_sxgmii0>; + phy-mode = "2500base-x"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sxgmii1>; + phy-mode = "2500base-x"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sxgmii2>; + phy-mode = "2500base-x"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sxgmii3>; + phy-mode = "2500base-x"; + }; + }; + }; + + fragment@2 { + target = <&mscc_felix>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts new file mode 100644 index 000000000000..8e90c3088ba1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85bb + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@1c { + /* 1st port on VSC8234 */ + reg = <0x1c>; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@4 { + target = <&mscc_felix>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts new file mode 100644 index 000000000000..5d0a094e6c44 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85xx + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-24801 card in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; + + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; + + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + __overlay__ { + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mscc_felix_ports>; + __overlay__ { + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts new file mode 100644 index 000000000000..1ef743c48e84 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85xx + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-24801 card in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; + + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; + + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + }; + + fragment@1 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sgmii3>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@2 { + target = <&mscc_felix>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 782853a449cc..177bc1405f0f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -211,6 +211,16 @@ status = "okay"; }; +&enetc_port1 { + phy-handle = <&qds_phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc_port2 { + status = "okay"; +}; + &esdhc { status = "okay"; }; @@ -326,12 +336,6 @@ }; }; -&enetc_port1 { - phy-handle = <&qds_phy1>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - &lpuart0 { status = "okay"; }; @@ -340,6 +344,11 @@ status = "okay"; }; +&mscc_felix_port4 { + ethernet = <&enetc_port2>; + status = "okay"; +}; + &sai1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 5a7b26a1bad2..5bb8c26e0825 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -1115,7 +1115,7 @@ interrupts = ; status = "disabled"; - ports { + mscc_felix_ports: ports { #address-cells = <1>; #size-cells = <0>; From 841b71c57bcf63137983bad340ffc7b6bfbc6b0a Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 16 Dec 2021 09:41:05 +0100 Subject: [PATCH 444/574] ARM: dts: imx6qdl: phytec: Add support for optional PEB-EVAL-01 board The PHYTEC PEV-EVAL-01 expansion board adds support for additional gpio-triggered user-leds and gpio-key support. Signed-off-by: Yunus Bas Signed-off-by: Shawn Guo --- .../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 + .../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 + .../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 + .../dts/imx6qdl-phytec-mira-peb-eval-01.dtsi | 71 +++++++++++++++++++ .../boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 + 5 files changed, 75 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts index 9f7f9f98139d..b057fa664a6b 100644 --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts @@ -8,6 +8,7 @@ #include "imx6dl.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" / { model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts index 2e70ea5623c6..db6e2cc36759 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts @@ -8,6 +8,7 @@ #include "imx6q.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts index 65d2e483c136..51ff601b1aec 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts @@ -8,6 +8,7 @@ #include "imx6q.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi new file mode 100644 index 000000000000..037b60197598 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik + * Author: Christian Hemp + */ + +#include + +/ { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + power { + label = "Power Button"; + gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + sleep { + label = "Sleep Button"; + gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>; + status = "disabled"; + + user-led1 { + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + + user-led2 { + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + + user-led3 { + gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0 + >; + }; + + pinctrl_user_leds: userledsgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts index f27d7ab42626..06fe0c5315fc 100644 --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts @@ -8,6 +8,7 @@ #include "imx6qp.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" / { model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; From d3af422c0587f55f9d9d3375bf6bb61bea53f014 Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 16 Dec 2021 09:41:06 +0100 Subject: [PATCH 445/574] ARM: dts: imx6qdl: phytec: Add support for optional PEB-AV-02 LCD adapter The PEB-AV-02 expansion adapter extends the phyBOARD-Mira boards to connect parallel LCD displays, either with capacitive or resistive touch. Signed-off-by: Yunus Bas Signed-off-by: Shawn Guo --- .../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 + .../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 + .../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 + .../dts/imx6qdl-phytec-mira-peb-av-02.dtsi | 119 ++++++++++++++++++ .../boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 + 5 files changed, 123 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts index b057fa664a6b..8165fae2b1d1 100644 --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts index db6e2cc36759..bbf5097ca974 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts @@ -9,6 +9,7 @@ #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts index 51ff601b1aec..95051e18324f 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi new file mode 100644 index 000000000000..393475cb0f4d --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik + * Author: Christian Hemp + */ + +/ { + display: display0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0>; + interface-pix-fmt = "rgb24"; + status = "disabled"; + + port@0 { + reg = <0>; + + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display0_out: endpoint { + remote-endpoint = <&peb_panel_lcd_in>; + }; + }; + }; + + panel-lcd { + compatible = "edt,etm0700g0edh6"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_pwr>; + power-supply = <®_display>; + enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + status = "disabled"; + + port { + peb_panel_lcd_in: endpoint { + remote-endpoint = <&display0_out>; + }; + }; + }; + + reg_display: regulator-peb-display { + compatible = "regulator-fixed"; + regulator-name = "peb-display"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&i2c1 { + edt_ft5x06: touchscreen@38 { + compatible = "edt,edt-ft5406"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + reg = <0x38>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_NONE>; + status = "disabled"; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_disp0: disp0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_disp0_pwr: disp0pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_edt_ft5x06: edtft5x06grp { + fsl,pins = < + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0xb0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts index 06fe0c5315fc..343639cb035c 100644 --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; From 0bc3e333a0c82ee8691bcfdf441644ce02bd8be0 Mon Sep 17 00:00:00 2001 From: Xiaoliang Yang Date: Thu, 16 Dec 2021 17:24:48 +0800 Subject: [PATCH 446/574] arm64: dts: imx8mp-evk: configure multiple queues on eqos Eqos ethernet support five queues on hardware, enable these queues and configure the priority of each queue. Uses Strict Priority as scheduling algorithms to ensure that the TSN function works. The priority of each queue is a bitmask value that maps VLAN tag priority to the queue. Since the hardware only supports five queues, this patch maps priority 0-4 to queues one by one, and priority 5-7 to queue 4. The total fifo size of 5 queues is 8192 bytes, if enable 5 queues with store-and-forward mode, it's not enough for large packets, which would trigger fifo overflow frequently. This patch set DMA to thresh mode to enable all 5 queues. Signed-off-by: Xiaoliang Yang Reviewed-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 68 ++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index cf03a82f9dcd..2eb943210678 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -86,6 +86,9 @@ pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; status = "okay"; mdio { @@ -103,6 +106,71 @@ realtek,clkout-disable; }; }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; }; &fec { From 3478494dcae155f0580e8f841458905f4fc739c2 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:42 +0300 Subject: [PATCH 447/574] ARM: tegra: Add 500 MHz entry to Tegra30 memory OPP table Extend memory OPPs with 500 MHz entry. This clock rate is used by ASUS Transformer tablets. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-peripherals-opp.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi index ff25350869b3..af9640401402 100644 --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -216,6 +216,18 @@ opp-supported-hw = <0x0008>; }; + opp-500000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x0007>; + }; + + opp-500000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x0008>; + }; + opp-533000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <533000000>; @@ -347,6 +359,12 @@ opp-peak-kBps = <3600000>; }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <4000000>; + }; + opp-533000000 { opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x000F>; From 83b7f0b8aeab4fc8271392fd32164efb7b3f55e9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:43 +0300 Subject: [PATCH 448/574] ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees Add OPP tables and power domains to all peripheral devices which support power management on Tegra20 SoC. Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../boot/dts/tegra20-acer-a500-picasso.dts | 1 + arch/arm/boot/dts/tegra20-colibri.dtsi | 3 +- arch/arm/boot/dts/tegra20-harmony.dts | 3 +- arch/arm/boot/dts/tegra20-paz00.dts | 1 + .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 912 ++++++++++++++++++ arch/arm/boot/dts/tegra20-seaboard.dts | 3 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 3 +- arch/arm/boot/dts/tegra20-trimslice.dts | 9 + arch/arm/boot/dts/tegra20-ventana.dts | 1 + arch/arm/boot/dts/tegra20.dtsi | 102 +- 10 files changed, 1033 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 2d5fead9de6b..4aa0eb0c50fe 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -718,6 +718,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <458>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; usb@c5000000 { diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index b1f2f7f82928..1eefb9ee4ac8 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -497,7 +497,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "VDD_CORE_1.2V"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -603,6 +603,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */ i2c-thermtrip { diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index f560bf743a19..79b6b79fab65 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -339,7 +339,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "vdd_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -565,6 +565,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; pcie@80003000 { diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 5ce6a1ff93de..fe1bffedc266 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -519,6 +519,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <0>; nvidia,sys-clock-req-active-high; + core-supply = <&core_vdd_reg>; }; usb@c5000000 { diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi index d4d0a5fa7015..1b808233a933 100644 --- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi @@ -1,6 +1,46 @@ // SPDX-License-Identifier: GPL-2.0 / { + core_opp_table: opp-table-core { + compatible = "operating-points-v2"; + opp-shared; + + core_opp_950: opp-950000 { + opp-microvolt = <950000 950000 1300000>; + opp-level = <950000>; + }; + + core_opp_1000: opp-1000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-level = <1000000>; + }; + + core_opp_1100: opp-1100000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-level = <1100000>; + }; + + core_opp_1200: opp-1200000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-level = <1200000>; + }; + + core_opp_1225: opp-1225000 { + opp-microvolt = <1225000 1225000 1300000>; + opp-level = <1225000>; + }; + + core_opp_1275: opp-1275000 { + opp-microvolt = <1275000 1275000 1300000>; + opp-level = <1275000>; + }; + + core_opp_1300: opp-1300000 { + opp-microvolt = <1300000 1300000 1300000>; + opp-level = <1300000>; + }; + }; + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; @@ -8,66 +48,77 @@ opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <36000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-47500000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <47500000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-50000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <50000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-54000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-57000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <57000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-100000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <100000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-108000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-126666000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <126666000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-150000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <150000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-190000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <190000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-216000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <216000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; opp-suspend; }; @@ -75,36 +126,897 @@ opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-333000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <333000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-380000000 { opp-microvolt = <1100000 1100000 1300000>; opp-hz = /bits/ 64 <380000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; }; opp-600000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; }; opp-666000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <666000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; }; opp-760000000 { opp-microvolt = <1300000 1300000 1300000>; opp-hz = /bits/ 64 <760000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1300>; + }; + }; + + host1x_dvfs_opp_table: opp-table-host1x { + compatible = "operating-points-v2"; + + opp-104500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <104500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-133000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-166000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <166000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + mpe_dvfs_opp_table: opp-table-mpe { + compatible = "operating-points-v2"; + + opp-104500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <104500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-142500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <142500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-152000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-228000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-228000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-237500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <237500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-266000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <266000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-275500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <275500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1100>; + }; + }; + + vi_dvfs_opp_table: opp-table-vi { + compatible = "operating-points-v2"; + + opp-85000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <85000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-100000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-150000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + epp_dvfs_opp_table: opp-table-epp { + compatible = "operating-points-v2"; + + opp-133000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-171000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + gr2d_dvfs_opp_table: opp-table-gr2d { + compatible = "operating-points-v2"; + + opp-133000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-171000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + gr3d_dvfs_opp_table: opp-table-gr3d { + compatible = "operating-points-v2"; + + opp-114000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <114000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-161500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-161500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-209000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-218500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-247000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-247000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-256500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <256500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-285000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-304000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-323000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <323000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-333500000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp-333500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1200>; + }; + + opp-351500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <351500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1275>; + }; + + opp-380000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-400000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1275>; + }; + + opp-400000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1200>; + }; + }; + + disp1_dvfs_opp_table: opp-table-disp1 { + compatible = "operating-points-v2"; + + opp-158000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-190000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + disp2_dvfs_opp_table: opp-table-disp2 { + compatible = "operating-points-v2"; + + opp-158000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-190000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + dsi_dvfs_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-100000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-500000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + hdmi_dvfs_opp_table: opp-table-hdmi { + compatible = "operating-points-v2"; + + opp-148500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <148500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + tvo_dvfs_opp_table: opp-table-tvo { + compatible = "operating-points-v2"; + + opp-250000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sclk_dvfs_opp_table: opp-table-sclk { + compatible = "operating-points-v2"; + + opp-95000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <95000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-123500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-133000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-152000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-159500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <159500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-171000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-180500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <180500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-207000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <207000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-218500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-222500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <222500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-229500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <229500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-240000000-1225 { + opp-microvolt = <1225000 1225000 1300000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1225>; + }; + + opp-240000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1200>; + }; + + opp-247000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp-256500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <256500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + + opp-260000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <260000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-262000000-1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <262000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1300>; + }; + + opp-264000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1275>; + }; + + opp-277500000-1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <277500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1300>; + }; + + opp-285000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1275>; + }; + + opp-292500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <292500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-300000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1275>; + }; + }; + + vde_dvfs_opp_table: opp-table-vde { + compatible = "operating-points-v2"; + + opp-95000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <95000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-123500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-123500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-152000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-152000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-171000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-209000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-209000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-218500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-237500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <237500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-275500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <275500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-285000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + }; + + ndflash_dvfs_opp_table: opp-table-ndflash { + compatible = "operating-points-v2"; + + opp-130000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <130000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-150000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-158000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-164000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <164000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + nor_dvfs_opp_table: opp-table-nor { + compatible = "operating-points-v2"; + + opp-92000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <92000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc2_dvfs_opp_table: opp-table-sdmmc2 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc4_dvfs_opp_table: opp-table-sdmmc4 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + pcie_dvfs_opp_table: opp-table-pcie { + compatible = "operating-points-v2"; + + opp-250000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + usbd_dvfs_opp_table: opp-table-usbd { + compatible = "operating-points-v2"; + + opp-480000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + usb2_dvfs_opp_table: opp-table-usb2 { + compatible = "operating-points-v2"; + + opp-480000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + usb3_dvfs_opp_table: opp-table-usb3 { + compatible = "operating-points-v2"; + + opp-480000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; }; }; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index f9309c07a9f2..c4a6a6a94559 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -444,7 +444,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "vdd_sm0,vdd_core"; regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1300000>; @@ -689,6 +689,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; memory-controller@7000f400 { diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 2ad56f84bb62..de39c5465c0a 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -357,7 +357,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "vdd_sys_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -477,6 +477,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; pcie@80003000 { diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 8bb0eaa610f2..9d0c86711de2 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -322,6 +322,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; pcie@80003000 { @@ -443,6 +444,14 @@ regulator-always-on; }; + vdd_core: regulator-core { + compatible = "regulator-fixed"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + sound { compatible = "nvidia,tegra-audio-trimslice"; nvidia,i2s-controller = <&tegra_i2s1>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index b1c92ba789be..b0a00970b61c 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -544,6 +544,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <458>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; usb@c5000000 { diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 6f493a8a8a9f..45fe111705af 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -42,6 +42,8 @@ clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; + power-domains = <&pd_core>; + operating-points-v2 = <&host1x_dvfs_opp_table>; #address-cells = <1>; #size-cells = <1>; @@ -55,6 +57,8 @@ clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + power-domains = <&pd_mpe>; + operating-points-v2 = <&mpe_dvfs_opp_table>; }; vi@54080000 { @@ -64,6 +68,8 @@ clocks = <&tegra_car TEGRA20_CLK_VI>; resets = <&tegra_car 20>; reset-names = "vi"; + power-domains = <&pd_venc>; + operating-points-v2 = <&vi_dvfs_opp_table>; }; epp@540c0000 { @@ -73,6 +79,8 @@ clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + power-domains = <&pd_core>; + operating-points-v2 = <&epp_dvfs_opp_table>; }; isp@54100000 { @@ -82,6 +90,7 @@ clocks = <&tegra_car TEGRA20_CLK_ISP>; resets = <&tegra_car 23>; reset-names = "isp"; + power-domains = <&pd_venc>; }; gr2d@54140000 { @@ -91,6 +100,8 @@ clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + power-domains = <&pd_core>; + operating-points-v2 = <&gr2d_dvfs_opp_table>; }; gr3d@54180000 { @@ -99,6 +110,8 @@ clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + power-domains = <&pd_3d>; + operating-points-v2 = <&gr3d_dvfs_opp_table>; }; dc@54200000 { @@ -110,6 +123,8 @@ clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp1_dvfs_opp_table>; nvidia,head = <0>; @@ -138,6 +153,8 @@ clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp2_dvfs_opp_table>; nvidia,head = <1>; @@ -166,6 +183,8 @@ clock-names = "hdmi", "parent"; resets = <&tegra_car 51>; reset-names = "hdmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&hdmi_dvfs_opp_table>; status = "disabled"; }; @@ -174,6 +193,8 @@ reg = <0x542c0000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_TVO>; + power-domains = <&pd_core>; + operating-points-v2 = <&tvo_dvfs_opp_table>; status = "disabled"; }; @@ -185,6 +206,8 @@ clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; + power-domains = <&pd_core>; + operating-points-v2 = <&dsi_dvfs_opp_table>; status = "disabled"; }; }; @@ -242,6 +265,13 @@ reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + sclk { + compatible = "nvidia,tegra20-sclk"; + clocks = <&tegra_car TEGRA20_CLK_SCLK>; + power-domains = <&pd_core>; + operating-points-v2 = <&sclk_dvfs_opp_table>; + }; }; flow-controller@60007000 { @@ -319,6 +349,8 @@ clocks = <&tegra_car TEGRA20_CLK_VDE>; reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; + power-domains = <&pd_vde>; + operating-points-v2 = <&vde_dvfs_opp_table>; }; apbmisc@70000800 { @@ -460,6 +492,8 @@ reset-names = "nand"; assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; assigned-clock-rates = <150000000>; + power-domains = <&pd_core>; + operating-points-v2 = <&ndflash_dvfs_opp_table>; status = "disabled"; }; @@ -473,6 +507,8 @@ clock-names = "gmi"; resets = <&tegra_car 42>; reset-names = "gmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&nor_dvfs_opp_table>; status = "disabled"; }; @@ -643,6 +679,52 @@ clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; + + pd_core: core-domain { + #power-domain-cells = <0>; + operating-points-v2 = <&core_opp_table>; + }; + + powergates { + pd_3d: td { + clocks = <&tegra_car TEGRA20_CLK_GR3D>; + resets = <&mc TEGRA20_MC_RESET_3D>, + <&tegra_car TEGRA20_CLK_GR3D>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA20_CLK_ISP>, + <&tegra_car TEGRA20_CLK_VI>, + <&tegra_car TEGRA20_CLK_CSI>; + resets = <&mc TEGRA20_MC_RESET_ISP>, + <&mc TEGRA20_MC_RESET_VI>, + <&tegra_car TEGRA20_CLK_ISP>, + <&tegra_car 20 /* VI */>, + <&tegra_car TEGRA20_CLK_CSI>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_vde: vdec { + clocks = <&tegra_car TEGRA20_CLK_VDE>; + resets = <&mc TEGRA20_MC_RESET_VDE>, + <&tegra_car TEGRA20_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_mpe: mpe { + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&mc TEGRA20_MC_RESET_MPEA>, + <&mc TEGRA20_MC_RESET_MPEB>, + <&mc TEGRA20_MC_RESET_MPEC>, + <&tegra_car TEGRA20_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; }; mc: memory-controller@7000f000 { @@ -662,12 +744,13 @@ reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; + power-domains = <&pd_core>; #address-cells = <1>; #size-cells = <0>; #interconnect-cells = <0>; - operating-points-v2 = <&emc_icc_dvfs_opp_table>; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; }; fuse@7000f800 { @@ -712,6 +795,9 @@ <&tegra_car 72>, <&tegra_car 74>; reset-names = "pex", "afi", "pcie_x"; + power-domains = <&pd_core>; + operating-points-v2 = <&pcie_dvfs_opp_table>; + status = "disabled"; pci@1,0 { @@ -753,6 +839,8 @@ reset-names = "usb"; nvidia,needs-double-reset; nvidia,phy = <&phy1>; + power-domains = <&pd_core>; + operating-points-v2 = <&usbd_dvfs_opp_table>; status = "disabled"; }; @@ -792,6 +880,8 @@ resets = <&tegra_car 58>; reset-names = "usb"; nvidia,phy = <&phy2>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb2_dvfs_opp_table>; status = "disabled"; }; @@ -820,6 +910,8 @@ resets = <&tegra_car 59>; reset-names = "usb"; nvidia,phy = <&phy3>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb3_dvfs_opp_table>; status = "disabled"; }; @@ -856,6 +948,8 @@ clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; status = "disabled"; }; @@ -867,6 +961,8 @@ clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc2_dvfs_opp_table>; status = "disabled"; }; @@ -878,6 +974,8 @@ clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; status = "disabled"; }; @@ -889,6 +987,8 @@ clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc4_dvfs_opp_table>; status = "disabled"; }; From b6db8f72dddc79752585b115e478b47197ef5761 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 8 Dec 2021 10:40:25 +0000 Subject: [PATCH 449/574] arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node Add Mali-G31 GPU node to SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211208104026.421-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 2639fd383010..cdf2adea4b10 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -112,6 +112,50 @@ }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1100000>; + }; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1100000>; + }; + + opp-62500000 { + opp-hz = /bits/ 64 <62500000>; + opp-microvolt = <1100000>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <1100000>; + }; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -638,6 +682,27 @@ dma-channels = <16>; }; + gpu: gpu@11840000 { + compatible = "renesas,r9a07g044-mali", + "arm,mali-bifrost"; + reg = <0x0 0x11840000 0x0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "job", "mmu", "gpu", "event"; + clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>, + <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>, + <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>; + clock-names = "gpu", "bus", "bus_ace"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_GPU_RESETN>, + <&cpg R9A07G044_GPU_AXI_RESETN>, + <&cpg R9A07G044_GPU_ACE_RESETN>; + reset-names = "rst", "axi_rst", "ace_rst"; + operating-points-v2 = <&gpu_opp_table>; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From d563f4bac9914fca6f34711ad22647125e773dd0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 8 Dec 2021 10:40:26 +0000 Subject: [PATCH 450/574] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator Add vdd core regulator (1.1 V). This patch add regulator support for gpu. The H/W manual mentions nothing about a gpu regulator. So using vdd core regulator for gpu. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211208104026.421-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 41fdae7ba66b..9112e79079a1 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -52,6 +52,15 @@ regulator-always-on; }; + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; @@ -130,6 +139,10 @@ clock-frequency = <24000000>; }; +&gpu { + mali-supply = <®_1p1v>; +}; + &ostm1 { status = "okay"; }; From d875175d87268cbd6fa8a6ccfaeba6d9991527f0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 13:35:32 +0100 Subject: [PATCH 451/574] dt-bindings: tegra: Describe recent developer kits consistently Add descriptions to entries that were missing one and don't try to combine multiple entries into one to avoid confusion. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/arm/tegra.yaml | 20 ++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index d79d36ac0c44..0235b510e0b0 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -108,14 +108,17 @@ properties: - nvidia,p2571 - nvidia,p2894-0050-a08 - const: nvidia,tegra210 - - items: - - enum: - - nvidia,p2771-0000 - - nvidia,p3509-0000+p3636-0001 + - description: Jetson TX2 Developer Kit + items: + - const: nvidia,p2771-0000 - const: nvidia,tegra186 - - items: - - enum: - - nvidia,p2972-0000 + - description: Jetson TX2 NX Developer Kit + items: + - const: nvidia,p3509-0000+p3636-0001 + - const: nvidia,tegra186 + - description: Jetson AGX Xavier Developer Kit + items: + - const: nvidia,p2972-0000 - const: nvidia,tegra194 - description: Jetson Xavier NX items: @@ -134,8 +137,7 @@ properties: - const: nvidia,p3509-0000+p3668-0001 - const: nvidia,tegra194 - items: - - enum: - - nvidia,tegra234-vdk + - const: nvidia,tegra234-vdk - const: nvidia,tegra234 additionalProperties: true From b39cc79565771f7e9ffd262d3b735cbe1c718f66 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 13:35:33 +0100 Subject: [PATCH 452/574] dt-bindings: tegra: Document Jetson AGX Orin (and devkit) Add the compatible strings for the Jetson AGX Orin and the corresponding developer kit. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 0235b510e0b0..3bd0920da274 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -139,5 +139,14 @@ properties: - items: - const: nvidia,tegra234-vdk - const: nvidia,tegra234 + - description: Jetson AGX Orin + items: + - const: nvidia,p3701-0000 + - const: nvidia,tegra234 + - description: Jetson AGX Orin Developer Kit + items: + - const: nvidia,p3737-0000+p3701-0000 + - const: nvidia,p3701-0000 + - const: nvidia,tegra234 additionalProperties: true From fc5e0e37621973758e7e49dd85f28673e72e4b85 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:34 +0100 Subject: [PATCH 453/574] dt-bindings: Update headers for Tegra234 Add a few more clocks that will be used in follow-up patches to enable more functionality on Tegra234. Signed-off-by: Mikko Perttunen Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- include/dt-bindings/clock/tegra234-clock.h | 17 ++++++++++++++--- include/dt-bindings/reset/tegra234-reset.h | 12 ++++++++++-- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 2c82072950ee..21ed0c732fb9 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -4,11 +4,22 @@ #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H +/** + * @file + * @defgroup bpmp_clock_ids Clock ID's + * @{ + */ /** @brief output of gate CLK_ENB_FUSE */ -#define TEGRA234_CLK_FUSE 40 +#define TEGRA234_CLK_FUSE 40U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ -#define TEGRA234_CLK_SDMMC4 123 +#define TEGRA234_CLK_SDMMC4 123U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ -#define TEGRA234_CLK_UARTA 155 +#define TEGRA234_CLK_UARTA 155U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ +#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ +#define TEGRA234_CLK_PLLC4 237U +/** @brief 32K input clock provided by PMIC */ +#define TEGRA234_CLK_CLK_32K 289U #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index b3c63be06d2d..50e13bced642 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -4,7 +4,15 @@ #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H #define DT_BINDINGS_RESET_TEGRA234_RESET_H -#define TEGRA234_RESET_SDMMC4 85 -#define TEGRA234_RESET_UARTA 100 +/** + * @file + * @defgroup bpmp_reset_ids Reset ID's + * @brief Identifiers for Resets controllable by firmware + * @{ + */ +#define TEGRA234_RESET_SDMMC4 85U +#define TEGRA234_RESET_UARTA 100U + +/** @} */ #endif From d9203d081a618fc8b3469b24f959495eaa138890 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 13:35:35 +0100 Subject: [PATCH 454/574] dt-bindings: sram: Document NVIDIA Tegra SYSRAM Tegra SoCs have extra on-chip RAM that can be used for inter-processor communication. Tegra186 and later make use of it to establish a two-way channel between the CCPLEX and BPMP. Add missing compatible strings for Tegra186 and Tegra194 as well as a new compatible string for Tegra234. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/sram/sram.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index d4e418b6a1c1..668a9a41a775 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -31,6 +31,9 @@ properties: - amlogic,meson-gxbb-sram - arm,juno-sram-ns - atmel,sama5d2-securam + - nvidia,tegra186-sysram + - nvidia,tegra194-sysram + - nvidia,tegra234-sysram - qcom,rpm-msg-ram - rockchip,rk3288-pmu-sram From 8c970e7ee7ae9c41aa2432f234c7b382391200f2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:46 +0100 Subject: [PATCH 455/574] dt-bindings: memory: tegra: Update for Tegra194 The #interconnect-cells properties are required to hook up memory clients to the MC/EMC in interconnects properties. Add a description for these properties. For the nested EMC controller, the list of required properties was missing. Add it so that the validation can be more strict. Also, allow multiple reg entries required by Tegra194 and later. While at it, also remove the dummy BPMP node from the example because it is incomplete and fails validation. It's also not necessary for this file and the BPMP DT schema already has a full example. Signed-off-by: Thierry Reding Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../nvidia,tegra186-mc.yaml | 78 ++++++++++++++++--- 1 file changed, 67 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 611bda38d187..b496564b1bdf 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -33,10 +33,12 @@ properties: - nvidia,tegra194-mc reg: - maxItems: 1 + minItems: 1 + maxItems: 3 interrupts: - maxItems: 1 + items: + - description: MC general interrupt "#address-cells": const: 2 @@ -48,6 +50,9 @@ properties: dma-ranges: true + "#interconnect-cells": + const: 1 + patternProperties: "^external-memory-controller@[0-9a-f]+$": description: @@ -65,10 +70,12 @@ patternProperties: - nvidia,tegra194-emc reg: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupts: - maxItems: 1 + items: + - description: EMC general interrupt clocks: items: @@ -78,11 +85,65 @@ patternProperties: items: - const: emc + "#interconnect-cells": + const: 0 + nvidia,bpmp: $ref: /schemas/types.yaml#/definitions/phandle description: phandle of the node representing the BPMP + allOf: + - if: + properties: + compatible: + const: nvidia,tegra186-emc + then: + properties: + reg: + maxItems: 1 + + - if: + properties: + compatible: + const: nvidia,tegra194-emc + then: + properties: + reg: + minItems: 2 + + additionalProperties: false + + required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#interconnect-cells" + - nvidia,bpmp + +allOf: + - if: + properties: + compatible: + const: nvidia,tegra186-mc + then: + properties: + reg: + maxItems: 1 + + - if: + properties: + compatible: + const: nvidia,tegra194-mc + then: + properties: + reg: + minItems: 3 + +additionalProperties: false + required: - compatible - reg @@ -90,8 +151,6 @@ required: - "#address-cells" - "#size-cells" -additionalProperties: false - examples: - | #include @@ -124,12 +183,9 @@ examples: clocks = <&bpmp TEGRA186_CLK_EMC>; clock-names = "emc"; + #interconnect-cells = <0>; + nvidia,bpmp = <&bpmp>; }; }; }; - - bpmp: bpmp { - compatible = "nvidia,tegra186-bpmp"; - #clock-cells = <1>; - }; From 57978838889d74ad3139cdf76ca2622e625f41e6 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 17 Nov 2021 09:56:07 +0000 Subject: [PATCH 456/574] dt-bindings: Add YAML bindings for NVENC and NVJPG Add YAML device tree bindings for the Tegra NVENC and NVJPG Host1x engines. Signed-off-by: Jon Hunter Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../gpu/host1x/nvidia,tegra210-nvenc.yaml | 135 ++++++++++++++++++ .../gpu/host1x/nvidia,tegra210-nvjpg.yaml | 94 ++++++++++++ 2 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml new file mode 100644 index 000000000000..e63ae1a00818 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra NVENC + +description: | + NVENC is the hardware video encoder present on NVIDIA Tegra210 + and newer chips. It is located on the Host1x bus and typically + programmed through Host1x channels. + +maintainers: + - Thierry Reding + - Mikko Perttunen + +properties: + $nodename: + pattern: "^nvenc@[0-9a-f]*$" + + compatible: + enum: + - nvidia,tegra210-nvenc + - nvidia,tegra186-nvenc + - nvidia,tegra194-nvenc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nvenc + + resets: + maxItems: 1 + + reset-names: + items: + - const: nvenc + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: true + + interconnects: + minItems: 2 + maxItems: 3 + + interconnect-names: + minItems: 2 + maxItems: 3 + + nvidia,host1x-class: + description: | + Host1x class of the engine, used to specify the targeted engine + when programming the engine through Host1x channels or when + configuring engine-specific behavior in Host1x. + default: 0x21 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + +allOf: + - if: + properties: + compatible: + enum: + - nvidia,tegra210-nvenc + - nvidia,tegra186-nvenc + then: + properties: + interconnects: + items: + - description: DMA read memory client + - description: DMA write memory client + interconnect-names: + items: + - const: dma-mem + - const: write + - if: + properties: + compatible: + enum: + - nvidia,tegra194-nvenc + then: + properties: + interconnects: + items: + - description: DMA read memory client + - description: DMA read 2 memory client + - description: DMA write memory client + interconnect-names: + items: + - const: dma-mem + - const: read-1 + - const: write + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + nvenc@154c0000 { + compatible = "nvidia,tegra186-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA186_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVENC>; + }; diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml new file mode 100644 index 000000000000..8647404d67e4 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra NVJPG + +description: | + NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210 + and newer chips. It is located on the Host1x bus and typically programmed + through Host1x channels. + +maintainers: + - Thierry Reding + - Mikko Perttunen + +properties: + $nodename: + pattern: "^nvjpg@[0-9a-f]*$" + + compatible: + enum: + - nvidia,tegra210-nvjpg + - nvidia,tegra186-nvjpg + - nvidia,tegra194-nvjpg + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nvjpg + + resets: + maxItems: 1 + + reset-names: + items: + - const: nvjpg + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: true + + interconnects: + items: + - description: DMA read memory client + - description: DMA write memory client + + interconnect-names: + items: + - const: dma-mem + - const: write + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + nvjpg@15380000 { + compatible = "nvidia,tegra186-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA186_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVJPG>; + }; From c3859c1436e31461f27365ec6fc751c9bbeff3e2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:47 +0100 Subject: [PATCH 457/574] dt-bindings: memory: tegra: Add Tegra234 support Document the variant of the memory controller and external memory controllers found on Tegra234 and add some memory client and SMMU stream ID definitions for use in device tree files. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- .../nvidia,tegra186-mc.yaml | 20 ++++++++++++ include/dt-bindings/clock/tegra234-clock.h | 9 ++++++ include/dt-bindings/memory/tegra234-mc.h | 32 +++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 include/dt-bindings/memory/tegra234-mc.h diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index b496564b1bdf..13c4c82fd0d3 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -31,6 +31,7 @@ properties: - enum: - nvidia,tegra186-mc - nvidia,tegra194-mc + - nvidia,tegra234-mc reg: minItems: 1 @@ -68,6 +69,7 @@ patternProperties: - enum: - nvidia,tegra186-emc - nvidia,tegra194-emc + - nvidia,tegra234-emc reg: minItems: 1 @@ -112,6 +114,15 @@ patternProperties: reg: minItems: 2 + - if: + properties: + compatible: + const: nvidia,tegra234-emc + then: + properties: + reg: + minItems: 2 + additionalProperties: false required: @@ -142,6 +153,15 @@ allOf: reg: minItems: 3 + - if: + properties: + compatible: + const: nvidia,tegra234-mc + then: + properties: + reg: + minItems: 3 + additionalProperties: false required: diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 21ed0c732fb9..8d7e66e1b6ef 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -9,6 +9,15 @@ * @defgroup bpmp_clock_ids Clock ID's * @{ */ +/** + * @brief controls the EMC clock frequency. + * @details Doing a clk_set_rate on this clock will select the + * appropriate clock source, program the source rate and execute a + * specific sequence to switch to the new clock source for both memory + * controllers. This can be used to control the balance between memory + * throughput and memory controller power. + */ +#define TEGRA234_CLK_EMC 31U /** @brief output of gate CLK_ENB_FUSE */ #define TEGRA234_CLK_FUSE 40U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h new file mode 100644 index 000000000000..2662f70c15c6 --- /dev/null +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + +#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H +#define DT_BINDINGS_MEMORY_TEGRA234_MC_H + +/* special clients */ +#define TEGRA234_SID_INVALID 0x00 +#define TEGRA234_SID_PASSTHROUGH 0x7f + + +/* NISO1 stream IDs */ +#define TEGRA234_SID_SDMMC4 0x02 +#define TEGRA234_SID_BPMP 0x10 + +/* + * memory client IDs + */ + +/* sdmmcd memory read client */ +#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 +/* sdmmcd memory write client */ +#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 +/* BPMP read client */ +#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 +/* BPMP write client */ +#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 +/* BPMPDMA read client */ +#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 +/* BPMPDMA write client */ +#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 + +#endif From 51a0f370886a76b4b7bd39ca9bf917a571068aac Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:24 +0100 Subject: [PATCH 458/574] dt-bindings: misc: Convert Tegra MISC to json-schema Convert the device tree bindings for the MISC register block found on NVIDIA Tegra SoCs from plain text to json-schema format. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/misc/nvidia,tegra186-misc.txt | 14 ----- .../bindings/misc/nvidia,tegra186-misc.yaml | 43 ++++++++++++++++ .../bindings/misc/nvidia,tegra20-apbmisc.txt | 17 ------- .../bindings/misc/nvidia,tegra20-apbmisc.yaml | 51 +++++++++++++++++++ 4 files changed, 94 insertions(+), 31 deletions(-) delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt deleted file mode 100644 index 43d777ed8316..000000000000 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt +++ /dev/null @@ -1,14 +0,0 @@ -NVIDIA Tegra186 (and later) MISC register block - -The MISC register block found on Tegra186 and later SoCs contains registers -that can be used to identify a given chip and various strapping options. - -Required properties: -- compatible: Must be: - - Tegra186: "nvidia,tegra186-misc" - - Tegra194: "nvidia,tegra194-misc" - - Tegra234: "nvidia,tegra234-misc" -- reg: Should contain 2 entries: The first entry gives the physical address - and length of the register region which contains revision and debug - features. The second entry specifies the physical address and length - of the register region indicating the strapping options. diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml new file mode 100644 index 000000000000..cacb845868f4 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) MISC register block + +maintainers: + - Thierry Reding + - Jon Hunter + +description: The MISC register block found on Tegra186 and later SoCs contains + registers that can be used to identify a given chip and various strapping + options. + +properties: + compatible: + enum: + - nvidia,tegra186-misc + - nvidia,tegra194-misc + - nvidia,tegra234-misc + + reg: + items: + - description: physical address and length of the registers which + contain revision and debug features + - description: physical address and length of the registers which + indicate strapping options + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + misc@100000 { + compatible = "nvidia,tegra186-misc"; + reg = <0x00100000 0xf000>, + <0x0010f000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt deleted file mode 100644 index 83f6a251ba3e..000000000000 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ /dev/null @@ -1,17 +0,0 @@ -NVIDIA Tegra APBMISC block - -Required properties: -- compatible: Must be: - - Tegra20: "nvidia,tegra20-apbmisc" - - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc" -- reg: Should contain 2 entries: the first entry gives the physical address - and length of the registers which contain revision and debug features. - The second entry gives the physical address and length of the - registers indicating the strapping options. - -Optional properties: -- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit). diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml new file mode 100644 index 000000000000..6f504fa74007 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra APBMISC block + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra210-apbmisc + - nvidia,tegra124-apbmisc + - nvidia,tegra114-apbmisc + - nvidia,tegra30-apbmisc + - const: nvidia,tegra20-apbmisc + + - items: + - const: nvidia,tegra20-apbmisc + + reg: + items: + - description: physical address and length of the registers which + contain revision and debug features + - description: physical address and length of the registers which + indicate strapping options + + nvidia,long-ram-code: + description: If present, the RAM code is long (4 bit). If not, short + (2 bit). + type: boolean + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + apbmisc@70000800 { + compatible = "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ + }; From 7fa307524a4d721d4a04523018509882c5414e72 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 13:35:37 +0100 Subject: [PATCH 459/574] arm64: tegra: Fixup SYSRAM references The json-schema bindings for SRAM expect the nodes to be called "sram" rather than "sysram" or "shmem". Furthermore, place the brackets around the SYSRAM references such that a two-element array is created rather than a two-element array nested in a single-element array. This is not relevant for device tree itself, but allows the nodes to be properly validated against json-schema bindings. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 9ac4f0140700..5f8132884be0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1771,7 +1771,7 @@ iommus = <&smmu TEGRA186_SID_BPMP>; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 851e049b3519..8d29b7fdb044 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2467,7 +2467,7 @@ compatible = "nvidia,tegra186-bpmp"; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index f0efb3a62804..28961ed31d87 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -122,20 +122,20 @@ }; }; - sysram@40000000 { + sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x50000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40000000 0x50000>; - cpu_bpmp_tx: shmem@4e000 { + cpu_bpmp_tx: sram@4e000 { reg = <0x4e000 0x1000>; label = "cpu-bpmp-tx"; pool; }; - cpu_bpmp_rx: shmem@4f000 { + cpu_bpmp_rx: sram@4f000 { reg = <0x4f000 0x1000>; label = "cpu-bpmp-rx"; pool; @@ -146,7 +146,7 @@ compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From e537adde131bd4cf426e6d77f99060ca302e2f08 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:38 +0100 Subject: [PATCH 460/574] arm64: tegra: Add clock for Tegra234 RTC The RTC device requires a clock. Add it. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 28961ed31d87..400c01acc19f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -93,6 +93,8 @@ reg = <0x0c2a0000 0x10000>; interrupt-parent = <&pmc>; interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA234_CLK_CLK_32K>; + clock-names = "rtc"; status = "disabled"; }; From 98094be152d34f8014ca67fbdc210e5261c4b09d Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:39 +0100 Subject: [PATCH 461/574] arm64: tegra: Update Tegra234 BPMP channel addresses On final Tegra234 systems, shared memory for communication with BPMP is located at offset 0x70000 in SYSRAM. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 400c01acc19f..844cab44aee6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -126,19 +126,19 @@ sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; - reg = <0x0 0x40000000 0x0 0x50000>; + reg = <0x0 0x40000000 0x0 0x80000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0x40000000 0x50000>; + ranges = <0x0 0x0 0x40000000 0x80000>; - cpu_bpmp_tx: sram@4e000 { - reg = <0x4e000 0x1000>; + cpu_bpmp_tx: sram@70000 { + reg = <0x70000 0x1000>; label = "cpu-bpmp-tx"; pool; }; - cpu_bpmp_rx: sram@4f000 { - reg = <0x4f000 0x1000>; + cpu_bpmp_rx: sram@71000 { + reg = <0x71000 0x1000>; label = "cpu-bpmp-rx"; pool; }; From e086d82d4f3e867a02a4ef4c245fc4f506173bbb Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:40 +0100 Subject: [PATCH 462/574] arm64: tegra: Fill in properties for Tegra234 eMMC Add missing properties to the eMMC controller, as required to use it on actual hardware. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 844cab44aee6..ffe300356e85 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -40,11 +40,24 @@ compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; interrupts = ; - clocks = <&bpmp TEGRA234_CLK_SDMMC4>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA234_CLK_SDMMC4>, + <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; + assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, + <&bpmp TEGRA234_CLK_PLLC4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; resets = <&bpmp TEGRA234_RESET_SDMMC4>; reset-names = "sdhci"; - dma-coherent; + nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; + nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; + nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; + nvidia,default-tap = <0x8>; + nvidia,default-trim = <0x14>; + nvidia,dqs-trim = <40>; + supports-cqe; status = "disabled"; }; From 06ad2ec4e5f84030ce6554d3859d6c21849bd5a3 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:41 +0100 Subject: [PATCH 463/574] arm64: tegra: Add Tegra234 TCU device Add a device for TCU (Tegra Combined UART) used for serial console. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index ffe300356e85..bd3a01142704 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -192,6 +192,14 @@ method = "smc"; }; + tcu: serial { + compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; + mbox-names = "rx", "tx"; + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From f0e1266818f58ab5e687b3aec53d0689c7dc7db0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Dec 2021 17:02:05 +0100 Subject: [PATCH 464/574] arm64: tegra: Add main and AON GPIO controllers on Tegra234 These two controllers expose general purpose I/O pins that can be used to control or monitor a variety of signals. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 74 ++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index bd3a01142704..f715671f0333 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -25,6 +25,65 @@ status = "okay"; }; + gpio: gpio@2200000 { + compatible = "nvidia,tegra234-gpio"; + reg-names = "security", "gpio"; + reg = <0x02200000 0x10000>, + <0x02210000 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x10000>; @@ -111,6 +170,21 @@ status = "disabled"; }; + gpio_aon: gpio@c2f0000 { + compatible = "nvidia,tegra234-gpio-aon"; + reg-names = "security", "gpio"; + reg = <0x0c2f0000 0x1000>, + <0x0c2f1000 0x1000>; + interrupts = , + , + , + ; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + }; + pmc: pmc@c360000 { compatible = "nvidia,tegra234-pmc"; reg = <0x0c360000 0x10000>, From a12cf5c339b082a93767b3fa5c85059b8269ab45 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 14:19:04 +0100 Subject: [PATCH 465/574] arm64: tegra: Describe Tegra234 CPU hierarchy The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each, for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches with each cluster having an additional 256 KiB unified L2 cache and a 2 MiB L3 cache. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++++- 1 file changed, 363 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index f715671f0333..b60e4f6f0658 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -252,12 +252,373 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0_0: cpu@0 { + compatible = "arm,cortex-a78"; device_type = "cpu"; - reg = <0x000>; + reg = <0x00000>; enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c0_0>; }; + + cpu0_1: cpu@100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x00100>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c0_1>; + }; + + cpu0_2: cpu@200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x00200>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c0_2>; + }; + + cpu0_3: cpu@300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x00300>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c0_3>; + }; + + cpu1_0: cpu@10000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x10000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c1_0>; + }; + + cpu1_1: cpu@10100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x10100>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c1_1>; + }; + + cpu1_2: cpu@10200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x10200>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c1_2>; + }; + + cpu1_3: cpu@10300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x10300>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c1_3>; + }; + + cpu2_0: cpu@20000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x20000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2_0>; + }; + + cpu2_1: cpu@20100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x20100>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2_1>; + }; + + cpu2_2: cpu@20200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x20200>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2_2>; + }; + + cpu2_3: cpu@20300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + reg = <0x20300>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2_3>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0_0>; + }; + + core1 { + cpu = <&cpu0_1>; + }; + + core2 { + cpu = <&cpu0_2>; + }; + + core3 { + cpu = <&cpu0_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu1_0>; + }; + + core1 { + cpu = <&cpu1_1>; + }; + + core2 { + cpu = <&cpu1_2>; + }; + + core3 { + cpu = <&cpu1_3>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu2_0>; + }; + + core1 { + cpu = <&cpu2_1>; + }; + + core2 { + cpu = <&cpu2_2>; + }; + + core3 { + cpu = <&cpu2_3>; + }; + }; + }; + + l2c0_0: l2-cache00 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c0>; + }; + + l2c0_1: l2-cache01 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c0>; + }; + + l2c0_2: l2-cache02 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c0>; + }; + + l2c0_3: l2-cache03 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c0>; + }; + + l2c1_0: l2-cache10 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c1>; + }; + + l2c1_1: l2-cache11 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c1>; + }; + + l2c1_2: l2-cache12 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c1>; + }; + + l2c1_3: l2-cache13 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c1>; + }; + + l2c2_0: l2-cache20 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c2>; + }; + + l2c2_1: l2-cache21 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c2>; + }; + + l2c2_2: l2-cache22 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c2>; + }; + + l2c2_3: l2-cache23 { + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + next-level-cache = <&l3c2>; + }; + + l3c0: l3-cache0 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + }; + + l3c1: l3-cache1 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + }; + + l3c2: l3-cache2 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + }; + }; + + pmu { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; + status = "okay"; }; psci { From 533337d5c843650043771503221774f3dffbead0 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 12 Nov 2021 13:35:42 +0100 Subject: [PATCH 466/574] arm64: tegra: Add NVIDIA Jetson AGX Orin Developer Kit support The Jetson AGX Orin Developer Kit is a continuation of the Jetson Developer Kit line using the new NVIDIA Tegra234 (Orin) SoC. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 1 + .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 25 +++++++++++++++++++ .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 24 ++++++++++++++++++ .../boot/dts/nvidia/tegra234-p3737-0000.dtsi | 5 ++++ 4 files changed, 55 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index c80f7dc2935e..ea3f338fd013 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -12,3 +12,4 @@ dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb +dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi new file mode 100644 index 000000000000..d3c936822186 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra234.dtsi" + +/ { + model = "NVIDIA Jetson AGX Orin"; + compatible = "nvidia,p3701-0000", "nvidia,tegra234"; + + bus@0 { + mmc@3460000 { + status = "okay"; + bus-width = <8>; + non-removable; + only-1-8-v; + }; + + rtc@c2a0000 { + status = "okay"; + }; + + pmc@c360000 { + nvidia,invert-interrupt; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts new file mode 100644 index 000000000000..efbbb878ba5a --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra234-p3701-0000.dtsi" +#include "tegra234-p3737-0000.dtsi" + +/ { + model = "NVIDIA Jetson AGX Orin Developer Kit"; + compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234"; + + aliases { + mmc3 = "/bus@0/mmc@3460000"; + serial0 = &tcu; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "serial0:115200n8"; + }; + + serial { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi new file mode 100644 index 000000000000..a85993c85e45 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + compatible = "nvidia,p3737-0000"; +}; From ff21087e6131e7d81c17d5b34bd786866ca90553 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Tue, 16 Nov 2021 17:32:36 +0530 Subject: [PATCH 467/574] arm64: tegra: Add support to enumerate SD in UHS mode Add support to enumerate SD in UHS mode on Tegra194. Add required device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic pad voltage switching and enumerate SD card in UHS-I modes. Signed-off-by: Prathamesh Shete Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 8d29b7fdb044..3b424496384e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -893,6 +894,9 @@ <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA194_SID_SDMMC1>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; nvidia,pad-autocal-pull-down-offset-3v3-timeout = @@ -904,6 +908,10 @@ nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; nvidia,default-tap = <0x9>; nvidia,default-trim = <0x5>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; status = "disabled"; }; @@ -920,6 +928,9 @@ <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA194_SID_SDMMC3>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc3_3v3>; + pinctrl-1 = <&sdmmc3_1v8>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; @@ -932,6 +943,10 @@ nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; nvidia,default-tap = <0x9>; nvidia,default-trim = <0x5>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; status = "disabled"; }; @@ -1472,6 +1487,25 @@ #interrupt-cells = <2>; interrupt-controller; + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = ; + }; + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = ; + }; + + sdmmc3_1v8: sdmmc3-1v8 { + pins = "sdmmc3-hv"; + power-source = ; + }; + }; smmu: iommu@12000000 { From f7eb2785728442cc349a68965bc3c9a869274336 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 17 Nov 2021 09:56:08 +0000 Subject: [PATCH 468/574] arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194 Populate the device-tree nodes for NVENC and NVJPG Host1x engines on Tegra186 and Tegra194. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 30 +++++++++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 54 ++++++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 5f8132884be0..fe588666bcfc 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1538,6 +1538,21 @@ iommus = <&smmu TEGRA186_SID_VIC>; }; + nvjpg@15380000 { + compatible = "nvidia,tegra186-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA186_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVJPG>; + }; + dsib: dsi@15400000 { compatible = "nvidia,tegra186-dsi"; reg = <0x15400000 0x10000>; @@ -1569,6 +1584,21 @@ iommus = <&smmu TEGRA186_SID_NVDEC>; }; + nvenc@154c0000 { + compatible = "nvidia,tegra186-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA186_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVENC>; + }; + sor0: sor@15540000 { compatible = "nvidia,tegra186-sor"; reg = <0x15540000 0x10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 3b424496384e..c97febf90ead 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1739,6 +1739,22 @@ iommus = <&smmu TEGRA194_SID_VIC>; }; + nvjpg@15380000 { + compatible = "nvidia,tegra194-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA194_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA194_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_NVJPG>; + dma-coherent; + }; + nvdec@15480000 { compatible = "nvidia,tegra194-nvdec"; reg = <0x15480000 0x00040000>; @@ -1758,6 +1774,25 @@ nvidia,host1x-class = <0xf0>; }; + nvenc@154c0000 { + compatible = "nvidia,tegra194-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA194_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA194_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "read-1", "write"; + iommus = <&smmu TEGRA194_SID_NVENC>; + dma-coherent; + + nvidia,host1x-class = <0x21>; + }; + dpaux0: dpaux@155c0000 { compatible = "nvidia,tegra194-dpaux"; reg = <0x155c0000 0x10000>; @@ -1894,6 +1929,25 @@ }; }; + nvenc@15a80000 { + compatible = "nvidia,tegra194-nvenc"; + reg = <0x15a80000 0x00040000>; + clocks = <&bpmp TEGRA194_CLK_NVENC1>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA194_RESET_NVENC1>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; + interconnect-names = "dma-mem", "read-1", "write"; + iommus = <&smmu TEGRA194_SID_NVENC1>; + dma-coherent; + + nvidia,host1x-class = <0x22>; + }; + sor0: sor@15b00000 { compatible = "nvidia,tegra194-sor"; reg = <0x15b00000 0x40000>; From e762232f946679b6be60244d78079aa12cc5ed68 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 1 Dec 2021 15:57:16 +0000 Subject: [PATCH 469/574] arm64: tegra: Add ISO SMMU controller for Tegra194 The display controllers are attached to a separate ARM SMMU instance that is dedicated to servicing isochronous memory clients. Add this ISO instance of the ARM SMMU to device tree. Please note that the display controllers are not hooked up to this SMMU yet, because we are still missing a means to transition framebuffers used by the bootloader to the kernel. This based upon an initial patch by Thierry Reding . Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 76 ++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c97febf90ead..f9b1900088ad 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1508,6 +1508,82 @@ }; + iommu@10000000 { + compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; + reg = <0x10000000 0x800000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <1>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; + smmu: iommu@12000000 { compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; reg = <0x12000000 0x800000>, From 4cc3e3e164c02c6f2fce38f2098a1fe1256ea58d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 17:58:55 +0100 Subject: [PATCH 470/574] arm64: tegra: Rename top-level clocks Clocks defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the clock to the node name. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 8a51751526ee..ecd58bd2770f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1023,7 +1023,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 6077d572d828..d3e622c4a439 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -301,7 +301,7 @@ vqmmc-supply = <&vdd_1v8>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi index 58aa0518965e..0a70daeffd85 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi @@ -40,7 +40,7 @@ non-removable; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 41beab626d95..ed73c3a0c140 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1586,7 +1586,7 @@ status = "okay"; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 030f264eccd5..cbd8cda48f37 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1645,7 +1645,7 @@ }; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 131c064d6991..43ff5e4bda19 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1726,7 +1726,7 @@ }; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; From 097e01c61015e41975873a1e51e3106456aa581a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 18:02:18 +0100 Subject: [PATCH 471/574] arm64: tegra: Rename top-level regulators Regulators defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the regulator to the node name. Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra132-norrin.dts | 26 +++++++------- .../boot/dts/nvidia/tegra186-p2771-0000.dts | 8 ++--- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 6 ++-- .../nvidia/tegra186-p3509-0000+p3636-0001.dts | 8 ++--- .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 10 +++--- .../boot/dts/nvidia/tegra194-p3509-0000.dtsi | 10 +++--- .../boot/dts/nvidia/tegra194-p3668-0000.dtsi | 2 +- .../arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +- .../arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 30 ++++++++-------- .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 36 +++++++++---------- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 18 +++++----- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 16 ++++----- 12 files changed, 86 insertions(+), 86 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index ecd58bd2770f..c84ed1cb9a8c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1057,7 +1057,7 @@ ddc-i2c-bus = <&dpaux>; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-vdd-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <19000000>; @@ -1066,7 +1066,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -1076,7 +1076,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -1086,7 +1086,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-vdd-3v3-run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -1098,7 +1098,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-vdd-3v3-hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -1106,7 +1106,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_led: regulator@5 { + vdd_led: regulator-vdd-led { compatible = "regulator-fixed"; regulator-name = "+VDD_LED"; regulator-min-microvolt = <3300000>; @@ -1116,7 +1116,7 @@ vin-supply = <&vdd_mux>; }; - vdd_usb1_vbus: regulator@6 { + vdd_usb1_vbus: regulator-vdd-usb1-vbus { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -1127,7 +1127,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@7 { + vdd_usb3_vbus: regulator-vdd-usb3-vbus { compatible = "regulator-fixed"; regulator-name = "+5V_USB_SS"; regulator-min-microvolt = <5000000>; @@ -1138,7 +1138,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_panel: regulator@8 { + vdd_3v3_panel: regulator-vdd-3v3-panel { compatible = "regulator-fixed"; regulator-name = "+3.3V_PANEL"; regulator-min-microvolt = <3300000>; @@ -1148,7 +1148,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@9 { + vdd_hdmi_pll: regulator-vdd-hdmi-pll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE"; regulator-min-microvolt = <1050000>; @@ -1157,7 +1157,7 @@ vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@10 { + vdd_5v0_hdmi: regulator-vdd-5v0-hdmi { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; @@ -1167,7 +1167,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_5v0_ts: regulator@11 { + vdd_5v0_ts: regulator-vdd-5v0-ts { compatible = "regulator-fixed"; regulator-name = "+5V_VDD_TS"; regulator-min-microvolt = <5000000>; @@ -1178,7 +1178,7 @@ enable-active-high; }; - vdd_3v3_lp0: regulator@12 { + vdd_3v3_lp0: regulator-vdd-3v3-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 52fa258533e6..2883049c4edf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -2250,7 +2250,7 @@ }; }; - vdd_sd: regulator@100 { + vdd_sd: regulator-vdd-sd { compatible = "regulator-fixed"; regulator-name = "SD_CARD_SW_PWR"; regulator-min-microvolt = <3300000>; @@ -2262,7 +2262,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi: regulator@101 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_HDMI_5V0"; regulator-min-microvolt = <5000000>; @@ -2274,7 +2274,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb0: regulator@102 { + vdd_usb0: regulator-vdd-usb0 { compatible = "regulator-fixed"; regulator-name = "VDD_USB0"; regulator-min-microvolt = <5000000>; @@ -2286,7 +2286,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb1: regulator@103 { + vdd_usb1: regulator-vdd-usb1 { compatible = "regulator-fixed"; regulator-name = "VDD_USB1"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index fcd71bfc6707..4917b43995b0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -393,7 +393,7 @@ method = "smc"; }; - gnd: regulator@0 { + gnd: regulator-gnd { compatible = "regulator-fixed"; regulator-name = "GND"; regulator-min-microvolt = <0>; @@ -402,7 +402,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; regulator-min-microvolt = <5000000>; @@ -411,7 +411,7 @@ regulator-boot-on; }; - vdd_1v8_ap: regulator@2 { + vdd_1v8_ap: regulator-vdd-1v8-ap { compatible = "regulator-fixed"; regulator-name = "VDD_1V8_AP"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index af33fe93e1d6..28d59792eaa1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -593,7 +593,7 @@ method = "smc"; }; - gnd: regulator@0 { + gnd: regulator-gnd { compatible = "regulator-fixed"; regulator-name = "GND"; regulator-min-microvolt = <0>; @@ -602,7 +602,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; regulator-min-microvolt = <5000000>; @@ -611,7 +611,7 @@ regulator-boot-on; }; - vdd_1v8_ap: regulator@2 { + vdd_1v8_ap: regulator-vdd-1v8-ap { compatible = "regulator-fixed"; regulator-name = "VDD_1V8_AP"; regulator-min-microvolt = <1800000>; @@ -623,7 +623,7 @@ vin-supply = <&vdd_1v8>; }; - vdd_hdmi: regulator@3 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index c4058ee36fec..ad217cac2b28 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -317,7 +317,7 @@ }; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VIN_SYS_5V0"; regulator-min-microvolt = <5000000>; @@ -326,7 +326,7 @@ regulator-boot-on; }; - vdd_hdmi: regulator@1 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; @@ -335,7 +335,7 @@ enable-active-high; }; - vdd_3v3_pcie: regulator@2 { + vdd_3v3_pcie: regulator-vdd-3v3-pcie { compatible = "regulator-fixed"; regulator-name = "PEX_3V3"; regulator-min-microvolt = <3300000>; @@ -345,7 +345,7 @@ enable-active-high; }; - vdd_12v_pcie: regulator@3 { + vdd_12v_pcie: regulator-vdd-12v-pcie { compatible = "regulator-fixed"; regulator-name = "VDD_12V"; regulator-min-microvolt = <1200000>; @@ -354,7 +354,7 @@ regulator-boot-on; }; - vdd_5v_sata: regulator@4 { + vdd_5v_sata: regulator-vdd-5v0-sata { compatible = "regulator-fixed"; regulator-name = "VDD_5V_SATA"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index a055f17218bb..8d3999cd1af2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -2000,7 +2000,7 @@ }; }; - vdd_5v0_sys: regulator@100 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V_SYS"; regulator-min-microvolt = <5000000>; @@ -2009,7 +2009,7 @@ regulator-boot-on; }; - vdd_3v3_sys: regulator@101 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SYS"; regulator-min-microvolt = <3300000>; @@ -2018,7 +2018,7 @@ regulator-boot-on; }; - vdd_3v3_ao: regulator@102 { + vdd_3v3_ao: regulator-vdd-3v3-ao { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_AO"; regulator-min-microvolt = <3300000>; @@ -2027,7 +2027,7 @@ regulator-boot-on; }; - vdd_1v8: regulator@103 { + vdd_1v8: regulator-vdd-1v8 { compatible = "regulator-fixed"; regulator-name = "VDD_1V8"; regulator-min-microvolt = <1800000>; @@ -2036,7 +2036,7 @@ regulator-boot-on; }; - vdd_hdmi: regulator@104 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi index 14da4206ea66..8c2c709dd54c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi @@ -20,7 +20,7 @@ }; }; - vdd_3v3_sd: regulator@0 { + vdd_3v3_sd: regulator-vdd-3v3-sd { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SD"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index d3e622c4a439..75eb743a7242 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -336,7 +336,7 @@ method = "smc"; }; - vdd_gpu: regulator@100 { + vdd_gpu: regulator-vdd-gpu { compatible = "pwm-regulator"; pwms = <&pwm 1 8000>; regulator-name = "VDD_GPU"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index d8409c1b4380..34276a84c68a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1555,7 +1555,7 @@ }; }; - vdd_sys_mux: regulator@0 { + vdd_sys_mux: regulator-vdd-sys-mux { compatible = "regulator-fixed"; regulator-name = "VDD_SYS_MUX"; regulator-min-microvolt = <5000000>; @@ -1564,7 +1564,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; regulator-min-microvolt = <5000000>; @@ -1576,7 +1576,7 @@ vin-supply = <&vdd_sys_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SYS"; regulator-min-microvolt = <3300000>; @@ -1591,7 +1591,7 @@ regulator-disable-ramp-delay = <10000>; }; - vdd_5v0_io: regulator@3 { + vdd_5v0_io: regulator-vdd-5v0-io { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_IO_SYS"; regulator-min-microvolt = <5000000>; @@ -1600,7 +1600,7 @@ regulator-boot-on; }; - vdd_3v3_sd: regulator@4 { + vdd_3v3_sd: regulator-vdd-3v3-sd { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SD"; regulator-min-microvolt = <3300000>; @@ -1613,7 +1613,7 @@ regulator-disable-ramp-delay = <4880>; }; - vdd_dsi_csi: regulator@5 { + vdd_dsi_csi: regulator-vdd-dsi-csi { compatible = "regulator-fixed"; regulator-name = "AVDD_DSI_CSI_1V2"; regulator-min-microvolt = <1200000>; @@ -1621,7 +1621,7 @@ vin-supply = <&vdd_sys_1v2>; }; - vdd_3v3_dis: regulator@6 { + vdd_3v3_dis: regulator-vdd-3v3-dis { compatible = "regulator-fixed"; regulator-name = "VDD_DIS_3V3_LCD"; regulator-min-microvolt = <3300000>; @@ -1632,7 +1632,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_1v8_dis: regulator@7 { + vdd_1v8_dis: regulator-vdd-1v8-dis { compatible = "regulator-fixed"; regulator-name = "VDD_LCD_1V8_DIS"; regulator-min-microvolt = <1800000>; @@ -1643,7 +1643,7 @@ vin-supply = <&vdd_1v8>; }; - vdd_5v0_rtl: regulator@8 { + vdd_5v0_rtl: regulator-vdd-5v0-rtl { compatible = "regulator-fixed"; regulator-name = "RTL_5V"; regulator-min-microvolt = <5000000>; @@ -1653,7 +1653,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb_vbus: regulator@9 { + vdd_usb_vbus: regulator-vdd-usb-vbus { compatible = "regulator-fixed"; regulator-name = "USB_VBUS_EN1"; regulator-min-microvolt = <5000000>; @@ -1663,7 +1663,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_hdmi: regulator@10 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_HDMI_5V0"; regulator-min-microvolt = <5000000>; @@ -1673,7 +1673,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_cam_1v2: regulator@11 { + vdd_cam_1v2: regulator-vdd-cam-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-1v2"; regulator-min-microvolt = <1200000>; @@ -1683,7 +1683,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_cam_2v8: regulator@12 { + vdd_cam_2v8: regulator-vdd-cam-2v8 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-2v8"; regulator-min-microvolt = <2800000>; @@ -1693,7 +1693,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_cam_1v8: regulator@13 { + vdd_cam_1v8: regulator-vdd-cam-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-1v8"; regulator-min-microvolt = <1800000>; @@ -1703,7 +1703,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_usb_vbus_otg: regulator@14 { + vdd_usb_vbus_otg: regulator-vdd-usb-vbus-otg { compatible = "regulator-fixed"; regulator-name = "USB_VBUS_EN0"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index ed73c3a0c140..5cfbc0394173 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1635,7 +1635,7 @@ method = "smc"; }; - battery_reg: regulator@0 { + battery_reg: regulator-vdd-ac-bat { compatible = "regulator-fixed"; regulator-name = "vdd-ac-bat"; regulator-min-microvolt = <5000000>; @@ -1643,7 +1643,7 @@ regulator-always-on; }; - vdd_3v3: regulator@1 { + vdd_3v3: regulator-vdd-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd-3v3"; regulator-enable-ramp-delay = <160>; @@ -1655,7 +1655,7 @@ enable-active-high; }; - max77620_gpio7: regulator@2 { + max77620_gpio7: regulator-max77620-gpio7 { compatible = "regulator-fixed"; regulator-name = "max77620-gpio7"; regulator-enable-ramp-delay = <240>; @@ -1669,7 +1669,7 @@ enable-active-high; }; - lcd_bl_en: regulator@3 { + lcd_bl_en: regulator-lcd-bl-en { compatible = "regulator-fixed"; regulator-name = "lcd-bl-en"; regulator-min-microvolt = <1800000>; @@ -1680,7 +1680,7 @@ enable-active-high; }; - en_vdd_sd: regulator@4 { + en_vdd_sd: regulator-vdd-sd { compatible = "regulator-fixed"; regulator-name = "en-vdd-sd"; regulator-enable-ramp-delay = <472>; @@ -1692,7 +1692,7 @@ enable-active-high; }; - en_vdd_cam: regulator@5 { + en_vdd_cam: regulator-vdd-cam { compatible = "regulator-fixed"; regulator-name = "en-vdd-cam"; regulator-min-microvolt = <1800000>; @@ -1702,7 +1702,7 @@ enable-active-high; }; - vdd_sys_boost: regulator@6 { + vdd_sys_boost: regulator-vdd-sys-boost { compatible = "regulator-fixed"; regulator-name = "vdd-sys-boost"; regulator-enable-ramp-delay = <3090>; @@ -1714,7 +1714,7 @@ enable-active-high; }; - vdd_hdmi: regulator@7 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "vdd-hdmi"; regulator-enable-ramp-delay = <468>; @@ -1727,21 +1727,21 @@ enable-active-high; }; - en_vdd_cpu_fixed: regulator@8 { + en_vdd_cpu_fixed: regulator-vdd-cpu-fixed { compatible = "regulator-fixed"; regulator-name = "vdd-cpu-fixed"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; - vdd_aux_3v3: regulator@9 { + vdd_aux_3v3: regulator-vdd-aux-3v3 { compatible = "regulator-fixed"; regulator-name = "aux-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vdd_snsr_pm: regulator@10 { + vdd_snsr_pm: regulator-vdd-snsr-pm { compatible = "regulator-fixed"; regulator-name = "snsr_pm"; regulator-min-microvolt = <3300000>; @@ -1750,7 +1750,7 @@ enable-active-high; }; - vdd_usb_5v0: regulator@11 { + vdd_usb_5v0: regulator-vdd-usb-5v0 { compatible = "regulator-fixed"; status = "disabled"; regulator-name = "vdd-usb-5v0"; @@ -1761,7 +1761,7 @@ enable-active-high; }; - vdd_cdc_1v2_aud: regulator@101 { + vdd_cdc_1v2_aud: regulator-vdd-cdc-1v2-aud { compatible = "regulator-fixed"; status = "disabled"; regulator-name = "vdd_cdc_1v2_aud"; @@ -1772,7 +1772,7 @@ enable-active-high; }; - vdd_disp_3v0: regulator@12 { + vdd_disp_3v0: regulator-vdd-disp-3v0 { compatible = "regulator-fixed"; regulator-name = "vdd-disp-3v0"; regulator-enable-ramp-delay = <232>; @@ -1784,7 +1784,7 @@ enable-active-high; }; - vdd_fan: regulator@13 { + vdd_fan: regulator-vdd-fan { compatible = "regulator-fixed"; regulator-name = "vdd-fan"; regulator-enable-ramp-delay = <284>; @@ -1795,7 +1795,7 @@ enable-active-high; }; - usb_vbus1: regulator@14 { + usb_vbus1: regulator-usb-vbus1 { compatible = "regulator-fixed"; regulator-name = "usb-vbus1"; regulator-min-microvolt = <5000000>; @@ -1806,7 +1806,7 @@ gpio-open-drain; }; - usb_vbus2: regulator@15 { + usb_vbus2: regulator-usb-vbus2 { compatible = "regulator-fixed"; regulator-name = "usb-vbus2"; regulator-min-microvolt = <5000000>; @@ -1817,7 +1817,7 @@ gpio-open-drain; }; - vdd_3v3_eth: regulator@16 { + vdd_3v3_eth: regulator-vdd-3v3-eth { compatible = "regulator-fixed"; regulator-name = "vdd-3v3-eth-a02"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index cbd8cda48f37..283b50febb6f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1762,7 +1762,7 @@ method = "smc"; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; @@ -1772,7 +1772,7 @@ regulator-boot-on; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SYS"; @@ -1789,7 +1789,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_sd: regulator@2 { + vdd_3v3_sd: regulator-vdd-3v3-sd { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SD"; @@ -1802,7 +1802,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi: regulator@3 { + vdd_hdmi: regulator-vdd-hdmi-5v0 { compatible = "regulator-fixed"; regulator-name = "VDD_HDMI_5V0"; @@ -1812,7 +1812,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_hub_3v3: regulator@4 { + vdd_hub_3v3: regulator-vdd-hub-3v3 { compatible = "regulator-fixed"; regulator-name = "VDD_HUB_3V3"; @@ -1825,7 +1825,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_cpu: regulator@5 { + vdd_cpu: regulator-vdd-cpu { compatible = "regulator-fixed"; regulator-name = "VDD_CPU"; @@ -1840,7 +1840,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_gpu: regulator@6 { + vdd_gpu: regulator-vdd-gpu { compatible = "pwm-regulator"; pwms = <&pwm 1 8000>; @@ -1855,7 +1855,7 @@ vin-supply = <&vdd_5v0_sys>; }; - avdd_io_edp_1v05: regulator@7 { + avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 { compatible = "regulator-fixed"; regulator-name = "AVDD_IO_EDP_1V05"; @@ -1868,7 +1868,7 @@ vin-supply = <&avdd_1v05_pll>; }; - vdd_5v0_usb: regulator@8 { + vdd_5v0_usb: regulator-vdd-5v-usb { compatible = "regulator-fixed"; regulator-name = "VDD_5V_USB"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 43ff5e4bda19..6d59c28ff2a3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1807,7 +1807,7 @@ method = "smc"; }; - ppvar_sys: regulator@0 { + ppvar_sys: regulator-ppvar-sys { compatible = "regulator-fixed"; regulator-name = "PPVAR_SYS"; regulator-min-microvolt = <4400000>; @@ -1815,7 +1815,7 @@ regulator-always-on; }; - pplcd_vdd: regulator@1 { + pplcd_vdd: regulator-pplcd-vdd { compatible = "regulator-fixed"; regulator-name = "PPLCD_VDD"; regulator-min-microvolt = <4400000>; @@ -1825,7 +1825,7 @@ regulator-boot-on; }; - pp3000_always: regulator@2 { + pp3000_always: regulator-pp3000-always { compatible = "regulator-fixed"; regulator-name = "PP3000_ALWAYS"; regulator-min-microvolt = <3000000>; @@ -1833,7 +1833,7 @@ regulator-always-on; }; - pp3300: regulator@3 { + pp3300: regulator-pp3000 { compatible = "regulator-fixed"; regulator-name = "PP3300"; regulator-min-microvolt = <3300000>; @@ -1843,7 +1843,7 @@ enable-active-high; }; - pp5000: regulator@4 { + pp5000: regulator-pp5000 { compatible = "regulator-fixed"; regulator-name = "PP5000"; regulator-min-microvolt = <5000000>; @@ -1851,7 +1851,7 @@ regulator-always-on; }; - pp1800_lcdio: regulator@5 { + pp1800_lcdio: regulator-pp1800-lcdio { compatible = "regulator-fixed"; regulator-name = "PP1800_LCDIO"; regulator-min-microvolt = <1800000>; @@ -1861,7 +1861,7 @@ regulator-boot-on; }; - pp1800_cam: regulator@6 { + pp1800_cam: regulator-pp1800-cam { compatible = "regulator-fixed"; regulator-name = "PP1800_CAM"; regulator-min-microvolt = <1800000>; @@ -1870,7 +1870,7 @@ enable-active-high; }; - usbc_vbus: regulator@7 { + usbc_vbus: regulator-usbc-vbus { compatible = "regulator-fixed"; regulator-name = "USBC_VBUS"; regulator-min-microvolt = <5000000>; From bd1fefcbdd8f1791c9a0e8dd169006c2a466cf17 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Mar 2020 16:45:38 +0100 Subject: [PATCH 472/574] arm64: tegra: Add native timer support on Tegra186 The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra186. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index fe588666bcfc..855ae6b705a8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -508,6 +508,22 @@ }; }; + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x0 0x03010000 0x0 0x000e0000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x40>; From 2c6fd24dcbf0a8cfb066ca886579a4a8b2275054 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:10:00 +0100 Subject: [PATCH 473/574] arm64: tegra: Fix unit-addresses on Norrin The AS3722 pinmux device tree node doesn't have a "reg" property and therefore must not have a unit-address, so drop it. While at it, add missing unit-addresses for the charger and smart battery IC's on the ChromeOS embedded controller's I2C tunnel bus. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index c84ed1cb9a8c..f9604968c01f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -564,7 +564,7 @@ pinctrl-names = "default"; pinctrl-0 = <&as3722_default>; - as3722_default: pinmux@0 { + as3722_default: pinmux { gpio0 { pins = "gpio0"; function = "gpio"; @@ -770,7 +770,7 @@ google,remote-bus = <0>; - charger: bq24735 { + charger: bq24735@9 { compatible = "ti,bq24735"; reg = <0x9>; interrupt-parent = <&gpio>; @@ -781,7 +781,7 @@ GPIO_ACTIVE_HIGH>; }; - battery: smart-battery { + battery: smart-battery@b { compatible = "sbs,sbs-battery"; reg = <0xb>; sbs,i2c-retry-count = <2>; From 64b407827670f9bd5fe08a4ed10732349339c572 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:11:53 +0100 Subject: [PATCH 474/574] arm64: tegra: Remove unsupported properties on Norrin The Tegra PMC device tree bindings don't support the "#wake-cells" and "nvidia,reset-gpio" properties, so remove them. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index f9604968c01f..f16acb4cabaa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -885,14 +885,12 @@ pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <0>; - #wake-cells = <3>; nvidia,cpu-pwr-good-time = <500>; nvidia,cpu-pwr-off-time = <300>; nvidia,core-pwr-good-time = <641 3845>; nvidia,core-pwr-off-time = <61036>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; - nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; }; usb@70090000 { From bb43b219c88c4d1fe7154af787024b885edd45f8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:13:37 +0100 Subject: [PATCH 475/574] arm64: tegra: Fix compatible string for Tegra132 timer The TKE (time-keeping engine) found on Tegra132 is not backwards compatible with the version found on Tegra20, so update the compatible string list accordingly. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 63aa3129d8fc..95bdcc8f31c9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -210,7 +210,7 @@ }; timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; reg = <0x0 0x60005000 0x0 0x400>; interrupts = , , From ed9e9a6eb118daa25c0dc04fd5fae55bf8a5356a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:17:07 +0100 Subject: [PATCH 476/574] arm64: tegra: Add OPP tables on Tegra132 Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the EMC. While at it, add the missing "#interconnect-cells" properties to the memory controller and external memory controller nodes. Also set the "#reset-cells" property for the memory controller because it exports the hotflush reset controls. Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra132-peripherals-opp.dtsi | 426 ++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra132.dtsi | 13 +- 2 files changed, 438 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi diff --git a/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi b/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi new file mode 100644 index 000000000000..66ffb7f8aaa7 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + /* EMC DVFS OPP table */ + emc_icc_dvfs_opp_table: opp-table-dvfs0 { + compatible = "operating-points-v2"; + + opp-12750000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0003>; + }; + + opp-12750000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0008>; + }; + + opp-12750000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0010>; + }; + + opp-12750000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0004>; + }; + + opp-20400000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0003>; + }; + + opp-20400000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0008>; + }; + + opp-20400000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0010>; + }; + + opp-20400000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0004>; + }; + + opp-40800000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + }; + + opp-40800000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0008>; + }; + + opp-40800000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0010>; + }; + + opp-40800000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0004>; + }; + + opp-68000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + }; + + opp-68000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0008>; + }; + + opp-68000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0010>; + }; + + opp-68000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0004>; + }; + + opp-102000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + }; + + opp-102000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0008>; + }; + + opp-102000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0010>; + }; + + opp-102000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0004>; + }; + + opp-204000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0003>; + opp-suspend; + }; + + opp-204000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0008>; + opp-suspend; + }; + + opp-204000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0010>; + opp-suspend; + }; + + opp-204000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0004>; + opp-suspend; + }; + + opp-264000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0003>; + }; + + opp-264000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0008>; + }; + + opp-264000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0010>; + }; + + opp-264000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0004>; + }; + + opp-300000000-850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + }; + + opp-300000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + }; + + opp-300000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0010>; + }; + + opp-300000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + }; + + opp-348000000-850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0003>; + }; + + opp-348000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0008>; + }; + + opp-348000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0010>; + }; + + opp-348000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0004>; + }; + + opp-396000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0008>; + }; + + opp-396000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0003>; + }; + + opp-396000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0010>; + }; + + opp-396000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0004>; + }; + + opp-528000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0008>; + }; + + opp-528000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0003>; + }; + + opp-528000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0010>; + }; + + opp-528000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0004>; + }; + + opp-600000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0008>; + }; + + opp-600000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0003>; + }; + + opp-600000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0010>; + }; + + opp-600000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + }; + + opp-792000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x000B>; + }; + + opp-792000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0010>; + }; + + opp-792000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0004>; + }; + + opp-924000000-1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + }; + + opp-1200000000-1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + }; + }; + + /* EMC bandwidth OPP table */ + emc_bw_dfs_opp_table: opp-table-dvfs1 { + compatible = "operating-points-v2"; + + opp-12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <204000>; + }; + + opp-20400000 { + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <326400>; + }; + + opp-40800000 { + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <652800>; + }; + + opp-68000000 { + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1088000>; + }; + + opp-102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1632000>; + }; + + opp-204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <3264000>; + opp-suspend; + }; + + opp-264000000 { + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4224000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4800000>; + }; + + opp-348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <5568000>; + }; + + opp-396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <6336000>; + }; + + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <8448000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <9600000>; + }; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <12672000>; + }; + + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + opp-peak-kBps = <14784000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <19200000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 95bdcc8f31c9..7f5cbcd63a25 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -8,6 +8,8 @@ #include #include +#include "tegra132-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra132", "nvidia,tegra124"; interrupt-parent = <&lic>; @@ -244,6 +246,10 @@ clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; + #cooling-cells = <2>; }; gpio: gpio@6000d000 { @@ -607,15 +613,20 @@ interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; }; emc: external-memory-controller@7001b000 { - compatible = "nvidia,tegra132-emc"; + compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; reg = <0x0 0x7001b000 0x0 0x1000>; clocks = <&tegra_car TEGRA124_CLK_EMC>; clock-names = "emc"; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; + + #interconnect-cells = <0>; }; sata@70020000 { From 92564257d7af8959eb1d5ba7ead6881c931e8bc3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:19:26 +0100 Subject: [PATCH 477/574] arm64: tegra: Fix Tegra132 I2C compatible string list The I2C controller found on Tegra124 is not fully compatible with the Tegra114 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 7f5cbcd63a25..0e8903027f04 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -400,7 +400,7 @@ }; i2c@7000c000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -415,7 +415,7 @@ }; i2c@7000c400 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c400 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -430,7 +430,7 @@ }; i2c@7000c500 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c500 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -445,7 +445,7 @@ }; i2c@7000c700 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c700 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -460,7 +460,7 @@ }; i2c@7000d000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -475,7 +475,7 @@ }; i2c@7000d100 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d100 0x0 0x100>; interrupts = ; #address-cells = <1>; From 9f27a6c421163541bc3354b573283e50f24a7c95 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:20:25 +0100 Subject: [PATCH 478/574] arm64: tegra: Drop unused AHCI clocks on Tegra132 The CML1 and PLL_E clocks are never explicitly used by the AHCI controller found on Tegra132, so drop them from the corresponding device tree node. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 0e8903027f04..16673d3bf6f9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -635,10 +635,8 @@ <0x0 0x70020000 0x0 0x7000>; /* SATA */ interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SATA>, - <&tegra_car TEGRA124_CLK_SATA_OOB>, - <&tegra_car TEGRA124_CLK_CML1>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "sata", "sata-oob", "cml1", "pll_e"; + <&tegra_car TEGRA124_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; resets = <&tegra_car 124>, <&tegra_car 129>, <&tegra_car 123>; From fce5d0731616549b9fc2c992b5896f7717fffdd4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:21:18 +0100 Subject: [PATCH 479/574] arm64: tegra: Sort Tegra132 XUSB clocks correctly Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 16673d3bf6f9..e41671fcd7e3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -674,8 +674,8 @@ <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA124_CLK_PLL_U_480M>, @@ -683,7 +683,7 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, From fe57ff5365c9aef12e80ee51e38d0ea6bb17b255 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:24:20 +0100 Subject: [PATCH 480/574] arm64: tegra: Rename thermal zones nodes The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 11 ++++--- .../nvidia/tegra186-p3509-0000+p3636-0001.dts | 32 +++++++++---------- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 27 +++++++--------- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 6 ++-- .../boot/dts/nvidia/tegra194-p3509-0000.dtsi | 6 ++-- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 30 +++++++---------- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 ++--- 8 files changed, 58 insertions(+), 64 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index e41671fcd7e3..3673f79adf1a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -895,7 +895,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -923,7 +923,8 @@ }; }; }; - mem { + + mem-thermal { polling-delay-passive = <0>; polling-delay = <0>; @@ -950,7 +951,8 @@ */ }; }; - gpu { + + gpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -978,7 +980,8 @@ }; }; }; - pllx { + + pllx-thermal { polling-delay-passive = <0>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 28d59792eaa1..33e707ef883b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -633,7 +633,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -687,21 +687,7 @@ }; }; - gpu { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; - - trips { - gpu_alert0: critical { - temperature = <99000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - aux { + aux-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -714,6 +700,20 @@ }; }; }; + + gpu-thermal { + polling-delay = <0>; + polling-delay-passive = <500>; + status = "okay"; + + trips { + gpu_alert0: critical { + temperature = <99000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; }; aconnect@2900000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 855ae6b705a8..a5c19e4b39c5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1976,12 +1976,12 @@ }; thermal-zones { - a57 { + /* Cortex-A57 cluster */ + cpu-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; trips { critical { @@ -1995,12 +1995,12 @@ }; }; - denver { + /* Denver cluster */ + aux-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; trips { critical { @@ -2014,12 +2014,11 @@ }; }; - gpu { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; trips { critical { @@ -2033,12 +2032,11 @@ }; }; - pll { + pll-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; trips { critical { @@ -2052,12 +2050,11 @@ }; }; - always_on { + ao-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; trips { critical { diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 9f34871b8f60..b79d7d89cf62 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -2097,7 +2097,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2151,7 +2151,7 @@ }; }; - gpu { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2165,7 +2165,7 @@ }; }; - aux { + aux-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 8d3999cd1af2..76d94ecd1cfe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -2103,7 +2103,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2157,7 +2157,7 @@ }; }; - gpu { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2171,7 +2171,7 @@ }; }; - aux { + aux-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f9b1900088ad..0ea613715c6f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2903,39 +2903,33 @@ }; thermal-zones { - cpu { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_CPU>; + cpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; status = "disabled"; }; - gpu { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_GPU>; + gpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; status = "disabled"; }; - aux { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_AUX>; + aux-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; status = "disabled"; }; - pllx { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_PLLX>; + pllx-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; status = "disabled"; }; - ao { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_AO>; + ao-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; status = "disabled"; }; - tj { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; + tj-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 283b50febb6f..9e60ebf2f5c0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1684,7 +1684,7 @@ }; thermal-zones { - cpu { + cpu-thermal { trips { cpu_trip_critical: critical { temperature = <96500>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index ccdc0dec4e59..af9237ad03c1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1981,7 +1981,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -2010,7 +2010,7 @@ }; }; - mem { + mem-thermal { polling-delay-passive = <0>; polling-delay = <0>; @@ -2056,7 +2056,7 @@ }; }; - gpu { + gpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -2085,7 +2085,7 @@ }; }; - pllx { + pllx-thermal { polling-delay-passive = <0>; polling-delay = <0>; From 4b5ae31fb75655d6270a160a3ebafc48474f597d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:25:50 +0100 Subject: [PATCH 481/574] arm64: tegra: Rename power-monitor input nodes Child nodes of the TI INA3221 power monitor device tree node should be called input@* according to the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++------ arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 12 ++++++------ .../dts/nvidia/tegra186-p3509-0000+p3636-0001.dts | 8 ++++---- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 2883049c4edf..c4dee05f330c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -1945,19 +1945,19 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_MUX"; shunt-resistor-micro-ohms = <20000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_5V0_IO_SYS"; shunt-resistor-micro-ohms = <5000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_3V3_SYS"; shunt-resistor-micro-ohms = <10000>; @@ -1970,19 +1970,19 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_3V3_IO_SLP"; shunt-resistor-micro-ohms = <10000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_1V8_IO"; shunt-resistor-micro-ohms = <10000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_M2_IN"; shunt-resistor-micro-ohms = <10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 4917b43995b0..3d8878c0ec03 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -73,19 +73,19 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_SYS_GPU"; shunt-resistor-micro-ohms = <10000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_SYS_SOC"; shunt-resistor-micro-ohms = <10000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_3V8_WIFI"; shunt-resistor-micro-ohms = <10000>; @@ -98,19 +98,19 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_IN"; shunt-resistor-micro-ohms = <5000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_SYS_CPU"; shunt-resistor-micro-ohms = <10000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_5V0_DDR"; shunt-resistor-micro-ohms = <10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 33e707ef883b..6cc51083adb7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -81,22 +81,22 @@ #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0>; label = "VDD_IN"; shunt-resistor-micro-ohms = <5>; }; - channel@1 { + input@1 { reg = <1>; label = "VDD_CPU_GPU"; shunt-resistor-micro-ohms = <5>; }; - channel@2 { + input@2 { reg = <2>; label = "VDD_SOC"; - shunt-resistor-micro-ohms = <>; + shunt-resistor-micro-ohms = <5>; }; }; }; From 548c9c5aaf85bb157b1a87fdc558e3767f5f0bde Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:27:11 +0100 Subject: [PATCH 482/574] arm64: tegra: Fix Tegra186 compatible string list The I2C controller found on Tegra186 is not fully compatible with the Tegra210 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index a5c19e4b39c5..21f823ea08c6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -585,7 +585,7 @@ }; gen1_i2c: i2c@3160000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x03160000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -598,7 +598,7 @@ }; cam_i2c: i2c@3180000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x03180000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -612,7 +612,7 @@ /* shares pads with dpaux1 */ dp_aux_ch1_i2c: i2c@3190000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x03190000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -629,7 +629,7 @@ /* controlled by BPMP, should not be enabled */ pwr_i2c: i2c@31a0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031a0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -643,7 +643,7 @@ /* shares pads with dpaux0 */ dp_aux_ch0_i2c: i2c@31b0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031b0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -659,7 +659,7 @@ }; gen7_i2c: i2c@31c0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031c0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -672,7 +672,7 @@ }; gen9_i2c: i2c@31e0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031e0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -1089,7 +1089,7 @@ }; gen2_i2c: i2c@c240000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x0c240000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -1102,7 +1102,7 @@ }; gen8_i2c: i2c@c250000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x0c250000 0x0 0x10000>; interrupts = ; #address-cells = <1>; From 2b14cbd643feea5fc17c6e8bead4e71088c69acd Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:28:29 +0100 Subject: [PATCH 483/574] arm64: tegra: Adjust length of CCPLEX cluster MMIO region The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4 MiB - 1. This was likely presumed to be the "limit" rather than length. Fix it up. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 21f823ea08c6..c91afff1b757 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1215,7 +1215,7 @@ ccplex@e000000 { compatible = "nvidia,tegra186-ccplex-cluster"; - reg = <0x0 0x0e000000 0x0 0x3fffff>; + reg = <0x0 0x0e000000 0x0 0x400000>; nvidia,bpmp = <&bpmp>; }; From e7445ab7dc5160540930912fae02660601b6de80 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:36:35 +0100 Subject: [PATCH 484/574] arm64: tegra: Drop unit-address for audio card graph endpoints Audio graph endpoints don't have a "reg" property, so they shouldn't have a unit-address either. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index b79d7d89cf62..2478ece9e67c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -1031,7 +1031,7 @@ i2s6_port: port@1 { reg = <1>; - i2s6_dap_ep: endpoint@0 { + i2s6_dap_ep: endpoint { dai-format = "i2s"; /* Place holder for external Codec */ }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 76d94ecd1cfe..6d4ed67ffeda 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -989,7 +989,7 @@ i2s5_port: port@1 { reg = <1>; - i2s5_dap_ep: endpoint@0 { + i2s5_dap_ep: endpoint { dai-format = "i2s"; /* Place holder for external Codec */ }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9e60ebf2f5c0..260de1122aa3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -688,7 +688,7 @@ i2s4_port: port@1 { reg = <1>; - i2s4_dap_ep: endpoint@0 { + i2s4_dap_ep: endpoint { dai-format = "i2s"; /* Placeholder for external Codec */ }; @@ -706,7 +706,7 @@ port@0 { reg = <0>; - dmic1_cif_ep: endpoint@0 { + dmic1_cif_ep: endpoint { remote-endpoint = <&xbar_dmic1_ep>; }; }; @@ -714,7 +714,7 @@ dmic1_port: port@1 { reg = <1>; - dmic1_dap_ep: endpoint@0 { + dmic1_dap_ep: endpoint { /* Placeholder for external Codec */ }; }; @@ -731,7 +731,7 @@ port@0 { reg = <0>; - dmic2_cif_ep: endpoint@0 { + dmic2_cif_ep: endpoint { remote-endpoint = <&xbar_dmic2_ep>; }; }; @@ -739,7 +739,7 @@ dmic2_port: port@1 { reg = <1>; - dmic2_dap_ep: endpoint@0 { + dmic2_dap_ep: endpoint { /* Placeholder for external Codec */ }; }; From 56797e625910497ef2a2dd40b76be2633a86f726 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:39:20 +0100 Subject: [PATCH 485/574] arm64: tegra: Use JEDEC vendor prefix for SPI NOR flash chips The standard "jedec," vendor prefix should be used for SPI NOR flash chips. This allows the right DT schema to be picked for validation. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 6d4ed67ffeda..1323fa9b8301 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -1878,7 +1878,7 @@ status = "okay"; flash@0 { - compatible = "spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <102000000>; spi-tx-bus-width = <4>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 260de1122aa3..9fc4a8f46250 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1637,7 +1637,7 @@ status = "okay"; flash@0 { - compatible = "spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <104000000>; spi-tx-bus-width = <2>; From 2fcb87970e4282a227e09108d479e860b5b9faf0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:40:59 +0100 Subject: [PATCH 486/574] arm64: tegra: Drop unsupported nvidia,lpdr property The Tegra194 pinmux DT bindings do not define the nvidia,lpdr property, so drop them from the device trees that have listed them. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 0ea613715c6f..5e1cbb788937 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -536,7 +536,6 @@ pex_rst { nvidia,pins = "pex_l5_rst_n_pgg1"; nvidia,schmitt = ; - nvidia,lpdr = ; nvidia,enable-input = ; nvidia,io-hv = ; nvidia,tristate = ; @@ -548,7 +547,6 @@ clkreq { nvidia,pins = "pex_l5_clkreq_n_pgg0"; nvidia,schmitt = ; - nvidia,lpdr = ; nvidia,enable-input = ; nvidia,io-hv = ; nvidia,tristate = ; From cd6157c1978c84d4fd9b9cedc736fc7b5fce4d09 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:43:20 +0100 Subject: [PATCH 487/574] arm64: tegra: Fix Tegra194 HSP compatible string The HSP instances on Tegra194 are not fully compatible with the version found on Tegra186, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 5e1cbb788937..d7fd6bdd131a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1195,7 +1195,7 @@ }; hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp"; reg = <0x03c00000 0xa0000>; interrupts = , , @@ -1373,7 +1373,7 @@ }; hsp_aon: hsp@c150000 { - compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp"; reg = <0x0c150000 0x90000>; interrupts = , , From 1ff75059077c0d37edb936d9232f76a74704be41 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:47:47 +0100 Subject: [PATCH 488/574] arm64: tegra: Drop unused properties for Tegra194 PCIe The num-viewport property is never used and can be dropped, whereas the "iommus" property is not needed since we use "iommu-map-mask" and "iommu-map" already. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index d7fd6bdd131a..bb51ccdb324d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2169,7 +2169,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <1>; - num-viewport = <8>; linux,pci-domain = <1>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; @@ -2202,7 +2201,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE1>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2223,7 +2221,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <1>; - num-viewport = <8>; linux,pci-domain = <2>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; @@ -2256,7 +2253,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE2>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2277,7 +2273,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <1>; - num-viewport = <8>; linux,pci-domain = <3>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; @@ -2310,7 +2305,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE3>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2331,7 +2325,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <4>; - num-viewport = <8>; linux,pci-domain = <4>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; @@ -2364,7 +2357,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE4>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2385,7 +2377,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <8>; - num-viewport = <8>; linux,pci-domain = <0>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; @@ -2418,7 +2409,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE0>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2439,7 +2429,6 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <8>; - num-viewport = <8>; linux,pci-domain = <5>; pinctrl-names = "default"; @@ -2476,7 +2465,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE5>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2516,7 +2504,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE4>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2556,7 +2543,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE0>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2599,7 +2585,6 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE5>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; iommu-map-mask = <0x0>; dma-coherent; From c453cc9e9e1afbb3c3c2bc2579e4cc2c8ee7641c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:50:44 +0100 Subject: [PATCH 489/574] arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock The "core_m" clock is not documented in the Tegra194 PCIe device tree bindings, so remove it. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index bb51ccdb324d..bb88d32e553e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2434,9 +2434,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, - <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; - clock-names = "core", "core_m"; + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; + clock-names = "core"; resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, <&bpmp TEGRA194_RESET_PEX1_CORE_5>; From 99d9bde5b4ab05c98f6c2c5e8fb276d3b7072be3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:51:54 +0100 Subject: [PATCH 490/574] arm64: tegra: Rename TCU node to "serial" The TCU is basically a serial port (albeit a fancy one), so it should be named "serial". Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index bb88d32e553e..abea546cb072 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2877,7 +2877,7 @@ iommus = <&smmu TEGRA194_SID_APE>; }; - tcu: tcu { + tcu: serial { compatible = "nvidia,tegra194-tcu"; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; From 1dcf00ae8205ee2fdbc0c55c41c486f287d20739 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:53:28 +0100 Subject: [PATCH 491/574] arm64: tegra: Remove unsupported regulator properties Remove the unsupported "regulator-disable-ramp-delay" properties which ended up in various DTS files for some reason. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 2 -- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 11 ----------- 2 files changed, 13 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 34276a84c68a..21d7e653ea5b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1588,7 +1588,6 @@ vin-supply = <&vdd_sys_mux>; regulator-enable-ramp-delay = <160>; - regulator-disable-ramp-delay = <10000>; }; vdd_5v0_io: regulator-vdd-5v0-io { @@ -1610,7 +1609,6 @@ vin-supply = <&vdd_3v3_sys>; regulator-enable-ramp-delay = <472>; - regulator-disable-ramp-delay = <4880>; }; vdd_dsi_csi: regulator-vdd-dsi-csi { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9fc4a8f46250..542f51c07781 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -266,7 +266,6 @@ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1170000>; regulator-enable-ramp-delay = <146>; - regulator-disable-ramp-delay = <4080>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <300>; regulator-always-on; @@ -282,7 +281,6 @@ regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1150000>; regulator-enable-ramp-delay = <176>; - regulator-disable-ramp-delay = <145800>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <300>; regulator-always-on; @@ -298,7 +296,6 @@ regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-enable-ramp-delay = <176>; - regulator-disable-ramp-delay = <32000>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <350>; regulator-always-on; @@ -314,7 +311,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <242>; - regulator-disable-ramp-delay = <118000>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <360>; regulator-always-on; @@ -330,7 +326,6 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-enable-ramp-delay = <26>; - regulator-disable-ramp-delay = <626>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; regulator-always-on; @@ -346,7 +341,6 @@ regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <650>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -360,7 +354,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <62>; - regulator-disable-ramp-delay = <650>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -378,7 +371,6 @@ regulator-min-microvolt = <850000>; regulator-max-microvolt = <1100000>; regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <610>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; regulator-disable-active-discharge; @@ -403,7 +395,6 @@ regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <24>; - regulator-disable-ramp-delay = <2768>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -417,7 +408,6 @@ regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <1160>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -1779,7 +1769,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <240>; - regulator-disable-ramp-delay = <11340>; regulator-always-on; regulator-boot-on; From 635fb5d4cb2590f3f655f05f880cefabf1cb43dd Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:54:48 +0100 Subject: [PATCH 492/574] arm64: tegra: Rename GPIO hog nodes to match schema GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to the DT schema. Rename all such nodes to allow validation to pass. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 5cfbc0394173..10347b6e6e84 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1383,7 +1383,7 @@ }; }; - gpio@0 { + hog-0 { gpio-hog; output-high; gpios = <2 GPIO_ACTIVE_HIGH>, From 31bc882c03d447b7ae5c28ed5480467ee714fd91 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 22 Mar 2019 14:41:53 +0100 Subject: [PATCH 493/574] arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB The XUSB pad controller handles the various PLL power supplies, so remove any references to them from the PCIe and XUSB controller device tree nodes. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 3 --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 5 ----- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 2e17df6f20ad..328fbfec4ee8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -11,11 +11,8 @@ pcie@1003000 { status = "okay"; - avdd-pll-uerefe-supply = <&avdd_1v05_pll>; hvddio-pex-supply = <&vdd_1v8>; dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; vddio-pex-ctl-supply = <&vdd_1v8>; pci@1,0 { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 21d7e653ea5b..4b43b89a9651 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1361,11 +1361,6 @@ dvddio-pex-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; avdd-usb-supply = <&vdd_3v3_sys>; - /* XXX what are these? */ - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; - hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; status = "okay"; From 54215999f30bf7672c302b34c91db76eed525b5e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 22 Mar 2019 14:43:03 +0100 Subject: [PATCH 494/574] arm64: tegra: smaug: Remove extra PLL power supplies for XUSB The XUSB pad controller handles the various PLL power supplies, so remove any references to them from the XUSB controller device tree node. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 6d59c28ff2a3..a263d51882ee 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1642,10 +1642,6 @@ dvddio-pex-supply = <&avddio_1v05>; hvddio-pex-supply = <&pp1800>; avdd-usb-supply = <&pp3300>; - avdd-pll-utmip-supply = <&pp1800>; - avdd-pll-uerefe-supply = <&pp1050_avdd>; - dvdd-pex-pll-supply = <&avddio_1v05>; - hvdd-pex-pll-e-supply = <&pp1800>; status = "okay"; }; From 9c1b3ef8e204ca952d0304d4b92fa54de8b9815a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 22 Mar 2019 14:56:11 +0100 Subject: [PATCH 495/574] arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB The XUSB pad controller handles the various PLL power supplies, so remove any references to them from the PCIe and XUSB controller device tree nodes. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 542f51c07781..72c2dc3c14ea 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -30,11 +30,8 @@ pcie@1003000 { status = "okay"; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; vddio-pex-ctl-supply = <&vdd_1v8>; pci@1,0 { @@ -446,11 +443,6 @@ avdd-usb-supply = <&vdd_3v3_sys>; dvddio-pex-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; - /* these really belong to the XUSB pad controller */ - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; - hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; status = "okay"; }; From 28a44b900e572ecb163cc4e042365b7df6e0fad3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 15:01:37 +0100 Subject: [PATCH 496/574] arm64: tegra: Add missing TSEC properties on Tegra210 Add missing interrupts, clocks, clock-names, reset and reset-names properties for the TSEC blocks found on Tegra210. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index af9237ad03c1..a49a12fd84b1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -181,6 +181,12 @@ tsec@54100000 { compatible = "nvidia,tegra210-tsec"; reg = <0x0 0x54100000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_TSEC>; + clock-names = "tsec"; + resets = <&tegra_car 83>; + reset-names = "tsec"; + status = "disabled"; }; dc@54200000 { @@ -283,6 +289,11 @@ tsec@54500000 { compatible = "nvidia,tegra210-tsec"; reg = <0x0 0x54500000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_TSECB>; + clock-names = "tsec"; + resets = <&tegra_car 206>; + reset-names = "tsec"; status = "disabled"; }; From f2ef6a9180f38f7b6f633a90126d27e8a669a688 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 15:05:32 +0100 Subject: [PATCH 497/574] arm64: tegra: Sort Tegra210 XUSB clocks correctly Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a49a12fd84b1..aa768ea108fe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1026,8 +1026,8 @@ <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA210_CLK_XUSB_SS>, - <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA210_CLK_PLL_U_480M>, @@ -1035,7 +1035,7 @@ <&tegra_car TEGRA210_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, From 02752947367289e8bfd0f09f9c4a5acfb0ac3602 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 15:06:19 +0100 Subject: [PATCH 498/574] arm64: tegra: Remove unused only-1-8-v properties The only-1-8-v property is not support by an DT schema, so drop it. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi | 1 - arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index d3c936822186..d95a542c0bca 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -11,7 +11,6 @@ status = "okay"; bus-width = <8>; non-removable; - only-1-8-v; }; rtc@c2a0000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts index b5d9a5526272..5804acfc428a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts @@ -26,7 +26,6 @@ status = "okay"; bus-width = <8>; non-removable; - only-1-8-v; }; rtc@c2a0000 { From 553f07360e23b2e17b26be2fcd9ebfc0c14d0e24 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 8 Dec 2021 16:29:11 +0100 Subject: [PATCH 499/574] arm64: tegra: Rename Ethernet PHY nodes Name the Ethernet PHY device tree nodes as expected by the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 3d8878c0ec03..aff857df25cf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -44,7 +44,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 6cc51083adb7..4631504c3c7a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -46,7 +46,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio_aon>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index ad217cac2b28..a7d7cfd66379 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -39,7 +39,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi index f16b0aa8a374..0bd66f9c620b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi @@ -36,7 +36,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>; From a52280c844c0549b16418dc7e70bdf46a66072eb Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Mon, 25 Oct 2021 12:08:42 +0100 Subject: [PATCH 500/574] arm64: tegra: Add dma-coherent for Tegra194 VIC DMA operations for the Tegra194 Video Image Compositor (VIC) are coherent and so populate the 'dma-coherent' property. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index abea546cb072..aeb79660c58e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1811,6 +1811,7 @@ <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA194_SID_VIC>; + dma-coherent; }; nvjpg@15380000 { From c2fee44399af4fda2dd8070cfb96cd6de2385442 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Thu, 16 Dec 2021 15:16:10 +0530 Subject: [PATCH 501/574] arm64: tegra: Update SDMMC4 speeds for Tegra194 Add required device-tree properties to populate all speed modes supported by SDMMC4 instance of Tegra194 SDHCI controller. Signed-off-by: Prathamesh Shete Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index aeb79660c58e..c830f508de42 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -976,6 +976,11 @@ nvidia,default-tap = <0x8>; nvidia,default-trim = <0x14>; nvidia,dqs-trim = <40>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; supports-cqe; status = "disabled"; }; From cc9396676c1bc4414fa62514daadfece55ef3cfb Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:49 +0100 Subject: [PATCH 502/574] arm64: tegra: Add EMC general interrupt on Tegra194 Add the missing EMC general interrupt for the external memory controller on Tegra194. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c830f508de42..3c4acfca459d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -592,6 +592,7 @@ compatible = "nvidia,tegra194-emc"; reg = <0x0 0x02c60000 0x0 0x90000>, <0x0 0x01780000 0x0 0x80000>; + interrupts = ; clocks = <&bpmp TEGRA194_CLK_EMC>; clock-names = "emc"; From eed280dfe91d84d6b9ad62e47d1b69aa8d9b4db2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:50 +0100 Subject: [PATCH 503/574] arm64: tegra: Add memory controller on Tegra234 This adds the memory controller and the embedded external memory controller found on the Tegra234 SoC. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index b60e4f6f0658..59ad115369bd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include / { @@ -84,6 +85,54 @@ gpio-controller; }; + mc: memory-controller@2c00000 { + compatible = "nvidia,tegra234-mc"; + reg = <0x02c00000 0x100000>, + <0x02b80000 0x040000>, + <0x01700000 0x100000>; + interrupts = ; + #interconnect-cells = <1>; + status = "okay"; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, + <0x02b80000 0x0 0x02b80000 0x0 0x040000>, + <0x02c00000 0x0 0x02c00000 0x0 0x100000>; + + /* + * Bit 39 of addresses passing through the memory + * controller selects the XBAR format used when memory + * is accessed. This is used to transparently access + * memory in the XBAR format used by the discrete GPU + * (bit 39 set) or Tegra (bit 39 clear). + * + * As a consequence, the operating system must ensure + * that bit 39 is never used implicitly, for example + * via an I/O virtual address mapping of an IOMMU. If + * devices require access to the XBAR switch, their + * drivers must set this bit explicitly. + * + * Limit the DMA range for memory clients to [38:0]. + */ + dma-ranges = <0x0 0x0 0x0 0x80 0x0>; + + emc: external-memory-controller@2c60000 { + compatible = "nvidia,tegra234-emc"; + reg = <0x0 0x02c60000 0x0 0x90000>, + <0x0 0x01780000 0x0 0x80000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_EMC>; + clock-names = "emc"; + status = "okay"; + + #interconnect-cells = <0>; + + nvidia,bpmp = <&bpmp>; + }; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x10000>; From 6de481e5ab0d69cddbc7c20e8471a950313d4e07 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:51 +0100 Subject: [PATCH 504/574] arm64: tegra: Hook up MMC and BPMP to memory controller Use the interconnects property to hook up the MMC and BPMP to the memory controller. This is needed to set the correct bus-level DMA mask, which is a prerequisite for adding IOMMU support. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 59ad115369bd..6b6f15804a1a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -156,6 +156,9 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; resets = <&bpmp TEGRA234_RESET_SDMMC4>; reset-names = "sdhci"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, + <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; + interconnect-names = "dma-mem", "write"; nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; @@ -288,6 +291,11 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; bpmp_i2c: i2c { compatible = "nvidia,tegra186-bpmp-i2c"; From 73e2b72a3518fb60b6a1c11286715f933bafdec2 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:44 +0300 Subject: [PATCH 505/574] ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees Add OPP tables and power domains to all peripheral devices which support power management on Tegra30 SoC. Tested-by: Peter Geis # Ouya T30 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../tegra30-asus-nexus7-grouper-common.dtsi | 1 + arch/arm/boot/dts/tegra30-beaver.dts | 1 + arch/arm/boot/dts/tegra30-cardhu.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 17 +- arch/arm/boot/dts/tegra30-ouya.dts | 1 + .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 1224 +++++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 153 +++ 7 files changed, 1395 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index d79a99470ac2..2c2ad2a38f04 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -968,6 +968,7 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; ahub@70080000 { diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 7c2b70b13cc4..5ad62b567d32 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1916,6 +1916,7 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&core_vdd_reg>; }; ahub@70080000 { diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index c2a56eb0b9fa..ba257ed36d9c 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -393,6 +393,7 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; ahub@70080000 { diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 9bf8170fee79..be691a1c33a1 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -767,9 +767,14 @@ vddctrl_reg: vddctrl { regulator-name = "+V1.0_VDD_CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; reg_1v8_vio: vio { @@ -892,15 +897,20 @@ }; /* SW: +V1.2_VDD_CORE */ - regulator@60 { + vdd_core: regulator@60 { compatible = "ti,tps62362"; reg = <0x60>; regulator-name = "tps62362-vout"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; + + nvidia,tegra-core-regulator; }; }; @@ -913,6 +923,7 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ i2c-thermtrip { diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index b28c5504e1b1..e604ad08a2c2 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -2195,6 +2195,7 @@ nvidia,core-pwr-off-time = <458>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; memory-controller@7000f000 { diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi index af9640401402..d100a1a8b705 100644 --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -1,6 +1,56 @@ // SPDX-License-Identifier: GPL-2.0 / { + core_opp_table: opp-table-core { + compatible = "operating-points-v2"; + opp-shared; + + core_opp_950: opp-950000 { + opp-microvolt = <950000 950000 1350000>; + opp-level = <950000>; + }; + + core_opp_1000: opp-1000000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-level = <1000000>; + }; + + core_opp_1050: opp-1050000 { + opp-microvolt = <1050000 1050000 1350000>; + opp-level = <1050000>; + }; + + core_opp_1100: opp-1100000 { + opp-microvolt = <1100000 1100000 1350000>; + opp-level = <1100000>; + }; + + core_opp_1150: opp-1150000 { + opp-microvolt = <1150000 1150000 1350000>; + opp-level = <1150000>; + }; + + core_opp_1200: opp-1200000 { + opp-microvolt = <1200000 1200000 1350000>; + opp-level = <1200000>; + }; + + core_opp_1250: opp-1250000 { + opp-microvolt = <1250000 1250000 1350000>; + opp-level = <1250000>; + }; + + core_opp_1300: opp-1300000 { + opp-microvolt = <1300000 1300000 1350000>; + opp-level = <1300000>; + }; + + core_opp_1350: opp-1350000 { + opp-microvolt = <1350000 1350000 1350000>; + opp-level = <1350000>; + }; + }; + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; @@ -8,126 +58,147 @@ opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-12750000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-12750000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-25500000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-25500000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-25500000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-27000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-27000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-27000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-51000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-51000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-51000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-54000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-54000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-54000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-102000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-102000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-102000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-108000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; }; opp-108000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-204000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; opp-suspend; }; @@ -135,6 +206,7 @@ opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; opp-suspend; }; @@ -142,138 +214,161 @@ opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; }; opp-333500000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; }; opp-333500000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-375000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; }; opp-375000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; }; opp-375000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-400000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; }; opp-400000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; }; opp-400000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-416000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; }; opp-416000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-450000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; }; opp-450000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-500000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <500000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; }; opp-500000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <500000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-533000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; }; opp-533000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-625000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; }; opp-625000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-667000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <667000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; }; opp-750000000-1300 { opp-microvolt = <1300000 1300000 1350000>; opp-hz = /bits/ 64 <750000000>; opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; }; opp-800000000-1300 { opp-microvolt = <1300000 1300000 1350000>; opp-hz = /bits/ 64 <800000000>; opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; }; opp-900000000-1350 { opp-microvolt = <1350000 1350000 1350000>; opp-hz = /bits/ 64 <900000000>; opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; }; }; @@ -401,4 +496,1133 @@ opp-peak-kBps = <7200000>; }; }; + + pcie_dvfs_opp_table: opp-table-pcie { + compatible = "operating-points-v2"; + + opp-250000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + host1x_dvfs_opp_table: opp-table-host1x { + compatible = "operating-points-v2"; + + opp-152000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-188000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <188000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1050>; + }; + + opp-222000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <222000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1100>; + }; + + opp-242000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <242000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-254000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <254000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1150>; + }; + + opp-267000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + mpe_dvfs_opp_table: opp-table-mpe { + compatible = "operating-points-v2"; + + opp-234000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <234000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + vi_dvfs_opp_table: opp-table-vi { + compatible = "operating-points-v2"; + + opp-216000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>; + }; + + opp-219000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <219000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-267000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1050>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-300000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1100>; + }; + + opp-371000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <371000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1150>; + }; + + opp-409000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <409000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-425000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <425000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1250>; + }; + + opp-470000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <470000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + }; + + epp_dvfs_opp_table: opp-table-epp { + compatible = "operating-points-v2"; + + opp-267000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + gr2d_dvfs_opp_table: opp-table-gr2d { + compatible = "operating-points-v2"; + + opp-267000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + gr3d_dvfs_opp_table: opp-table-gr3d { + compatible = "operating-points-v2"; + + opp-234000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <234000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>, <&core_opp_1000>; + }; + + opp-247000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>, <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>, <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>, <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>, <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>, <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>, <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>, <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>, <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>, <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>, <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>, <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>, <&core_opp_1350>; + }; + }; + + disp1_dvfs_opp_table: opp-table-disp1 { + compatible = "operating-points-v2"; + + opp-120000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <120000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1000>; + }; + + opp-155000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <155000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1200>; + }; + + opp-268000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <268000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1050>; + }; + }; + + disp2_dvfs_opp_table: opp-table-disp2 { + compatible = "operating-points-v2"; + + opp-120000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <120000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1000>; + }; + + opp-155000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <155000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1200>; + }; + + opp-268000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <268000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1050>; + }; + }; + + hdmi_dvfs_opp_table: opp-table-hdmi { + compatible = "operating-points-v2"; + + opp-148500000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <148500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + tvo_dvfs_opp_table: opp-table-tvo { + compatible = "operating-points-v2"; + + opp-297000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <297000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + }; + + dsia_dvfs_opp_table: opp-table-dsia { + compatible = "operating-points-v2"; + + opp-275000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + dsib_dvfs_opp_table: opp-table-dsib { + compatible = "operating-points-v2"; + + opp-275000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sclk_dvfs_opp_table: opp-table-sclk { + compatible = "operating-points-v2"; + + opp-51000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; + }; + + opp-136000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <136000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-164000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <164000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-191000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <191000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-205000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <205000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-216000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1150>; + }; + + opp-227000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <227000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1100>; + }; + + opp-267000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-334000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <334000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1250>; + }; + + opp-378000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <378000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + }; + + pll_c_dvfs_opp_table: opp-table-pllc { + compatible = "operating-points-v2"; + + opp-533000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-667000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-800000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-1066000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <1066000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + + opp-1200000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1350>; + }; + }; + + pll_e_dvfs_opp_table: opp-table-plle { + compatible = "operating-points-v2"; + + opp-100000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + pll_m_dvfs_opp_table: opp-table-pllm { + compatible = "operating-points-v2"; + + opp-533000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-667000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-800000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-1066000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <1066000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + vde_dvfs_opp_table: opp-table-vde { + compatible = "operating-points-v2"; + + opp-228000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-275000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-352000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <352000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-400000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-437000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <437000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + fuse_burn_dvfs_opp_table: opp-table-fuseburn { + compatible = "operating-points-v2"; + + opp-26000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <26000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1150>; + }; + }; + + nor_dvfs_opp_table: opp-table-nor { + compatible = "operating-points-v2"; + + opp-108000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-115000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <115000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-130000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <130000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1050>; + }; + + opp-133000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1150>; + }; + }; + + pwm_dvfs_opp_table: opp-table-pwm { + compatible = "operating-points-v2"; + + opp-408000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sbc1_dvfs_opp_table: opp-table-sbc1 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc2_dvfs_opp_table: opp-table-sbc2 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc3_dvfs_opp_table: opp-table-sbc3 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc4_dvfs_opp_table: opp-table-sbc4 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc5_dvfs_opp_table: opp-table-sbc5 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc6_dvfs_opp_table: opp-table-sbc6 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { + compatible = "operating-points-v2"; + + opp-104000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <104000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-208000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <208000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { + compatible = "operating-points-v2"; + + opp-104000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <104000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-208000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <208000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + usbd_dvfs_opp_table: opp-table-usbd { + compatible = "operating-points-v2"; + + opp-480000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + usb2_dvfs_opp_table: opp-table-usb2 { + compatible = "operating-points-v2"; + + opp-480000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + usb3_dvfs_opp_table: opp-table-usb3 { + compatible = "operating-points-v2"; + + opp-480000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 46befba0bc72..83095a467b35 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -55,6 +55,8 @@ <&tegra_car 72>, <&tegra_car 74>; reset-names = "pex", "afi", "pcie_x"; + power-domains = <&pd_core>; + operating-points-v2 = <&pcie_dvfs_opp_table>; status = "disabled"; pci@1,0 { @@ -124,6 +126,8 @@ resets = <&tegra_car 28>; reset-names = "host1x"; iommus = <&mc TEGRA_SWGROUP_HC>; + power-domains = <&pd_heg>; + operating-points-v2 = <&host1x_dvfs_opp_table>; #address-cells = <1>; #size-cells = <1>; @@ -137,6 +141,8 @@ clocks = <&tegra_car TEGRA30_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + power-domains = <&pd_mpe>; + operating-points-v2 = <&mpe_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_MPE>; }; @@ -148,6 +154,8 @@ clocks = <&tegra_car TEGRA30_CLK_VI>; resets = <&tegra_car 20>; reset-names = "vi"; + power-domains = <&pd_venc>; + operating-points-v2 = <&vi_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_VI>; }; @@ -159,6 +167,8 @@ clocks = <&tegra_car TEGRA30_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + power-domains = <&pd_heg>; + operating-points-v2 = <&epp_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_EPP>; }; @@ -170,6 +180,7 @@ clocks = <&tegra_car TEGRA30_CLK_ISP>; resets = <&tegra_car 23>; reset-names = "isp"; + power-domains = <&pd_venc>; iommus = <&mc TEGRA_SWGROUP_ISP>; }; @@ -181,6 +192,8 @@ clocks = <&tegra_car TEGRA30_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + power-domains = <&pd_heg>; + operating-points-v2 = <&gr2d_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_G2>; }; @@ -194,6 +207,9 @@ resets = <&tegra_car 24>, <&tegra_car 98>; reset-names = "3d", "3d2"; + power-domains = <&pd_3d0>, <&pd_3d1>; + power-domain-names = "3d0", "3d1"; + operating-points-v2 = <&gr3d_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_NV>, <&mc TEGRA_SWGROUP_NV2>; @@ -208,6 +224,8 @@ clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp1_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_DC>; @@ -238,6 +256,8 @@ clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp2_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_DCB>; @@ -268,6 +288,8 @@ clock-names = "hdmi", "parent"; resets = <&tegra_car 51>; reset-names = "hdmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&hdmi_dvfs_opp_table>; status = "disabled"; }; @@ -276,6 +298,8 @@ reg = <0x542c0000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_TVO>; + power-domains = <&pd_core>; + operating-points-v2 = <&tvo_dvfs_opp_table>; status = "disabled"; }; @@ -287,6 +311,8 @@ clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; + power-domains = <&pd_core>; + operating-points-v2 = <&dsia_dvfs_opp_table>; status = "disabled"; }; @@ -298,6 +324,8 @@ clock-names = "dsi", "parent"; resets = <&tegra_car 84>; reset-names = "dsi"; + power-domains = <&pd_core>; + operating-points-v2 = <&dsib_dvfs_opp_table>; status = "disabled"; }; }; @@ -358,6 +386,34 @@ reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + sclk { + compatible = "nvidia,tegra30-sclk"; + clocks = <&tegra_car TEGRA30_CLK_SCLK>; + power-domains = <&pd_core>; + operating-points-v2 = <&sclk_dvfs_opp_table>; + }; + + pll-c { + compatible = "nvidia,tegra30-pllc"; + clocks = <&tegra_car TEGRA30_CLK_PLL_C>; + power-domains = <&pd_core>; + operating-points-v2 = <&pll_c_dvfs_opp_table>; + }; + + pll-e { + compatible = "nvidia,tegra30-plle"; + clocks = <&tegra_car TEGRA30_CLK_PLL_E>; + power-domains = <&pd_core>; + operating-points-v2 = <&pll_e_dvfs_opp_table>; + }; + + pll-m { + compatible = "nvidia,tegra30-pllm"; + clocks = <&tegra_car TEGRA30_CLK_PLL_M>; + power-domains = <&pd_core>; + operating-points-v2 = <&pll_m_dvfs_opp_table>; + }; }; flow-controller@60007000 { @@ -468,6 +524,8 @@ reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; iommus = <&mc TEGRA_SWGROUP_VDE>; + power-domains = <&pd_vde>; + operating-points-v2 = <&vde_dvfs_opp_table>; }; apbmisc@70000800 { @@ -565,6 +623,8 @@ clock-names = "gmi"; resets = <&tegra_car 42>; reset-names = "gmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&nor_dvfs_opp_table>; status = "disabled"; }; @@ -575,6 +635,8 @@ clocks = <&tegra_car TEGRA30_CLK_PWM>; resets = <&tegra_car 17>; reset-names = "pwm"; + power-domains = <&pd_core>; + operating-points-v2 = <&pwm_dvfs_opp_table>; status = "disabled"; }; @@ -676,6 +738,8 @@ reset-names = "spi"; dmas = <&apbdma 15>, <&apbdma 15>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc1_dvfs_opp_table>; status = "disabled"; }; @@ -690,6 +754,8 @@ reset-names = "spi"; dmas = <&apbdma 16>, <&apbdma 16>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc2_dvfs_opp_table>; status = "disabled"; }; @@ -704,6 +770,8 @@ reset-names = "spi"; dmas = <&apbdma 17>, <&apbdma 17>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc3_dvfs_opp_table>; status = "disabled"; }; @@ -718,6 +786,8 @@ reset-names = "spi"; dmas = <&apbdma 18>, <&apbdma 18>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc4_dvfs_opp_table>; status = "disabled"; }; @@ -732,6 +802,8 @@ reset-names = "spi"; dmas = <&apbdma 27>, <&apbdma 27>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc5_dvfs_opp_table>; status = "disabled"; }; @@ -746,6 +818,8 @@ reset-names = "spi"; dmas = <&apbdma 28>, <&apbdma 28>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc6_dvfs_opp_table>; status = "disabled"; }; @@ -765,6 +839,72 @@ clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; + + pd_core: core-domain { + #power-domain-cells = <0>; + operating-points-v2 = <&core_opp_table>; + }; + + powergates { + pd_3d0: td { + clocks = <&tegra_car TEGRA30_CLK_GR3D>; + resets = <&mc TEGRA30_MC_RESET_3D>, + <&tegra_car TEGRA30_CLK_GR3D>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_3d1: td2 { + clocks = <&tegra_car TEGRA30_CLK_GR3D2>; + resets = <&mc TEGRA30_MC_RESET_3D2>, + <&tegra_car TEGRA30_CLK_GR3D2>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA30_CLK_ISP>, + <&tegra_car TEGRA30_CLK_VI>, + <&tegra_car TEGRA30_CLK_CSI>; + resets = <&mc TEGRA30_MC_RESET_ISP>, + <&mc TEGRA30_MC_RESET_VI>, + <&tegra_car TEGRA30_CLK_ISP>, + <&tegra_car 20 /* VI */>, + <&tegra_car TEGRA30_CLK_CSI>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_vde: vdec { + clocks = <&tegra_car TEGRA30_CLK_VDE>; + resets = <&mc TEGRA30_MC_RESET_VDE>, + <&tegra_car TEGRA30_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_mpe: mpe { + clocks = <&tegra_car TEGRA30_CLK_MPE>; + resets = <&mc TEGRA30_MC_RESET_MPE>, + <&tegra_car TEGRA30_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_heg: heg { + clocks = <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + resets = <&mc TEGRA30_MC_RESET_2D>, + <&mc TEGRA30_MC_RESET_EPP>, + <&mc TEGRA30_MC_RESET_HC>, + <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; }; mc: memory-controller@7000f000 { @@ -785,6 +925,7 @@ reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_EMC>; + power-domains = <&pd_core>; nvidia,memory-controller = <&mc>; operating-points-v2 = <&emc_icc_dvfs_opp_table>; @@ -799,6 +940,8 @@ clock-names = "fuse"; resets = <&tegra_car 39>; reset-names = "fuse"; + power-domains = <&pd_core>; + operating-points-v2 = <&fuse_burn_dvfs_opp_table>; }; tsensor: tsensor@70014000 { @@ -921,6 +1064,8 @@ clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; status = "disabled"; }; @@ -943,6 +1088,8 @@ clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; status = "disabled"; }; @@ -967,6 +1114,8 @@ reset-names = "usb"; nvidia,needs-double-reset; nvidia,phy = <&phy1>; + power-domains = <&pd_core>; + operating-points-v2 = <&usbd_dvfs_opp_table>; status = "disabled"; }; @@ -1008,6 +1157,8 @@ resets = <&tegra_car 58>; reset-names = "usb"; nvidia,phy = <&phy2>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb2_dvfs_opp_table>; status = "disabled"; }; @@ -1048,6 +1199,8 @@ resets = <&tegra_car 59>; reset-names = "usb"; nvidia,phy = <&phy3>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb3_dvfs_opp_table>; status = "disabled"; }; From 1caf3ef4c0febbfe3180da3a57e53ebfa4a0fa3b Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:45 +0300 Subject: [PATCH 506/574] ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x Memory access must be blocked before hardware reset is asserted and before power is gated, otherwise a serious hardware fault is inevitable. Add reset for memory clients to the GR2D, GR3D and Host1x nodes. Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 45fe111705af..4068952cc6c0 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -40,8 +40,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA20_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; + reset-names = "host1x", "mc"; power-domains = <&pd_core>; operating-points-v2 = <&host1x_dvfs_opp_table>; @@ -98,8 +98,8 @@ reg = <0x54140000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; + resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; + reset-names = "2d", "mc"; power-domains = <&pd_core>; operating-points-v2 = <&gr2d_dvfs_opp_table>; }; @@ -108,8 +108,8 @@ compatible = "nvidia,tegra20-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; + resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; + reset-names = "3d", "mc"; power-domains = <&pd_3d>; operating-points-v2 = <&gr3d_dvfs_opp_table>; }; From 2c16be669291b7be4df37066acc331615f747182 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:46 +0300 Subject: [PATCH 507/574] ARM: tegra: Add Memory Client resets to Tegra30 GR2D, GR3D and Host1x Memory access must be blocked before hardware reset is asserted and before power is gated, otherwise a serious hardware fault is inevitable. Add reset for memory clients to the GR2D, GR3D and Host1x nodes. Tested-by: Peter Geis # Ouya T30 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 83095a467b35..b0160883336f 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -123,8 +123,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA30_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>; + reset-names = "host1x", "mc"; iommus = <&mc TEGRA_SWGROUP_HC>; power-domains = <&pd_heg>; operating-points-v2 = <&host1x_dvfs_opp_table>; @@ -190,8 +190,8 @@ reg = <0x54140000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; + resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>; + reset-names = "2d", "mc"; power-domains = <&pd_heg>; operating-points-v2 = <&gr2d_dvfs_opp_table>; @@ -205,8 +205,10 @@ <&tegra_car TEGRA30_CLK_GR3D2>; clock-names = "3d", "3d2"; resets = <&tegra_car 24>, - <&tegra_car 98>; - reset-names = "3d", "3d2"; + <&tegra_car 98>, + <&mc TEGRA30_MC_RESET_3D>, + <&mc TEGRA30_MC_RESET_3D2>; + reset-names = "3d", "3d2", "mc", "mc2"; power-domains = <&pd_3d0>, <&pd_3d1>; power-domain-names = "3d0", "3d1"; operating-points-v2 = <&gr3d_dvfs_opp_table>; From 279e7aa30424ea900d34ef3a540e2f26a930353d Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:47 +0300 Subject: [PATCH 508/574] ARM: tegra20/30: Disable unused host1x hardware MPE, VI, EPP and ISP were never used and we don't have drivers for them. Since these modules are enabled by default in a device-tree, a device is created for them, blocking voltage scaling because there is no driver to bind, and thus, state of PMC driver is never synced. Disable them. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 4 ++++ arch/arm/boot/dts/tegra30.dtsi | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 4068952cc6c0..c8f2061b927f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -59,6 +59,7 @@ reset-names = "mpe"; power-domains = <&pd_mpe>; operating-points-v2 = <&mpe_dvfs_opp_table>; + status = "disabled"; }; vi@54080000 { @@ -70,6 +71,7 @@ reset-names = "vi"; power-domains = <&pd_venc>; operating-points-v2 = <&vi_dvfs_opp_table>; + status = "disabled"; }; epp@540c0000 { @@ -81,6 +83,7 @@ reset-names = "epp"; power-domains = <&pd_core>; operating-points-v2 = <&epp_dvfs_opp_table>; + status = "disabled"; }; isp@54100000 { @@ -91,6 +94,7 @@ resets = <&tegra_car 23>; reset-names = "isp"; power-domains = <&pd_venc>; + status = "disabled"; }; gr2d@54140000 { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index b0160883336f..dc1f86309672 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -145,6 +145,8 @@ operating-points-v2 = <&mpe_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_MPE>; + + status = "disabled"; }; vi@54080000 { @@ -158,6 +160,8 @@ operating-points-v2 = <&vi_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_VI>; + + status = "disabled"; }; epp@540c0000 { @@ -171,6 +175,8 @@ operating-points-v2 = <&epp_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_EPP>; + + status = "disabled"; }; isp@54100000 { @@ -183,6 +189,8 @@ power-domains = <&pd_venc>; iommus = <&mc TEGRA_SWGROUP_ISP>; + + status = "disabled"; }; gr2d@54140000 { From dcbc40848de4f07a0c92a348a57d078e881292c9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:22 +0300 Subject: [PATCH 509/574] ARM: tegra: Add S/PDIF node to Tegra20 device-tree Add S/PDIF node to Tegra20 device-tree. It's needed for enabling HDMI audio support. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index c8f2061b927f..2d2f446373b2 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -189,6 +189,7 @@ reset-names = "hdmi"; power-domains = <&pd_core>; operating-points-v2 = <&hdmi_dvfs_opp_table>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -388,6 +389,23 @@ status = "disabled"; }; + tegra_spdif: spdif@70002400 { + compatible = "nvidia,tegra20-spdif"; + reg = <0x70002400 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>, + <&tegra_car TEGRA20_CLK_SPDIF_IN>; + clock-names = "out", "in"; + resets = <&tegra_car 10>; + dmas = <&apbdma 3>, <&apbdma 3>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>; + }; + tegra_i2s1: i2s@70002800 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; From dd2cac867a786cb13821f98afd6730761ebc0773 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:23 +0300 Subject: [PATCH 510/574] ARM: tegra: Add HDMI audio graph to Tegra20 device-tree Add HDMI audio graph to Tegra20 device-tree to enable HDMI audio on Tegra20 devices. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 2d2f446373b2..1bf5bd5efd93 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -178,7 +178,7 @@ }; }; - hdmi@54280000 { + tegra_hdmi: hdmi@54280000 { compatible = "nvidia,tegra20-hdmi"; reg = <0x54280000 0x00040000>; interrupts = ; @@ -1040,4 +1040,24 @@ interrupt-affinity = <&{/cpus/cpu@0}>, <&{/cpus/cpu@1}>; }; + + sound-hdmi { + compatible = "simple-audio-card"; + simple-audio-card,name = "NVIDIA Tegra20 HDMI"; + + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + + cpu { + sound-dai = <&tegra_spdif>; + }; + + codec { + sound-dai = <&tegra_hdmi>; + }; + }; + }; }; From 7a53acabf80fc7b3462c52da4eb04daa213c7619 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:24 +0300 Subject: [PATCH 511/574] ARM: tegra: acer-a500: Enable S/PDIF and HDMI audio Enable S/PDIF controller to enable HDMI audio support on Acer A500. Use nvidia,fixed-parent-rate property that prevents audio rate conflict between S/PDIF and I2S. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 4aa0eb0c50fe..a170a4ba36c1 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -376,8 +376,16 @@ }; }; + tegra_spdif: spdif@70002400 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + tegra_i2s1: i2s@70002800 { status = "okay"; + + nvidia,fixed-parent-rate; }; uartb: serial@70006040 { From 919be27fd0046ed2554f1ff9cbd49d3798446cb5 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:25 +0300 Subject: [PATCH 512/574] ARM: tegra: paz00: Enable S/PDIF and HDMI audio Enable S/PDIF controller to enable HDMI audio support on Toshiba AC100. Use nvidia,fixed-parent-rate property that prevents audio rate conflict between S/PDIF and I2S. Tested-by: Agneli Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-paz00.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index fe1bffedc266..d53a175dc17a 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -264,8 +264,16 @@ }; }; + spdif@70002400 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + i2s@70002800 { status = "okay"; + + nvidia,fixed-parent-rate; }; serial@70006000 { From 9ca9a608a787f0f67adea8757fad86d6632c6232 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 26 Jul 2018 17:40:25 +0200 Subject: [PATCH 513/574] ARM: tegra: Add back gpio-ranges properties The properties have been commented out to prevent a regression a while ago. The first regression should be resolved by commit 44af7927316e ("spi: Map SPI OF client IRQ at probe time"). The second regression is probably addressed by commit 494fd7b7ad10 ("PM / core: fix deferred probe breaking suspend resume order") and/or maybe others. Readd the gpio-ranges properties to see whether regressions still get reported. This reverts commit 4f1d841475e1 ("ARM: tegra: Comment out gpio-ranges properties"). Signed-off-by: Stefan Agner Reviewed-by: Dmitry Osipenko Tested-by: Dmitry Osipenko [treding@nvidia.com: drop redundant gpio-ranges from Ouya DTS file] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 2 -- arch/arm/boot/dts/tegra124.dtsi | 2 -- arch/arm/boot/dts/tegra20.dtsi | 2 -- arch/arm/boot/dts/tegra30-ouya.dts | 4 ---- arch/arm/boot/dts/tegra30.dtsi | 2 -- 5 files changed, 12 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index ae1be90a9385..f20be4ca16a1 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -261,9 +261,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; - /* gpio-ranges = <&pinmux 0 0 246>; - */ }; vde@6001a000 { diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index e87da6c24f7c..ada152b50ade 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -308,9 +308,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; - /* gpio-ranges = <&pinmux 0 0 251>; - */ }; apbdma: dma@60020000 { diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 1bf5bd5efd93..62bf0b306472 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -328,9 +328,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; - /* gpio-ranges = <&pinmux 0 0 224>; - */ }; vde@6001a000 { diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index e604ad08a2c2..a5cfbab5f565 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -68,10 +68,6 @@ }; }; - gpio: gpio@6000d000 { - gpio-ranges = <&pinmux 0 0 248>; - }; - pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index dc1f86309672..9dab8d2c158a 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -507,9 +507,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; - /* gpio-ranges = <&pinmux 0 0 248>; - */ }; vde@6001a000 { From 3951cc6bae4cd252a2efec5bad5d30265d525e0f Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 16 Dec 2021 09:41:07 +0100 Subject: [PATCH 514/574] ARM: dts: imx6: phytec: Add PEB-WLBT-05 support The PEB-WLBT-05 is equipped with a Sterling-LWB radio module, which is capable of Wi-Fi 802.11 b/g/n and Bluetooth 4.2. Signed-off-by: Yunus Bas Signed-off-by: Shawn Guo --- .../boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 + .../boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 + .../boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 + .../dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi | 85 ++++++++++++++++++ .../boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 + .../dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 1 + .../dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi | 90 +++++++++++++++++++ .../dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 1 + .../dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 1 + .../dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi | 19 ++++ 10 files changed, 201 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts index 8165fae2b1d1..d906a7f05aaa 100644 --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts index bbf5097ca974..322f071d972f 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts @@ -10,6 +10,7 @@ #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts index 95051e18324f..3f13726c8058 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi new file mode 100644 index 000000000000..84f884d6e55b --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +#include +#include + +/ { + reg_wl_en: regulator-wl-en { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wl>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + status = "disabled"; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_bt>; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_wl>; + vmmc-supply = <®_wl_en>; + bus-width = <4>; + non-removable; + no-1-8-v; + status = "disabled"; + + brmcf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl_uart3_bt: uart3grp-bt { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0xb0b1 /* BT ENABLE */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0xb0b1 /* DEV WAKEUP */ + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0xb0b1 /* HOST WAKEUP */ + >; + }; + + pinctrl_usdhc3_wl: usdhc3grp-wl { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_wl: wlgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0xb0b1 /* WLAN ENABLE */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts index 343639cb035c..a18266598d39 100644 --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts index bff98e676980..607eddc5030f 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6ul-phytec-segin.dtsi" #include "imx6ul-phytec-segin-peb-eval-01.dtsi" #include "imx6ul-phytec-segin-peb-av-02.dtsi" +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi new file mode 100644 index 000000000000..04477fd4b9a9 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +#include +#include + +/ { + reg_wl_en: regulator-wl-en { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wl>; + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3031 /* BT ENABLE */ + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3031 /* HOST WAKEUP */ + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x3031 /* DEV WAKEUP */ + >; + }; + + pinctrl_uart2_bt: uart2grp-bt { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x17059 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x17059 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x17059 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x17059 + >; + }; + + pinctrl_usdhc2_wl: usdhc2grp-wl { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x10051 + MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10061 + MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x10051 + MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x10051 + MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x10051 + MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x10051 + >; + }; + + pinctrl_wl: wlgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 /* WLAN ENABLE */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt &pinctrl_bt>; + uart-has-rtscts; + status = "disabled"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_wl>; + vmmc-supply = <®_wl_en>; + bus-width = <4>; + non-removable; + no-1-8-v; + status = "disabled"; + + brmcf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts index c8d3eff9ed4b..1d7362b5ac91 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6ull-phytec-segin.dtsi" #include "imx6ull-phytec-segin-peb-eval-01.dtsi" #include "imx6ull-phytec-segin-peb-av-02.dtsi" +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND"; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts index e168494e0a6d..4bcbae024d8d 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6ull-phytec-phycore-som.dtsi" #include "imx6ull-phytec-segin.dtsi" #include "imx6ull-phytec-segin-peb-eval-01.dtsi" +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND"; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi new file mode 100644 index 000000000000..df25814a3371 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi" + +&iomuxc { + /delete-node/ wlgrp; +}; + +&iomuxc_snvs { + pinctrl_wl: wlgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 + >; + }; +}; From e1e06edd94d5b3171401a1435a17251102cc8494 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 14 Dec 2021 18:46:21 -0600 Subject: [PATCH 515/574] dt-bindings: soc: add binding for i.MX8MN DISP blk-ctrl Add the DT binding for the i.MX8MN DISP blk-ctrl. Signed-off-by: Adam Ford Reviewed-by: Rob Herring Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- .../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml new file mode 100644 index 000000000000..fbeaac399c50 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MN DISP blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the display and MIPI CSI + peripherals located in the DISP domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mn-disp-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 5 + maxItems: 5 + + power-domain-names: + items: + - const: bus + - const: isi + - const: lcdif + - const: mipi-dsi + - const: mipi-csi + + clocks: + minItems: 11 + maxItems: 11 + + clock-names: + items: + - const: disp_axi + - const: disp_apb + - const: disp_axi_root + - const: disp_apb_root + - const: lcdif-axi + - const: lcdif-apb + - const: lcdif-pix + - const: dsi-pclk + - const: dsi-ref + - const: csi-aclk + - const: csi-pclk + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + disp_blk_ctl: blk_ctrl@32e28000 { + compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; + reg = <0x32e28000 0x100>; + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, + <&pgc_dispmix>, <&pgc_mipi>, + <&pgc_mipi>; + power-domain-names = "bus", "isi", "lcdif", "mipi-dsi", + "mipi-csi"; + clocks = <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root", + "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk", + "dsi-ref", "csi-aclk", "csi-pclk"; + #power-domain-cells = <1>; + }; From c9b7011768b5dbb68792b4bacad5ae913059ed74 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 16 Dec 2021 16:04:49 +0100 Subject: [PATCH 516/574] arm64: dts: renesas: Fix pin controller node names Align all pin controller node names with the expectations of the DT bindings in Documentation/devicetree/bindings/pinctrl/pinctrl.yaml. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/09a09c8ac9cb1a11b859c1ab9d9eae84cfefb1bb.1639666967.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 2 +- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index f89bcc698420..1e7ed12ebc87 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -87,7 +87,7 @@ status = "disabled"; }; - pfc: pin-controller@e6050000 { + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a779a0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index cdf2adea4b10..19287cccb1f0 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -633,7 +633,7 @@ status = "disabled"; }; - pinctrl: pin-controller@11030000 { + pinctrl: pinctrl@11030000 { compatible = "renesas,r9a07g044-pinctrl"; reg = <0 0x11030000 0 0x10000>; gpio-controller; From b59e11495b1a0e94d6357ce5df54e24ecbeb8319 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 17 Dec 2021 14:51:51 +0100 Subject: [PATCH 517/574] ARM: tegra: Add memory client hotflush resets on Tegra114 Add the host1x, gr2d and gr3d memory client hotflush resets on Tegra114. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index f20be4ca16a1..09996acad639 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -38,8 +38,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA114_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>; + reset-names = "host1x", "mc"; iommus = <&mc TEGRA_SWGROUP_HC>; #address-cells = <1>; @@ -52,8 +52,8 @@ reg = <0x54140000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; + resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; + reset-names = "2d", "mc"; iommus = <&mc TEGRA_SWGROUP_G2>; }; @@ -62,8 +62,8 @@ compatible = "nvidia,tegra114-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; + resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; + reset-names = "3d", "mc"; iommus = <&mc TEGRA_SWGROUP_NV>; }; From bd048487af68a9782ebccc3af6606e9e0d7d9f8b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 17 Dec 2021 14:52:37 +0100 Subject: [PATCH 518/574] ARM: tegra: Add host1x hotflush reset on Tegra124 Add the host1x memory client hotflush reset on Tegra124. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index ada152b50ade..a9ab548781e1 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -94,8 +94,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA124_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA124_MC_RESET_HC>; + reset-names = "host1x", "mc"; iommus = <&mc TEGRA_SWGROUP_HC>; #address-cells = <2>; From e109c0acb835f81ef228c78d7ae76bbcf9470e20 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:25 +0100 Subject: [PATCH 519/574] dt-bindings: mmc: tegra: Convert to json-schema Convert the NVIDIA Tegra SDHCI bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/mmc/nvidia,tegra20-sdhci.txt | 143 -------- .../bindings/mmc/nvidia,tegra20-sdhci.yaml | 311 ++++++++++++++++++ 2 files changed, 311 insertions(+), 143 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt create mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt deleted file mode 100644 index 96c0b1440c9c..000000000000 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ /dev/null @@ -1,143 +0,0 @@ -* NVIDIA Tegra Secure Digital Host Controller - -This controller on Tegra family SoCs provides an interface for MMC, SD, -and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the sdhci-tegra driver. - -Required properties: -- compatible : should be one of: - - "nvidia,tegra20-sdhci": for Tegra20 - - "nvidia,tegra30-sdhci": for Tegra30 - - "nvidia,tegra114-sdhci": for Tegra114 - - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132 - - "nvidia,tegra210-sdhci": for Tegra210 - - "nvidia,tegra186-sdhci": for Tegra186 - - "nvidia,tegra194-sdhci": for Tegra194 -- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries. - One for the module clock and one for the timeout clock. - For all other Tegra devices, must contain a single entry for - the module clock. See ../clocks/clock-bindings.txt for details. -- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the - strings 'sdhci' and 'tmclk' to represent the module and - the timeout clocks, respectively. - For all other Tegra devices must contain the string 'sdhci' - to represent the module clock. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - sdhci - -Optional properties: -- power-gpios : Specify GPIOs for power control - -Example: - -sdhci@c8000200 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000200 0x200>; - interrupts = <47>; - clocks = <&tegra_car 14>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 155 0>; /* gpio PT3 */ - bus-width = <8>; -}; - -Optional properties for Tegra210, Tegra186 and Tegra194: -- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage - configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8" - for controllers supporting multiple voltage levels. The order of names - should correspond to the pin configuration states in pinctrl-0 and - pinctrl-1. -- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for - Tegra210 where pad config registers are in the pinmux register domain - for pull-up-strength and pull-down-strength values configuration when - using pads at 3V3 and 1V8 levels. -- nvidia,only-1-8-v : The presence of this property indicates that the - controller operates at a 1.8 V fixed I/O voltage. -- nvidia,pad-autocal-pull-up-offset-3v3, - nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength - calibration offsets for 3.3 V signaling modes. -- nvidia,pad-autocal-pull-up-offset-1v8, - nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength - calibration offsets for 1.8 V signaling modes. -- nvidia,pad-autocal-pull-up-offset-3v3-timeout, - nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive - strength used as a fallback in case the automatic calibration times - out on a 3.3 V signaling mode. -- nvidia,pad-autocal-pull-up-offset-1v8-timeout, - nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive - strength used as a fallback in case the automatic calibration times - out on a 1.8 V signaling mode. -- nvidia,pad-autocal-pull-up-offset-sdr104, - nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength - calibration offsets for SDR104 mode. -- nvidia,pad-autocal-pull-up-offset-hs400, - nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength - calibration offsets for HS400 mode. -- nvidia,default-tap : Specify the default inbound sampling clock - trimmer value for non-tunable modes. -- nvidia,default-trim : Specify the default outbound clock trimmer - value. -- nvidia,dqs-trim : Specify DQS trim value for HS400 timing - - Notes on the pad calibration pull up and pulldown offset values: - - The property values are drive codes which are programmed into the - PD_OFFSET and PU_OFFSET sections of the - SDHCI_TEGRA_AUTO_CAL_CONFIG register. - - A higher value corresponds to higher drive strength. Please refer - to the reference manual of the SoC for correct values. - - The SDR104 and HS400 timing specific values are used in - corresponding modes if specified. - - Notes on tap and trim values: - - The values are used for compensating trace length differences - by adjusting the sampling point. - - The values are programmed to the Vendor Clock Control Register. - Please refer to the reference manual of the SoC for correct - values. - - The DQS trim values are only used on controllers which support - HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports - HS400. - -Example: -sdhci@700b0000 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; - nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; - status = "disabled"; -}; - -sdhci@700b0000 { - compatible = "nvidia,tegra210-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, - <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; - clock-names = "sdhci", "tmclk"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; - nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; - status = "disabled"; -}; diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml new file mode 100644 index 000000000000..f7a9fcc6bbbd --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -0,0 +1,311 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Secure Digital Host Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + This controller on Tegra family SoCs provides an interface for MMC, SD, and + SDIO types of memory cards. + + This file documents differences between the core properties described by + mmc-controller.yaml and the properties for the Tegra SDHCI controller. + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-sdhci + - nvidia,tegra30-sdhci + - nvidia,tegra114-sdhci + - nvidia,tegra124-sdhci + - nvidia,tegra210-sdhci + - nvidia,tegra186-sdhci + - nvidia,tegra194-sdhci + + - items: + - const: nvidia,tegra132-sdhci + - const: nvidia,tegra124-sdhci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + assigned-clocks: true + assigned-clock-parents: true + assigned-clock-rates: true + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + resets: + items: + - description: module reset + + reset-names: + items: + - const: sdhci + + power-gpios: + description: specify GPIOs for power control + maxItems: 1 + + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the core power domain + + nvidia,default-tap: + description: Specify the default inbound sampling clock trimmer value for + non-tunable modes. + + The values are used for compensating trace length differences by + adjusting the sampling point. The values are programmed to the Vendor + Clock Control Register. Please refer to the reference manual of the SoC + for correct values. + + The DQS trim values are only used on controllers which support HS400 + timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,default-trim: + description: Specify the default outbound clock trimmer value. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,dqs-trim: + description: Specify DQS trim value for HS400 timing. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-1v8: + description: Specify drive strength calibration offsets for 1.8 V + signaling modes. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-1v8-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 1.8 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-3v3: + description: Specify drive strength calibration offsets for 3.3 V + signaling modes. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-3v3-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 3.3 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-sdr104: + description: Specify drive strength calibration offsets for SDR104 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-hs400: + description: Specify drive strength calibration offsets for HS400 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-1v8: + description: Specify drive strength calibration offsets for 1.8 V + signaling modes. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-1v8-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 1.8 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-3v3: + description: Specify drive strength calibration offsets for 3.3 V + signaling modes. + + The property values are drive codes which are programmed into the + PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG + register. A higher value corresponds to higher drive strength. Please + refer to the reference manual of the SoC for correct values. The SDR104 + and HS400 timing specific values are used in corresponding modes if + specified. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-3v3-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 3.3 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-sdr104: + description: Specify drive strength calibration offsets for SDR104 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-hs400: + description: Specify drive strength calibration offsets for HS400 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,only-1-8v: + description: The presence of this property indicates that the controller + operates at a 1.8 V fixed I/O voltage. + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - reset-names + +allOf: + - $ref: "mmc-controller.yaml" + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-sdhci + - nvidia,tegra30-sdhci + - nvidia,tegra114-sdhci + - nvidia,tegra124-sdhci + clocks: + items: + - description: module clock + minItems: 1 + maxItems: 1 + else: + properties: + clocks: + items: + - description: module clock + - description: timeout clock + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: sdhci + - const: tmclk + minItems: 2 + maxItems: 2 + required: + - clock-names + + - if: + properties: + compatible: + contains: + const: nvidia,tegra210-sdhci + then: + properties: + pinctrl-names: + oneOf: + - items: + - const: sdmmc-3v3 + description: pad configuration for 3.3 V + - const: sdmmc-1v8 + description: pad configuration for 1.8 V + - const: sdmmc-3v3-drv + description: pull-up/down configuration for 3.3 V + - const: sdmmc-1v8-drv + description: pull-up/down configuration for 1.8 V + - items: + - const: sdmmc-3v3-drv + description: pull-up/down configuration for 3.3 V + - const: sdmmc-1v8-drv + description: pull-up/down configuration for 1.8 V + - items: + - const: sdmmc-1v8-drv + description: pull-up/down configuration for 1.8 V + required: + - clock-names + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-sdhci + - nvidia,tegra194-sdhci + then: + properties: + pinctrl-names: + items: + - const: sdmmc-3v3 + description: pad configuration for 3.3 V + - const: sdmmc-1v8 + description: pad configuration for 1.8 V + required: + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + mmc@c8000200 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000200 0x200>; + interrupts = <47>; + clocks = <&tegra_car 14>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + bus-width = <8>; + }; + + - | + #include + #include + + mmc@700b0000 { + compatible = "nvidia,tegra210-sdhci"; + reg = <0x700b0000 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, + <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; + clock-names = "sdhci", "tmclk"; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", + "sdmmc-3v3-drv", "sdmmc-1v8-drv"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + pinctrl-2 = <&sdmmc1_3v3_drv>; + pinctrl-3 = <&sdmmc1_1v8_drv>; + nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; + nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; + nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; + nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; + nvidia,default-tap = <0x2>; + nvidia,default-trim = <0x4>; + assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, + <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, + <&tegra_car TEGRA210_CLK_PLL_C4>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; + }; From 068cf93f900267fb4aaf2b14ff369f80aa4b5406 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:26 +0100 Subject: [PATCH 520/574] dt-bindings: mailbox: tegra: Convert to json-schema Convert the NVIDIA Tegra HSP bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/mailbox/nvidia,tegra186-hsp.txt | 72 ------------ .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 111 ++++++++++++++++++ 2 files changed, 111 insertions(+), 72 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt deleted file mode 100644 index ff3eafc5a882..000000000000 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt +++ /dev/null @@ -1,72 +0,0 @@ -NVIDIA Tegra Hardware Synchronization Primitives (HSP) - -The HSP modules are used for the processors to share resources and communicate -together. It provides a set of hardware synchronization primitives for -interprocessor communication. So the interprocessor communication (IPC) -protocols can use hardware synchronization primitives, when operating between -two processors not in an SMP relationship. - -The features that HSP supported are shared mailboxes, shared semaphores, -arbitrated semaphores and doorbells. - -Required properties: -- name : Should be hsp -- compatible - Array of strings. - one of: - - "nvidia,tegra186-hsp" - - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp" -- reg : Offset and length of the register set for the device. -- interrupt-names - Array of strings. - Contains a list of names for the interrupts described by the interrupt - property. May contain the following entries, in any order: - - "doorbell" - - "sharedN", where 'N' is a number from zero up to the number of - external interrupts supported by the HSP instance minus one. - Users of this binding MUST look up entries in the interrupt property - by name, using this interrupt-names property to do so. -- interrupts - Array of interrupt specifiers. - Must contain one entry per entry in the interrupt-names property, - in a matching order. -- #mbox-cells : Should be 2. - -The mbox specifier of the "mboxes" property in the client node should contain -two cells. The first cell determines the HSP type and the second cell is used -to identify the mailbox that the client is going to use. - -For doorbells, the second cell specifies the index of the doorbell to use. - -For shared mailboxes, the second cell is composed of two fields: -- bits 31..24: - A bit mask of flags that further specify how the shared mailbox will be - used. Valid flags are: - - bit 31: - Defines the direction of the mailbox. If set, the mailbox will be used - as a producer (i.e. used to send data). If cleared, the mailbox is the - consumer of data sent by a producer. - -- bits 23.. 0: - The index of the shared mailbox to use. The number of available mailboxes - may vary by instance of the HSP block and SoC generation. - -The following file contains definitions that can be used to construct mailbox -specifiers: - - - -Example: - -hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra186-hsp"; - reg = <0x0 0x03c00000 0x0 0xa0000>; - interrupts = ; - interrupt-names = "doorbell"; - #mbox-cells = <2>; -}; - -client { - ... - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml new file mode 100644 index 000000000000..c43fc4c56f77 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Hardware Synchronization Primitives (HSP) + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The HSP modules are used for the processors to share resources and + communicate together. It provides a set of hardware synchronization + primitives for interprocessor communication. So the interprocessor + communication (IPC) protocols can use hardware synchronization + primitives, when operating between two processors not in an SMP + relationship. + + The features that HSP supported are shared mailboxes, shared + semaphores, arbitrated semaphores and doorbells. + + The mbox specifier of the "mboxes" property in the client node should + contain two cells. The first cell determines the HSP type and the + second cell is used to identify the mailbox that the client is going + to use. + + For doorbells, the second cell specifies the index of the doorbell to + use. + + For shared mailboxes, the second cell is composed of two fields: + - bits 31..24: + A bit mask of flags that further specify how the shared mailbox + will be used. Valid flags are: + - bit 31: + Defines the direction of the mailbox. If set, the mailbox + will be used as a producer (i.e. used to send data). If + cleared, the mailbox is the consumer of data sent by a + producer. + + - bits 23..0: + The index of the shared mailbox to use. The number of available + mailboxes may vary by instance of the HSP block and SoC + generation. + + The following file contains definitions that can be used to + construct mailbox specifiers: + + + +properties: + $nodename: + pattern: "^hsp@[0-9a-f]+$" + + compatible: + oneOf: + - const: nvidia,tegra186-hsp + - const: nvidia,tegra194-hsp + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 9 + + interrupt-names: + oneOf: + # shared interrupts are optional + - items: + - const: doorbell + + - items: + - const: doorbell + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + + - items: + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + + "#mbox-cells": + const: 2 + +additionalProperties: false + +examples: + - | + #include + #include + + hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x03c00000 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <2>; + }; + + client { + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>; + }; From 0637af949a8c75d171a635eb0e41a9104f23bb6b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:27 +0100 Subject: [PATCH 521/574] dt-bindings: mailbox: tegra: Document Tegra234 HSP Add the compatible string for the HSP block found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml index c43fc4c56f77..9f7a7296b57f 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -57,6 +57,9 @@ properties: oneOf: - const: nvidia,tegra186-hsp - const: nvidia,tegra194-hsp + - items: + - const: nvidia,tegra234-hsp + - const: nvidia,tegra194-hsp reg: maxItems: 1 From 2f9df754d0c20da8a2f64c461c4567a38b289ef9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:28 +0100 Subject: [PATCH 522/574] dt-bindings: rtc: tegra: Convert to json-schema Convert the NVIDIA Tegra RTC bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/rtc/nvidia,tegra20-rtc.txt | 24 -------- .../bindings/rtc/nvidia,tegra20-rtc.yaml | 60 +++++++++++++++++++ 2 files changed, 60 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt create mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt deleted file mode 100644 index b7d98ed3e098..000000000000 --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt +++ /dev/null @@ -1,24 +0,0 @@ -NVIDIA Tegra20 real-time clock - -The Tegra RTC maintains seconds and milliseconds counters, and five alarm -registers. The alarms and other interrupts may wake the system from low-power -state. - -Required properties: - -- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise, - must contain '"nvidia,-rtc", "nvidia,tegra20-rtc"', where - can be tegra30, tegra114, tegra124, or tegra132. -- reg : Specifies base physical address and size of the registers. -- interrupts : A single interrupt specifier. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - -Example: - -timer { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; -}; diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml new file mode 100644 index 000000000000..94266de73cb9 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra real-time clock + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The Tegra RTC maintains seconds and milliseconds counters, and five + alarm registers. The alarms and other interrupts may wake the system + from low-power state. + +properties: + compatible: + oneOf: + - const: nvidia,tegra20-rtc + - items: + - enum: + - nvidia,tegra30-rtc + - nvidia,tegra114-rtc + - nvidia,tegra124-rtc + - nvidia,tegra210-rtc + - nvidia,tegra186-rtc + - nvidia,tegra194-rtc + - const: nvidia,tegra20-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rtc + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + timer@7000e000 { + compatible = "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <0 2 0x04>; + clocks = <&tegra_car 4>; + }; From aa8f488fd616e23ce03311f2365ab07eab9bd350 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:29 +0100 Subject: [PATCH 523/574] dt-bindings: rtc: tegra: Document Tegra234 RTC Add the compatible string for the RTC block found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml index 94266de73cb9..17d6280e5515 100644 --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml @@ -27,6 +27,7 @@ properties: - nvidia,tegra210-rtc - nvidia,tegra186-rtc - nvidia,tegra194-rtc + - nvidia,tegra234-rtc - const: nvidia,tegra20-rtc reg: From 25388844f92f0560961cb7dd374bcdf343d5b1f9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:30 +0100 Subject: [PATCH 524/574] dt-bindings: fuse: tegra: Convert to json-schema Convert the NVIDIA Tegra FUSE bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/fuse/nvidia,tegra20-fuse.txt | 42 --------- .../bindings/fuse/nvidia,tegra20-fuse.yaml | 88 +++++++++++++++++++ 2 files changed, 88 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt create mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt deleted file mode 100644 index b109911669e4..000000000000 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt +++ /dev/null @@ -1,42 +0,0 @@ -NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block. - -Required properties: -- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30, - must contain "nvidia,tegra30-efuse". For Tegra114, must contain - "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse". - For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse". - For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain - "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse". - For Tegra234 must contain "nvidia,tegra234-efuse". - Details: - nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data - due to a hardware bug. Tegra20 also lacks certain information which is - available in later generations such as fab code, lot code, wafer id,.. - nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse: - The differences between these SoCs are the size of the efuse array, - the location of the spare (OEM programmable) bits and the location of - the speedo data. -- reg: Should contain 1 entry: the entry gives the physical address and length - of the fuse registers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - fuse -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - fuse - -Example: - - fuse@7000f800 { - compatible = "nvidia,tegra20-efuse"; - reg = <0x7000f800 0x400>, - <0x70000000 0x400>; - clocks = <&tegra_car TEGRA20_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml new file mode 100644 index 000000000000..2bd901dda976 --- /dev/null +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra FUSE block + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-efuse + - nvidia,tegra30-efuse + - nvidia,tegra114-efuse + - nvidia,tegra124-efuse + - nvidia,tegra210-efuse + - nvidia,tegra186-efuse + - nvidia,tegra194-efuse + + - items: + - const: nvidia,tegra132-efuse + - const: nvidia,tegra124-efuse + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: fuse + + resets: + maxItems: 1 + + reset-names: + items: + - const: fuse + + operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the core power domain + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + +if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-efuse + - nvidia,tegra30-efuse + - nvidia,tegra114-efuse + - nvidia,tegra124-efuse + - nvidia,tegra132-efuse + - nvidia,tegra210-efuse +then: + required: + - resets + - reset-names + +examples: + - | + #include + + fuse@7000f800 { + compatible = "nvidia,tegra20-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA20_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; From f8dd779bcb4b5a0f891f82a3f23f337ce82da783 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:31 +0100 Subject: [PATCH 525/574] dt-bindings: fuse: tegra: Document Tegra234 FUSE Add the compatible string for the FUSE block found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml index 2bd901dda976..481901269872 100644 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml @@ -21,6 +21,7 @@ properties: - nvidia,tegra210-efuse - nvidia,tegra186-efuse - nvidia,tegra194-efuse + - nvidia,tegra234-efuse - items: - const: nvidia,tegra132-efuse From d5de8b7608e9e710b18a080b322b11cb40a11efc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:32 +0100 Subject: [PATCH 526/574] dt-bindings: mmc: tegra: Document Tegra234 SDHCI Add the compatible string for the SDHCI block found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml index f7a9fcc6bbbd..ce64b3498378 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -33,6 +33,12 @@ properties: - const: nvidia,tegra132-sdhci - const: nvidia,tegra124-sdhci + - items: + - enum: + - nvidia,tegra194-sdhci + - nvidia,tegra234-sdhci + - const: nvidia,tegra186-sdhci + reg: maxItems: 1 From 96b594d2a0932d1c9ae1c48144a63aabc972222d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:33 +0100 Subject: [PATCH 527/574] dt-bindings: serial: 8250: Document Tegra234 UART Add the compatible string for the UART found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/serial/8250.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index fa767440f281..3bab2f27b970 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -113,9 +113,10 @@ properties: - nvidia,tegra30-uart - nvidia,tegra114-uart - nvidia,tegra124-uart + - nvidia,tegra210-uart - nvidia,tegra186-uart - nvidia,tegra194-uart - - nvidia,tegra210-uart + - nvidia,tegra234-uart - const: nvidia,tegra20-uart reg: From 5cda3b25cb04222988786ebebe346a7655bde05a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:34 +0100 Subject: [PATCH 528/574] dt-bindings: tegra: pmc: Convert to json-schema Convert the NVIDIA Tegra186 (and later) PMC bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../arm/tegra/nvidia,tegra186-pmc.txt | 133 ------------ .../arm/tegra/nvidia,tegra186-pmc.yaml | 198 ++++++++++++++++++ 2 files changed, 198 insertions(+), 133 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt deleted file mode 100644 index 576462fae27f..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ /dev/null @@ -1,133 +0,0 @@ -NVIDIA Tegra Power Management Controller (PMC) - -Required properties: -- compatible: Should contain one of the following: - - "nvidia,tegra186-pmc": for Tegra186 - - "nvidia,tegra194-pmc": for Tegra194 - - "nvidia,tegra234-pmc": for Tegra234 -- reg: Must contain an (offset, length) pair of the register set for each - entry in reg-names. -- reg-names: Must include the following entries: - - "pmc" - - "wake" - - "aotag" - - "scratch" - - "misc" (Only for Tegra194 and later) - -Optional properties: -- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value must be 2. - -Example: - -SoC DTSI: - - pmc@c3600000 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - }; - -Board DTS: - - pmc@c360000 { - nvidia,invert-interrupt; - }; - -== Pad Control == - -On Tegra SoCs a pad is a set of pins which are configured as a group. -The pin grouping is a fixed attribute of the hardware. The PMC can be -used to set pad power state and signaling voltage. A pad can be either -in active or power down mode. The support for power state and signaling -voltage configuration varies depending on the pad in question. 3.3 V and -1.8 V signaling voltages are supported on pins where software -controllable signaling voltage switching is available. - -Pad configurations are described with pin configuration nodes which -are placed under the pmc node and they are referred to by the pinctrl -client properties. For more information see -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. - -The following pads are present on Tegra186: -csia csib dsi mipi-bias -pex-clk-bias pex-clk3 pex-clk2 pex-clk1 -usb0 usb1 usb2 usb-bias -uart audio hsic dbg -hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv -sdmmc4 cam dsib dsic -dsid csic csid csie -dsif spi ufs dmic-hv -edp sdmmc1-hv sdmmc3-hv conn -audio-hv ao-hv - -Required pin configuration properties: - - pins: A list of strings, each of which contains the name of a pad - to be configured. - -Optional pin configuration properties: - - low-power-enable: Configure the pad into power down mode - - low-power-disable: Configure the pad into active mode - - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or - TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. - The values are defined in - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. - -Note: The power state can be configured on all of the above pads except - for ao-hv. Following pads have software configurable signaling - voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv, - ao-hv. - -Pad configuration state example: - pmc: pmc@7000e400 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - - ... - - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = ; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1-hv"; - power-source = ; - }; - - hdmi_off: hdmi-off { - pins = "hdmi"; - low-power-enable; - } - - hdmi_on: hdmi-on { - pins = "hdmi"; - low-power-disable; - } - }; - -Pinctrl client example: - sdmmc1: sdhci@3400000 { - ... - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - }; - - ... - - sor0: sor@15540000 { - ... - pinctrl-0 = <&hdmi_off>; - pinctrl-1 = <&hdmi_on>; - pinctrl-names = "hdmi-on", "hdmi-off"; - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml new file mode 100644 index 000000000000..0faa403f68c8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Power Management Controller (PMC) + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + enum: + - nvidia,tegra186-pmc + - nvidia,tegra194-pmc + - nvidia,tegra234-pmc + + reg: + minItems: 4 + maxItems: 5 + + reg-names: + minItems: 4 + items: + - const: pmc + - const: wake + - const: aotag + - const: scratch + - const: misc + + interrupt-controller: true + + "#interrupt-cells": + description: Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + const: 2 + + nvidia,invert-interrupt: + description: If present, inverts the PMU interrupt signal. + $ref: /schemas/types.yaml#/definitions/flag + +if: + properties: + compatible: + contains: + const: nvidia,tegra186-pmc +then: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 +else: + properties: + reg: + minItems: 5 + + reg-names: + minItems: 5 + +patternProperties: + "^[a-z0-9]+-[a-z0-9]+$": + if: + type: object + then: + description: | + These are pad configuration nodes. On Tegra SoCs a pad is a set of + pins which are configured as a group. The pin grouping is a fixed + attribute of the hardware. The PMC can be used to set pad power + state and signaling voltage. A pad can be either in active or + power down mode. The support for power state and signaling voltage + configuration varies depending on the pad in question. 3.3 V and + 1.8 V signaling voltages are supported on pins where software + controllable signaling voltage switching is available. + + Pad configurations are described with pin configuration nodes + which are placed under the pmc node and they are referred to by + the pinctrl client properties. For more information see + + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + + The following pads are present on Tegra186: + + csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, + pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg, + hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib, + dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp, + sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv + + The following pads are present on Tegra194: + + csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, + pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart, + pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12, + soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2, + hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst, + pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif, + spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn, + audio-hv, ao-hv + + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string + description: Must contain the name of the pad(s) to be + configured. + + low-power-enable: + description: Configure the pad into power down mode. + $ref: /schemas/types.yaml#/definitions/flag + + low-power-disable: + description: Configure the pad into active mode. + $ref: /schemas/types.yaml#/definitions/flag + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling + voltages. + + The values are defined in + + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h + + The power state can be configured on all of the above pads + except for ao-hv. Following pads have software configurable + signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, + audio-hv, ao-hv. + + phandle: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +dependencies: + interrupt-controller: ['#interrupt-cells'] + "#interrupt-cells": + required: + - interrupt-controller + +examples: + - | + #include + #include + #include + #include + #include + + pmc@c3600000 { + compatible = "nvidia,tegra186-pmc"; + reg = <0x0c360000 0x10000>, + <0x0c370000 0x10000>, + <0x0c380000 0x10000>, + <0x0c390000 0x10000>; + reg-names = "pmc", "wake", "aotag", "scratch"; + nvidia,invert-interrupt; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = ; + }; + }; + + sdmmc1: mmc@3400000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x03400000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_SDMMC1>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; + resets = <&bpmp TEGRA186_RESET_SDMMC1>; + reset-names = "sdhci"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_SDMMC1>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + }; From d289f9de8b952bac7805c82d3f9dfd6440f62c8c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:35 +0100 Subject: [PATCH 529/574] dt-bindings: firmware: tegra: Convert to json-schema Convert the NVIDIA Tegra186 (and later) BPMP bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../firmware/nvidia,tegra186-bpmp.txt | 107 ---------- .../firmware/nvidia,tegra186-bpmp.yaml | 186 ++++++++++++++++++ 2 files changed, 186 insertions(+), 107 deletions(-) delete mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt deleted file mode 100644 index e44a13bc06ed..000000000000 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt +++ /dev/null @@ -1,107 +0,0 @@ -NVIDIA Tegra Boot and Power Management Processor (BPMP) - -The BPMP is a specific processor in Tegra chip, which is designed for -booting process handling and offloading the power management, clock -management, and reset control tasks from the CPU. The binding document -defines the resources that would be used by the BPMP firmware driver, -which can create the interprocessor communication (IPC) between the CPU -and BPMP. - -Required properties: -- compatible - Array of strings - One of: - - "nvidia,tegra186-bpmp" -- mboxes : The phandle of mailbox controller and the mailbox specifier. -- shmem : List of the phandle of the TX and RX shared memory area that - the IPC between CPU and BPMP is based on. -- #clock-cells : Should be 1. -- #power-domain-cells : Should be 1. -- #reset-cells : Should be 1. - -This node is a mailbox consumer. See the following files for details of -the mailbox subsystem, and the specifiers implemented by the relevant -provider(s): - -- .../mailbox/mailbox.txt -- .../mailbox/nvidia,tegra186-hsp.txt - -This node is a clock, power domain, and reset provider. See the following -files for general documentation of those features, and the specifiers -implemented by this node: - -- .../clock/clock-bindings.txt -- -- ../power/power-domain.yaml -- -- .../reset/reset.txt -- - -The BPMP implements some services which must be represented by separate nodes. -For example, it can provide access to certain I2C controllers, and the I2C -bindings represent each I2C controller as a device tree node. Such nodes should -be nested directly inside the main BPMP node. - -Software can determine whether a child node of the BPMP node represents a device -by checking for a compatible property. Any node with a compatible property -represents a device that can be instantiated. Nodes without a compatible -property may be used to provide configuration information regarding the BPMP -itself, although no such configuration nodes are currently defined by this -binding. - -The BPMP firmware defines no single global name-/numbering-space for such -services. Put another way, the numbering scheme for I2C buses is distinct from -the numbering scheme for any other service the BPMP may provide (e.g. a future -hypothetical SPI bus service). As such, child device nodes will have no reg -property, and the BPMP node will have no #address-cells or #size-cells property. - -The shared memory bindings for BPMP ------------------------------------ - -The shared memory area for the IPC TX and RX between CPU and BPMP are -predefined and work on top of sysram, which is an SRAM inside the chip. - -See ".../sram/sram.txt" for the bindings. - -Example: - -hsp_top0: hsp@3c00000 { - ... - #mbox-cells = <2>; -}; - -sysram@30000000 { - compatible = "nvidia,tegra186-sysram", "mmio-sram"; - reg = <0x0 0x30000000 0x0 0x50000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; - - cpu_bpmp_tx: shmem@4e000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4e000 0x0 0x1000>; - label = "cpu-bpmp-tx"; - pool; - }; - - cpu_bpmp_rx: shmem@4f000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4f000 0x0 0x1000>; - label = "cpu-bpmp-rx"; - pool; - }; -}; - -bpmp { - compatible = "nvidia,tegra186-bpmp"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - - i2c { - compatible = "..."; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml new file mode 100644 index 000000000000..833c07f1685c --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Boot and Power Management Processor (BPMP) + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The BPMP is a specific processor in Tegra chip, which is designed for + booting process handling and offloading the power management, clock + management, and reset control tasks from the CPU. The binding document + defines the resources that would be used by the BPMP firmware driver, + which can create the interprocessor communication (IPC) between the + CPU and BPMP. + + This node is a mailbox consumer. See the following files for details + of the mailbox subsystem, and the specifiers implemented by the + relevant provider(s): + + - .../mailbox/mailbox.txt + - .../mailbox/nvidia,tegra186-hsp.yaml + + This node is a clock, power domain, and reset provider. See the + following files for general documentation of those features, and the + specifiers implemented by this node: + + - .../clock/clock-bindings.txt + - + - ../power/power-domain.yaml + - + - .../reset/reset.txt + - + + The BPMP implements some services which must be represented by + separate nodes. For example, it can provide access to certain I2C + controllers, and the I2C bindings represent each I2C controller as a + device tree node. Such nodes should be nested directly inside the main + BPMP node. + + Software can determine whether a child node of the BPMP node + represents a device by checking for a compatible property. Any node + with a compatible property represents a device that can be + instantiated. Nodes without a compatible property may be used to + provide configuration information regarding the BPMP itself, although + no such configuration nodes are currently defined by this binding. + + The BPMP firmware defines no single global name-/numbering-space for + such services. Put another way, the numbering scheme for I2C buses is + distinct from the numbering scheme for any other service the BPMP may + provide (e.g. a future hypothetical SPI bus service). As such, child + device nodes will have no reg property, and the BPMP node will have no + "#address-cells" or "#size-cells" property. + + The shared memory area for the IPC TX and RX between CPU and BPMP are + predefined and work on top of sysram, which is an SRAM inside the + chip. See ".../sram/sram.yaml" for the bindings. + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra194-bpmp + - nvidia,tegra234-bpmp + - const: nvidia,tegra186-bpmp + - const: nvidia,tegra186-bpmp + + mboxes: + description: A phandle and channel specifier for the mailbox used to + communicate with the BPMP. + maxItems: 1 + + shmem: + description: List of the phandle to the TX and RX shared memory area + that the IPC between CPU and BPMP is based on. + minItems: 2 + maxItems: 2 + + "#clock-cells": + const: 1 + + "#power-domain-cells": + const: 1 + + "#reset-cells": + const: 1 + + interconnects: + items: + - description: memory read client + - description: memory write client + - description: DMA read client + - description: DMA write client + + interconnect-names: + items: + - const: read + - const: write + - const: dma-mem # dma-read + - const: dma-write + + iommus: + maxItems: 1 + + i2c: + type: object + + thermal: + type: object + +additionalProperties: false + +required: + - compatible + - mboxes + - shmem + - "#clock-cells" + - "#power-domain-cells" + - "#reset-cells" + +examples: + - | + #include + #include + #include + + hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x03c00000 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <2>; + }; + + sram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-sram"; + reg = <0x30000000 0x50000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000000 0x50000>; + + cpu_bpmp_tx: sram@4e000 { + reg = <0x4e000 0x1000>; + label = "cpu-bpmp-tx"; + pool; + }; + + cpu_bpmp_rx: sram@4f000 { + reg = <0x4f000 0x1000>; + label = "cpu-bpmp-rx"; + pool; + }; + }; + + bpmp { + compatible = "nvidia,tegra186-bpmp"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; + iommus = <&smmu TEGRA186_SID_BPMP>; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB + TEGRA_HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + #thermal-sensor-cells = <1>; + }; + }; From a12e1b7812ff81236732abf0f361d59c32890f9a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:37 +0100 Subject: [PATCH 530/574] dt-bindings: thermal: tegra186-bpmp: Convert to json-schema Convert the Tegra186 (and later) BPMP thermal device tree bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../thermal/nvidia,tegra186-bpmp-thermal.txt | 33 --------------- .../thermal/nvidia,tegra186-bpmp-thermal.yaml | 42 +++++++++++++++++++ 2 files changed, 42 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt create mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt deleted file mode 100644 index fc87f6aa1b8f..000000000000 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt +++ /dev/null @@ -1,33 +0,0 @@ -NVIDIA Tegra186 BPMP thermal sensor - -In Tegra186, the BPMP (Boot and Power Management Processor) implements an -interface that is used to read system temperatures, including CPU cluster -and GPU temperatures. This binding describes the thermal sensor that is -exposed by BPMP. - -The BPMP thermal node must be located directly inside the main BPMP node. See -../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. - -This node represents a thermal sensor. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details of the -core thermal binding. - -Required properties: -- compatible: - Array of strings. - One of: - - "nvidia,tegra186-bpmp-thermal" - - "nvidia,tegra194-bpmp-thermal" -- #thermal-sensor-cells: Cell for sensor index. - Single-cell integer. - Must be <1>. - -Example: - -bpmp { - ... - - bpmp_thermal: thermal { - compatible = "nvidia,tegra186-bpmp-thermal"; - #thermal-sensor-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml new file mode 100644 index 000000000000..c91fd07e4061 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) BPMP thermal sensor + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + In Tegra186, the BPMP (Boot and Power Management Processor) implements + an interface that is used to read system temperatures, including CPU + cluster and GPU temperatures. This binding describes the thermal + sensor that is exposed by BPMP. + + The BPMP thermal node must be located directly inside the main BPMP + node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the + BPMP binding. + + This node represents a thermal sensor. See + + Documentation/devicetree/bindings/thermal/thermal-sensor.yaml + + for details of the core thermal binding. + +properties: + compatible: + enum: + - nvidia,tegra186-bpmp-thermal + - nvidia,tegra194-bpmp-thermal + + '#thermal-sensor-cells': + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of cells needed in the phandle specifier to + identify a given sensor. Must be 1 and the single cell specifies + the sensor index. + const: 1 + +additionalProperties: false From 8461fe3e443b28dc44773c98c642d094caa1976d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:38 +0100 Subject: [PATCH 531/574] dt-bindings: serial: tegra-tcu: Convert to json-schema Convert the Tegra TCU device tree bindings to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/serial/nvidia,tegra194-tcu.txt | 35 ------------ .../bindings/serial/nvidia,tegra194-tcu.yaml | 56 +++++++++++++++++++ 2 files changed, 56 insertions(+), 35 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt deleted file mode 100644 index 085a8591accd..000000000000 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt +++ /dev/null @@ -1,35 +0,0 @@ -NVIDIA Tegra Combined UART (TCU) - -The TCU is a system for sharing a hardware UART instance among multiple -systems within the Tegra SoC. It is implemented through a mailbox- -based protocol where each "virtual UART" has a pair of mailboxes, one -for transmitting and one for receiving, that is used to communicate -with the hardware implementing the TCU. - -Required properties: -- name : Should be tcu -- compatible - Array of strings - One of: - - "nvidia,tegra194-tcu" -- mbox-names: - "rx" - Mailbox for receiving data from hardware UART - "tx" - Mailbox for transmitting data to hardware UART -- mboxes: Mailboxes corresponding to the mbox-names. - -This node is a mailbox consumer. See the following files for details of -the mailbox subsystem, and the specifiers implemented by the relevant -provider(s): - -- .../mailbox/mailbox.txt -- .../mailbox/nvidia,tegra186-hsp.txt - -Example bindings: ------------------ - -tcu: tcu { - compatible = "nvidia,tegra194-tcu"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, - <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; - mbox-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml new file mode 100644 index 000000000000..7987eca0bb52 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Combined UART (TCU) + +maintainers: + - Thierry Reding + - Jonathan Hunter + +description: + The TCU is a system for sharing a hardware UART instance among multiple + systems within the Tegra SoC. It is implemented through a mailbox- + based protocol where each "virtual UART" has a pair of mailboxes, one + for transmitting and one for receiving, that is used to communicate + with the hardware implementing the TCU. + +properties: + $nodename: + pattern: "^serial(@.*)?$" + + compatible: + const: nvidia,tegra194-tcu + + mbox-names: + items: + - const: rx + - const: tx + + mboxes: + description: | + List of phandles to mailbox channels used for receiving and + transmitting data from and to the hardware UART. + items: + - description: mailbox for receiving data from hardware UART + - description: mailbox for transmitting data to hardware UART + +required: + - compatible + - mbox-names + - mboxes + +additionalProperties: false + +examples: + - | + #include + + tcu: serial { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; + mbox-names = "rx", "tx"; + }; From cd1fe47862c71994390e810182785a4f4d371875 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:39 +0100 Subject: [PATCH 532/574] dt-bindings: serial: Document Tegra234 TCU Add the compatible string for the TCU found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/serial/nvidia,tegra194-tcu.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml index 7987eca0bb52..e2d111b3e0b0 100644 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml @@ -22,7 +22,12 @@ properties: pattern: "^serial(@.*)?$" compatible: - const: nvidia,tegra194-tcu + oneOf: + - const: nvidia,tegra194-tcu + - items: + - enum: + - nvidia,tegra234-tcu + - const: nvidia,tegra194-tcu mbox-names: items: From a90901a5a373b364d1495dbd853d31f391c021a8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 16:55:59 +0100 Subject: [PATCH 533/574] dt-bindings: usb: tegra-xudc: Document interconnects and iommus properties Add the interconnects, interconnect-names and iommus properties to the device tree bindings for the Tegra XUDC controller. These are used to describe the device's paths to and from memory. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/usb/nvidia,tegra-xudc.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index 8428415896ce..a39c76b89484 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -59,6 +59,19 @@ properties: - const: fs_src - const: hs_src + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + power-domains: items: - description: XUSBB(device) power-domain From b58db7135a1279ca77db9444701dbee02fa29fb7 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:45 +0300 Subject: [PATCH 534/574] dt-bindings: ARM: tegra: Document ASUS Transformers Document Tegra20/30/114-based ASUS Transformer Series tablet devices. This group includes EeePad TF101, Prime TF201, Pad TF300T, TF300TG Infinity TF700T, TF701T. Signed-off-by: David Heidelberg Signed-off-by: Anton Bambura Signed-off-by: Svyatoslav Ryhel Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 3bd0920da274..64b7b770a0dc 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -36,6 +36,9 @@ properties: - toradex,colibri_t20-iris - const: toradex,colibri_t20 - const: nvidia,tegra20 + - items: + - const: asus,tf101 + - const: nvidia,tegra20 - items: - const: acer,picasso - const: nvidia,tegra20 @@ -49,6 +52,18 @@ properties: - nvidia,cardhu-a04 - const: nvidia,cardhu - const: nvidia,tegra30 + - items: + - const: asus,tf201 + - const: nvidia,tegra30 + - items: + - const: asus,tf300t + - const: nvidia,tegra30 + - items: + - const: asus,tf300tg + - const: nvidia,tegra30 + - items: + - const: asus,tf700t + - const: nvidia,tegra30 - items: - const: toradex,apalis_t30-eval - const: toradex,apalis_t30 @@ -76,6 +91,7 @@ properties: - const: nvidia,tegra30 - items: - enum: + - asus,tf701t - nvidia,dalmore - nvidia,roth - nvidia,tn7 From f64de71a9383457345ca6cd653c02f5b80a695e3 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 12 Dec 2021 00:13:46 +0300 Subject: [PATCH 535/574] dt-bindings: ARM: tegra: Document Pegatron Chagall Document Pegatron Chagall, which is Tegra30-based tablet device. Acked-by: Rob Herring Signed-off-by: David Heidelberg Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 64b7b770a0dc..49841ca272ee 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -89,6 +89,9 @@ properties: - items: - const: ouya,ouya - const: nvidia,tegra30 + - items: + - const: pegatron,chagall + - const: nvidia,tegra30 - items: - enum: - asus,tf701t From d0e70d13048419913c4723793c9f600acd861b36 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:11 +0300 Subject: [PATCH 536/574] dt-bindings: clock: tegra-car: Document new clock sub-nodes Document sub-nodes which describe Tegra SoC clocks that require a higher voltage of the core power domain in order to operate properly on a higher clock rates. Each node contains a phandle to OPP table and power domain. The root PLLs and system clocks don't have any specific device dedicated to them, clock controller is in charge of managing power for them. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../bindings/clock/nvidia,tegra20-car.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml index 459d2a525393..f832abb7f11a 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml @@ -42,6 +42,36 @@ properties: "#reset-cells": const: 1 +patternProperties: + "^(sclk)|(pll-[cem])$": + type: object + properties: + compatible: + enum: + - nvidia,tegra20-sclk + - nvidia,tegra30-sclk + - nvidia,tegra30-pllc + - nvidia,tegra30-plle + - nvidia,tegra30-pllm + + operating-points-v2: true + + clocks: + items: + - description: node's clock + + power-domains: + maxItems: 1 + description: phandle to the core SoC power domain + + required: + - compatible + - operating-points-v2 + - clocks + - power-domains + + additionalProperties: false + required: - compatible - reg @@ -59,6 +89,13 @@ examples: reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + sclk { + compatible = "nvidia,tegra20-sclk"; + operating-points-v2 = <&opp_table>; + clocks = <&tegra_car TEGRA20_CLK_SCLK>; + power-domains = <&domain>; + }; }; usb-controller@c5004000 { From 425a68a963698867a9b6a8d82fcd41354a01f0ab Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:13 +0300 Subject: [PATCH 537/574] dt-bindings: host1x: Document OPP and power domain properties Document new DVFS OPP table and power domain properties of the Host1x bus and devices sitting on the bus. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../display/tegra/nvidia,tegra20-host1x.txt | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 8a6d3e1ee306..62861a8fb5c6 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -20,6 +20,18 @@ Required properties: - reset-names: Must include the following entries: - host1x +Optional properties: +- operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. + +For each opp entry in 'operating-points-v2' table of host1x and its modules: +- opp-supported-hw: One bitfield indicating: + On Tegra20: SoC process ID mask + On Tegra30+: SoC speedo ID mask + + A bitwise AND is performed against the value and if any bit + matches, the OPP gets enabled. + Each host1x client module having to perform DMA through the Memory Controller should have the interconnect endpoints set to the Memory Client and External Memory respectively. @@ -45,6 +57,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to MPE power domain. - vi: video input @@ -128,6 +142,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to VENC power domain. - epp: encoder pre-processor @@ -147,6 +163,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. - isp: image signal processor @@ -166,6 +184,7 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - power-domains: Phandle to VENC or core power domain. - gr2d: 2D graphics engine @@ -185,6 +204,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. - gr3d: 3D graphics engine @@ -209,6 +230,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandles to 3D or core power domain. - dc: display controller @@ -241,6 +264,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to core power domain. - hdmi: High Definition Multimedia Interface @@ -267,6 +292,7 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - operating-points-v2: See ../bindings/opp/opp.txt for details. - tvo: TV encoder output @@ -277,6 +303,10 @@ of the following host1x client modules: - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. + Optional properties: + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to core power domain. + - dsi: display serial interface Required properties: @@ -305,6 +335,7 @@ of the following host1x client modules: - nvidia,panel: phandle of a display panel - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang up with in order to support up to 8 data lanes + - operating-points-v2: See ../bindings/opp/opp.txt for details. - sor: serial output resource @@ -408,6 +439,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_HOST1X>; resets = <&tegra_car 28>; reset-names = "host1x"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; #address-cells = <1>; #size-cells = <1>; @@ -421,6 +454,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; vi@54080000 { @@ -429,6 +464,7 @@ Example: interrupts = ; assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + operating-points-v2 = <&dvfs_opp_table>; clocks = <&tegra_car TEGRA210_CLK_VI>; power-domains = <&pd_venc>; @@ -510,6 +546,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; isp { @@ -528,6 +566,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; gr3d { @@ -536,6 +576,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; dc@54200000 { @@ -547,6 +589,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, <&mc TEGRA20_MC_DISPLAY0B &emc>, @@ -571,6 +615,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, <&mc TEGRA20_MC_DISPLAY0BB &emc>, @@ -596,6 +642,7 @@ Example: resets = <&tegra_car 51>; reset-names = "hdmi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; tvo { @@ -604,6 +651,7 @@ Example: interrupts = <0 76 0x04>; clocks = <&tegra_car TEGRA20_CLK_TVO>; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; dsi { @@ -615,6 +663,7 @@ Example: resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; }; From 0c41e287f7541aee58c5a0c4437524fbdbf63bd9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:14 +0300 Subject: [PATCH 538/574] dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D Memory Client should be blocked before hardware reset is asserted in order to prevent memory corruption and hanging of memory controller. Document Memory Client resets of Host1x, GR2D and GR3D hardware units. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../bindings/display/tegra/nvidia,tegra20-host1x.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 62861a8fb5c6..e61999ce54e9 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -19,6 +19,7 @@ Required properties: See ../reset/reset.txt for details. - reset-names: Must include the following entries: - host1x + - mc Optional properties: - operating-points-v2: See ../bindings/opp/opp.txt for details. @@ -198,6 +199,7 @@ of the following host1x client modules: See ../reset/reset.txt for details. - reset-names: Must include the following entries: - 2d + - mc Optional properties: - interconnects: Must contain entry for the GR2D memory clients. @@ -224,6 +226,8 @@ of the following host1x client modules: - reset-names: Must include the following entries: - 3d - 3d2 (Only required on SoCs with two 3D clocks) + - mc + - mc2 (Only required on SoCs with two 3D clocks) Optional properties: - interconnects: Must contain entry for the GR3D memory clients. From ccc3016261edc37d66123946ede157f8c22205da Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:32 +0300 Subject: [PATCH 539/574] media: dt: bindings: tegra-vde: Convert to schema Convert NVIDIA Tegra video decoder binding to schema. Reviewed-by: Rob Herring Acked-by: Hans Verkuil Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../bindings/media/nvidia,tegra-vde.txt | 64 ----------- .../bindings/media/nvidia,tegra-vde.yaml | 107 ++++++++++++++++++ 2 files changed, 107 insertions(+), 64 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt create mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt deleted file mode 100644 index 602169b8aa19..000000000000 --- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt +++ /dev/null @@ -1,64 +0,0 @@ -NVIDIA Tegra Video Decoder Engine - -Required properties: -- compatible : Must contain one of the following values: - - "nvidia,tegra20-vde" - - "nvidia,tegra30-vde" - - "nvidia,tegra114-vde" - - "nvidia,tegra124-vde" - - "nvidia,tegra132-vde" -- reg : Must contain an entry for each entry in reg-names. -- reg-names : Must include the following entries: - - sxe - - bsev - - mbe - - ppe - - mce - - tfe - - ppb - - vdma - - frameid -- iram : Must contain phandle to the mmio-sram device node that represents - IRAM region used by VDE. -- interrupts : Must contain an entry for each entry in interrupt-names. -- interrupt-names : Must include the following entries: - - sync-token - - bsev - - sxe -- clocks : Must include the following entries: - - vde -- resets : Must contain an entry for each entry in reset-names. -- reset-names : Should include the following entries: - - vde - -Optional properties: -- resets : Must contain an entry for each entry in reset-names. -- reset-names : Must include the following entries: - - mc -- iommus: Must contain phandle to the IOMMU device node. - -Example: - -video-codec@6001a000 { - compatible = "nvidia,tegra20-vde"; - reg = <0x6001a000 0x1000 /* Syntax Engine */ - 0x6001b000 0x1000 /* Video Bitstream Engine */ - 0x6001c000 0x100 /* Macroblock Engine */ - 0x6001c200 0x100 /* Post-processing Engine */ - 0x6001c400 0x100 /* Motion Compensation Engine */ - 0x6001c600 0x100 /* Transform Engine */ - 0x6001c800 0x100 /* Pixel prediction block */ - 0x6001ca00 0x100 /* Video DMA */ - 0x6001d800 0x300 /* Video frame controls */>; - reg-names = "sxe", "bsev", "mbe", "ppe", "mce", - "tfe", "ppb", "vdma", "frameid"; - iram = <&vde_pool>; /* IRAM region */ - interrupts = , /* Sync token interrupt */ - , /* BSE-V interrupt */ - ; /* SXE interrupt */ - interrupt-names = "sync-token", "bsev", "sxe"; - clocks = <&tegra_car TEGRA20_CLK_VDE>; - reset-names = "vde", "mc"; - resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; - iommus = <&mc TEGRA_SWGROUP_VDE>; -}; diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml new file mode 100644 index 000000000000..c143aaa06346 --- /dev/null +++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Video Decoder Engine + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra132-vde + - nvidia,tegra124-vde + - nvidia,tegra114-vde + - items: + - const: nvidia,tegra30-vde + - const: nvidia,tegra20-vde + - items: + - const: nvidia,tegra20-vde + + reg: + maxItems: 9 + + reg-names: + items: + - const: sxe + - const: bsev + - const: mbe + - const: ppe + - const: mce + - const: tfe + - const: ppb + - const: vdma + - const: frameid + + clocks: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: vde + - const: mc + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: sync-token + - const: bsev + - const: sxe + + iommus: + maxItems: 1 + + iram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of the SRAM MMIO node. + +required: + - compatible + - reg + - reg-names + - clocks + - resets + - reset-names + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + video-codec@6001a000 { + compatible = "nvidia,tegra20-vde"; + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x300>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&iram>; /* IRAM MMIO region */ + interrupts = <0 9 4>, /* Sync token */ + <0 10 4>, /* BSE-V */ + <0 12 4>; /* SXE */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&clk 61>; + reset-names = "vde", "mc"; + resets = <&rst 61>, <&mem 13>; + iommus = <&mem 15>; + }; From c9059a6bb993db31cd85f3a4081766af9e61be40 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:33 +0300 Subject: [PATCH 540/574] media: dt: bindings: tegra-vde: Document OPP and power domain Document new OPP table and power domain properties of the video decoder hardware. Reviewed-by: Rob Herring Acked-by: Hans Verkuil Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../devicetree/bindings/media/nvidia,tegra-vde.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml index c143aaa06346..4ecdee1be37e 100644 --- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml +++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml @@ -68,6 +68,16 @@ properties: description: Phandle of the SRAM MMIO node. + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, + which is a bitfield indicating SoC speedo or process ID mask. + + power-domains: + maxItems: 1 + description: + Phandle to the SoC core power domain. + required: - compatible - reg @@ -104,4 +114,6 @@ examples: reset-names = "vde", "mc"; resets = <&rst 61>, <&mem 13>; iommus = <&mem 15>; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; From 914ed1f56581f99094035f1cc989ab4498104e94 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 17 Dec 2021 14:53:08 +0100 Subject: [PATCH 541/574] arm64: tegra: Add host1x hotflush reset on Tegra210 Add the host1x memory client hotflush reset on Tegra210. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index aa768ea108fe..218a2b32200f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -93,8 +93,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA210_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; + reset-names = "host1x", "mc"; #address-cells = <2>; #size-cells = <2>; From 1f1cb308abc5272551b7db9c0d31733478f829bf Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Mon, 6 Dec 2021 11:56:17 +1300 Subject: [PATCH 542/574] arm/arm64: dts: Enable CP0 GPIOs for CN9130-CRB Enable the CP0 GPIO devices for the CN9130-CRB. This is needed for a number of the peripheral devices to function. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 505ae69289f6..c491e3379405 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -17,6 +17,8 @@ ethernet0 = &cp0_eth0; ethernet1 = &cp0_eth1; ethernet2 = &cp0_eth2; + gpio1 = &cp0_gpio1; + gpio2 = &cp0_gpio2; }; memory@0 { @@ -114,6 +116,14 @@ }; }; +&cp0_gpio1 { + status = "okay"; +}; + +&cp0_gpio2 { + status = "okay"; +}; + &cp0_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&cp0_i2c0_pins>; From 35d544a273eafc3d00074973771ebaa7e358d0fd Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Mon, 6 Dec 2021 11:56:18 +1300 Subject: [PATCH 543/574] arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree The CN9130-CRB boards have a MV88E6393X switch connected to eth0. Add the necessary dts nodes and properties for this. Signed-off-by: Chris Packham Reviewed-by: Russell King (Oracle) Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 130 ++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index c491e3379405..d9f9f2c19740 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -73,6 +73,17 @@ enable-active-high; regulator-always-on; }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&cp0_i2c1>; + mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>; + los-gpio = <&expander0 15 GPIO_ACTIVE_HIGH>; + tx-disable-gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + status = "okay"; + }; }; &uart0 { @@ -195,6 +206,125 @@ phy0: ethernet-phy@0 { reg = <0>; }; + + switch6: switch0@6 { + /* Actual device is MV88E6393X */ + compatible = "marvell,mv88e6190"; + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + interrupt-parent = <&cp0_gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "p1"; + phy-handle = <&switch0phy1>; + }; + + port@2 { + reg = <2>; + label = "p2"; + phy-handle = <&switch0phy2>; + }; + + port@3 { + reg = <3>; + label = "p3"; + phy-handle = <&switch0phy3>; + }; + + port@4 { + reg = <4>; + label = "p4"; + phy-handle = <&switch0phy4>; + }; + + port@5 { + reg = <5>; + label = "p5"; + phy-handle = <&switch0phy5>; + }; + + port@6 { + reg = <6>; + label = "p6"; + phy-handle = <&switch0phy6>; + }; + + port@7 { + reg = <7>; + label = "p7"; + phy-handle = <&switch0phy7>; + }; + + port@8 { + reg = <8>; + label = "p8"; + phy-handle = <&switch0phy8>; + }; + + port@9 { + reg = <9>; + label = "p9"; + phy-mode = "10gbase-r"; + sfp = <&sfp>; + managed = "in-band-status"; + }; + + port@a { + reg = <10>; + label = "cpu"; + ethernet = <&cp0_eth0>; + }; + + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy1: switch0phy1@1 { + reg = <0x1>; + }; + + switch0phy2: switch0phy2@2 { + reg = <0x2>; + }; + + switch0phy3: switch0phy3@3 { + reg = <0x3>; + }; + + switch0phy4: switch0phy4@4 { + reg = <0x4>; + }; + + switch0phy5: switch0phy5@5 { + reg = <0x5>; + }; + + switch0phy6: switch0phy6@6 { + reg = <0x6>; + }; + + switch0phy7: switch0phy7@7 { + reg = <0x7>; + }; + + switch0phy8: switch0phy8@8 { + reg = <0x8>; + }; + }; + }; }; &cp0_xmdio { From 73a78b6130d9e13daca22b86ad52f063b9403e03 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 8 Dec 2021 03:40:35 +0100 Subject: [PATCH 544/574] arm64: dts: marvell: armada-37xx: Add xtal clock to comphy node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Kernel driver phy-mvebu-a3700-comphy.c needs to know the rate of the reference xtal clock. So add missing xtal clock source into comphy device tree node. If the property is not present, the driver defaults to 25 MHz xtal rate (which, as far as we know, is used by all the existing boards). Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 9acc5d2b5a00..673f4906eef9 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -265,6 +265,8 @@ "lane2_sata_usb3"; #address-cells = <1>; #size-cells = <0>; + clocks = <&xtalclk>; + clock-names = "xtal"; comphy0: phy@0 { reg = <0>; From effd42600b987c1e95f946b14fefc1c7639e7439 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 12 Nov 2021 14:44:02 +0100 Subject: [PATCH 545/574] arm64: dts: marvell: cn9130: add GPIO and SPI aliases CN9130 has one CP115 built in, which like the CP110 has 2 GPIO and 2 SPI controllers built-in. However, unlike the Armada 7k and 8k the SoC DTSI doesn't add the required aliases as both the Orion SPI driver and MVEBU GPIO drivers require the aliases to be present. So add the required aliases for GPIO and SPI controllers. Fixes: 6b8970bd8d7a ("arm64: dts: marvell: Add support for Marvell CN9130 SoC support") Signed-off-by: Robert Marko Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/cn9130.dtsi b/arch/arm64/boot/dts/marvell/cn9130.dtsi index a2b7e5ec979d..71769ac7f058 100644 --- a/arch/arm64/boot/dts/marvell/cn9130.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi @@ -11,6 +11,13 @@ model = "Marvell Armada CN9130 SoC"; compatible = "marvell,cn9130", "marvell,armada-ap807-quad", "marvell,armada-ap807"; + + aliases { + gpio1 = &cp0_gpio1; + gpio2 = &cp0_gpio2; + spi1 = &cp0_spi0; + spi2 = &cp0_spi1; + }; }; /* From 0734f8311ce72c9041e5142769eff2083889c172 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 12 Nov 2021 14:44:03 +0100 Subject: [PATCH 546/574] arm64: dts: marvell: cn9130: enable CP0 GPIO controllers CN9130 has a built-in CP115 which has 2 GPIO controllers, but unlike in Armada 7k and 8k both are left disabled by the SoC DTSI. This first of all makes no sense as they are always present due to being SoC built-in and its an issue as boards like CN9130-CRB use the CPO GPIO2 pins for regulators and SD card support without enabling them first. So, enable both of them like Armada 7k and 8k do. Fixes: 6b8970bd8d7a ("arm64: dts: marvell: Add support for Marvell CN9130 SoC support") Signed-off-by: Robert Marko Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/cn9130.dtsi b/arch/arm64/boot/dts/marvell/cn9130.dtsi index 71769ac7f058..327b04134134 100644 --- a/arch/arm64/boot/dts/marvell/cn9130.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi @@ -42,3 +42,11 @@ #undef CP11X_PCIE0_BASE #undef CP11X_PCIE1_BASE #undef CP11X_PCIE2_BASE + +&cp0_gpio1 { + status = "okay"; +}; + +&cp0_gpio2 { + status = "okay"; +}; From 62480772263ab6b52e758f2346c70a526abd1d28 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 9 Nov 2021 17:46:04 +0100 Subject: [PATCH 547/574] ARM: dts: armada-38x: Add generic compatible to UART nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add generic compatible string "ns16550a" to serial port nodes of Armada 38x. This makes it possible to use earlycon. Fixes: 0d3d96ab0059 ("ARM: mvebu: add Device Tree description of the Armada 380/385 SoCs") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-38x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 9b1a24cc5e91..df3c8d1d8f64 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -168,7 +168,7 @@ }; uart0: serial@12000 { - compatible = "marvell,armada-38x-uart"; + compatible = "marvell,armada-38x-uart", "ns16550a"; reg = <0x12000 0x100>; reg-shift = <2>; interrupts = ; @@ -178,7 +178,7 @@ }; uart1: serial@12100 { - compatible = "marvell,armada-38x-uart"; + compatible = "marvell,armada-38x-uart", "ns16550a"; reg = <0x12100 0x100>; reg-shift = <2>; interrupts = ; From eafba51c545a165b29777cde1fc8b04781a0a8db Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Wed, 15 Dec 2021 10:44:49 +0100 Subject: [PATCH 548/574] dt-bindings: soc: bcm: Convert brcm,bcm2835-vchiq to json-schema This converts the VCHIQ bindings to YAML format. Signed-off-by: Stefan Wahren Co-developed-by: Nicolas Saenz Julienne Signed-off-by: Nicolas Saenz Julienne Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211215094448.280796-1-nsaenz@kernel.org --- .../bindings/soc/bcm/brcm,bcm2835-vchiq.txt | 17 ------ .../bindings/soc/bcm/brcm,bcm2835-vchiq.yaml | 53 +++++++++++++++++++ 2 files changed, 53 insertions(+), 17 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt create mode 100644 Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.yaml diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt deleted file mode 100644 index f331316183f6..000000000000 --- a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt +++ /dev/null @@ -1,17 +0,0 @@ -Broadcom VCHIQ firmware services - -Required properties: - -- compatible: Should be "brcm,bcm2835-vchiq" on BCM2835, otherwise - "brcm,bcm2836-vchiq". -- reg: Physical base address and length of the doorbell register pair -- interrupts: The interrupt number - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt - -Example: - -mailbox@7e00b840 { - compatible = "brcm,bcm2835-vchiq"; - reg = <0x7e00b840 0xf>; - interrupts = <0 2>; -}; diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.yaml b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.yaml new file mode 100644 index 000000000000..e04439b3355b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/bcm/brcm,bcm2835-vchiq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom VCHIQ firmware services + +maintainers: + - Nicolas Saenz Julienne + +description: + The VCHIQ communication channel can be provided by BCM283x and Capri SoCs, + to communicate with the VPU-side OS services. + +properties: + compatible: + oneOf: + - description: BCM2835 based boards + items: + - enum: + - brcm,bcm2835-vchiq + + - description: BCM2836/BCM2837 based boards + items: + - enum: + - brcm,bcm2836-vchiq + - const: brcm,bcm2835-vchiq + + reg: + description: Physical base address and length of the doorbell register pair + minItems: 1 + + interrupts: + description: Interrupt number of the doorbell interrupt + minItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + mailbox@7e00b840 { + compatible = "brcm,bcm2835-vchiq"; + reg = <0x7e00b840 0xf>; + interrupts = <0 2>; + }; + +... From 13391025039fe86c68741e45a8b7bc158c69d68e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 2 Dec 2021 15:14:13 -0800 Subject: [PATCH 549/574] ARM: dts: Cygnus: Fixed iProc PCIe controller properties Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. We also need to re-arrange the 'ranges' property to show the two cells as being separate instead of combined since the DT checker is not able to differentiate otherwise. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 8ecb7861ce10..e73a19409d71 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -274,8 +274,8 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; phys = <&pcie0_phy>; phy-names = "pcie-phy"; @@ -283,7 +283,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -309,8 +309,8 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; phys = <&pcie1_phy>; phy-names = "pcie-phy"; @@ -318,7 +318,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; From 89b9492c113c4a22361f32639c6af041bcada2b6 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Dec 2021 16:06:22 -0800 Subject: [PATCH 550/574] ARM: dts: Cygnus: Update PCIe PHY node unit name(s) Update the PCIe PHY node unit name and its sub-nodes to help with upcoming changes converting the Cygnus PCIe PHY DT binding to YAML and later the iProc PCIe controller binding to YAML. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index e73a19409d71..ad65be871938 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -112,18 +112,18 @@ status = "disabled"; }; - pcie_phy: phy@301d0a0 { + pcie_phy: pcie_phy@301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; #address-cells = <1>; #size-cells = <0>; - pcie0_phy: phy@0 { + pcie0_phy: pcie-phy@0 { reg = <0>; #phy-cells = <0>; }; - pcie1_phy: phy@1 { + pcie1_phy: pcie-phy@1 { reg = <1>; #phy-cells = <0>; }; From d2b820bb16c509b313b87f616dcf6aa612d01fb9 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 2 Dec 2021 15:15:27 -0800 Subject: [PATCH 551/574] ARM: dts: HR2: Fixed iProc PCIe MSI sub-node Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-hr2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index 84cda16f68a2..33e6ba63a1ee 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -318,7 +318,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -354,7 +354,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; From 69c4e53bdd055ecc27761f6971a50c631ff9072e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 2 Dec 2021 15:16:27 -0800 Subject: [PATCH 552/574] ARM: dts: NSP: Fixed iProc PCIe MSI sub-node Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 1c08daa18858..f242763c3bde 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -587,7 +587,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -624,7 +624,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -661,7 +661,7 @@ status = "disabled"; msi-parent = <&msi2>; - msi2: msi-controller { + msi2: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; From 9a68c53f875e88edd3403c001ad85f4ac0ed3486 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Dec 2021 10:19:09 -0800 Subject: [PATCH 553/574] ARM: dts: NSP: Rename SATA unit name Rename the SATA controller unit name from ahci to sata in preparation for adding the Broadcom SATA3 controller YAML binding which will bring validation. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index f242763c3bde..5b1dc58d40ba 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -534,7 +534,7 @@ }; }; - sata: ahci@41000 { + sata: sata@41000 { compatible = "brcm,bcm-nsp-ahci"; reg-names = "ahci", "top-ctrl"; reg = <0x41000 0x1000>, <0x40020 0x1c>; From 5e33f1c4a7cb914a003a304ab8eef705b17aabb7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 17 Dec 2021 00:03:19 +0800 Subject: [PATCH 554/574] ARM: dts: BCM5301X: correct RX delay and enable flow control on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current 'rx-internal-delay-ps' property value on the Realtek switch node, 2000, will be divided by 300, resulting in 6.66, which will be rounded to the closest step value, 7. Change it to 2100 to be accurate. See ef136837aaf6 ("net: dsa: rtl8365mb: set RGMII RX delay in steps of 0.3 ns") for reference. Flow control needs to be enabled on both sides of the internal and external switch. It is already enabled on the CPU port of the Realtek switch so we also enable it on the external switch port of the Broadcom switch as well. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 16dea851719f..df8199fd4eb4 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -138,7 +138,7 @@ ethernet = <&sw0_p5>; phy-mode = "rgmii"; tx-internal-delay-ps = <2000>; - rx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2100>; fixed-link { speed = <1000>; @@ -213,6 +213,7 @@ fixed-link { speed = <1000>; full-duplex; + pause; }; }; From 2d6a1c7d57723efcb23a345d0ea5a10d76350390 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Fri, 17 Dec 2021 18:15:45 +0200 Subject: [PATCH 555/574] dt-bindings: Add vendor prefix for WinLink WinLink Co., Ltd is a hardware design and manufacturing company based in South Korea. Official web-site: [1]. [1] http://win-link.net/ Signed-off-by: Sam Protsenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211217161549.24836-4-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 66d6432fd781..95a847dfd29a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1318,6 +1318,8 @@ patternProperties: description: Wiligear, Ltd. "^winbond,.*": description: Winbond Electronics corp. + "^winlink,.*": + description: WinLink Co., Ltd "^winstar,.*": description: Winstar Display Corp. "^wits,.*": From e1ba2f940ba4c4c3b4d0a520301a920591c421f9 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Fri, 17 Dec 2021 18:15:46 +0200 Subject: [PATCH 556/574] dt-bindings: arm: samsung: Document E850-96 board binding Add binding for the WinLink E850-96 board, which is based on Samsung Exynos850 SoC. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211217161549.24836-5-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index d88571202713..052cd94113d4 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -205,6 +205,12 @@ properties: - samsung,jackpotlte # Samsung Galaxy A8 (2018) - const: samsung,exynos7885 + - description: Exynos850 based boards + items: + - enum: + - winlink,e850-96 # WinLink E850-96 + - const: samsung,exynos850 + - description: Exynos Auto v9 based boards items: - enum: From 51b1a5729469cef57a3c97aa014aa6e1d2b8d864 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Fri, 17 Dec 2021 18:15:47 +0200 Subject: [PATCH 557/574] dt-bindings: pinctrl: samsung: Add pin drive definitions for Exynos850 All Exynos850 GPIO blocks can use EXYNOS5420_PIN_DRV* definitions, except GPIO_HSI block. Add pin drive strength definitions for GPIO_HSI block correspondingly. Signed-off-by: Sam Protsenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211217161549.24836-6-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/pinctrl/samsung.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h index b1832506b923..950970634dfe 100644 --- a/include/dt-bindings/pinctrl/samsung.h +++ b/include/dt-bindings/pinctrl/samsung.h @@ -36,7 +36,10 @@ #define EXYNOS5260_PIN_DRV_LV4 2 #define EXYNOS5260_PIN_DRV_LV6 3 -/* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ +/* + * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except + * GPIO_HSI block) + */ #define EXYNOS5420_PIN_DRV_LV1 0 #define EXYNOS5420_PIN_DRV_LV2 1 #define EXYNOS5420_PIN_DRV_LV3 2 @@ -56,6 +59,14 @@ #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf +/* Drive strengths for Exynos850 GPIO_HSI block */ +#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ +#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ +#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ +#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ + #define EXYNOS_PIN_FUNC_INPUT 0 #define EXYNOS_PIN_FUNC_OUTPUT 1 #define EXYNOS_PIN_FUNC_2 2 From 8a3804c030e44335890bc9ca70cfa987488d9ec6 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 17 Dec 2021 16:12:32 -0600 Subject: [PATCH 558/574] ARM: dts: Remove "spidev" nodes "spidev" is not a real device, but a Linux implementation detail. It has never been documented either. The kernel has WARNed on the use of it for over 6 years. Time to remove its usage from the tree. Signed-off-by: Rob Herring Acked-by: Nicolas Ferre Acked-by: Viresh Kumar Cc: Mark Brown Link: https://lore.kernel.org/r/20211217221232.3664417-1-robh@kernel.org' Reviwed-by: Mark Brown Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/at91-q5xr5.dts | 18 ---------- arch/arm/boot/dts/at91-wb50n.dts | 6 ---- arch/arm/boot/dts/imx28-tx28.dts | 36 ------------------- arch/arm/boot/dts/imx53-tx53.dtsi | 11 ------ arch/arm/boot/dts/imx6qdl-tx6.dtsi | 12 ------- .../boot/dts/imx6ul-imx6ull-opos6uldev.dtsi | 12 ------- arch/arm/boot/dts/imx6ul-prti6g.dts | 6 ---- arch/arm/boot/dts/imx6ul-tx6ul.dtsi | 24 ------------- arch/arm/boot/dts/omap3-tao3530.dtsi | 14 -------- .../dts/qcom-mdm9615-wp8548-mangoh-green.dts | 2 +- arch/arm/boot/dts/spear1310-evb.dts | 16 --------- arch/arm/boot/dts/spear1340-evb.dts | 16 --------- 12 files changed, 1 insertion(+), 172 deletions(-) diff --git a/arch/arm/boot/dts/at91-q5xr5.dts b/arch/arm/boot/dts/at91-q5xr5.dts index 5827383b181b..47a00062f01f 100644 --- a/arch/arm/boot/dts/at91-q5xr5.dts +++ b/arch/arm/boot/dts/at91-q5xr5.dts @@ -147,12 +147,6 @@ reg = <0x8000 0x3E000>; }; }; - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <2000000>; - reg = <1>; - }; }; &spi1 { @@ -160,18 +154,6 @@ pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>; cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>; status = "okay"; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <2000000>; - reg = <0>; - }; - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <2000000>; - reg = <1>; - }; }; &usart0 { diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts index a5e45bb95c04..89f0f717f7ed 100644 --- a/arch/arm/boot/dts/at91-wb50n.dts +++ b/arch/arm/boot/dts/at91-wb50n.dts @@ -90,12 +90,6 @@ &spi1 { status = "okay"; - - spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <8000000>; - }; }; &usb0 { diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 164254c28f8e..9e5651c7ea6b 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -239,24 +239,6 @@ >; /* enable this and disable ssp3 below, if you need full duplex SPI transfer */ status = "disabled"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <57600000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <57600000>; - }; - - spi@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <57600000>; - }; }; }; @@ -700,24 +682,6 @@ pinctrl-0 = <&spi3_pins_a>; clock-frequency = <57600000>; status = "okay"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <57600000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <57600000>; - }; - - spi@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <57600000>; - }; }; &usb0 { diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index 7c9730f3f820..81c2726a328a 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -192,17 +192,6 @@ &gpio3 19 GPIO_ACTIVE_HIGH >; - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <54000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <54000000>; - }; }; &esdhc1 { diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index 362e65ccaa78..bcc5bbcce769 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -259,18 +259,6 @@ &gpio3 19 GPIO_ACTIVE_HIGH >; status = "disabled"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <54000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <54000000>; - }; }; &fec { diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi index 935a77d717a6..18cac19aa9b0 100644 --- a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi +++ b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi @@ -114,18 +114,6 @@ pinctrl-0 = <&pinctrl_ecspi4>; cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>; status = "okay"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <5000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <5000000>; - }; }; &i2c1 { diff --git a/arch/arm/boot/dts/imx6ul-prti6g.dts b/arch/arm/boot/dts/imx6ul-prti6g.dts index d62015701d0a..c18390f238e1 100644 --- a/arch/arm/boot/dts/imx6ul-prti6g.dts +++ b/arch/arm/boot/dts/imx6ul-prti6g.dts @@ -78,12 +78,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <1000000>; - }; }; &fec1 { diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index 938a32ced88d..c485d058e079 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -227,18 +227,6 @@ &gpio1 10 GPIO_ACTIVE_HIGH >; status = "disabled"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <660000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <660000>; - }; }; sound { @@ -290,18 +278,6 @@ &gpio1 10 GPIO_ACTIVE_HIGH >; status = "disabled"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <60000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <60000000>; - }; }; &fec1 { diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index 580bfa1931c8..7f440d11f7e7 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -197,25 +197,11 @@ &mcspi1 { pinctrl-names = "default"; pinctrl-0 = <&mcspi1_pins>; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpha; - }; }; &mcspi3 { pinctrl-names = "default"; pinctrl-0 = <&mcspi3_pins>; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpha; - }; }; #include "twl4030.dtsi" diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts index 942e3a2cac35..0827de5426c1 100644 --- a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts @@ -103,7 +103,7 @@ &gsbi3_spi { spi@0 { - compatible = "swir,mangoh-iotport-spi", "spidev"; + compatible = "swir,mangoh-iotport-spi"; spi-max-frequency = <24000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts index 8fcb6be6e7c7..4cbadcb41084 100644 --- a/arch/arm/boot/dts/spear1310-evb.dts +++ b/arch/arm/boot/dts/spear1310-evb.dts @@ -395,22 +395,6 @@ pl022,wait-state = <0>; pl022,duplex = <0>; }; - - spidev@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <25000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; }; wdt@ec800620 { diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts index f70ff56d4542..fd194ebeedc9 100644 --- a/arch/arm/boot/dts/spear1340-evb.dts +++ b/arch/arm/boot/dts/spear1340-evb.dts @@ -489,22 +489,6 @@ ts,i-drive = <1>; }; }; - - spidev@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <25000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; }; timer@ec800600 { From bc9fd597b3009d3412022c7beb3fbb01c9d27b31 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 17 Nov 2021 11:51:04 +0800 Subject: [PATCH 559/574] dt-bindings: aspeed: Add Secure Boot Controller bindings The secure boot controller was first introduced in the AST2600. Signed-off-by: Joel Stanley Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211117035106.321454-2-joel@jms.id.au Signed-off-by: Joel Stanley --- .../bindings/arm/aspeed/aspeed,sbc.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml new file mode 100644 index 000000000000..c72aab706484 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +# Copyright 2021 Joel Stanley, IBM Corp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ASPEED Secure Boot Controller + +maintainers: + - Joel Stanley + - Andrew Jeffery + +description: | + The ASPEED SoCs have a register bank for interacting with the secure boot + controller. + +properties: + compatible: + items: + - const: aspeed,ast2600-sbc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + sbc: secure-boot-controller@1e6f2000 { + compatible = "aspeed,ast2600-sbc"; + reg = <0x1e6f2000 0x1000>; + }; From fea289467608ffddb2f8d3a740912047974bb183 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 17 Nov 2021 11:51:05 +0800 Subject: [PATCH 560/574] ARM: dts: aspeed: Add secure boot controller node The ast2600 has a secure boot controller. Signed-off-by: Joel Stanley Reviewed-by: Ryan Chen Link: https://lore.kernel.org/r/20211117035106.321454-3-joel@jms.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 5106a424f1ce..16b36c13695a 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -384,6 +384,11 @@ status = "disabled"; }; + sbc: secure-boot-controller@1e6f2000 { + compatible = "aspeed,ast2600-sbc"; + reg = <0x1e6f2000 0x1000>; + }; + gpio0: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; From 0720caa3f81d6b8c1ee5d51d3d251dc43030e687 Mon Sep 17 00:00:00 2001 From: Lei YU Date: Fri, 10 Dec 2021 17:34:43 +0800 Subject: [PATCH 561/574] ARM: dts: Add openbmc-flash-layout-64-alt.dtsi Add openbmc-flash-layout-64-alt.dtsi to describe the partitions of the secondary flash for OpenBMC's 64M static layout. The layout is the same as openbmc-flash-layout-64.dtsi and the labels are prepended with "alt-" for the partitions. Signed-off-by: Lei YU Reviewed-by: Patrick Williams Link: https://lore.kernel.org/r/20211210093443.2140557-1-yulei.sh@bytedance.com Signed-off-by: Joel Stanley --- .../boot/dts/openbmc-flash-layout-64-alt.dtsi | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi new file mode 100644 index 000000000000..650525867561 --- /dev/null +++ b/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Bytedance. + */ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0xe0000>; // 896KB + label = "alt-u-boot"; + }; + + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB + label = "alt-u-boot-env"; + }; + + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB + label = "alt-kernel"; + }; + + rofs@a00000 { + reg = <0xa00000 0x2000000>; // 32MB + label = "alt-rofs"; + }; + + rwfs@6000000 { + reg = <0x2a00000 0x1600000>; // 22MB + label = "alt-rwfs"; + }; +}; From b26965e99788ea163fc217bdca1c2b17a5d70c90 Mon Sep 17 00:00:00 2001 From: Lei YU Date: Fri, 10 Dec 2021 17:36:23 +0800 Subject: [PATCH 562/574] ARM: dts: aspeed: g220a: Enable secondary flash Enable the secondary flash of the g220a's BMC and the wdt2. Signed-off-by: Lei YU Link: https://lore.kernel.org/r/20211210093623.2140640-1-yulei.sh@bytedance.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts index 01dace8f5e5f..0d1fb5ccfd36 100644 --- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts +++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts @@ -260,6 +260,13 @@ spi-max-frequency = <50000000>; #include "openbmc-flash-layout-64.dtsi" }; + flash@1 { + status = "okay"; + label = "alt-bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; }; &spi1 { @@ -278,6 +285,11 @@ status = "okay"; }; +&wdt2 { + status = "okay"; + aspeed,alt-boot; +}; + &gpio { status = "okay"; gpio-line-names = From a8c729e966c4e9d033242d948b0e53c2a62d32e2 Mon Sep 17 00:00:00 2001 From: Howard Chiu Date: Tue, 7 Dec 2021 17:49:24 +0800 Subject: [PATCH 563/574] ARM: dts: aspeed: Adding Facebook Bletchley BMC Initial introduction of Facebook Bletchley equipped with Aspeed 2600 BMC SoC. Signed-off-by: Howard Chiu Link: https://lore.kernel.org/r/20211207094923.422422-1-howard.chiu@quantatw.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + .../dts/aspeed-bmc-facebook-bletchley.dts | 756 ++++++++++++++++++ 2 files changed, 757 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 78b71e02624c..6ff97305200d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1482,6 +1482,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ aspeed-bmc-bytedance-g220a.dtb \ + aspeed-bmc-facebook-bletchley.dtb \ aspeed-bmc-facebook-cloudripper.dtb \ aspeed-bmc-facebook-cmm.dtb \ aspeed-bmc-facebook-elbert.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts new file mode 100644 index 000000000000..f973ea883b97 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -0,0 +1,756 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2021 Facebook Inc. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model = "Facebook Bletchley BMC"; + compatible = "facebook,bletchley-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + bootargs = "console=ttyS4,57600n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + spi_gpio: spi-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + gpio-sck = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + + tpmdev@0 { + compatible = "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; + + switchphy: ethernet-phy@0 { + // Fixed link + }; + + leds { + compatible = "gpio-leds"; + + sys_log_id { + retain-state-shutdown; + default-state = "keep"; + gpios = <&front_leds 0 GPIO_ACTIVE_HIGH>; + }; + fan0_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_ioexp 8 GPIO_ACTIVE_HIGH>; + }; + fan1_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_ioexp 9 GPIO_ACTIVE_HIGH>; + }; + fan2_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_ioexp 10 GPIO_ACTIVE_HIGH>; + }; + fan3_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_ioexp 11 GPIO_ACTIVE_HIGH>; + }; + fan0_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_ioexp 12 GPIO_ACTIVE_HIGH>; + }; + fan1_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_ioexp 13 GPIO_ACTIVE_HIGH>; + }; + fan2_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_ioexp 14 GPIO_ACTIVE_HIGH>; + }; + fan3_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_ioexp 15 GPIO_ACTIVE_HIGH>; + }; + sled0_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled0_leds 0 GPIO_ACTIVE_LOW>; + }; + sled0_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled0_leds 1 GPIO_ACTIVE_LOW>; + }; + sled1_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled1_leds 0 GPIO_ACTIVE_LOW>; + }; + sled1_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled1_leds 1 GPIO_ACTIVE_LOW>; + }; + sled2_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled2_leds 0 GPIO_ACTIVE_LOW>; + }; + sled2_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled2_leds 1 GPIO_ACTIVE_LOW>; + }; + sled3_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled3_leds 0 GPIO_ACTIVE_LOW>; + }; + sled3_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled3_leds 1 GPIO_ACTIVE_LOW>; + }; + sled4_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled4_leds 0 GPIO_ACTIVE_LOW>; + }; + sled4_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled4_leds 1 GPIO_ACTIVE_LOW>; + }; + sled5_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled5_leds 0 GPIO_ACTIVE_LOW>; + }; + sled5_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled5_leds 1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&switchphy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&rtc { + status = "okay"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + +&i2c0 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled0_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED0_MS_DETECT1","SLED0_VBUS_BMC_EN","SLED0_INA230_ALERT","SLED0_P12V_STBY_ALERT", + "SLED0_SSD_ALERT","SLED0_MS_DETECT0","SLED0_RST_CCG5","SLED0_FUSB302_INT", + "SLED0_MD_STBY_RESET","SLED0_MD_IOEXP_EN_FAULT","SLED0_MD_DIR","SLED0_MD_DECAY", + "SLED0_MD_MODE1","SLED0_MD_MODE2","SLED0_MD_MODE3","power-host0"; + }; + + sled0_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled0-amber","led-sled0-blue","SLED0_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled0_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c1 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled1_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED1_MS_DETECT1","SLED1_VBUS_BMC_EN","SLED1_INA230_ALERT","SLED1_P12V_STBY_ALERT", + "SLED1_SSD_ALERT","SLED1_MS_DETECT0","SLED1_RST_CCG5","SLED1_FUSB302_INT", + "SLED1_MD_STBY_RESET","SLED1_MD_IOEXP_EN_FAULT","SLED1_MD_DIR","SLED1_MD_DECAY", + "SLED1_MD_MODE1","SLED1_MD_MODE2","SLED1_MD_MODE3","power-host1"; + }; + + sled1_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled1-amber","led-sled1-blue","SLED1_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled1_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled2_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED2_MS_DETECT1","SLED2_VBUS_BMC_EN","SLED2_INA230_ALERT","SLED2_P12V_STBY_ALERT", + "SLED2_SSD_ALERT","SLED2_MS_DETECT0","SLED2_RST_CCG5","SLED2_FUSB302_INT", + "SLED2_MD_STBY_RESET","SLED2_MD_IOEXP_EN_FAULT","SLED2_MD_DIR","SLED2_MD_DECAY", + "SLED2_MD_MODE1","SLED2_MD_MODE2","SLED2_MD_MODE3","power-host2"; + }; + + sled2_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled2-amber","led-sled2-blue","SLED2_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled2_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c3 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled3_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED3_MS_DETECT1","SLED3_VBUS_BMC_EN","SLED3_INA230_ALERT","SLED3_P12V_STBY_ALERT", + "SLED3_SSD_ALERT","SLED3_MS_DETECT0","SLED3_RST_CCG5","SLED3_FUSB302_INT", + "SLED3_MD_STBY_RESET","SLED3_MD_IOEXP_EN_FAULT","SLED3_MD_DIR","SLED3_MD_DECAY", + "SLED3_MD_MODE1","SLED3_MD_MODE2","SLED3_MD_MODE3","power-host3"; + }; + + sled3_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled3-amber","led-sled3-blue","SLED3_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled3_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c4 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled4_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED4_MS_DETECT1","SLED4_VBUS_BMC_EN","SLED4_INA230_ALERT","SLED4_P12V_STBY_ALERT", + "SLED4_SSD_ALERT","SLED4_MS_DETECT0","SLED4_RST_CCG5","SLED4_FUSB302_INT", + "SLED4_MD_STBY_RESET","SLED4_MD_IOEXP_EN_FAULT","SLED4_MD_DIR","SLED4_MD_DECAY", + "SLED4_MD_MODE1","SLED4_MD_MODE2","SLED4_MD_MODE3","power-host4"; + }; + + sled4_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled4-amber","led-sled4-blue","SLED4_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled4_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c5 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled5_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED5_MS_DETECT1","SLED5_VBUS_BMC_EN","SLED5_INA230_ALERT","SLED5_P12V_STBY_ALERT", + "SLED5_SSD_ALERT","SLED5_MS_DETECT0","SLED5_RST_CCG5","SLED5_FUSB302_INT", + "SLED5_MD_STBY_RESET","SLED5_MD_IOEXP_EN_FAULT","SLED5_MD_DIR","SLED5_MD_DECAY", + "SLED5_MD_MODE1","SLED5_MD_MODE2","SLED5_MD_MODE3","power-host5"; + }; + + sled5_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled5-amber","led-sled5-blue","SLED5_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled5_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c6 { + status = "okay"; + + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&i2c7 { + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c9 { + status = "okay"; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; +}; + +&i2c10 { + status = "okay"; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + hdc1080@40 { + compatible = "ti,hdc1080"; + reg = <0x40>; + }; + + front_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-fault-identify","power-p5v-stby-good", + "power-p1v0-dvdd-good","power-p1v0-avdd-good", + "","","","", + "","","","", + "","","",""; + }; +}; + +&i2c12 { + status = "okay"; + + adm1278@11 { + compatible = "adi,adm1278"; + reg = <0x11>; + }; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + tmp421@4d { + compatible = "ti,tmp421"; + reg = <0x4d>; + }; + + fan_ioexp: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-fan0","presence-fan1", + "presence-fan2","presence-fan3", + "power-fan0-good","power-fan1-good", + "power-fan2-good","power-fan3-good", + "","","","", + "","","",""; + }; +}; + +&i2c13 { + multi-master; + aspeed,hw-timeout-ms = <1000>; + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","SEL_SPI2_MUX","SPI2_MUX1", + "SPI2_MUX2","SPI2_MUX3","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","SWITCH_FRU_MUX","","","","","","", + /*H0-H7*/ "presence-riser1","presence-riser2", + "presence-sled0","presence-sled1", + "presence-sled2","presence-sled3", + "presence-sled4","presence-sled5", + /*I0-I7*/ "REV_ID0","","REV_ID1","REV_ID2", + "","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "ALERT_SLED0","ALERT_SLED1", + "ALERT_SLED2","ALERT_SLED3", + "ALERT_SLED4","ALERT_SLED5", + "P12V_AUX_ALERT1","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","", + "","BOARD_ID0","BOARD_ID1","BOARD_ID2", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","BAT_DETECT", + "BMC_BT_WP0","BMC_BT_WP1","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","RST_BMC_MVL","","", + "USB2_SEL0_A","USB2_SEL1_A", + "USB2_SEL0_B","USB2_SEL1_B", + /*W0-W7*/ "RST_FRONT_IOEXP","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","BSM_FLASH_LATCH","","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + +&adc0 { + vref = <1800>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; From 4fcbe1f5b6ba71e0c464a303e3769bf1ce1fe54c Mon Sep 17 00:00:00 2001 From: Oskar Senft Date: Tue, 30 Nov 2021 13:48:55 -0500 Subject: [PATCH 564/574] ARM: dts: aspeed: tyan-s7106: Add uart_routing and fix vuart config Configure the vuart in such a way that it does not inhibit the SuperIO's UART from functioning correctly. This allows the same DTS to be used for both configurations with SuperIO and VUART (depending on the BIOS build). The decision on whether to actually enable VUART can then be made at runtime. This change also enables the new uart_routing driver for the SuperIO case. Signed-off-by: Oskar Senft Link: https://lore.kernel.org/r/20211130184855.1779353-1-osk@google.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts index 60ac6d3f03b5..aff27c1d4b06 100644 --- a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts +++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts @@ -3,6 +3,7 @@ #include "aspeed-g5.dtsi" #include +#include / { model = "Tyan S7106 BMC"; @@ -127,8 +128,23 @@ status = "okay"; }; +&uart_routing { + status = "okay"; +}; + &vuart { status = "okay"; + + /* We enable the VUART here, but leave it in a state that does + * not interfere with the SuperIO. The goal is to have both the + * VUART and the SuperIO available and decide at runtime whether + * the VUART should actually be used. For that reason, configure + * an "invalid" IO address and an IRQ that is not used by the + * BMC. + */ + + aspeed,lpc-io-reg = <0xffff>; + aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; }; &lpc_ctrl { From 30daf3cd8997d0ba4bda2b4a7f7c5122c81216f1 Mon Sep 17 00:00:00 2001 From: Ali El-Haj-Mahmoud Date: Tue, 30 Nov 2021 13:01:10 -0500 Subject: [PATCH 565/574] ARM: dts: aspeed: Add TYAN S8036 BMC machine The TYAN S8036 is a server platform with an ASPEED AST2500 BMC. Signed-off-by: Ali El-Haj-Mahmoud Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20211130180110.2217042-1-aaelhaj@google.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts | 470 ++++++++++++++++++++ 2 files changed, 471 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6ff97305200d..25005a7b5b84 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1521,6 +1521,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-supermicro-x11spi.dtb \ aspeed-bmc-inventec-transformers.dtb \ aspeed-bmc-tyan-s7106.dtb \ + aspeed-bmc-tyan-s8036.dtb \ aspeed-bmc-vegman-n110.dtb \ aspeed-bmc-vegman-rx20.dtb \ aspeed-bmc-vegman-sx20.dtb diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts new file mode 100644 index 000000000000..708ee78e4b83 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts @@ -0,0 +1,470 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include + +/ { + model = "Tyan S8036 BMC"; + compatible = "tyan,s8036-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + p2a_memory: region@987f0000 { + no-map; + reg = <0x987f0000 0x00010000>; /* 64KB */ + }; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; /* 16M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + identify { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + label = "bmc"; + status = "okay"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + }; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + /* RS-232 connector on header */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart3 { + /* Alternative to vuart to internally connect (route) to uart1 + * when vuart cannot be used due to BIOS limitations. + */ + status = "okay"; +}; + +&uart4 { + /* Alternative to vuart to internally connect (route) to the + * external port usually used by uart1 when vuart cannot be + * used due to BIOS limitations. + */ + status = "okay"; +}; + +&uart5 { + /* BMC "debug" (console) UART; connected to RS-232 connector + * on header; selectable via jumpers as alternative to uart2 + */ + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&vuart { + status = "okay"; + + /* We enable the VUART here, but leave it in a state that does + * not interfere with the SuperIO. The goal is to have both the + * VUART and the SuperIO available and decide at runtime whether + * the VUART should actually be used. For that reason, configure + * an "invalid" IO address and an IRQ that is not used by the + * BMC. + */ + aspeed,lpc-io-reg = <0xffff>; + aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&p2a { + status = "okay"; + memory-region = <&p2a_memory>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&adc { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default>; + + /* CPU fan */ + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + /* PWM group for chassis fans #1, #2, #3 and #4 */ + fan@2 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + /* PWM group for chassis fans #5 and #6 */ + fan@6 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; +}; + +&i2c0 { + /* Directly connected to Sideband-Temperature Sensor Interface (APML) */ + status = "okay"; +}; + +&i2c1 { + /* Directly connected to IPMB HDR. */ + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + /* BMC EEPROM, incl. mainboard FRU */ + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + /* Also connected to: + * - BCM5720 + * - FPGA + * - FAN HDR + * - FPIO HDR + */ +}; + +&i2c3 { + status = "okay"; + + /* PSU1 FRU @ 0xA0 */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + /* PSU2 FRU @ 0xA2 */ + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + /* PSU1 @ 0xB0 */ + power-supply@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + /* PSU2 @ 0xB2 */ + power-supply@59 { + compatible = "pmbus"; + reg = <0x59>; + }; + +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + /* Hardware monitor with temperature sensors */ + nct7802@28 { + compatible = "nuvoton,nct7802"; + reg = <0x28>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* LTD */ + reg = <0>; + status = "okay"; + }; + + channel@1 { /* RTD1 */ + reg = <1>; + status = "okay"; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@2 { /* RTD2 */ + reg = <2>; + status = "okay"; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@3 { /* RTD3 */ + reg = <3>; + status = "okay"; + sensor-type = "temperature"; + }; + }; + + /* Also connected to: + * - PCA9544 + * - CLK BUFF + * - OCP FRU + */ +}; + +&i2c6 { + status = "okay"; + /* Connected to: + * - PCA9548 @0xE0 + * - PCA9548 @0xE2 + * - PCA9544 @0xE4 + */ +}; + +&i2c7 { + status = "okay"; + + /* Connected to: + * - PCH SMBUS #4 + */ +}; + +&i2c8 { + status = "okay"; + + /* Not connected */ +}; + +&mac0 { + status = "okay"; + use-ncsi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&ibt { + status = "okay"; +}; + +&kcs1 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */ +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +/* We're following the GPIO naming as defined at + * https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md. + * + * Notes on led-identify and id-button: + * - A physical button is connected to id-button which + * triggers the clock on a D flip-flop. The /Q output of the + * flip-flop drives its D input. + * - The flip-flop's Q output drives led-identify which is + * connected to LEDs. + * - With that, every button press toggles the LED between on and off. + * + * Notes on power-, reset- and nmi- button and control: + * - The -button signals can be used to monitor physical buttons. + * - The -control signals can be used to actuate the specific + * operation. + * - In hardware, the -button signals are connected to the -control + * signals through drivers with the -control signals being + * protected through diodes. + */ +&gpio { + status = "okay"; + gpio-line-names = + /*A0*/ "", + /*A1*/ "", + /*A2*/ "led-identify", /* in/out: BMC_CHASSIS_ID_LED_L */ + /*A3*/ "", + /*A4*/ "", + /*A5*/ "", + /*A6*/ "", + /*A7*/ "", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0*/ "", + /*D1*/ "", + /*D2*/ "power-chassis-good", /* in: PWR_GOOD_LED -- Check if this is Z3?*/ + /*D3*/ "platform-reset", /* in: RESET_LED_L */ + /*D4*/ "", + /*D5*/ "", + /*D6*/ "", + /*D7*/ "", + /*E0*/ "power-button", /* in: BMC_SYS_MON_PWR_BTN_L */ + /*E1*/ "power-chassis-control", /* out: BMC_ASSERT_PWR_BTN */ + /*E2*/ "reset-button", /* in: BMC_SYS_MOS_RST_BTN_L*/ + /*E3*/ "reset-control", /* out: BMC_ASSERT_RST_BTN */ + /*E4*/ "nmi-button", /* in: BMC_SYS_MON_NMI_BTN_L */ + /*E5*/ "nmi-control", /* out: BMC_ASSERT_NMI_BTN */ + /*E6*/ "TSI_RESERT", + /*E7*/ "led-heartbeat", /* out: BMC_GPIOE7 */ + /*F0*/ "", + /*F1*/ "clear-cmos-control", /* out: BMC_ASSERT_CLR_CMOS_L */ + /*F2*/ "", + /*F3*/ "", + /*F4*/ "led-fault", /* out: BMC_HWM_FAULT_LED_L */ + /*F5*/ "BMC_SYS_FAULT_LED_L", + /*F6*/ "BMC_ASSERT_BIOS_WP_L", + /*F7*/ "", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0*/ "", + /*Q1*/ "", + /*Q2*/ "", + /*Q3*/ "", + /*Q4*/ "", + /*Q5*/ "", + /*Q6*/ "id-button", /* in: BMC_CHASSIS_ID_BTN_L */ + /*Q7*/ "", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z2*/ "","","", + /*Z3*/ "post-complete", /* BMC_SYS_MON_PWROK */ + /*Z4-Z7*/ "","","","", + /*AA0*/ "", + /*AA1*/ "", + /*AA2*/ "", + /*AA3*/ "", + /*AA4*/ "", + /*AA5*/ "", + /*AA6*/ "", + /*AA7*/ "BMC_ASSERT_BMC_READY", + /*AB0*/ "BMC_SPD_SEL", + /*AB1-AB7*/ "","","","","","",""; +}; From 1fe5c05c7c25b5ffa66d623c790f39babd2f5e7f Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 8 Dec 2021 11:06:40 -0600 Subject: [PATCH 566/574] ARM: dts: aspeed: p10: Enable USB host ports Ensure both controllers are enabled on, and add GPIO hog for USB power control to set the USB power to always on. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20211208170641.13322-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 12 +++++++++++- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 6 ++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index f42e2d776ba8..3e9edc893f55 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -280,7 +280,7 @@ /*L0-L7*/ "","","","","","","","", /*M0-M7*/ "","","","","","","","", /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", + /*O0-O7*/ "","","","usb-power","","","","", /*P0-P7*/ "","","","","led-pcieslot-power","","","", /*Q0-Q7*/ "","","regulator-standby-faulted","","","","","", /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","", @@ -292,6 +292,12 @@ /*X0-X7*/ "","","","","","","","", /*Y0-Y7*/ "","","","","","","","", /*Z0-Z7*/ "","","","","","","",""; + + usb_power { + gpio-hog; + gpios = ; + output-high; + }; }; &i2c0 { @@ -2375,6 +2381,10 @@ }; }; +&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 866f32cdccea..cb7d86a2862c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -275,6 +275,12 @@ output-high; line-name = "I2C3_MUX_OE_N"; }; + + usb_power { + gpio-hog; + gpios = ; + output-high; + }; }; &emmc_controller { From 62589e873d8e7cef7efd583ace1bb6ec90f252b7 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 8 Dec 2021 13:17:57 -0600 Subject: [PATCH 567/574] ARM: dts: aspeed: p10: Add TPM device Add the Nuvoton NPCT75X, a TIS I2C TPM. Modified Eddie's change to include the general compatible string, and combine the rainier and everest patches. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20211208191758.20517-8-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 5 +++++ arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 3e9edc893f55..22c06ff7a7ed 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -1887,6 +1887,11 @@ &i2c12 { status = "okay"; + + tpm@2e { + compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; }; &i2c13 { diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index cb7d86a2862c..c47974219832 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -2067,6 +2067,11 @@ &i2c12 { status = "okay"; + tpm@2e { + compatible = "nuvoton,npct75x"; + reg = <0x2e>; + }; + eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; From a350dc623e3678b9bc6c6385df72a66a1ee69c7f Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo Date: Mon, 8 Nov 2021 11:01:55 -0800 Subject: [PATCH 568/574] ARM: dts: aspeed: add LCLK setting into LPC IBT node If LPC BT driver is registered ahead of lpc-ctrl module, LPC BT hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property setting into LPC IBT node as one of required properties to enable the LCLK by the LPC IBT driver. Note: dtbs should be re-compiled after applying this change since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo Reviewed-by: Joel Stanley Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20211108190200.290957-2-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 1 + arch/arm/boot/dts/aspeed-g5.dtsi | 1 + arch/arm/boot/dts/aspeed-g6.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index b313a1cf5f73..f14dace34c5a 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -381,6 +381,7 @@ compatible = "aspeed,ast2400-ibt-bmc"; reg = <0x140 0x18>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index c7049454c7cb..d0cc4be2de59 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -507,6 +507,7 @@ compatible = "aspeed,ast2500-ibt-bmc"; reg = <0x140 0x18>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 16b36c13695a..539edbd7aaee 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -586,6 +586,7 @@ compatible = "aspeed,ast2600-ibt-bmc"; reg = <0x140 0x18>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; }; From 002c42d37e45ff5b5248576c77437ccafb651454 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo Date: Mon, 8 Nov 2021 11:01:56 -0800 Subject: [PATCH 569/574] dt-bindings: ipmi: bt-bmc: add 'clocks' as a required property If LPC BT driver is registered ahead of lpc-ctrl module, LPC BT hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property as one of required properties to enable the LCLK by the LPC IBT driver. Note: dtsi change in this patch series should be applied along with, and dtbs should be re-compiled after applying this series since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211108190200.290957-3-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley --- .../devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt index c9902fd4b38b..25f86da804b7 100644 --- a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt +++ b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt @@ -11,6 +11,7 @@ Required properties: "aspeed,ast2500-ibt-bmc" "aspeed,ast2600-ibt-bmc" - reg: physical address and size of the registers +- clocks: clock for the device Optional properties: @@ -23,4 +24,5 @@ Example: compatible = "aspeed,ast2400-ibt-bmc"; reg = <0x1e789140 0x18>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; }; From 45cd8bbaaa18ab1c4f4387529db72b33be463197 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo Date: Mon, 8 Nov 2021 11:01:58 -0800 Subject: [PATCH 570/574] ARM: dts: aspeed: add LCLK setting into LPC KCS nodes If LPC KCS driver is registered ahead of lpc-ctrl module, LPC KCS hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property setting into LPC KCS node as one of required properties to enable the LCLK by the LPC KCS driver. Note: dtbs should be re-compiled after applying this change since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo Reviewed-by: Joel Stanley Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20211108190200.290957-5-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 4 ++++ arch/arm/boot/dts/aspeed-g6.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index d0cc4be2de59..7495f93c5069 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -446,6 +446,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -453,6 +454,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -460,6 +462,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -467,6 +470,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 539edbd7aaee..c32e87fad4dc 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -525,6 +525,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; kcs_chan = <1>; status = "disabled"; }; @@ -533,6 +534,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -540,6 +542,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -547,6 +550,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; From 19fd04fb9247fb5dce01919fa83ed037ec569247 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 16 Dec 2021 16:38:12 +0530 Subject: [PATCH 571/574] arm64: dts: qcom: sm8450: Add usb nodes SM8450 features a single USB controller which connects to both HS and SS phy. Add the USB and the phy nodes for Qualcomm SM8450 SoC. Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211216110813.658384-1-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 89 ++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 62082ed5335d..10c25ad2d0c7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -626,6 +626,52 @@ #hwlock-cells = <1>; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8450-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_1_qmpphy: phy-wrapper@88e9000 { + compatible = "qcom,sm8450-qmp-usb3-phy"; + reg = <0 0x088e9000 0 0x200>, + <0 0x088e8000 0 0x20>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "com_aux"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + usb_1_ssphy: phy@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x400>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells = <0>; + #clock-cells = <1>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8450-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; @@ -1013,6 +1059,49 @@ #clock-cells = <0>; }; }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; }; timer { From 27a0d0b846d9add93a65c25149aae14ec3f75524 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 16 Dec 2021 16:38:13 +0530 Subject: [PATCH 572/574] arm64: dts: qcom: sm8450-qrd: Enable USB nodes Enable the usb phy and usb controller in peripheral mode. This helps to get the adb working with the QRD board. Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211216110813.658384-2-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 4b7ad190d538..b68ab247e6ae 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -373,3 +373,26 @@ vdda-max-microamp = <173000>; vdda-pll-max-microamp = <24900>; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5b_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p07>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p91>; +}; From c23f1b77358c173a25ef21303d2a8cc893e9ce22 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 22 Dec 2021 09:08:13 -0600 Subject: [PATCH 573/574] arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX The SM6125_VDDCX constant is introduced through a separate branch and is not available in the dts branch. Temporarily replace the constant with it's value to avoid the build breakage. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index e81b2a7794fb..49e6bca646c2 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -449,7 +449,7 @@ <&xo_board>; clock-names = "iface", "core", "xo"; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd 0>; bus-width = <8>; non-removable; @@ -474,7 +474,7 @@ pinctrl-1 = <&sdc2_state_off>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd 0>; bus-width = <4>; status = "disabled"; From 8b0c59c622dc4dab970ec63264fb5b152944ac80 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 23 Dec 2021 00:17:17 +0100 Subject: [PATCH 574/574] Revert "ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U" This reverts commit 3d2d52a0d1835b56f6bd67d268f6c39df0e41692, it caused a build regression: arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:109.4-14: Warning (reg_format): /switch/ports:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #address-cells value arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #size-cells value Reported-by: Stephen Rothwell Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 -------------------- 1 file changed, 77 deletions(-) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index df8199fd4eb4..249476fdad7a 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -93,83 +93,6 @@ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; }; - - switch { - compatible = "realtek,rtl8365mb"; - /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ - mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; - reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - realtek,disable-leds; - dsa,member = <1 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - port@0 { - reg = <0>; - label = "lan5"; - phy-handle = <ðphy0>; - }; - - port@1 { - reg = <1>; - label = "lan6"; - phy-handle = <ðphy1>; - }; - - port@2 { - reg = <2>; - label = "lan7"; - phy-handle = <ðphy2>; - }; - - port@3 { - reg = <3>; - label = "lan8"; - phy-handle = <ðphy3>; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&sw0_p5>; - phy-mode = "rgmii"; - tx-internal-delay-ps = <2000>; - rx-internal-delay-ps = <2100>; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - - mdio { - compatible = "realtek,smi-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - }; - - ethphy3: ethernet-phy@3 { - reg = <3>; - }; - }; - }; }; &srab {