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usb: musb: Remove ifdefs for musb_host_rx in musb_host.c part5
Remove ifdefs for musb_host_rx to get closer to building in all the DMA drivers. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Tony Lindgren
Felipe Balbi
parent
e530bb8f79
commit
ac33cdb166
@ -1661,6 +1661,122 @@ static int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
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return done;
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}
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/* Disadvantage of using mode 1:
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* It's basically usable only for mass storage class; essentially all
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* other protocols also terminate transfers on short packets.
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*
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* Details:
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* An extra IN token is sent at the end of the transfer (due to AUTOREQ)
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* If you try to use mode 1 for (transfer_buffer_length - 512), and try
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* to use the extra IN token to grab the last packet using mode 0, then
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* the problem is that you cannot be sure when the device will send the
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* last packet and RxPktRdy set. Sometimes the packet is recd too soon
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* such that it gets lost when RxCSR is re-set at the end of the mode 1
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* transfer, while sometimes it is recd just a little late so that if you
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* try to configure for mode 0 soon after the mode 1 transfer is
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* completed, you will find rxcount 0. Okay, so you might think why not
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* wait for an interrupt when the pkt is recd. Well, you won't get any!
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*/
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static int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma,
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struct musb_hw_ep *hw_ep,
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struct musb_qh *qh,
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struct urb *urb,
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size_t len,
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u8 iso_err)
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{
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struct musb *musb = hw_ep->musb;
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void __iomem *epio = hw_ep->regs;
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struct dma_channel *channel = hw_ep->rx_channel;
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u16 rx_count, val;
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int length, pipe, done;
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dma_addr_t buf;
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rx_count = musb_readw(epio, MUSB_RXCOUNT);
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pipe = urb->pipe;
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if (usb_pipeisoc(pipe)) {
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int d_status = 0;
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struct usb_iso_packet_descriptor *d;
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d = urb->iso_frame_desc + qh->iso_idx;
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if (iso_err) {
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d_status = -EILSEQ;
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urb->error_count++;
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}
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if (rx_count > d->length) {
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if (d_status == 0) {
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d_status = -EOVERFLOW;
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urb->error_count++;
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}
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dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",
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rx_count, d->length);
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length = d->length;
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} else
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length = rx_count;
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d->status = d_status;
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buf = urb->transfer_dma + d->offset;
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} else {
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length = rx_count;
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buf = urb->transfer_dma + urb->actual_length;
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}
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channel->desired_mode = 0;
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#ifdef USE_MODE1
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/* because of the issue below, mode 1 will
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* only rarely behave with correct semantics.
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*/
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if ((urb->transfer_flags & URB_SHORT_NOT_OK)
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&& (urb->transfer_buffer_length - urb->actual_length)
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> qh->maxpacket)
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channel->desired_mode = 1;
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if (rx_count < hw_ep->max_packet_sz_rx) {
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length = rx_count;
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channel->desired_mode = 0;
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} else {
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length = urb->transfer_buffer_length;
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}
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#endif
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/* See comments above on disadvantages of using mode 1 */
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val = musb_readw(epio, MUSB_RXCSR);
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val &= ~MUSB_RXCSR_H_REQPKT;
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if (channel->desired_mode == 0)
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val &= ~MUSB_RXCSR_H_AUTOREQ;
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else
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val |= MUSB_RXCSR_H_AUTOREQ;
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val |= MUSB_RXCSR_DMAENAB;
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/* autoclear shouldn't be set in high bandwidth */
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if (qh->hb_mult == 1)
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val |= MUSB_RXCSR_AUTOCLEAR;
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musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val);
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/* REVISIT if when actual_length != 0,
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* transfer_buffer_length needs to be
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* adjusted first...
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*/
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done = dma->channel_program(channel, qh->maxpacket,
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channel->desired_mode,
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buf, length);
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if (!done) {
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dma->channel_release(channel);
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hw_ep->rx_channel = NULL;
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channel = NULL;
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val = musb_readw(epio, MUSB_RXCSR);
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val &= ~(MUSB_RXCSR_DMAENAB
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| MUSB_RXCSR_H_AUTOREQ
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| MUSB_RXCSR_AUTOCLEAR);
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musb_writew(epio, MUSB_RXCSR, val);
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}
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return done;
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}
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#else
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static inline int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
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struct musb_hw_ep *hw_ep,
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@ -1670,6 +1786,16 @@ static inline int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
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{
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return false;
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}
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static inline int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma,
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struct musb_hw_ep *hw_ep,
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struct musb_qh *qh,
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struct urb *urb,
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size_t len,
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u8 iso_err)
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{
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return false;
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}
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#endif
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/*
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@ -1859,121 +1985,21 @@ void musb_host_rx(struct musb *musb, u8 epnum)
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/* we are expecting IN packets */
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if ((musb_dma_inventra(musb) || musb_dma_ux500(musb) ||
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musb_dma_cppi41(musb)) && dma) {
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struct dma_controller *c;
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u16 rx_count;
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int ret, length;
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dma_addr_t buf;
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dev_dbg(hw_ep->musb->controller,
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"RX%d count %d, buffer 0x%llx len %d/%d\n",
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epnum, musb_readw(epio, MUSB_RXCOUNT),
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(unsigned long long) urb->transfer_dma
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+ urb->actual_length,
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qh->offset,
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urb->transfer_buffer_length);
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rx_count = musb_readw(epio, MUSB_RXCOUNT);
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dev_dbg(musb->controller, "RX%d count %d, buffer 0x%llx len %d/%d\n",
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epnum, rx_count,
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(unsigned long long) urb->transfer_dma
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+ urb->actual_length,
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qh->offset,
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urb->transfer_buffer_length);
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c = musb->dma_controller;
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if (usb_pipeisoc(pipe)) {
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int d_status = 0;
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struct usb_iso_packet_descriptor *d;
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d = urb->iso_frame_desc + qh->iso_idx;
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if (iso_err) {
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d_status = -EILSEQ;
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urb->error_count++;
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}
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if (rx_count > d->length) {
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if (d_status == 0) {
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d_status = -EOVERFLOW;
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urb->error_count++;
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}
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dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
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rx_count, d->length);
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length = d->length;
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} else
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length = rx_count;
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d->status = d_status;
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buf = urb->transfer_dma + d->offset;
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} else {
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length = rx_count;
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buf = urb->transfer_dma +
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urb->actual_length;
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}
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dma->desired_mode = 0;
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#ifdef USE_MODE1
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/* because of the issue below, mode 1 will
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* only rarely behave with correct semantics.
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*/
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if ((urb->transfer_flags &
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URB_SHORT_NOT_OK)
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&& (urb->transfer_buffer_length -
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urb->actual_length)
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> qh->maxpacket)
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dma->desired_mode = 1;
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if (rx_count < hw_ep->max_packet_sz_rx) {
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length = rx_count;
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dma->desired_mode = 0;
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} else {
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length = urb->transfer_buffer_length;
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}
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#endif
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/* Disadvantage of using mode 1:
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* It's basically usable only for mass storage class; essentially all
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* other protocols also terminate transfers on short packets.
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*
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* Details:
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* An extra IN token is sent at the end of the transfer (due to AUTOREQ)
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* If you try to use mode 1 for (transfer_buffer_length - 512), and try
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* to use the extra IN token to grab the last packet using mode 0, then
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* the problem is that you cannot be sure when the device will send the
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* last packet and RxPktRdy set. Sometimes the packet is recd too soon
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* such that it gets lost when RxCSR is re-set at the end of the mode 1
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* transfer, while sometimes it is recd just a little late so that if you
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* try to configure for mode 0 soon after the mode 1 transfer is
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* completed, you will find rxcount 0. Okay, so you might think why not
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* wait for an interrupt when the pkt is recd. Well, you won't get any!
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*/
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val = musb_readw(epio, MUSB_RXCSR);
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val &= ~MUSB_RXCSR_H_REQPKT;
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if (dma->desired_mode == 0)
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val &= ~MUSB_RXCSR_H_AUTOREQ;
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done = musb_rx_dma_in_inventra_cppi41(c, hw_ep, qh,
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urb, xfer_len,
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iso_err);
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if (done)
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goto finish;
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else
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val |= MUSB_RXCSR_H_AUTOREQ;
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val |= MUSB_RXCSR_DMAENAB;
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/* autoclear shouldn't be set in high bandwidth */
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if (qh->hb_mult == 1)
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val |= MUSB_RXCSR_AUTOCLEAR;
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musb_writew(epio, MUSB_RXCSR,
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MUSB_RXCSR_H_WZC_BITS | val);
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/* REVISIT if when actual_length != 0,
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* transfer_buffer_length needs to be
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* adjusted first...
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*/
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ret = c->channel_program(
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dma, qh->maxpacket,
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dma->desired_mode, buf, length);
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if (!ret) {
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c->channel_release(dma);
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hw_ep->rx_channel = NULL;
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dma = NULL;
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val = musb_readw(epio, MUSB_RXCSR);
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val &= ~(MUSB_RXCSR_DMAENAB
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| MUSB_RXCSR_H_AUTOREQ
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| MUSB_RXCSR_AUTOCLEAR);
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musb_writew(epio, MUSB_RXCSR, val);
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}
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dev_err(musb->controller, "error: rx_dma failed\n");
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}
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if (!dma) {
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