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ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi
No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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@ -90,7 +90,6 @@
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serial@70006000 {
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status = "okay";
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clock-frequency = <408000000>;
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};
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i2c@7000c000 {
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@ -120,13 +120,11 @@
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serial@70006000 {
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status = "okay";
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clock-frequency = <408000000>;
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};
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serial@70006200 {
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compatible = "nvidia,tegra30-hsuart";
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status = "okay";
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clock-frequency = <408000000>;
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};
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i2c@7000c000 {
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@ -234,6 +234,7 @@
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <0 36 0x04>;
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clock-frequency = <408000000>;
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nvidia,dma-request-selector = <&apbdma 8>;
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clocks = <&tegra_car 6>;
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status = "disabled";
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@ -243,6 +244,7 @@
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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clock-frequency = <408000000>;
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interrupts = <0 37 0x04>;
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nvidia,dma-request-selector = <&apbdma 9>;
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clocks = <&tegra_car 160>;
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@ -253,6 +255,7 @@
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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clock-frequency = <408000000>;
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interrupts = <0 46 0x04>;
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nvidia,dma-request-selector = <&apbdma 10>;
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clocks = <&tegra_car 55>;
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@ -263,6 +266,7 @@
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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clock-frequency = <408000000>;
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interrupts = <0 90 0x04>;
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nvidia,dma-request-selector = <&apbdma 19>;
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clocks = <&tegra_car 65>;
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@ -273,6 +277,7 @@
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006400 0x100>;
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reg-shift = <2>;
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clock-frequency = <408000000>;
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interrupts = <0 91 0x04>;
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nvidia,dma-request-selector = <&apbdma 20>;
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clocks = <&tegra_car 66>;
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