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https://github.com/edk2-porting/linux-next.git
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ARM: davinci: dm365: Remove legacy clock init
This removes the unused legacy clock init code from arch/arm/mach-davinci/dm365.c. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
David Lechner
Sekhar Nori
parent
feee4eda2d
commit
ab0f2a60bb
@ -40,11 +40,6 @@
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#include "davinci.h"
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#include "mux.h"
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#ifndef CONFIG_COMMON_CLK
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#include "clock.h"
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#include "psc.h"
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#endif
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#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
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#define DM365_RTC_BASE 0x01c69000
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#define DM365_KEYSCAN_BASE 0x01c69400
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@ -60,441 +55,6 @@
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#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
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#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
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#ifndef CONFIG_COMMON_CLK
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static struct pll_data pll1_data = {
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.num = 1,
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.phys_base = DAVINCI_PLL1_BASE,
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.flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
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};
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static struct pll_data pll2_data = {
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.num = 2,
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.phys_base = DAVINCI_PLL2_BASE,
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.flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
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};
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static struct clk ref_clk = {
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.name = "ref_clk",
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.rate = DM365_REF_FREQ,
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};
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static struct clk pll1_clk = {
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.name = "pll1",
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.parent = &ref_clk,
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.flags = CLK_PLL,
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.pll_data = &pll1_data,
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};
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static struct clk pll1_aux_clk = {
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.name = "pll1_aux_clk",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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};
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static struct clk pll1_sysclkbp = {
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.name = "pll1_sysclkbp",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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.div_reg = BPDIV
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};
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static struct clk clkout0_clk = {
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.name = "clkout0",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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};
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static struct clk pll1_sysclk1 = {
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.name = "pll1_sysclk1",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk pll1_sysclk2 = {
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.name = "pll1_sysclk2",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV2,
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};
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static struct clk pll1_sysclk3 = {
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.name = "pll1_sysclk3",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV3,
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};
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static struct clk pll1_sysclk4 = {
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.name = "pll1_sysclk4",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV4,
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};
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static struct clk pll1_sysclk5 = {
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.name = "pll1_sysclk5",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV5,
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};
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static struct clk pll1_sysclk6 = {
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.name = "pll1_sysclk6",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV6,
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};
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static struct clk pll1_sysclk7 = {
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.name = "pll1_sysclk7",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV7,
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};
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static struct clk pll1_sysclk8 = {
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.name = "pll1_sysclk8",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV8,
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};
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static struct clk pll1_sysclk9 = {
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.name = "pll1_sysclk9",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV9,
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};
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static struct clk pll2_clk = {
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.name = "pll2",
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.parent = &ref_clk,
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.flags = CLK_PLL,
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.pll_data = &pll2_data,
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};
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static struct clk pll2_aux_clk = {
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.name = "pll2_aux_clk",
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.parent = &pll2_clk,
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.flags = CLK_PLL | PRE_PLL,
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};
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static struct clk clkout1_clk = {
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.name = "clkout1",
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.parent = &pll2_clk,
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.flags = CLK_PLL | PRE_PLL,
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};
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static struct clk pll2_sysclk1 = {
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.name = "pll2_sysclk1",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk pll2_sysclk2 = {
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.name = "pll2_sysclk2",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV2,
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};
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static struct clk pll2_sysclk3 = {
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.name = "pll2_sysclk3",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV3,
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};
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static struct clk pll2_sysclk4 = {
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.name = "pll2_sysclk4",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV4,
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};
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static struct clk pll2_sysclk5 = {
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.name = "pll2_sysclk5",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV5,
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};
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static struct clk pll2_sysclk6 = {
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.name = "pll2_sysclk6",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV6,
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};
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static struct clk pll2_sysclk7 = {
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.name = "pll2_sysclk7",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV7,
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};
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static struct clk pll2_sysclk8 = {
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.name = "pll2_sysclk8",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV8,
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};
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static struct clk pll2_sysclk9 = {
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.name = "pll2_sysclk9",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV9,
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};
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static struct clk vpss_dac_clk = {
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.name = "vpss_dac",
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.parent = &pll1_sysclk3,
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.lpsc = DM365_LPSC_DAC_CLK,
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};
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static struct clk vpss_master_clk = {
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.name = "vpss_master",
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.parent = &pll1_sysclk5,
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.lpsc = DM365_LPSC_VPSSMSTR,
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.flags = CLK_PSC,
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};
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static struct clk vpss_slave_clk = {
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.name = "vpss_slave",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_VPSSSLV,
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};
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static struct clk arm_clk = {
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.name = "arm_clk",
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.parent = &pll2_sysclk2,
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.lpsc = DAVINCI_LPSC_ARM,
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.flags = ALWAYS_ENABLED,
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};
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static struct clk uart0_clk = {
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.name = "uart0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_UART0,
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};
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static struct clk uart1_clk = {
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.name = "uart1",
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.parent = &pll1_sysclk4,
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.lpsc = DAVINCI_LPSC_UART1,
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};
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static struct clk i2c_clk = {
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.name = "i2c",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_I2C,
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};
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static struct clk mmcsd0_clk = {
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.name = "mmcsd0",
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.parent = &pll1_sysclk8,
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.lpsc = DAVINCI_LPSC_MMC_SD,
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};
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static struct clk mmcsd1_clk = {
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.name = "mmcsd1",
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.parent = &pll1_sysclk4,
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.lpsc = DM365_LPSC_MMC_SD1,
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};
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static struct clk spi0_clk = {
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.name = "spi0",
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.parent = &pll1_sysclk4,
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.lpsc = DAVINCI_LPSC_SPI,
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};
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static struct clk spi1_clk = {
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.name = "spi1",
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.parent = &pll1_sysclk4,
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.lpsc = DM365_LPSC_SPI1,
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};
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static struct clk spi2_clk = {
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.name = "spi2",
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.parent = &pll1_sysclk4,
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.lpsc = DM365_LPSC_SPI2,
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};
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static struct clk spi3_clk = {
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.name = "spi3",
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.parent = &pll1_sysclk4,
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.lpsc = DM365_LPSC_SPI3,
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};
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static struct clk spi4_clk = {
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.name = "spi4",
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.parent = &pll1_aux_clk,
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.lpsc = DM365_LPSC_SPI4,
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};
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static struct clk gpio_clk = {
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.name = "gpio",
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.parent = &pll1_sysclk4,
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.lpsc = DAVINCI_LPSC_GPIO,
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};
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static struct clk aemif_clk = {
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.name = "aemif",
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.parent = &pll1_sysclk4,
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.lpsc = DAVINCI_LPSC_AEMIF,
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};
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static struct clk pwm0_clk = {
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.name = "pwm0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM0,
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};
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static struct clk pwm1_clk = {
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.name = "pwm1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM1,
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};
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static struct clk pwm2_clk = {
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.name = "pwm2",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM2,
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};
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static struct clk pwm3_clk = {
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.name = "pwm3",
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.parent = &ref_clk,
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.lpsc = DM365_LPSC_PWM3,
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};
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static struct clk timer0_clk = {
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.name = "timer0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER0,
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};
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static struct clk timer1_clk = {
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.name = "timer1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER1,
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};
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static struct clk timer2_clk = {
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.name = "timer2",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER2,
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.usecount = 1,
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};
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static struct clk timer3_clk = {
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.name = "timer3",
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.parent = &pll1_aux_clk,
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.lpsc = DM365_LPSC_TIMER3,
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};
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static struct clk usb_clk = {
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.name = "usb",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_USB,
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};
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static struct clk emac_clk = {
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.name = "emac",
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.parent = &pll1_sysclk4,
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.lpsc = DM365_LPSC_EMAC,
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};
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static struct clk voicecodec_clk = {
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.name = "voice_codec",
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.parent = &pll2_sysclk4,
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.lpsc = DM365_LPSC_VOICE_CODEC,
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};
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static struct clk asp0_clk = {
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.name = "asp0",
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.parent = &pll1_sysclk4,
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.lpsc = DM365_LPSC_McBSP1,
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};
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static struct clk rto_clk = {
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.name = "rto",
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.parent = &pll1_sysclk4,
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.lpsc = DM365_LPSC_RTO,
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};
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static struct clk mjcp_clk = {
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.name = "mjcp",
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.parent = &pll1_sysclk3,
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.lpsc = DM365_LPSC_MJCP,
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};
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static struct clk_lookup dm365_clks[] = {
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CLK(NULL, "ref", &ref_clk),
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CLK(NULL, "pll1", &pll1_clk),
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CLK(NULL, "pll1_aux", &pll1_aux_clk),
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CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
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CLK(NULL, "clkout0", &clkout0_clk),
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CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
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CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
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CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
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CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
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CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
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CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
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CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
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CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
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CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
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CLK(NULL, "pll2", &pll2_clk),
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CLK(NULL, "pll2_aux", &pll2_aux_clk),
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CLK(NULL, "clkout1", &clkout1_clk),
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CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
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CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
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CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
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CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
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CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
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CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
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CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
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CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
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CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
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CLK(NULL, "vpss_dac", &vpss_dac_clk),
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CLK("vpss", "master", &vpss_master_clk),
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CLK("vpss", "slave", &vpss_slave_clk),
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CLK(NULL, "arm", &arm_clk),
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CLK("serial8250.0", NULL, &uart0_clk),
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CLK("serial8250.1", NULL, &uart1_clk),
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CLK("i2c_davinci.1", NULL, &i2c_clk),
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CLK("da830-mmc.0", NULL, &mmcsd0_clk),
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CLK("da830-mmc.1", NULL, &mmcsd1_clk),
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CLK("spi_davinci.0", NULL, &spi0_clk),
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CLK("spi_davinci.1", NULL, &spi1_clk),
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CLK("spi_davinci.2", NULL, &spi2_clk),
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CLK("spi_davinci.3", NULL, &spi3_clk),
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CLK("spi_davinci.4", NULL, &spi4_clk),
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CLK(NULL, "gpio", &gpio_clk),
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CLK(NULL, "aemif", &aemif_clk),
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CLK(NULL, "pwm0", &pwm0_clk),
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CLK(NULL, "pwm1", &pwm1_clk),
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CLK(NULL, "pwm2", &pwm2_clk),
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CLK(NULL, "pwm3", &pwm3_clk),
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CLK(NULL, "timer0", &timer0_clk),
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CLK(NULL, "timer1", &timer1_clk),
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CLK("davinci-wdt", NULL, &timer2_clk),
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CLK(NULL, "timer3", &timer3_clk),
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CLK(NULL, "usb", &usb_clk),
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CLK("davinci_emac.1", NULL, &emac_clk),
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CLK("davinci_mdio.0", "fck", &emac_clk),
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CLK("davinci_voicecodec", NULL, &voicecodec_clk),
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CLK("davinci-mcbsp", NULL, &asp0_clk),
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CLK(NULL, "rto", &rto_clk),
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CLK(NULL, "mjcp", &mjcp_clk),
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CLK(NULL, NULL, NULL),
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};
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#endif
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/*----------------------------------------------------------------------*/
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#define INTMUX 0x18
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#define EVTMUX 0x1c
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@ -1061,8 +621,6 @@ static struct davinci_id dm365_ids[] = {
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},
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};
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static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
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static struct davinci_timer_info dm365_timer_info = {
|
||||
.timers = davinci_timer_instance,
|
||||
.clockevent_id = T0_BOT,
|
||||
@ -1123,8 +681,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = {
|
||||
.jtag_id_reg = 0x01c40028,
|
||||
.ids = dm365_ids,
|
||||
.ids_num = ARRAY_SIZE(dm365_ids),
|
||||
.psc_bases = dm365_psc_bases,
|
||||
.psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
|
||||
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
|
||||
.pinmux_pins = dm365_pins,
|
||||
.pinmux_pins_num = ARRAY_SIZE(dm365_pins),
|
||||
@ -1178,7 +734,6 @@ void __init dm365_init(void)
|
||||
|
||||
void __init dm365_init_time(void)
|
||||
{
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
void __iomem *pll1, *pll2, *psc;
|
||||
struct clk *clk;
|
||||
|
||||
@ -1196,10 +751,6 @@ void __init dm365_init_time(void)
|
||||
clk = clk_get(NULL, "timer0");
|
||||
|
||||
davinci_timer_init(clk);
|
||||
#else
|
||||
davinci_clk_init(dm365_clks);
|
||||
davinci_timer_init(&timer0_clk);
|
||||
#endif
|
||||
}
|
||||
|
||||
void __init dm365_register_clocks(void)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user