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ASoC: SOF: Intel: hda: do not leave clock gating off upon error

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The misc clock gating (MISCBDCGE) is disabled for controller reset and
reenabled once reset is complete.

Fix the case when error happens during reset, and clock gating is
left disabled. The clock gating should be reenabled also in this case.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20200325211233.27394-5-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Kai Vehmanen 2020-03-25 16:12:32 -05:00 committed by Mark Brown
parent 9ef91cad92
commit aae5a6e92f
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 5 additions and 3 deletions
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8
sound/soc/sof/intel/hda-ctrl.c
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@ -183,7 +183,7 @@ int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
ret = hda_dsp_ctrl_link_reset(sdev, true);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to reset HDA controller\n");
return ret;
goto err;
}
usleep_range(500, 1000);
@ -192,7 +192,7 @@ int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
ret = hda_dsp_ctrl_link_reset(sdev, false);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
return ret;
goto err;
}
usleep_range(1000, 1200);
@ -202,7 +202,8 @@ int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
/* check to see if controller is ready */
if (!snd_hdac_chip_readb(bus, GCTL)) {
dev_dbg(bus->dev, "controller not ready!\n");
return -EBUSY;
ret = -EBUSY;
goto err;
}
/* Accept unsolicited responses */
@ -268,6 +269,7 @@ int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
bus->chip_init = true;
err:
hda_dsp_ctrl_misc_clock_gating(sdev, true);
return ret;