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Bulk pin control changes for the v3.12 series:

Browse Source 
- Refactorings for generic pin config handling in the core.
 
 - Factor out a set of device tree utilities for use in all
   drivers, to parse and allocate maps from the device tree.
 
 - Some fixes to the core such as more nitpicky locking.
 
 - Pushed down config array iteration into the drivers.
   This patch is necessary for drivers that want to iterate
   over configs and pile up a stack of alterations to the
   same register(s), or if the driver wants to take a local
   spinlock when committing the configuration.
 
 - A new driver for the Texas Instruments Palmas PMIC by
   Laxman Dewangan. This is used on the Tegra systems.
 
 - A major cleanup and modernization of the PFC (Super Hitachi
   and ARM SHmobile) pin controller and subdrivers.
 
 - Support for the A20 and A31 sunxi (AllWinner) SoCs.
 
 - A huge pile of fixes and cleanups: Axel Lin, Jingoo Han
   Dan Carpenter, Julia Lawall and Sachin Kamat did an
   excellent job here.
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Merge tag 'pinctrl-v3.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control changes from Linus Walleij:
 "Here is the bulk of pin control changes for the v3.12 series.  Most of
  the relevant information is in the tag.

  I merged in v3.11-rc7 last week to get rid of a largeish conflict
  within the sunxi (AllWinner) driver in linux-next and fix up the
  non-trivial merge the right way.  That driver had a rather large fix
  adding locking late in the release cycle.

  Overall the bulk changes this time is cleanups and refactorings and
  not much new features, which is nice.

   - Refactorings for generic pin config handling in the core.

   - Factor out a set of device tree utilities for use in all drivers,
     to parse and allocate maps from the device tree.

   - Some fixes to the core such as more nitpicky locking.

   - Pushed down config array iteration into the drivers.

     This patch is necessary for drivers that want to iterate over
     configs and pile up a stack of alterations to the same register(s),
     or if the driver wants to take a local spinlock when committing the
     configuration.

   - A new driver for the Texas Instruments Palmas PMIC by Laxman
     Dewangan.  This is used on the Tegra systems.

   - A major cleanup and modernization of the PFC (Super Hitachi and ARM
     SHmobile) pin controller and subdrivers.

   - Support for the A20 and A31 sunxi (AllWinner) SoCs.

   - A huge pile of fixes and cleanups: Axel Lin, Jingoo Han Dan
     Carpenter, Julia Lawall and Sachin Kamat did an excellent job here"

* tag 'pinctrl-v3.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (124 commits)
  pinctrl: sunxi: Fix off-by-one for valid offset range checking
  pinctrl: sunxi: drop lock on error path
  pinctrl: pinconf-generic: Remove ti prefix in dev_err messages
  pinctrl: rockchip: Implement .request() and .free() callbacks
  pinctrl: at91: fix get_pullup/down function return
  pinctrl: sh-pfc: remove unnecessary platform_set_drvdata()
  pinctrl: Add s5pv210 support to pinctrl-exynos
  pinctrl: utils: include export.h to avoid warnings
  pinctrl: s3c24xx: off by one in s3c24xx_eint_init()
  pinctrl: mvebu: testing the wrong variable
  pinctrl: abx500: fix bitwise AND test
  pinctrl: mvebu: Convert to use devm_ioremap_resource
  pinctrl: Pass all configs to driver on pin_config_set()
  pinctrl: tz1090-pdc: Convert to devm_ioremap_resource
  pinctrl: tz1090: Convert to devm_ioremap_resource
  pinctrl: tegra: Convert to devm_ioremap_resource
  pinctrl: rockchip: Simplify pin_to_bank equation
  pinctrl: spear: Convert to devm_ioremap_resource
  pinctrl: rockchip: Remove of_match_ptr macro for DT only driver
  pinctrl: palmas: PINCTRL_PALMAS needs to select PINMUX
  ...
This commit is contained in:
Linus Torvalds 2013-09-04 16:24:33 -07:00
commit aa7054f5a5
74 changed files with 9309 additions and 5764 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
Documentation/devicetree/bindings/gpio/gpio.txt
View File

@ -75,23 +75,36 @@ Example of two SOC GPIO banks defined as gpio-controller nodes:
gpio-controller;
};
2.1) gpio-controller and pinctrl subsystem
------------------------------------------
2.1) gpio- and pin-controller interaction
-----------------------------------------
gpio-controller on a SOC might be tightly coupled with the pinctrl
subsystem, in the sense that the pins can be used by other functions
together with optional gpio feature.
Some or all of the GPIOs provided by a GPIO controller may be routed to pins
on the package via a pin controller. This allows muxing those pins between
GPIO and other functions.
While the pin allocation is totally managed by the pin ctrl subsystem,
gpio (under gpiolib) is still maintained by gpio drivers. It may happen
that different pin ranges in a SoC is managed by different gpio drivers.
It is useful to represent which GPIOs correspond to which pins on which pin
controllers. The gpio-ranges property described below represents this, and
contains information structures as follows:
This makes it logical to let gpio drivers announce their pin ranges to
the pin ctrl subsystem and call 'pinctrl_request_gpio' in order to
request the corresponding pin before any gpio usage.
gpio-range-list ::= <single-gpio-range> [gpio-range-list]
single-gpio-range ::=
<pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
gpio-phandle : phandle to pin controller node.
gpio-base : Base GPIO ID in the GPIO controller
pinctrl-base : Base pinctrl pin ID in the pin controller
count : The number of GPIOs/pins in this range
For this, the gpio controller can use a pinctrl phandle and pins to
announce the pinrange to the pin ctrl subsystem. For example,
The "pin controller node" mentioned above must conform to the bindings
described in ../pinctrl/pinctrl-bindings.txt.
Previous versions of this binding required all pin controller nodes that
were referenced by any gpio-ranges property to contain a property named
#gpio-range-cells with value <3>. This requirement is now deprecated.
However, that property may still exist in older device trees for
compatibility reasons, and would still be required even in new device
trees that need to be compatible with older software.
Example:
qe_pio_e: gpio-controller@1460 {
#gpio-cells = <2>;
@ -99,16 +112,8 @@ announce the pinrange to the pin ctrl subsystem. For example,
reg = <0x1460 0x18>;
gpio-controller;
gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
};
}
where,
&pinctrl1 and &pinctrl2 is the phandle to the pinctrl DT node.
Next values specify the base pin and number of pins for the range
handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under
pinctrl2 with gpio offset 10 is handled by this gpio controller.
The pinctrl node must have "#gpio-range-cells" property to show number of
arguments to pass with phandle from gpio controllers node.
Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
pins 50..59.

41
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
View File

@ -127,21 +127,20 @@ whether there is any interaction between the child and intermediate parent
nodes, is again defined entirely by the binding for the individual pin
controller device.
== Using generic pinconfig options ==
== Generic pin configuration node content ==
Generic pinconfig parameters can be used by defining a separate node containing
the applicable parameters (and optional values), like:
Many data items that are represented in a pin configuration node are common
and generic. Pin control bindings should use the properties defined below
where they are applicable; not all of these properties are relevant or useful
for all hardware or binding structures. Each individual binding document
should state which of these generic properties, if any, are used, and the
structure of the DT nodes that contain these properties.
pcfg_pull_up: pcfg_pull_up {
bias-pull-up;
drive-strength = <20>;
};
This node should then be referenced in the appropriate pinctrl node as a phandle
and parsed in the driver using the pinconf_generic_parse_dt_config function.
Supported configuration parameters are:
Supported generic properties are:
pins - the list of pins that properties in the node
apply to
function - the mux function to select
bias-disable - disable any pin bias
bias-high-impedance - high impedance mode ("third-state", "floating")
bias-bus-hold - latch weakly
@ -160,7 +159,21 @@ low-power-disable - disable low power mode
output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
Arguments for parameters:
Some of the generic properties take arguments. For those that do, the
arguments are described below.
- pins takes a list of pin names or IDs as a required argument. The specific
binding for the hardware defines:
- Whether the entries are integers or strings, and their meaning.
- function takes a list of function names/IDs as a required argument. The
specific binding for the hardware defines:
- Whether the entries are integers or strings, and their meaning.
- Whether only a single entry is allowed (which is applied to all entries
in the pins property), or whether there may alternatively be one entry per
entry in the pins property, in which case the list lengths must match, and
for each list index i, the function at list index i is applied to the pin
at list index i.
- bias-pull-up, -down and -pin-default take as optional argument on hardware
supporting it the pull strength in Ohm. bias-disable will disable the pull.
@ -170,7 +183,5 @@ Arguments for parameters:
- input-debounce takes the debounce time in usec as argument
or 0 to disable debouncing
All parameters not listed here, do not take an argument.
More in-depth documentation on these parameters can be found in
<include/linux/pinctrl/pinconfig-generic.h>

96
Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt Normal file
View File

@ -0,0 +1,96 @@
Palmas Pincontrol bindings
The pins of Palmas device can be set on different option and provides
the configuration for Pull UP/DOWN, open drain etc.
Required properties:
- compatible: It must be one of following:
- "ti,palmas-pinctrl" for Palma series of the pincontrol.
- "ti,tps65913-pinctrl" for Palma series device TPS65913.
- "ti,tps80036-pinctrl" for Palma series device TPS80036.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Palmas's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
list of pins. This configuration can include the mux function to select on
those pin(s), and various pin configuration parameters, such as pull-up,
open drain.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
Optional properties:
- ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode.
Selection primary or secondary function associated to I2C2_SCL_SCE,
I2C2_SDA_SDO pin/pad for DVFS1 interface
- ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode.
Selection primary or secondary function associated to GPADC_START
and SYSEN2 pin/pad for DVFS2 interface
This binding uses the following generic properties as defined in
pinctrl-bindings.txt:
Required: pins
Options: function, bias-disable, bias-pull-up, bias-pull-down,
bias-pin-default, drive-open-drain.
Note that many of these properties are only valid for certain specific pins.
See the Palmas device datasheet for complete details regarding which pins
support which functionality.
Valid values for pin names are:
gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9,
gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, vac, powergood,
nreswarm, pwrdown, gpadc_start, reset_in, nsleep, enable1, enable2,
int.
Valid value of function names are:
gpio, led, pwm, regen, sysen, clk32kgaudio, id, vbus_det, chrg_det,
vac, vacok, powergood, usb_psel, msecure, pwrhold, int, nreswarm,
simrsto, simrsti, low_vbat, wireless_chrg1, rcm, pwrdown, gpadc_start,
reset_in, nsleep, enable.
There are 4 special functions: opt0, opt1, opt2 and opt3. If any of these
functions is selected then directly pins register will be written with 0, 1, 2
or 3 respectively if it is valid for that pins or list of pins.
Example:
palmas: tps65913 {
....
pinctrl {
compatible = "ti,tps65913-pinctrl";
ti,palmas-enable-dvfs1;
pinctrl-names = "default";
pinctrl-0 = <&palmas_pins_state>;
palmas_pins_state: pinmux {
gpio0 {
pins = "gpio0";
function = "id";
bias-pull-up;
};
vac {
pins = "vac";
function = "vacok";
bias-pull-down;
};
gpio5 {
pins = "gpio5";
function = "opt0";
drive-open-drain = <1>;
};
};
};
....
};

3
Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
View File

@ -12,6 +12,7 @@ Required Properties:
- "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
- "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
- "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
- "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
@ -128,7 +129,7 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
- samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller
found on Samsung S3C64xx SoCs,
- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos4210 SoC.
found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
- interrupt-parent: phandle of the interrupt parent to which the external
wakeup interrupts are forwarded to.
- interrupts: interrupt used by multiplexed wakeup interrupts.

101
Documentation/pinctrl.txt
View File

@ -81,7 +81,7 @@ int __init foo_probe(void)
struct pinctrl_dev *pctl;
pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
if (IS_ERR(pctl))
if (!pctl)
pr_err("could not register foo pin driver\n");
}
@ -795,18 +795,97 @@ special GPIO-handler is registered.
GPIO mode pitfalls
==================
Sometime the developer may be confused by a datasheet talking about a pin
being possible to set into "GPIO mode". It appears that what hardware
engineers mean with "GPIO mode" is not necessarily the use case that is
implied in the kernel interface <linux/gpio.h>: a pin that you grab from
kernel code and then either listen for input or drive high/low to
assert/deassert some external line.
Due to the naming conventions used by hardware engineers, where "GPIO"
is taken to mean different things than what the kernel does, the developer
may be confused by a datasheet talking about a pin being possible to set
into "GPIO mode". It appears that what hardware engineers mean with
"GPIO mode" is not necessarily the use case that is implied in the kernel
interface <linux/gpio.h>: a pin that you grab from kernel code and then
either listen for input or drive high/low to assert/deassert some
external line.
Rather hardware engineers think that "GPIO mode" means that you can
software-control a few electrical properties of the pin that you would
not be able to control if the pin was in some other mode, such as muxed in
for a device.
The GPIO portions of a pin and its relation to a certain pin controller
configuration and muxing logic can be constructed in several ways. Here
are two examples:
(A)
pin config
logic regs
| +- SPI
Physical pins --- pad --- pinmux -+- I2C
| +- mmc
| +- GPIO
pin
multiplex
logic regs
Here some electrical properties of the pin can be configured no matter
whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
pin, you can also drive it high/low from "GPIO" registers.
Alternatively, the pin can be controlled by a certain peripheral, while
still applying desired pin config properties. GPIO functionality is thus
orthogonal to any other device using the pin.
In this arrangement the registers for the GPIO portions of the pin controller,
or the registers for the GPIO hardware module are likely to reside in a
separate memory range only intended for GPIO driving, and the register
range dealing with pin config and pin multiplexing get placed into a
different memory range and a separate section of the data sheet.
(B)
pin config
logic regs
| +- SPI
Physical pins --- pad --- pinmux -+- I2C
| | +- mmc
| |
GPIO pin
multiplex
logic regs
In this arrangement, the GPIO functionality can always be enabled, such that
e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
pulsed out. It is likely possible to disrupt the traffic on the pin by doing
wrong things on the GPIO block, as it is never really disconnected. It is
possible that the GPIO, pin config and pin multiplex registers are placed into
the same memory range and the same section of the data sheet, although that
need not be the case.
From a kernel point of view, however, these are different aspects of the
hardware and shall be put into different subsystems:
- Registers (or fields within registers) that control electrical
properties of the pin such as biasing and drive strength should be
exposed through the pinctrl subsystem, as "pin configuration" settings.
- Registers (or fields within registers) that control muxing of signals
from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
be exposed through the pinctrl subssytem, as mux functions.
- Registers (or fields within registers) that control GPIO functionality
such as setting a GPIO's output value, reading a GPIO's input value, or
setting GPIO pin direction should be exposed through the GPIO subsystem,
and if they also support interrupt capabilities, through the irqchip
abstraction.
Depending on the exact HW register design, some functions exposed by the
GPIO subsystem may call into the pinctrl subsystem in order to
co-ordinate register settings across HW modules. In particular, this may
be needed for HW with separate GPIO and pin controller HW modules, where
e.g. GPIO direction is determined by a register in the pin controller HW
module rather than the GPIO HW module.
Electrical properties of the pin such as biasing and drive strength
may be placed at some pin-specific register in all cases or as part
of the GPIO register in case (B) especially. This doesn't mean that such
properties necessarily pertain to what the Linux kernel calls "GPIO".
Example: a pin is usually muxed in to be used as a UART TX line. But during
system sleep, we need to put this pin into "GPIO mode" and ground it.
@ -856,7 +935,7 @@ static unsigned long uart_sleep_mode[] = {
PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
};
static struct pinctrl_map __initdata pinmap[] = {
static struct pinctrl_map pinmap[] __initdata = {
PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
"u0_group", "u0"),
PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
@ -951,7 +1030,7 @@ Since the above construct is pretty common there is a helper macro to make
it even more compact which assumes you want to use pinctrl-foo and position
0 for mapping, for example:
static struct pinctrl_map __initdata mapping[] = {
static struct pinctrl_map mapping[] __initdata = {
PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
};
@ -970,7 +1049,7 @@ static unsigned long i2c_pin_configs[] = {
FOO_SLEW_RATE_SLOW,
};
static struct pinctrl_map __initdata mapping[] = {
static struct pinctrl_map mapping[] __initdata = {
PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
@ -984,7 +1063,7 @@ order to explicitly indicate that the states were provided and intended to
be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
a named state without causing any pin controller to be programmed:
static struct pinctrl_map __initdata mapping[] = {
static struct pinctrl_map mapping[] __initdata = {
PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
};

2
MAINTAINERS
View File

@ -813,7 +813,7 @@ F: arch/arm/mach-prima2/
F: drivers/dma/sirf-dma.c
F: drivers/i2c/busses/i2c-sirf.c
F: drivers/mmc/host/sdhci-sirf.c
F: drivers/pinctrl/pinctrl-sirf.c
F: drivers/pinctrl/sirf/
F: drivers/spi/spi-sirf.c
ARM/EBSA110 MACHINE SUPPORT

6
arch/arm/boot/dts/atlas6.dtsi
View File

@ -329,6 +329,12 @@
sirf,function = "uart0";
};
};
uart0_noflow_pins_a: uart0@1 {
uart {
sirf,pins = "uart0_nostreamctrlgrp";
sirf,function = "uart0_nostreamctrl";
};
};
uart1_pins_a: uart1@0 {
uart {
sirf,pins = "uart1grp";

15
drivers/pinctrl/Kconfig
View File

@ -61,7 +61,7 @@ config PINCTRL_AT91
config PINCTRL_BAYTRAIL
bool "Intel Baytrail GPIO pin control"
depends on GPIOLIB && ACPI && X86
select IRQ_DOMAIN
select IRQ_DOMAIN
help
driver for memory mapped GPIO functionality on Intel Baytrail
platforms. Supports 3 banks with 102, 28 and 44 gpios.
@ -252,7 +252,7 @@ config PINCTRL_SAMSUNG
config PINCTRL_EXYNOS
bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
depends on OF && GPIOLIB && ARCH_EXYNOS
depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)
select PINCTRL_SAMSUNG
config PINCTRL_EXYNOS5440
@ -261,6 +261,17 @@ config PINCTRL_EXYNOS5440
select PINMUX
select PINCONF
config PINCTRL_PALMAS
bool "Pinctrl driver for the PALMAS Series MFD devices"
depends on OF && MFD_PALMAS
select PINMUX
select GENERIC_PINCONF
help
Palmas device supports the configuration of pins for different
functionality. This driver supports the pinmux, push-pull and
open drain configuration for the Palmas series devices like
TPS65913, TPS80036 etc.
config PINCTRL_S3C24XX
bool "Samsung S3C24XX SoC pinctrl driver"
depends on ARCH_S3C24XX

3
drivers/pinctrl/Makefile
View File

@ -2,7 +2,7 @@
ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG
obj-$(CONFIG_PINCTRL) += core.o
obj-$(CONFIG_PINCTRL) += core.o pinctrl-utils.o
obj-$(CONFIG_PINMUX) += pinmux.o
obj-$(CONFIG_PINCONF) += pinconf.o
ifeq ($(CONFIG_OF),y)
@ -32,6 +32,7 @@ obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/

75
drivers/pinctrl/core.c
View File

@ -153,9 +153,7 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
pin = pctldev->desc->pins[i].number;
desc = pin_desc_get(pctldev, pin);
/* Pin space may be sparse */
if (desc == NULL)
continue;
if (desc->name && !strcmp(name, desc->name))
if (desc && !strcmp(name, desc->name))
return pin;
}
@ -357,14 +355,17 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio)
/* Loop over the pin controllers */
list_for_each_entry(pctldev, &pinctrldev_list, node) {
/* Loop over the ranges */
mutex_lock(&pctldev->mutex);
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
/* Check if any gpio range overlapped with gpio chip */
if (range->base + range->npins - 1 < chip->base ||
range->base > chip->base + chip->ngpio - 1)
continue;
mutex_unlock(&pctldev->mutex);
mutex_unlock(&pinctrldev_list_mutex);
return true;
}
mutex_unlock(&pctldev->mutex);
}
mutex_unlock(&pinctrldev_list_mutex);
@ -392,6 +393,8 @@ static int pinctrl_get_device_gpio_range(unsigned gpio,
{
struct pinctrl_dev *pctldev = NULL;
mutex_lock(&pinctrldev_list_mutex);
/* Loop over the pin controllers */
list_for_each_entry(pctldev, &pinctrldev_list, node) {
struct pinctrl_gpio_range *range;
@ -400,10 +403,13 @@ static int pinctrl_get_device_gpio_range(unsigned gpio,
if (range != NULL) {
*outdev = pctldev;
*outrange = range;
mutex_unlock(&pinctrldev_list_mutex);
return 0;
}
}
mutex_unlock(&pinctrldev_list_mutex);
return -EPROBE_DEFER;
}
@ -556,11 +562,15 @@ int pinctrl_request_gpio(unsigned gpio)
return ret;
}
mutex_lock(&pctldev->mutex);
/* Convert to the pin controllers number space */
pin = gpio_to_pin(range, gpio);
ret = pinmux_request_gpio(pctldev, range, pin, gpio);
mutex_unlock(&pctldev->mutex);
return ret;
}
EXPORT_SYMBOL_GPL(pinctrl_request_gpio);
@ -1227,23 +1237,36 @@ EXPORT_SYMBOL_GPL(pinctrl_force_default);
#ifdef CONFIG_PM
/**
* pinctrl_pm_select_state() - select pinctrl state for PM
* @dev: device to select default state for
* @state: state to set
*/
static int pinctrl_pm_select_state(struct device *dev,
struct pinctrl_state *state)
{
struct dev_pin_info *pins = dev->pins;
int ret;
if (IS_ERR(state))
return 0; /* No such state */
ret = pinctrl_select_state(pins->p, state);
if (ret)
dev_err(dev, "failed to activate pinctrl state %s\n",
state->name);
return ret;
}
/**
* pinctrl_pm_select_default_state() - select default pinctrl state for PM
* @dev: device to select default state for
*/
int pinctrl_pm_select_default_state(struct device *dev)
{
struct dev_pin_info *pins = dev->pins;
int ret;
if (!pins)
if (!dev->pins)
return 0;
if (IS_ERR(pins->default_state))
return 0; /* No default state */
ret = pinctrl_select_state(pins->p, pins->default_state);
if (ret)
dev_err(dev, "failed to activate default pinctrl state\n");
return ret;
return pinctrl_pm_select_state(dev, dev->pins->default_state);
}
EXPORT_SYMBOL_GPL(pinctrl_pm_select_default_state);
@ -1253,17 +1276,10 @@ EXPORT_SYMBOL_GPL(pinctrl_pm_select_default_state);
*/
int pinctrl_pm_select_sleep_state(struct device *dev)
{
struct dev_pin_info *pins = dev->pins;
int ret;
if (!pins)
if (!dev->pins)
return 0;
if (IS_ERR(pins->sleep_state))
return 0; /* No sleep state */
ret = pinctrl_select_state(pins->p, pins->sleep_state);
if (ret)
dev_err(dev, "failed to activate pinctrl sleep state\n");
return ret;
return pinctrl_pm_select_state(dev, dev->pins->sleep_state);
}
EXPORT_SYMBOL_GPL(pinctrl_pm_select_sleep_state);
@ -1273,17 +1289,10 @@ EXPORT_SYMBOL_GPL(pinctrl_pm_select_sleep_state);
*/
int pinctrl_pm_select_idle_state(struct device *dev)
{
struct dev_pin_info *pins = dev->pins;
int ret;
if (!pins)
if (!dev->pins)
return 0;
if (IS_ERR(pins->idle_state))
return 0; /* No idle state */
ret = pinctrl_select_state(pins->p, pins->idle_state);
if (ret)
dev_err(dev, "failed to activate pinctrl idle state\n");
return ret;
return pinctrl_pm_select_state(dev, dev->pins->idle_state);
}
EXPORT_SYMBOL_GPL(pinctrl_pm_select_idle_state);
#endif

39
drivers/pinctrl/mvebu/pinctrl-mvebu.c
View File

@ -191,18 +191,27 @@ static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
}
static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned gid, unsigned long config)
unsigned gid, unsigned long *configs,
unsigned num_configs)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
int i, ret;
if (!grp->ctrl)
return -EINVAL;
if (grp->ctrl->mpp_set)
return grp->ctrl->mpp_set(grp->ctrl, config);
for (i = 0; i < num_configs; i++) {
if (grp->ctrl->mpp_set)
ret = grp->ctrl->mpp_set(grp->ctrl, configs[i]);
else
ret = mvebu_common_mpp_set(pctl, grp, configs[i]);
return mvebu_common_mpp_set(pctl, grp, config);
if (ret)
return ret;
} /* for each config */
return 0;
}
static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
@ -303,6 +312,7 @@ static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid,
struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
struct mvebu_mpp_ctrl_setting *setting;
int ret;
unsigned long config;
setting = mvebu_pinctrl_find_setting_by_name(pctl, grp,
func->name);
@ -313,7 +323,8 @@ static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid,
return -EINVAL;
}
ret = mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
config = setting->val;
ret = mvebu_pinconf_group_set(pctldev, grp->gid, &config, 1);
if (ret) {
dev_err(pctl->dev, "cannot set group %s to %s\n",
func->groups[gid], func->name);
@ -329,6 +340,7 @@ static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mvebu_pinctrl_group *grp;
struct mvebu_mpp_ctrl_setting *setting;
unsigned long config;
grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
if (!grp)
@ -341,7 +353,9 @@ static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
if (!setting)
return -ENOTSUPP;
return mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
config = setting->val;
return mvebu_pinconf_group_set(pctldev, grp->gid, &config, 1);
}
static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
@ -430,7 +444,7 @@ static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
}
*map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
if (map == NULL) {
if (*map == NULL) {
dev_err(pctl->dev,
"cannot allocate pinctrl_map memory for %s\n",
np->name);
@ -579,7 +593,7 @@ static int mvebu_pinctrl_build_functions(struct platform_device *pdev,
int mvebu_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
struct device_node *np = pdev->dev.of_node;
struct resource *res;
struct mvebu_pinctrl *pctl;
void __iomem *base;
struct pinctrl_pin_desc *pdesc;
@ -591,11 +605,10 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
return -EINVAL;
}
base = of_iomap(np, 0);
if (!base) {
dev_err(&pdev->dev, "unable to get base address\n");
return -ENODEV;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
GFP_KERNEL);

96
drivers/pinctrl/pinconf-generic.c
View File

@ -24,6 +24,7 @@
#include <linux/of.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
#ifdef CONFIG_DEBUG_FS
@ -236,4 +237,99 @@ out:
kfree(cfg);
return ret;
}
int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *np, struct pinctrl_map **map,
unsigned *reserved_maps, unsigned *num_maps,
enum pinctrl_map_type type)
{
int ret;
const char *function;
struct device *dev = pctldev->dev;
unsigned long *configs = NULL;
unsigned num_configs = 0;
unsigned reserve;
struct property *prop;
const char *group;
ret = of_property_read_string(np, "function", &function);
if (ret < 0) {
/* EINVAL=missing, which is fine since it's optional */
if (ret != -EINVAL)
dev_err(dev, "could not parse property function\n");
function = NULL;
}
ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs);
if (ret < 0) {
dev_err(dev, "could not parse node property\n");
return ret;
}
reserve = 0;
if (function != NULL)
reserve++;
if (num_configs)
reserve++;
ret = of_property_count_strings(np, "pins");
if (ret < 0) {
dev_err(dev, "could not parse property pins\n");
goto exit;
}
reserve *= ret;
ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
num_maps, reserve);
if (ret < 0)
goto exit;
of_property_for_each_string(np, "pins", prop, group) {
if (function) {
ret = pinctrl_utils_add_map_mux(pctldev, map,
reserved_maps, num_maps, group,
function);
if (ret < 0)
goto exit;
}
if (num_configs) {
ret = pinctrl_utils_add_map_configs(pctldev, map,
reserved_maps, num_maps, group, configs,
num_configs, type);
if (ret < 0)
goto exit;
}
}
ret = 0;
exit:
kfree(configs);
return ret;
}
EXPORT_SYMBOL_GPL(pinconf_generic_dt_subnode_to_map);
int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config, struct pinctrl_map **map,
unsigned *num_maps, enum pinctrl_map_type type)
{
unsigned reserved_maps;
struct device_node *np;
int ret;
reserved_maps = 0;
*map = NULL;
*num_maps = 0;
for_each_child_of_node(np_config, np) {
ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps, type);
if (ret < 0) {
pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
return ret;
}
}
return 0;
}
EXPORT_SYMBOL_GPL(pinconf_generic_dt_node_to_map);
#endif

73
drivers/pinctrl/pinconf.c
View File

@ -158,7 +158,7 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinconf_ops *ops = pctldev->desc->confops;
int i, ret;
int ret;
if (!ops) {
dev_err(pctldev->dev, "missing confops\n");
@ -171,17 +171,15 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting)
dev_err(pctldev->dev, "missing pin_config_set op\n");
return -EINVAL;
}
for (i = 0; i < setting->data.configs.num_configs; i++) {
ret = ops->pin_config_set(pctldev,
setting->data.configs.group_or_pin,
setting->data.configs.configs[i]);
if (ret < 0) {
dev_err(pctldev->dev,
"pin_config_set op failed for pin %d config %08lx\n",
setting->data.configs.group_or_pin,
setting->data.configs.configs[i]);
return ret;
}
ret = ops->pin_config_set(pctldev,
setting->data.configs.group_or_pin,
setting->data.configs.configs,
setting->data.configs.num_configs);
if (ret < 0) {
dev_err(pctldev->dev,
"pin_config_set op failed for pin %d\n",
setting->data.configs.group_or_pin);
return ret;
}
break;
case PIN_MAP_TYPE_CONFIGS_GROUP:
@ -190,17 +188,15 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting)
"missing pin_config_group_set op\n");
return -EINVAL;
}
for (i = 0; i < setting->data.configs.num_configs; i++) {
ret = ops->pin_config_group_set(pctldev,
setting->data.configs.group_or_pin,
setting->data.configs.configs[i]);
if (ret < 0) {
dev_err(pctldev->dev,
"pin_config_group_set op failed for group %d config %08lx\n",
setting->data.configs.group_or_pin,
setting->data.configs.configs[i]);
return ret;
}
ret = ops->pin_config_group_set(pctldev,
setting->data.configs.group_or_pin,
setting->data.configs.configs,
setting->data.configs.num_configs);
if (ret < 0) {
dev_err(pctldev->dev,
"pin_config_group_set op failed for group %d\n",
setting->data.configs.group_or_pin);
return ret;
}
break;
default:
@ -428,12 +424,11 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
{
struct pinctrl_maps *maps_node;
const struct pinctrl_map *map;
struct pinctrl_dev *pctldev = NULL;
const struct pinctrl_map *found = NULL;
struct pinctrl_dev *pctldev;
const struct pinconf_ops *confops = NULL;
const struct pinctrl_map_configs *configs;
struct dbg_cfg *dbg = &pinconf_dbg_conf;
int i, j;
bool found = false;
unsigned long config;
mutex_lock(&pinctrl_maps_mutex);
@ -450,14 +445,8 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
for (j = 0; j < map->data.configs.num_configs; j++) {
if (!strcmp(map->data.configs.group_or_pin,
dbg->pin_name)) {
/*
* We found the right pin / state, read the
* config and he pctldev for later use
*/
configs = &map->data.configs;
pctldev = get_pinctrl_dev_from_devname
(map->ctrl_dev_name);
found = true;
/* We found the right pin / state */
found = map;
break;
}
}
@ -473,7 +462,8 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
goto exit;
}
config = *(configs->configs);
pctldev = get_pinctrl_dev_from_devname(found->ctrl_dev_name);
config = *found->data.configs.configs;
seq_printf(s, "Dev %s has config of %s in state %s: 0x%08lX\n",
dbg->dev_name, dbg->pin_name,
dbg->state_name, config);
@ -505,12 +495,12 @@ static int pinconf_dbg_config_write(struct file *file,
{
struct pinctrl_maps *maps_node;
const struct pinctrl_map *map;
struct pinctrl_dev *pctldev = NULL;
const struct pinctrl_map *found = NULL;
struct pinctrl_dev *pctldev;
const struct pinconf_ops *confops = NULL;
struct dbg_cfg *dbg = &pinconf_dbg_conf;
const struct pinctrl_map_configs *configs;
char config[MAX_NAME_LEN+1];
bool found = false;
char buf[128];
char *b = &buf[0];
int buf_size;
@ -518,7 +508,7 @@ static int pinconf_dbg_config_write(struct file *file,
int i;
/* Get userspace string and assure termination */
buf_size = min(count, (sizeof(buf)-1));
buf_size = min(count, (size_t)(sizeof(buf)-1));
if (copy_from_user(buf, user_buf, buf_size))
return -EFAULT;
buf[buf_size] = 0;
@ -588,10 +578,7 @@ static int pinconf_dbg_config_write(struct file *file,
/* we found the right pin / state, so overwrite config */
if (!strcmp(map->data.configs.group_or_pin, dbg->pin_name)) {
found = true;
pctldev = get_pinctrl_dev_from_devname(
map->ctrl_dev_name);
configs = &map->data.configs;
found = map;
break;
}
}
@ -601,10 +588,12 @@ static int pinconf_dbg_config_write(struct file *file,
goto exit;
}
pctldev = get_pinctrl_dev_from_devname(found->ctrl_dev_name);
if (pctldev)
confops = pctldev->desc->confops;
if (confops && confops->pin_config_dbg_parse_modify) {
configs = &found->data.configs;
for (i = 0; i < configs->num_configs; i++) {
confops->pin_config_dbg_parse_modify(pctldev,
config,

183
drivers/pinctrl/pinctrl-abx500.c
View File

@ -426,7 +426,7 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
ret = abx500_gpio_set_bits(chip,
AB8500_GPIO_ALTFUN_REG,
af.alt_bit2,
!!(af.alta_val && BIT(1)));
!!(af.alta_val & BIT(1)));
} else
ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
offset, 1);
@ -447,7 +447,7 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
ret = abx500_gpio_set_bits(chip,
AB8500_GPIO_ALTFUN_REG,
af.alt_bit2,
!!(af.altb_val && BIT(1)));
!!(af.altb_val & BIT(1)));
break;
case ABX500_ALT_C:
@ -457,7 +457,7 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
goto out;
ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
af.alt_bit2, !!(af.altc_val && BIT(0)));
af.alt_bit2, !!(af.altc_val & BIT(0)));
if (ret < 0)
goto out;
@ -1041,98 +1041,115 @@ static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long config)
unsigned long *configs,
unsigned num_configs)
{
struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
struct gpio_chip *chip = &pct->chip;
unsigned offset;
int ret = -EINVAL;
enum pin_config_param param = pinconf_to_config_param(config);
enum pin_config_param argument = pinconf_to_config_argument(config);
int i;
enum pin_config_param param;
enum pin_config_param argument;
dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n",
pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
(param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") :
(argument ? "pull up" : "pull down"));
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
argument = pinconf_to_config_argument(configs[i]);
/* on ABx500, there is no GPIO0, so adjust the offset */
offset = pin - 1;
dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n",
pin, configs[i],
(param == PIN_CONFIG_OUTPUT) ? "output " : "input",
(param == PIN_CONFIG_OUTPUT) ?
(argument ? "high" : "low") :
(argument ? "pull up" : "pull down"));
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ret = abx500_gpio_direction_input(chip, offset);
if (ret < 0)
goto out;
/*
* Some chips only support pull down, while some actually
* support both pull up and pull down. Such chips have
* a "pullud" range specified for the pins that support
* both features. If the pin is not within that range, we
* fall back to the old bit set that only support pull down.
*/
if (abx500_pullud_supported(chip, pin))
ret = abx500_set_pull_updown(pct,
pin,
ABX500_GPIO_PULL_NONE);
else
/* Chip only supports pull down */
ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
offset, ABX500_GPIO_PULL_NONE);
break;
/* on ABx500, there is no GPIO0, so adjust the offset */
offset = pin - 1;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = abx500_gpio_direction_input(chip, offset);
if (ret < 0)
goto out;
/*
* if argument = 1 set the pull down
* else clear the pull down
* Some chips only support pull down, while some actually
* support both pull up and pull down. Such chips have
* a "pullud" range specified for the pins that support
* both features. If the pin is not within that range, we
* fall back to the old bit set that only support pull down.
*/
if (abx500_pullud_supported(chip, pin))
ret = abx500_set_pull_updown(pct,
pin,
argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
else
/* Chip only supports pull down */
ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
offset,
argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
break;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ret = abx500_gpio_direction_input(chip, offset);
if (ret < 0)
goto out;
/*
* Some chips only support pull down, while some
* actually support both pull up and pull down. Such
* chips have a "pullud" range specified for the pins
* that support both features. If the pin is not
* within that range, we fall back to the old bit set
* that only support pull down.
*/
if (abx500_pullud_supported(chip, pin))
ret = abx500_set_pull_updown(pct,
pin,
ABX500_GPIO_PULL_NONE);
else
/* Chip only supports pull down */
ret = abx500_gpio_set_bits(chip,
AB8500_GPIO_PUD1_REG, offset,
ABX500_GPIO_PULL_NONE);
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = abx500_gpio_direction_input(chip, offset);
if (ret < 0)
goto out;
/*
* if argument = 1 set the pull up
* else clear the pull up
*/
ret = abx500_gpio_direction_input(chip, offset);
/*
* Some chips only support pull down, while some actually
* support both pull up and pull down. Such chips have
* a "pullud" range specified for the pins that support
* both features. If the pin is not within that range, do
* nothing
*/
if (abx500_pullud_supported(chip, pin))
ret = abx500_set_pull_updown(pct,
pin,
argument ? ABX500_GPIO_PULL_UP : ABX500_GPIO_PULL_NONE);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = abx500_gpio_direction_input(chip, offset);
if (ret < 0)
goto out;
/*
* if argument = 1 set the pull down
* else clear the pull down
* Some chips only support pull down, while some
* actually support both pull up and pull down. Such
* chips have a "pullud" range specified for the pins
* that support both features. If the pin is not
* within that range, we fall back to the old bit set
* that only support pull down.
*/
if (abx500_pullud_supported(chip, pin))
ret = abx500_set_pull_updown(pct,
pin,
argument ? ABX500_GPIO_PULL_DOWN :
ABX500_GPIO_PULL_NONE);
else
/* Chip only supports pull down */
ret = abx500_gpio_set_bits(chip,
AB8500_GPIO_PUD1_REG,
offset,
argument ? ABX500_GPIO_PULL_DOWN :
ABX500_GPIO_PULL_NONE);
break;
case PIN_CONFIG_OUTPUT:
ret = abx500_gpio_direction_output(chip, offset, argument);
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = abx500_gpio_direction_input(chip, offset);
if (ret < 0)
goto out;
/*
* if argument = 1 set the pull up
* else clear the pull up
*/
ret = abx500_gpio_direction_input(chip, offset);
/*
* Some chips only support pull down, while some
* actually support both pull up and pull down. Such
* chips have a "pullud" range specified for the pins
* that support both features. If the pin is not
* within that range, do nothing
*/
if (abx500_pullud_supported(chip, pin))
ret = abx500_set_pull_updown(pct,
pin,
argument ? ABX500_GPIO_PULL_UP :
ABX500_GPIO_PULL_NONE);
break;
default:
dev_err(chip->dev, "illegal configuration requested\n");
}
case PIN_CONFIG_OUTPUT:
ret = abx500_gpio_direction_output(chip, offset,
argument);
break;
default:
dev_err(chip->dev, "illegal configuration requested\n");
}
} /* for each config */
out:
if (ret < 0)
dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);

62
drivers/pinctrl/pinctrl-at91.c
View File

@ -325,7 +325,7 @@ static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
{
return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1;
return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
}
static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
@ -445,7 +445,7 @@ static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
{
return (__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1;
return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1);
}
static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
@ -736,30 +736,40 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
}
static int at91_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long config)
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
unsigned mask;
void __iomem *pio;
int i;
unsigned long config;
dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config);
pio = pin_to_controller(info, pin_to_bank(pin_id));
mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
for (i = 0; i < num_configs; i++) {
config = configs[i];
if (config & PULL_UP && config & PULL_DOWN)
return -EINVAL;
dev_dbg(info->dev,
"%s:%d, pin_id=%d, config=0x%lx",
__func__, __LINE__, pin_id, config);
pio = pin_to_controller(info, pin_to_bank(pin_id));
mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
at91_mux_set_pullup(pio, mask, config & PULL_UP);
at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
if (info->ops->set_deglitch)
info->ops->set_deglitch(pio, mask, config & DEGLITCH);
if (info->ops->set_debounce)
info->ops->set_debounce(pio, mask, config & DEBOUNCE,
if (config & PULL_UP && config & PULL_DOWN)
return -EINVAL;
at91_mux_set_pullup(pio, mask, config & PULL_UP);
at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
if (info->ops->set_deglitch)
info->ops->set_deglitch(pio, mask, config & DEGLITCH);
if (info->ops->set_debounce)
info->ops->set_debounce(pio, mask, config & DEBOUNCE,
(config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
if (info->ops->set_pulldown)
info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
info->ops->disable_schmitt_trig(pio, mask);
if (info->ops->set_pulldown)
info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
info->ops->disable_schmitt_trig(pio, mask);
} /* for each config */
return 0;
}
@ -1241,18 +1251,22 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
switch (type) {
case IRQ_TYPE_EDGE_RISING:
irq_set_handler(d->irq, handle_simple_irq);
writel_relaxed(mask, pio + PIO_ESR);
writel_relaxed(mask, pio + PIO_REHLSR);
break;
case IRQ_TYPE_EDGE_FALLING:
irq_set_handler(d->irq, handle_simple_irq);
writel_relaxed(mask, pio + PIO_ESR);
writel_relaxed(mask, pio + PIO_FELLSR);
break;
case IRQ_TYPE_LEVEL_LOW:
irq_set_handler(d->irq, handle_level_irq);
writel_relaxed(mask, pio + PIO_LSR);
writel_relaxed(mask, pio + PIO_FELLSR);
break;
case IRQ_TYPE_LEVEL_HIGH:
irq_set_handler(d->irq, handle_level_irq);
writel_relaxed(mask, pio + PIO_LSR);
writel_relaxed(mask, pio + PIO_REHLSR);
break;
@ -1261,6 +1275,7 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
* disable additional interrupt modes:
* fall back to default behavior
*/
irq_set_handler(d->irq, handle_simple_irq);
writel_relaxed(mask, pio + PIO_AIMDR);
return 0;
case IRQ_TYPE_NONE:
@ -1402,6 +1417,8 @@ static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct at91_gpio_chip *at91_gpio = h->host_data;
void __iomem *pio = at91_gpio->regbase;
u32 mask = 1 << hw;
irq_set_lockdep_class(virq, &gpio_lock_class);
@ -1409,8 +1426,13 @@ static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
* Can use the "simple" and not "edge" handler since it's
* shorter, and the AIC handles interrupts sanely.
*/
irq_set_chip_and_handler(virq, &gpio_irqchip,
handle_simple_irq);
irq_set_chip(virq, &gpio_irqchip);
if ((at91_gpio->ops == &at91sam9x5_ops) &&
(readl_relaxed(pio + PIO_AIMMR) & mask) &&
(readl_relaxed(pio + PIO_ELSR) & mask))
irq_set_handler(virq, handle_level_irq);
else
irq_set_handler(virq, handle_simple_irq);
set_irq_flags(virq, IRQF_VALID);
irq_set_chip_data(virq, at91_gpio);

41
drivers/pinctrl/pinctrl-baytrail.c
View File

@ -130,25 +130,25 @@ struct byt_gpio {
struct pinctrl_gpio_range *range;
};
#define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
int reg)
{
struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
struct byt_gpio *vg = to_byt_gpio(chip);
u32 reg_offset;
void __iomem *ptr;
if (reg == BYT_INT_STAT_REG)
reg_offset = (offset / 32) * 4;
else
reg_offset = vg->range->pins[offset] * 16;
ptr = (void __iomem *) (vg->reg_base + reg_offset + reg);
return ptr;
return vg->reg_base + reg_offset + reg;
}
static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
struct byt_gpio *vg = to_byt_gpio(chip);
pm_runtime_get(&vg->pdev->dev);
@ -157,7 +157,7 @@ static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
{
struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
struct byt_gpio *vg = to_byt_gpio(chip);
void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
u32 value;
@ -218,7 +218,7 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
struct byt_gpio *vg = to_byt_gpio(chip);
void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
unsigned long flags;
u32 old_val;
@ -237,7 +237,7 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
struct byt_gpio *vg = to_byt_gpio(chip);
void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
unsigned long flags;
u32 value;
@ -245,7 +245,7 @@ static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
spin_lock_irqsave(&vg->lock, flags);
value = readl(reg) | BYT_DIR_MASK;
value = value & (~BYT_INPUT_EN); /* active low */
value &= ~BYT_INPUT_EN; /* active low */
writel(value, reg);
spin_unlock_irqrestore(&vg->lock, flags);
@ -256,16 +256,20 @@ static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
static int byt_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
struct byt_gpio *vg = to_byt_gpio(chip);
void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
unsigned long flags;
u32 reg_val;
spin_lock_irqsave(&vg->lock, flags);
reg_val = readl(reg) | (BYT_DIR_MASK | !!value);
reg_val &= ~(BYT_OUTPUT_EN | !value);
writel(reg_val, reg);
reg_val = readl(reg) | BYT_DIR_MASK;
reg_val &= ~BYT_OUTPUT_EN;
if (value)
writel(reg_val | BYT_LEVEL, reg);
else
writel(reg_val & ~BYT_LEVEL, reg);
spin_unlock_irqrestore(&vg->lock, flags);
@ -274,7 +278,7 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
struct byt_gpio *vg = to_byt_gpio(chip);
int i;
unsigned long flags;
u32 conf0, val, offs;
@ -294,16 +298,16 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
val & BYT_LEVEL ? "hi" : "lo",
vg->range->pins[i], offs,
conf0 & 0x7,
conf0 & BYT_TRIG_NEG ? "fall " : "",
conf0 & BYT_TRIG_POS ? "rise " : "",
conf0 & BYT_TRIG_LVL ? "lvl " : "");
conf0 & BYT_TRIG_NEG ? " fall" : "",
conf0 & BYT_TRIG_POS ? " rise" : "",
conf0 & BYT_TRIG_LVL ? " level" : "");
}
spin_unlock_irqrestore(&vg->lock, flags);
}
static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
struct byt_gpio *vg = to_byt_gpio(chip);
return irq_create_mapping(vg->domain, offset);
}
@ -516,6 +520,7 @@ static int byt_gpio_remove(struct platform_device *pdev)
{
struct byt_gpio *vg = platform_get_drvdata(pdev);
int err;
pm_runtime_disable(&pdev->dev);
err = gpiochip_remove(&vg->chip);
if (err)

39
drivers/pinctrl/pinctrl-bcm2835.c
View File

@ -893,28 +893,35 @@ static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
}
static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long config)
unsigned pin, unsigned long *configs,
unsigned num_configs)
{
struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
enum bcm2835_pinconf_param param = BCM2835_PINCONF_UNPACK_PARAM(config);
u16 arg = BCM2835_PINCONF_UNPACK_ARG(config);
enum bcm2835_pinconf_param param;
u16 arg;
u32 off, bit;
int i;
if (param != BCM2835_PINCONF_PARAM_PULL)
return -EINVAL;
for (i = 0; i < num_configs; i++) {
param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]);
arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]);
off = GPIO_REG_OFFSET(pin);
bit = GPIO_REG_SHIFT(pin);
if (param != BCM2835_PINCONF_PARAM_PULL)
return -EINVAL;
bcm2835_gpio_wr(pc, GPPUD, arg & 3);
/*
* Docs say to wait 150 cycles, but not of what. We assume a
* 1 MHz clock here, which is pretty slow...
*/
udelay(150);
bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
udelay(150);
bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
off = GPIO_REG_OFFSET(pin);
bit = GPIO_REG_SHIFT(pin);
bcm2835_gpio_wr(pc, GPPUD, arg & 3);
/*
* Docs say to wait 150 cycles, but not of what. We assume a
* 1 MHz clock here, which is pretty slow...
*/
udelay(150);
bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
udelay(150);
bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
} /* for each config */
return 0;
}

58
drivers/pinctrl/pinctrl-exynos.c
View File

@ -660,6 +660,64 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
exynos_pinctrl_resume_bank(drvdata, bank);
}
/* pin banks of s5pv210 pin-controller */
static struct samsung_pin_bank s5pv210_pin_bank[] = {
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpe0", 0x1c),
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpf0", 0x24),
EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf3", 0x30),
EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
};
struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
{
/* pin-controller instance 0 data */
.pin_banks = s5pv210_pin_bank,
.nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
.weint_con = EXYNOS_WKUP_ECON_OFFSET,
.weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
.weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
.svc = EXYNOS_SVC_OFFSET,
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.label = "s5pv210-gpio-ctrl0",
},
};
/* pin banks of exynos4210 pin-controller 0 */
static struct samsung_pin_bank exynos4210_pin_banks0[] = {
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),

107
drivers/pinctrl/pinctrl-exynos5440.c
View File

@ -401,64 +401,71 @@ static const struct pinmux_ops exynos5440_pinmux_ops = {
/* set the pin config settings for a specified pin */
static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long config)
unsigned long *configs,
unsigned num_configs)
{
struct exynos5440_pinctrl_priv_data *priv;
void __iomem *base;
enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(config);
u32 cfg_value = PINCFG_UNPACK_VALUE(config);
enum pincfg_type cfg_type;
u32 cfg_value;
u32 data;
int i;
priv = pinctrl_dev_get_drvdata(pctldev);
base = priv->reg_base;
switch (cfg_type) {
case PINCFG_TYPE_PUD:
/* first set pull enable/disable bit */
data = readl(base + GPIO_PE);
data &= ~(1 << pin);
if (cfg_value)
data |= (1 << pin);
writel(data, base + GPIO_PE);
for (i = 0; i < num_configs; i++) {
cfg_type = PINCFG_UNPACK_TYPE(configs[i]);
cfg_value = PINCFG_UNPACK_VALUE(configs[i]);
/* then set pull up/down bit */
data = readl(base + GPIO_PS);
data &= ~(1 << pin);
if (cfg_value == 2)
data |= (1 << pin);
writel(data, base + GPIO_PS);
break;
switch (cfg_type) {
case PINCFG_TYPE_PUD:
/* first set pull enable/disable bit */
data = readl(base + GPIO_PE);
data &= ~(1 << pin);
if (cfg_value)
data |= (1 << pin);
writel(data, base + GPIO_PE);
case PINCFG_TYPE_DRV:
/* set the first bit of the drive strength */
data = readl(base + GPIO_DS0);
data &= ~(1 << pin);
data |= ((cfg_value & 1) << pin);
writel(data, base + GPIO_DS0);
cfg_value >>= 1;
/* then set pull up/down bit */
data = readl(base + GPIO_PS);
data &= ~(1 << pin);
if (cfg_value == 2)
data |= (1 << pin);
writel(data, base + GPIO_PS);
break;
/* set the second bit of the driver strength */
data = readl(base + GPIO_DS1);
data &= ~(1 << pin);
data |= ((cfg_value & 1) << pin);
writel(data, base + GPIO_DS1);
break;
case PINCFG_TYPE_SKEW_RATE:
data = readl(base + GPIO_SR);
data &= ~(1 << pin);
data |= ((cfg_value & 1) << pin);
writel(data, base + GPIO_SR);
break;
case PINCFG_TYPE_INPUT_TYPE:
data = readl(base + GPIO_TYPE);
data &= ~(1 << pin);
data |= ((cfg_value & 1) << pin);
writel(data, base + GPIO_TYPE);
break;
default:
WARN_ON(1);
return -EINVAL;
}
case PINCFG_TYPE_DRV:
/* set the first bit of the drive strength */
data = readl(base + GPIO_DS0);
data &= ~(1 << pin);
data |= ((cfg_value & 1) << pin);
writel(data, base + GPIO_DS0);
cfg_value >>= 1;
/* set the second bit of the driver strength */
data = readl(base + GPIO_DS1);
data &= ~(1 << pin);
data |= ((cfg_value & 1) << pin);
writel(data, base + GPIO_DS1);
break;
case PINCFG_TYPE_SKEW_RATE:
data = readl(base + GPIO_SR);
data &= ~(1 << pin);
data |= ((cfg_value & 1) << pin);
writel(data, base + GPIO_SR);
break;
case PINCFG_TYPE_INPUT_TYPE:
data = readl(base + GPIO_TYPE);
data &= ~(1 << pin);
data |= ((cfg_value & 1) << pin);
writel(data, base + GPIO_TYPE);
break;
default:
WARN_ON(1);
return -EINVAL;
}
} /* for each config */
return 0;
}
@ -510,7 +517,8 @@ static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
/* set the pin config settings for a specified pin group */
static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long config)
unsigned group, unsigned long *configs,
unsigned num_configs)
{
struct exynos5440_pinctrl_priv_data *priv;
const unsigned int *pins;
@ -520,7 +528,8 @@ static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
pins = priv->pin_groups[group].pins;
for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
exynos5440_pinconf_set(pctldev, pins[cnt], config);
exynos5440_pinconf_set(pctldev, pins[cnt], configs,
num_configs);
return 0;
}

66
drivers/pinctrl/pinctrl-falcon.c
View File

@ -75,6 +75,7 @@ enum falcon_mux {
FALCON_MUX_GPIO = 0,
FALCON_MUX_RST,
FALCON_MUX_NTR,
FALCON_MUX_PPS,
FALCON_MUX_MDIO,
FALCON_MUX_LED,
FALCON_MUX_SPI,
@ -114,7 +115,7 @@ static struct ltq_mfp_pin falcon_mfp[] = {
MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE),
MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE),
MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE),
MFP_FALCON(GPIO5, NTR, GPIO, NONE, NONE),
MFP_FALCON(GPIO5, NTR, GPIO, PPS, NONE),
MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE),
MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE),
MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE),
@ -168,6 +169,7 @@ static struct ltq_mfp_pin falcon_mfp[] = {
static const unsigned pins_por[] = {GPIO0};
static const unsigned pins_ntr[] = {GPIO4};
static const unsigned pins_ntr8k[] = {GPIO5};
static const unsigned pins_pps[] = {GPIO5};
static const unsigned pins_hrst[] = {GPIO6};
static const unsigned pins_mdio[] = {GPIO7, GPIO8};
static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
@ -186,6 +188,7 @@ static struct ltq_pin_group falcon_grps[] = {
GRP_MUX("por", RST, pins_por),
GRP_MUX("ntr", NTR, pins_ntr),
GRP_MUX("ntr8k", NTR, pins_ntr8k),
GRP_MUX("pps", PPS, pins_pps),
GRP_MUX("hrst", RST, pins_hrst),
GRP_MUX("mdio", MDIO, pins_mdio),
GRP_MUX("bootled", LED, pins_bled),
@ -201,7 +204,7 @@ static struct ltq_pin_group falcon_grps[] = {
};
static const char * const ltq_rst_grps[] = {"por", "hrst"};
static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k"};
static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k", "pps"};
static const char * const ltq_mdio_grps[] = {"mdio"};
static const char * const ltq_bled_grps[] = {"bootled"};
static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
@ -235,7 +238,8 @@ static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
}
static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
unsigned group, unsigned long config)
unsigned group, unsigned long *configs,
unsigned num_configs)
{
return -ENOTSUPP;
}
@ -276,39 +280,47 @@ static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
}
static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
unsigned pin, unsigned long config)
unsigned pin, unsigned long *configs,
unsigned num_configs)
{
enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config);
int arg = LTQ_PINCONF_UNPACK_ARG(config);
enum ltq_pinconf_param param;
int arg;
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
void __iomem *mem = info->membase[PORT(pin)];
u32 reg;
int i;
switch (param) {
case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
reg = LTQ_PADC_DCC;
break;
for (i = 0; i < num_configs; i++) {
param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
case LTQ_PINCONF_PARAM_SLEW_RATE:
reg = LTQ_PADC_SRC;
break;
switch (param) {
case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
reg = LTQ_PADC_DCC;
break;
case LTQ_PINCONF_PARAM_PULL:
if (arg == 1)
reg = LTQ_PADC_PDEN;
else
reg = LTQ_PADC_PUEN;
break;
case LTQ_PINCONF_PARAM_SLEW_RATE:
reg = LTQ_PADC_SRC;
break;
default:
pr_err("%s: Invalid config param %04x\n",
pinctrl_dev_get_name(pctrldev), param);
return -ENOTSUPP;
}
case LTQ_PINCONF_PARAM_PULL:
if (arg == 1)
reg = LTQ_PADC_PDEN;
else
reg = LTQ_PADC_PUEN;
break;
default:
pr_err("%s: Invalid config param %04x\n",
pinctrl_dev_get_name(pctrldev), param);
return -ENOTSUPP;
}
pad_w32(mem, BIT(PORT_PIN(pin)), reg);
if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
return -ENOTSUPP;
} /* for each config */
pad_w32(mem, BIT(PORT_PIN(pin)), reg);
if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
return -ENOTSUPP;
return 0;
}

177
drivers/pinctrl/pinctrl-imx.c
View File

@ -27,18 +27,6 @@
#include "core.h"
#include "pinctrl-imx.h"
#define IMX_PMX_DUMP(info, p, m, c, n) \
{ \
int i, j; \
printk(KERN_DEBUG "Format: Pin Mux Config\n"); \
for (i = 0; i < n; i++) { \
j = p[i]; \
printk(KERN_DEBUG "%s %d 0x%lx\n", \
info->pins[j].name, \
m[i], c[i]); \
} \
}
/* The bits in CONFIG cell defined in binding doc*/
#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
#define IMX_PAD_SION 0x40000000 /* set SION */
@ -98,7 +86,7 @@ static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
if (selector >= info->ngroups)
return -EINVAL;
*pins = info->groups[selector].pins;
*pins = info->groups[selector].pin_ids;
*npins = info->groups[selector].npins;
return 0;
@ -134,7 +122,7 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
}
for (i = 0; i < grp->npins; i++) {
if (!(grp->configs[i] & IMX_NO_PAD_CTL))
if (!(grp->pins[i].config & IMX_NO_PAD_CTL))
map_num++;
}
@ -159,11 +147,11 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
/* create config map */
new_map++;
for (i = j = 0; i < grp->npins; i++) {
if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) {
new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, grp->pins[i]);
new_map[j].data.configs.configs = &grp->configs[i];
pin_get_name(pctldev, grp->pins[i].pin);
new_map[j].data.configs.configs = &grp->pins[i].config;
new_map[j].data.configs.num_configs = 1;
j++;
}
@ -197,28 +185,23 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
const unsigned *pins, *mux, *input_val;
u16 *input_reg;
unsigned int npins, pin_id;
int i;
struct imx_pin_group *grp;
/*
* Configure the mux mode for each pin in the group for a specific
* function.
*/
pins = info->groups[group].pins;
npins = info->groups[group].npins;
mux = info->groups[group].mux_mode;
input_val = info->groups[group].input_val;
input_reg = info->groups[group].input_reg;
WARN_ON(!pins || !npins || !mux || !input_val || !input_reg);
grp = &info->groups[group];
npins = grp->npins;
dev_dbg(ipctl->dev, "enable function %s group %s\n",
info->functions[selector].name, info->groups[group].name);
info->functions[selector].name, grp->name);
for (i = 0; i < npins; i++) {
pin_id = pins[i];
struct imx_pin *pin = &grp->pins[i];
pin_id = pin->pin;
pin_reg = &info->pin_regs[pin_id];
if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
@ -231,20 +214,50 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
u32 reg;
reg = readl(ipctl->base + pin_reg->mux_reg);
reg &= ~(0x7 << 20);
reg |= (mux[i] << 20);
reg |= (pin->mux_mode << 20);
writel(reg, ipctl->base + pin_reg->mux_reg);
} else {
writel(mux[i], ipctl->base + pin_reg->mux_reg);
writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
}
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
pin_reg->mux_reg, mux[i]);
pin_reg->mux_reg, pin->mux_mode);
/* some pins also need select input setting, set it if found */
if (input_reg[i]) {
writel(input_val[i], ipctl->base + input_reg[i]);
/*
* If the select input value begins with 0xff, it's a quirky
* select input and the value should be interpreted as below.
* 31 23 15 7 0
* | 0xff | shift | width | select |
* It's used to work around the problem that the select
* input for some pin is not implemented in the select
* input register but in some general purpose register.
* We encode the select input value, width and shift of
* the bit field into input_val cell of pin function ID
* in device tree, and then decode them here for setting
* up the select input bits in general purpose register.
*/
if (pin->input_val >> 24 == 0xff) {
u32 val = pin->input_val;
u8 select = val & 0xff;
u8 width = (val >> 8) & 0xff;
u8 shift = (val >> 16) & 0xff;
u32 mask = ((1 << width) - 1) << shift;
/*
* The input_reg[i] here is actually some IOMUXC general
* purpose register, not regular select input register.
*/
val = readl(ipctl->base + pin->input_val);
val &= ~mask;
val |= select << shift;
writel(val, ipctl->base + pin->input_val);
} else if (pin->input_val) {
/*
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
writel(pin->input_val, ipctl->base + pin->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
input_reg[i], input_val[i]);
pin->input_reg, pin->input_val);
}
}
@ -310,11 +323,13 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
}
static int imx_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long config)
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
int i;
if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
dev_err(info->dev, "Pin(%s) does not support config function\n",
@ -325,17 +340,19 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
dev_dbg(ipctl->dev, "pinconf set pin %s\n",
info->pins[pin_id].name);
if (info->flags & SHARE_MUX_CONF_REG) {
u32 reg;
reg = readl(ipctl->base + pin_reg->conf_reg);
reg &= ~0xffff;
reg |= config;
writel(reg, ipctl->base + pin_reg->conf_reg);
} else {
writel(config, ipctl->base + pin_reg->conf_reg);
}
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
pin_reg->conf_reg, config);
for (i = 0; i < num_configs; i++) {
if (info->flags & SHARE_MUX_CONF_REG) {
u32 reg;
reg = readl(ipctl->base + pin_reg->conf_reg);
reg &= ~0xffff;
reg |= configs[i];
writel(reg, ipctl->base + pin_reg->conf_reg);
} else {
writel(configs[i], ipctl->base + pin_reg->conf_reg);
}
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
pin_reg->conf_reg, configs[i]);
} /* for each config */
return 0;
}
@ -373,8 +390,9 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
seq_printf(s, "\n");
grp = &info->groups[group];
for (i = 0; i < grp->npins; i++) {
name = pin_get_name(pctldev, grp->pins[i]);
ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
struct imx_pin *pin = &grp->pins[i];
name = pin_get_name(pctldev, pin->pin);
ret = imx_pinconf_get(pctldev, pin->pin, &config);
if (ret)
return;
seq_printf(s, "%s: 0x%lx", name, config);
@ -426,28 +444,31 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
* do sanity check and calculate pins number
*/
list = of_get_property(np, "fsl,pins", &size);
if (!list) {
dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
return -EINVAL;
}
/* we do not check return since it's safe node passed down */
if (!size || size % pin_size) {
dev_err(info->dev, "Invalid fsl,pins property\n");
dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
return -EINVAL;
}
grp->npins = size / pin_size;
grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin),
GFP_KERNEL);
grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
GFP_KERNEL);
grp->input_reg = devm_kzalloc(info->dev, grp->npins * sizeof(u16),
GFP_KERNEL);
grp->input_val = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
GFP_KERNEL);
grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
GFP_KERNEL);
if (!grp->pins || ! grp->pin_ids)
return -ENOMEM;
for (i = 0; i < grp->npins; i++) {
u32 mux_reg = be32_to_cpu(*list++);
u32 conf_reg;
unsigned int pin_id;
struct imx_pin_reg *pin_reg;
struct imx_pin *pin = &grp->pins[i];
if (info->flags & SHARE_MUX_CONF_REG)
conf_reg = mux_reg;
@ -456,23 +477,23 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
pin_reg = &info->pin_regs[pin_id];
grp->pins[i] = pin_id;
pin->pin = pin_id;
grp->pin_ids[i] = pin_id;
pin_reg->mux_reg = mux_reg;
pin_reg->conf_reg = conf_reg;
grp->input_reg[i] = be32_to_cpu(*list++);
grp->mux_mode[i] = be32_to_cpu(*list++);
grp->input_val[i] = be32_to_cpu(*list++);
pin->input_reg = be32_to_cpu(*list++);
pin->mux_mode = be32_to_cpu(*list++);
pin->input_val = be32_to_cpu(*list++);
/* SION bit is in mux register */
config = be32_to_cpu(*list++);
if (config & IMX_PAD_SION)
grp->mux_mode[i] |= IOMUXC_CONFIG_SION;
grp->configs[i] = config & ~IMX_PAD_SION;
}
pin->mux_mode |= IOMUXC_CONFIG_SION;
pin->config = config & ~IMX_PAD_SION;
#ifdef DEBUG
IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
#endif
dev_dbg(info->dev, "%s: %d 0x%08lx", info->pins[i].name,
pin->mux_mode, pin->config);
}
return 0;
}
@ -484,7 +505,6 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
struct device_node *child;
struct imx_pmx_func *func;
struct imx_pin_group *grp;
int ret;
static u32 grp_index;
u32 i = 0;
@ -496,7 +516,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
func->name = np->name;
func->num_groups = of_get_child_count(np);
if (func->num_groups <= 0) {
dev_err(info->dev, "no groups defined\n");
dev_err(info->dev, "no groups defined in %s\n", np->full_name);
return -EINVAL;
}
func->groups = devm_kzalloc(info->dev,
@ -505,9 +525,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
for_each_child_of_node(np, child) {
func->groups[i] = child->name;
grp = &info->groups[grp_index++];
ret = imx_pinctrl_parse_groups(child, grp, info, i++);
if (ret)
return ret;
imx_pinctrl_parse_groups(child, grp, info, i++);
}
return 0;
@ -518,7 +536,6 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
{
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
int ret;
u32 nfuncs = 0;
u32 i = 0;
@ -545,13 +562,8 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
if (!info->groups)
return -ENOMEM;
for_each_child_of_node(np, child) {
ret = imx_pinctrl_parse_functions(child, info, i++);
if (ret) {
dev_err(&pdev->dev, "failed to parse function\n");
return ret;
}
}
for_each_child_of_node(np, child)
imx_pinctrl_parse_functions(child, info, i++);
return 0;
}
@ -580,9 +592,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENOENT;
ipctl->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);

36
drivers/pinctrl/pinctrl-imx.h
View File

@ -17,30 +17,36 @@
struct platform_device;
/**
* struct imx_pin_group - describes a single i.MX pin
* @pin: the pin_id of this pin
* @mux_mode: the mux mode for this pin.
* @input_reg: the select input register offset for this pin if any
* 0 if no select input setting needed.
* @input_val: the select input value for this pin.
* @configs: the config for this pin.
*/
struct imx_pin {
unsigned int pin;
unsigned int mux_mode;
u16 input_reg;
unsigned int input_val;
unsigned long config;
};
/**
* struct imx_pin_group - describes an IMX pin group
* @name: the name of this specific pin group
* @pins: an array of discrete physical pins used in this group, taken
* from the driver-local pin enumeration space
* @npins: the number of pins in this group array, i.e. the number of
* elements in .pins so we can iterate over that array
* @mux_mode: the mux mode for each pin in this group. The size of this
* array is the same as pins.
* @input_reg: select input register offset for this mux if any
* 0 if no select input setting needed.
* @input_val: the select input value for each pin in this group. The size of
* this array is the same as pins.
* @configs: the config for each pin in this group. The size of this
* array is the same as pins.
* @pin_ids: array of pin_ids. pinctrl forces us to maintain such an array
* @pins: array of pins
*/
struct imx_pin_group {
const char *name;
unsigned int *pins;
unsigned npins;
unsigned int *mux_mode;
u16 *input_reg;
unsigned int *input_val;
unsigned long *configs;
unsigned int *pin_ids;
struct imx_pin *pins;
};
/**

85
drivers/pinctrl/pinctrl-mxs.c
View File

@ -233,7 +233,8 @@ static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
}
static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long config)
unsigned pin, unsigned long *configs,
unsigned num_configs)
{
return -ENOTSUPP;
}
@ -249,7 +250,8 @@ static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
}
static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long config)
unsigned group, unsigned long *configs,
unsigned num_configs)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
struct mxs_group *g = &d->soc->groups[group];
@ -257,49 +259,56 @@ static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
u8 ma, vol, pull, bank, shift;
u16 pin;
u32 i;
int n;
unsigned long config;
ma = CONFIG_TO_MA(config);
vol = CONFIG_TO_VOL(config);
pull = CONFIG_TO_PULL(config);
for (n = 0; n < num_configs; n++) {
config = configs[n];
for (i = 0; i < g->npins; i++) {
bank = PINID_TO_BANK(g->pins[i]);
pin = PINID_TO_PIN(g->pins[i]);
ma = CONFIG_TO_MA(config);
vol = CONFIG_TO_VOL(config);
pull = CONFIG_TO_PULL(config);
/* drive */
reg = d->base + d->soc->regs->drive;
reg += bank * 0x40 + pin / 8 * 0x10;
for (i = 0; i < g->npins; i++) {
bank = PINID_TO_BANK(g->pins[i]);
pin = PINID_TO_PIN(g->pins[i]);
/* mA */
if (config & MA_PRESENT) {
shift = pin % 8 * 4;
writel(0x3 << shift, reg + CLR);
writel(ma << shift, reg + SET);
/* drive */
reg = d->base + d->soc->regs->drive;
reg += bank * 0x40 + pin / 8 * 0x10;
/* mA */
if (config & MA_PRESENT) {
shift = pin % 8 * 4;
writel(0x3 << shift, reg + CLR);
writel(ma << shift, reg + SET);
}
/* vol */
if (config & VOL_PRESENT) {
shift = pin % 8 * 4 + 2;
if (vol)
writel(1 << shift, reg + SET);
else
writel(1 << shift, reg + CLR);
}
/* pull */
if (config & PULL_PRESENT) {
reg = d->base + d->soc->regs->pull;
reg += bank * 0x10;
shift = pin;
if (pull)
writel(1 << shift, reg + SET);
else
writel(1 << shift, reg + CLR);
}
}
/* vol */
if (config & VOL_PRESENT) {
shift = pin % 8 * 4 + 2;
if (vol)
writel(1 << shift, reg + SET);
else
writel(1 << shift, reg + CLR);
}
/* cache the config value for mxs_pinconf_group_get() */
g->config = config;
/* pull */
if (config & PULL_PRESENT) {
reg = d->base + d->soc->regs->pull;
reg += bank * 0x10;
shift = pin;
if (pull)
writel(1 << shift, reg + SET);
else
writel(1 << shift, reg + CLR);
}
}
/* cache the config value for mxs_pinconf_group_get() */
g->config = config;
} /* for each config */
return 0;
}

425
drivers/pinctrl/pinctrl-nomadik.c
View File

@ -337,97 +337,6 @@ static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
}
static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
{
static const char *afnames[] = {
[NMK_GPIO_ALT_GPIO] = "GPIO",
[NMK_GPIO_ALT_A] = "A",
[NMK_GPIO_ALT_B] = "B",
[NMK_GPIO_ALT_C] = "C"
};
static const char *pullnames[] = {
[NMK_GPIO_PULL_NONE] = "none",
[NMK_GPIO_PULL_UP] = "up",
[NMK_GPIO_PULL_DOWN] = "down",
[3] /* illegal */ = "??"
};
static const char *slpmnames[] = {
[NMK_GPIO_SLPM_INPUT] = "input/wakeup",
[NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
};
int pin = PIN_NUM(cfg);
int pull = PIN_PULL(cfg);
int af = PIN_ALT(cfg);
int slpm = PIN_SLPM(cfg);
int output = PIN_DIR(cfg);
int val = PIN_VAL(cfg);
bool glitch = af == NMK_GPIO_ALT_C;
dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
output ? "output " : "input",
output ? (val ? "high" : "low") : "");
if (sleep) {
int slpm_pull = PIN_SLPM_PULL(cfg);
int slpm_output = PIN_SLPM_DIR(cfg);
int slpm_val = PIN_SLPM_VAL(cfg);
af = NMK_GPIO_ALT_GPIO;
/*
* The SLPM_* values are normal values + 1 to allow zero to
* mean "same as normal".
*/
if (slpm_pull)
pull = slpm_pull - 1;
if (slpm_output)
output = slpm_output - 1;
if (slpm_val)
val = slpm_val - 1;
dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
pin,
slpm_pull ? pullnames[pull] : "same",
slpm_output ? (output ? "output" : "input") : "same",
slpm_val ? (val ? "high" : "low") : "same");
}
if (output)
__nmk_gpio_make_output(nmk_chip, offset, val);
else {
__nmk_gpio_make_input(nmk_chip, offset);
__nmk_gpio_set_pull(nmk_chip, offset, pull);
}
__nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
/*
* If the pin is switching to altfunc, and there was an interrupt
* installed on it which has been lazy disabled, actually mask the
* interrupt to prevent spurious interrupts that would occur while the
* pin is under control of the peripheral. Only SKE does this.
*/
if (af != NMK_GPIO_ALT_GPIO)
nmk_gpio_disable_lazy_irq(nmk_chip, offset);
/*
* If we've backed up the SLPM registers (glitch workaround), modify
* the backups since they will be restored.
*/
if (slpmregs) {
if (slpm == NMK_GPIO_SLPM_NOCHANGE)
slpmregs[nmk_chip->bank] |= BIT(offset);
else
slpmregs[nmk_chip->bank] &= ~BIT(offset);
} else
__nmk_gpio_set_slpm(nmk_chip, offset, slpm);
__nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
}
/*
* Safe sequence used to switch IOs between GPIO and Alternate-C mode:
* - Save SLPM registers
@ -474,210 +383,6 @@ static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
}
}
static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
{
static unsigned int slpm[NUM_BANKS];
unsigned long flags;
bool glitch = false;
int ret = 0;
int i;
for (i = 0; i < num; i++) {
if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
glitch = true;
break;
}
}
spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
if (glitch) {
memset(slpm, 0xff, sizeof(slpm));
for (i = 0; i < num; i++) {
int pin = PIN_NUM(cfgs[i]);
int offset = pin % NMK_GPIO_PER_CHIP;
if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
}
nmk_gpio_glitch_slpm_init(slpm);
}
for (i = 0; i < num; i++) {
struct nmk_gpio_chip *nmk_chip;
int pin = PIN_NUM(cfgs[i]);
nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
if (!nmk_chip) {
ret = -EINVAL;
break;
}
clk_enable(nmk_chip->clk);
spin_lock(&nmk_chip->lock);
__nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
cfgs[i], sleep, glitch ? slpm : NULL);
spin_unlock(&nmk_chip->lock);
clk_disable(nmk_chip->clk);
}
if (glitch)
nmk_gpio_glitch_slpm_restore(slpm);
spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
return ret;
}
/**
* nmk_config_pin - configure a pin's mux attributes
* @cfg: pin confguration
* @sleep: Non-zero to apply the sleep mode configuration
* Configures a pin's mode (alternate function or GPIO), its pull up status,
* and its sleep mode based on the specified configuration. The @cfg is
* usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
* are constructed using, and can be further enhanced with, the macros in
* <linux/platform_data/pinctrl-nomadik.h>
*
* If a pin's mode is set to GPIO, it is configured as an input to avoid
* side-effects. The gpio can be manipulated later using standard GPIO API
* calls.
*/
int nmk_config_pin(pin_cfg_t cfg, bool sleep)
{
return __nmk_config_pins(&cfg, 1, sleep);
}
EXPORT_SYMBOL(nmk_config_pin);
/**
* nmk_config_pins - configure several pins at once
* @cfgs: array of pin configurations
* @num: number of elments in the array
*
* Configures several pins using nmk_config_pin(). Refer to that function for
* further information.
*/
int nmk_config_pins(pin_cfg_t *cfgs, int num)
{
return __nmk_config_pins(cfgs, num, false);
}
EXPORT_SYMBOL(nmk_config_pins);
int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
{
return __nmk_config_pins(cfgs, num, true);
}
EXPORT_SYMBOL(nmk_config_pins_sleep);
/**
* nmk_gpio_set_slpm() - configure the sleep mode of a pin
* @gpio: pin number
* @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
*
* This register is actually in the pinmux layer, not the GPIO block itself.
* The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
* mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
* Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
* HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
* When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
* the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
*
* If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
* mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
* entered) regardless of the altfunction selected. Also wake-up detection is
* ENABLED.
*
* If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
* controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
* (for altfunction GPIO) or respective on-chip peripherals (for other
* altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
*
* Note that enable_irq_wake() will automatically enable wakeup detection.
*/
int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
{
struct nmk_gpio_chip *nmk_chip;
unsigned long flags;
nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
if (!nmk_chip)
return -EINVAL;
clk_enable(nmk_chip->clk);
spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
spin_lock(&nmk_chip->lock);
__nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
spin_unlock(&nmk_chip->lock);
spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
clk_disable(nmk_chip->clk);
return 0;
}
/**
* nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
* @gpio: pin number
* @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
*
* Enables/disables pull up/down on a specified pin. This only takes effect if
* the pin is configured as an input (either explicitly or by the alternate
* function).
*
* NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
* configured as an input. Otherwise, due to the way the controller registers
* work, this function will change the value output on the pin.
*/
int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
{
struct nmk_gpio_chip *nmk_chip;
unsigned long flags;
nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
if (!nmk_chip)
return -EINVAL;
clk_enable(nmk_chip->clk);
spin_lock_irqsave(&nmk_chip->lock, flags);
__nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
spin_unlock_irqrestore(&nmk_chip->lock, flags);
clk_disable(nmk_chip->clk);
return 0;
}
/* Mode functions */
/**
* nmk_gpio_set_mode() - set the mux mode of a gpio pin
* @gpio: pin number
* @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
* NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
*
* Sets the mode of the specified pin to one of the alternate functions or
* plain GPIO.
*/
int nmk_gpio_set_mode(int gpio, int gpio_mode)
{
struct nmk_gpio_chip *nmk_chip;
unsigned long flags;
nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
if (!nmk_chip)
return -EINVAL;
clk_enable(nmk_chip->clk);
spin_lock_irqsave(&nmk_chip->lock, flags);
__nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
spin_unlock_irqrestore(&nmk_chip->lock, flags);
clk_disable(nmk_chip->clk);
return 0;
}
EXPORT_SYMBOL(nmk_gpio_set_mode);
static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
{
int i;
@ -1350,10 +1055,6 @@ static int nmk_gpio_probe(struct platform_device *dev)
pdata->num_gpio = NMK_GPIO_PER_CHIP;
}
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (!res)
return -ENOENT;
irq = platform_get_irq(dev, 0);
if (irq < 0)
return irq;
@ -1362,6 +1063,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
if (secondary_irq >= 0 && !pdata->get_secondary_status)
return -EINVAL;
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&dev->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
@ -1807,7 +1509,7 @@ static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
const struct nmk_pingroup *g;
static unsigned int slpm[NUM_BANKS];
unsigned long flags;
unsigned long flags = 0;
bool glitch;
int ret = -EINVAL;
int i;
@ -1993,7 +1695,7 @@ static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
}
static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long config)
unsigned long *configs, unsigned num_configs)
{
static const char *pullnames[] = {
[NMK_GPIO_PULL_NONE] = "none",
@ -2010,20 +1712,9 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
struct pinctrl_gpio_range *range;
struct gpio_chip *chip;
unsigned bit;
/*
* The pin config contains pin number and altfunction fields, here
* we just ignore that part. It's being handled by the framework and
* pinmux callback respectively.
*/
pin_cfg_t cfg = (pin_cfg_t) config;
int pull = PIN_PULL(cfg);
int slpm = PIN_SLPM(cfg);
int output = PIN_DIR(cfg);
int val = PIN_VAL(cfg);
bool lowemi = PIN_LOWEMI(cfg);
bool gpiomode = PIN_GPIOMODE(cfg);
bool sleep = PIN_SLEEPMODE(cfg);
pin_cfg_t cfg;
int pull, slpm, output, val, i;
bool lowemi, gpiomode, sleep;
range = nmk_match_gpio_range(pctldev, pin);
if (!range) {
@ -2038,54 +1729,74 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
chip = range->gc;
nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
if (sleep) {
int slpm_pull = PIN_SLPM_PULL(cfg);
int slpm_output = PIN_SLPM_DIR(cfg);
int slpm_val = PIN_SLPM_VAL(cfg);
/* All pins go into GPIO mode at sleep */
gpiomode = true;
for (i = 0; i < num_configs; i++) {
/*
* The SLPM_* values are normal values + 1 to allow zero to
* mean "same as normal".
* The pin config contains pin number and altfunction fields,
* here we just ignore that part. It's being handled by the
* framework and pinmux callback respectively.
*/
if (slpm_pull)
pull = slpm_pull - 1;
if (slpm_output)
output = slpm_output - 1;
if (slpm_val)
val = slpm_val - 1;
cfg = (pin_cfg_t) configs[i];
pull = PIN_PULL(cfg);
slpm = PIN_SLPM(cfg);
output = PIN_DIR(cfg);
val = PIN_VAL(cfg);
lowemi = PIN_LOWEMI(cfg);
gpiomode = PIN_GPIOMODE(cfg);
sleep = PIN_SLEEPMODE(cfg);
dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
pin,
slpm_pull ? pullnames[pull] : "same",
slpm_output ? (output ? "output" : "input") : "same",
slpm_val ? (val ? "high" : "low") : "same");
}
if (sleep) {
int slpm_pull = PIN_SLPM_PULL(cfg);
int slpm_output = PIN_SLPM_DIR(cfg);
int slpm_val = PIN_SLPM_VAL(cfg);
dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
pin, cfg, pullnames[pull], slpmnames[slpm],
output ? "output " : "input",
output ? (val ? "high" : "low") : "",
lowemi ? "on" : "off");
/* All pins go into GPIO mode at sleep */
gpiomode = true;
clk_enable(nmk_chip->clk);
bit = pin % NMK_GPIO_PER_CHIP;
if (gpiomode)
/* No glitch when going to GPIO mode */
__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
if (output)
__nmk_gpio_make_output(nmk_chip, bit, val);
else {
__nmk_gpio_make_input(nmk_chip, bit);
__nmk_gpio_set_pull(nmk_chip, bit, pull);
}
/* TODO: isn't this only applicable on output pins? */
__nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
/*
* The SLPM_* values are normal values + 1 to allow zero
* to mean "same as normal".
*/
if (slpm_pull)
pull = slpm_pull - 1;
if (slpm_output)
output = slpm_output - 1;
if (slpm_val)
val = slpm_val - 1;
dev_dbg(nmk_chip->chip.dev,
"pin %d: sleep pull %s, dir %s, val %s\n",
pin,
slpm_pull ? pullnames[pull] : "same",
slpm_output ? (output ? "output" : "input")
: "same",
slpm_val ? (val ? "high" : "low") : "same");
}
dev_dbg(nmk_chip->chip.dev,
"pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
pin, cfg, pullnames[pull], slpmnames[slpm],
output ? "output " : "input",
output ? (val ? "high" : "low") : "",
lowemi ? "on" : "off");
clk_enable(nmk_chip->clk);
bit = pin % NMK_GPIO_PER_CHIP;
if (gpiomode)
/* No glitch when going to GPIO mode */
__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
if (output)
__nmk_gpio_make_output(nmk_chip, bit, val);
else {
__nmk_gpio_make_input(nmk_chip, bit);
__nmk_gpio_set_pull(nmk_chip, bit, pull);
}
/* TODO: isn't this only applicable on output pins? */
__nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
__nmk_gpio_set_slpm(nmk_chip, bit, slpm);
clk_disable(nmk_chip->clk);
} /* for each config */
__nmk_gpio_set_slpm(nmk_chip, bit, slpm);
clk_disable(nmk_chip->clk);
return 0;
}

1095
drivers/pinctrl/pinctrl-palmas.c Normal file
View File

File diff suppressed because it is too large Load Diff

100
drivers/pinctrl/pinctrl-rockchip.c
View File

@ -36,7 +36,7 @@
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "core.h"
@ -167,18 +167,14 @@ static const inline struct rockchip_pin_group *pinctrl_name_to_group(
const struct rockchip_pinctrl *info,
const char *name)
{
const struct rockchip_pin_group *grp = NULL;
int i;
for (i = 0; i < info->ngroups; i++) {
if (strcmp(info->groups[i].name, name))
continue;
grp = &info->groups[i];
break;
if (!strcmp(info->groups[i].name, name))
return &info->groups[i];
}
return grp;
return NULL;
}
/*
@ -190,8 +186,7 @@ static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
{
struct rockchip_pin_bank *b = info->ctrl->pin_banks;
while ((pin >= b->pin_base) &&
((b->pin_base + b->nr_pins - 1) < pin))
while (pin >= (b->pin_base + b->nr_pins))
b++;
return b;
@ -204,17 +199,12 @@ static struct rockchip_pin_bank *bank_num_to_bank(
struct rockchip_pin_bank *b = info->ctrl->pin_banks;
int i;
for (i = 0; i < info->ctrl->nr_banks; i++) {
for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
if (b->bank_num == num)
break;
b++;
return b;
}
if (b->bank_num != num)
return ERR_PTR(-EINVAL);
return b;
return ERR_PTR(-EINVAL);
}
/*
@ -584,32 +574,45 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
/* set the pin config settings for a specified pin */
static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long config)
unsigned long *configs, unsigned num_configs)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
enum pin_config_param param = pinconf_to_config_param(config);
u16 arg = pinconf_to_config_argument(config);
enum pin_config_param param;
u16 arg;
int i;
int rc;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
return rockchip_set_pull(bank, pin - bank->pin_base, param);
break;
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
if (!rockchip_pinconf_pull_valid(info->ctrl, param))
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
rc = rockchip_set_pull(bank, pin - bank->pin_base,
param);
if (rc)
return rc;
break;
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
if (!rockchip_pinconf_pull_valid(info->ctrl, param))
return -ENOTSUPP;
if (!arg)
return -EINVAL;
rc = rockchip_set_pull(bank, pin - bank->pin_base,
param);
if (rc)
return rc;
break;
default:
return -ENOTSUPP;
if (!arg)
return -EINVAL;
return rockchip_set_pull(bank, pin - bank->pin_base, param);
break;
default:
return -ENOTSUPP;
break;
}
break;
}
} /* for each config */
return 0;
}
@ -881,6 +884,16 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
* GPIO handling
*/
static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
{
return pinctrl_request_gpio(chip->base + offset);
}
static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
{
pinctrl_free_gpio(chip->base + offset);
}
static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
{
struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
@ -954,6 +967,8 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
}
static const struct gpio_chip rockchip_gpiolib_chip = {
.request = rockchip_gpio_request,
.free = rockchip_gpio_free,
.set = rockchip_gpio_set,
.get = rockchip_gpio_get,
.direction_input = rockchip_gpio_direction_input,
@ -1270,11 +1285,6 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
info->dev = dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "cannot find IO resource\n");
return -ENOENT;
}
info->reg_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(info->reg_base))
return PTR_ERR(info->reg_base);
@ -1379,7 +1389,7 @@ static struct platform_driver rockchip_pinctrl_driver = {
.driver = {
.name = "rockchip-pinctrl",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(rockchip_pinctrl_dt_match),
.of_match_table = rockchip_pinctrl_dt_match,
},
};

2
drivers/pinctrl/pinctrl-s3c24xx.c
View File

@ -549,7 +549,7 @@ static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
irq = bank->eint_offset;
mask = bank->eint_mask;
for (pin = 0; mask; ++pin, mask >>= 1) {
if (irq > NUM_EINT)
if (irq >= NUM_EINT)
break;
if (!(mask & 1))
continue;

29
drivers/pinctrl/pinctrl-samsung.c
View File

@ -442,9 +442,17 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
/* set the pin config settings for a specified pin */
static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long config)
unsigned long *configs, unsigned num_configs)
{
return samsung_pinconf_rw(pctldev, pin, &config, true);
int i, ret;
for (i = 0; i < num_configs; i++) {
ret = samsung_pinconf_rw(pctldev, pin, &configs[i], true);
if (ret < 0)
return ret;
} /* for each config */
return 0;
}
/* get the pin config settings for a specified pin */
@ -456,7 +464,8 @@ static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
/* set the pin config settings for a specified pin group */
static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long config)
unsigned group, unsigned long *configs,
unsigned num_configs)
{
struct samsung_pinctrl_drv_data *drvdata;
const unsigned int *pins;
@ -466,7 +475,7 @@ static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev,
pins = drvdata->pin_groups[group].pins;
for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++)
samsung_pinconf_set(pctldev, pins[cnt], config);
samsung_pinconf_set(pctldev, pins[cnt], configs, num_configs);
return 0;
}
@ -767,6 +776,10 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
}
}
ret = samsung_pinctrl_parse_dt(pdev, drvdata);
if (ret)
return ret;
drvdata->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, drvdata);
if (!drvdata->pctl_dev) {
dev_err(&pdev->dev, "could not register pinctrl driver\n");
@ -784,12 +797,6 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange);
}
ret = samsung_pinctrl_parse_dt(pdev, drvdata);
if (ret) {
pinctrl_unregister(drvdata->pctl_dev);
return ret;
}
return 0;
}
@ -1115,6 +1122,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = (void *)exynos5250_pin_ctrl },
{ .compatible = "samsung,exynos5420-pinctrl",
.data = (void *)exynos5420_pin_ctrl },
{ .compatible = "samsung,s5pv210-pinctrl",
.data = (void *)s5pv210_pin_ctrl },
#endif
#ifdef CONFIG_PINCTRL_S3C64XX
{ .compatible = "samsung,s3c64xx-pinctrl",

1
drivers/pinctrl/pinctrl-samsung.h
View File

@ -260,5 +260,6 @@ extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
extern struct samsung_pin_ctrl s3c2416_pin_ctrl[];
extern struct samsung_pin_ctrl s3c2440_pin_ctrl[];
extern struct samsung_pin_ctrl s3c2450_pin_ctrl[];
extern struct samsung_pin_ctrl s5pv210_pin_ctrl[];
#endif /* __PINCTRL_SAMSUNG_H */

33
drivers/pinctrl/pinctrl-single.c
View File

@ -209,7 +209,7 @@ struct pcs_device {
static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *config);
static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long config);
unsigned long *configs, unsigned num_configs);
static enum pin_config_param pcs_bias[] = {
PIN_CONFIG_BIAS_PULL_DOWN,
@ -536,7 +536,7 @@ static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
int i;
for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
config = pinconf_to_config_packed(pcs_bias[i], 0);
pcs_pinconf_set(pctldev, pin, config);
pcs_pinconf_set(pctldev, pin, &config, 1);
}
}
@ -622,22 +622,28 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
}
static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long config)
unsigned pin, unsigned long *configs,
unsigned num_configs)
{
struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
struct pcs_function *func;
unsigned offset = 0, shift = 0, i, data, ret;
u16 arg;
int j;
ret = pcs_get_function(pctldev, pin, &func);
if (ret)
return ret;
for (i = 0; i < func->nconfs; i++) {
if (pinconf_to_config_param(config) == func->conf[i].param) {
for (j = 0; j < num_configs; j++) {
for (i = 0; i < func->nconfs; i++) {
if (pinconf_to_config_param(configs[j])
!= func->conf[i].param)
continue;
offset = pin * (pcs->width / BITS_PER_BYTE);
data = pcs->read(pcs->base + offset);
arg = pinconf_to_config_argument(config);
arg = pinconf_to_config_argument(configs[j]);
switch (func->conf[i].param) {
/* 2 parameters */
case PIN_CONFIG_INPUT_SCHMITT:
@ -667,10 +673,14 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
return -ENOTSUPP;
}
pcs->write(data, pcs->base + offset);
return 0;
break;
}
}
return -ENOTSUPP;
if (i >= func->nconfs)
return -ENOTSUPP;
} /* for each config */
return 0;
}
static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
@ -695,7 +705,8 @@ static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
}
static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long config)
unsigned group, unsigned long *configs,
unsigned num_configs)
{
const unsigned *pins;
unsigned npins;
@ -705,7 +716,7 @@ static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
if (ret)
return ret;
for (i = 0; i < npins; i++) {
if (pcs_pinconf_set(pctldev, pins[i], config))
if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
return -ENOTSUPP;
}
return 0;

27
drivers/pinctrl/pinctrl-st.c
View File

@ -288,8 +288,8 @@ struct st_pinctrl {
/* SOC specific data */
/* STiH415 data */
unsigned int stih415_input_delays[] = {0, 500, 1000, 1500};
unsigned int stih415_output_delays[] = {0, 1000, 2000, 3000};
static unsigned int stih415_input_delays[] = {0, 500, 1000, 1500};
static unsigned int stih415_output_delays[] = {0, 1000, 2000, 3000};
#define STIH415_PCTRL_COMMON_DATA \
.rt_style = st_retime_style_packed, \
@ -324,7 +324,7 @@ static const struct st_pctl_data stih415_right_data = {
};
/* STiH416 data */
unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250, 1500,
static unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250, 1500,
1750, 2000, 2250, 2500, 2750, 3000, 3250 };
static const struct st_pctl_data stih416_data = {
@ -811,7 +811,7 @@ static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
return info->nfunctions;
}
const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
@ -909,15 +909,18 @@ static void st_pinconf_set_retime(struct st_pinctrl *info,
config, pin);
}
static int st_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long config)
static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *configs, unsigned num_configs)
{
int pin = st_gpio_pin(pin_id);
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
int i;
st_pinconf_set_config(pc, pin, config);
st_pinconf_set_retime(info, pc, pin, config);
for (i = 0; i < num_configs; i++) {
st_pinconf_set_config(pc, pin, configs[i]);
st_pinconf_set_retime(info, pc, pin, configs[i]);
} /* for each config */
return 0;
}
@ -1222,11 +1225,9 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
if (of_address_to_resource(np, 0, &res))
return -ENODEV;
bank->base = devm_request_and_ioremap(dev, &res);
if (!bank->base) {
dev_err(dev, "Can't get IO memory mapping!\n");
return -ENODEV;
}
bank->base = devm_ioremap_resource(dev, &res);
if (IS_ERR(bank->base))
return PTR_ERR(bank->base);
bank->gpio_chip = st_gpio_template;
bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;

1848
drivers/pinctrl/pinctrl-sunxi-pins.h
View File

File diff suppressed because it is too large Load Diff

99
drivers/pinctrl/pinctrl-sunxi.c
View File

@ -175,7 +175,7 @@ static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
}
*map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
if (!map)
if (!*map)
return -ENOMEM;
of_property_for_each_string(node, "allwinner,pins", prop, group) {
@ -274,7 +274,8 @@ static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
unsigned group,
unsigned long config)
unsigned long *configs,
unsigned num_configs)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sunxi_pinctrl_group *g = &pctl->groups[group];
@ -282,56 +283,52 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
u32 val, mask;
u16 strength;
u8 dlevel;
int i;
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_DRIVE_STRENGTH:
strength = pinconf_to_config_argument(config);
if (strength > 40)
return -EINVAL;
/*
* We convert from mA to what the register expects:
* 0: 10mA
* 1: 20mA
* 2: 30mA
* 3: 40mA
*/
dlevel = strength / 10 - 1;
spin_lock_irqsave(&pctl->lock, flags);
spin_lock_irqsave(&pctl->lock, flags);
for (i = 0; i < num_configs; i++) {
switch (pinconf_to_config_param(configs[i])) {
case PIN_CONFIG_DRIVE_STRENGTH:
strength = pinconf_to_config_argument(configs[i]);
if (strength > 40) {
spin_unlock_irqrestore(&pctl->lock, flags);
return -EINVAL;
}
/*
* We convert from mA to what the register expects:
* 0: 10mA
* 1: 20mA
* 2: 30mA
* 3: 40mA
*/
dlevel = strength / 10 - 1;
val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
writel((val & ~mask)
| dlevel << sunxi_dlevel_offset(g->pin),
pctl->membase + sunxi_dlevel_reg(g->pin));
break;
case PIN_CONFIG_BIAS_PULL_UP:
val = readl(pctl->membase + sunxi_pull_reg(g->pin));
mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
pctl->membase + sunxi_pull_reg(g->pin));
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
val = readl(pctl->membase + sunxi_pull_reg(g->pin));
mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
pctl->membase + sunxi_pull_reg(g->pin));
break;
default:
break;
}
/* cache the config value */
g->config = configs[i];
} /* for each config */
val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin),
pctl->membase + sunxi_dlevel_reg(g->pin));
spin_unlock_irqrestore(&pctl->lock, flags);
break;
case PIN_CONFIG_BIAS_PULL_UP:
spin_lock_irqsave(&pctl->lock, flags);
val = readl(pctl->membase + sunxi_pull_reg(g->pin));
mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
pctl->membase + sunxi_pull_reg(g->pin));
spin_unlock_irqrestore(&pctl->lock, flags);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
spin_lock_irqsave(&pctl->lock, flags);
val = readl(pctl->membase + sunxi_pull_reg(g->pin));
mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
pctl->membase + sunxi_pull_reg(g->pin));
spin_unlock_irqrestore(&pctl->lock, flags);
break;
default:
break;
}
/* cache the config value */
g->config = config;
spin_unlock_irqrestore(&pctl->lock, flags);
return 0;
}
@ -524,7 +521,7 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
struct sunxi_desc_function *desc;
if (offset > chip->ngpio)
if (offset >= chip->ngpio)
return -ENXIO;
desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
@ -687,6 +684,8 @@ static struct of_device_id sunxi_pinctrl_match[] = {
{ .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
{ .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
{ .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
{ .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data },
{ .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)&sun7i_a20_pinctrl_data },
{}
};
MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);

223
drivers/pinctrl/pinctrl-tegra.c
View File

@ -32,6 +32,7 @@
#include "core.h"
#include "pinctrl-tegra.h"
#include "pinctrl-utils.h"
struct tegra_pmx {
struct device *dev;
@ -90,107 +91,6 @@ static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
}
#endif
static int reserve_map(struct device *dev, struct pinctrl_map **map,
unsigned *reserved_maps, unsigned *num_maps,
unsigned reserve)
{
unsigned old_num = *reserved_maps;
unsigned new_num = *num_maps + reserve;
struct pinctrl_map *new_map;
if (old_num >= new_num)
return 0;
new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
if (!new_map) {
dev_err(dev, "krealloc(map) failed\n");
return -ENOMEM;
}
memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
*map = new_map;
*reserved_maps = new_num;
return 0;
}
static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, const char *group,
const char *function)
{
if (WARN_ON(*num_maps == *reserved_maps))
return -ENOSPC;
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[*num_maps].data.mux.group = group;
(*map)[*num_maps].data.mux.function = function;
(*num_maps)++;
return 0;
}
static int add_map_configs(struct device *dev, struct pinctrl_map **map,
unsigned *reserved_maps, unsigned *num_maps,
const char *group, unsigned long *configs,
unsigned num_configs)
{
unsigned long *dup_configs;
if (WARN_ON(*num_maps == *reserved_maps))
return -ENOSPC;
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
GFP_KERNEL);
if (!dup_configs) {
dev_err(dev, "kmemdup(configs) failed\n");
return -ENOMEM;
}
(*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
(*map)[*num_maps].data.configs.group_or_pin = group;
(*map)[*num_maps].data.configs.configs = dup_configs;
(*map)[*num_maps].data.configs.num_configs = num_configs;
(*num_maps)++;
return 0;
}
static int add_config(struct device *dev, unsigned long **configs,
unsigned *num_configs, unsigned long config)
{
unsigned old_num = *num_configs;
unsigned new_num = old_num + 1;
unsigned long *new_configs;
new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
GFP_KERNEL);
if (!new_configs) {
dev_err(dev, "krealloc(configs) failed\n");
return -ENOMEM;
}
new_configs[old_num] = config;
*configs = new_configs;
*num_configs = new_num;
return 0;
}
static void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map,
unsigned num_maps)
{
int i;
for (i = 0; i < num_maps; i++)
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
kfree(map[i].data.configs.configs);
kfree(map);
}
static const struct cfg_param {
const char *property;
enum tegra_pinconf_param param;
@ -212,12 +112,13 @@ static const struct cfg_param {
{"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
};
static int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map,
unsigned *reserved_maps,
unsigned *num_maps)
{
struct device *dev = pctldev->dev;
int ret, i;
const char *function;
u32 val;
@ -241,7 +142,8 @@ static int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
ret = of_property_read_u32(np, cfg_params[i].property, &val);
if (!ret) {
config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
ret = add_config(dev, &configs, &num_configs, config);
ret = pinctrl_utils_add_config(pctldev, &configs,
&num_configs, config);
if (ret < 0)
goto exit;
/* EINVAL=missing, which is fine since it's optional */
@ -263,22 +165,25 @@ static int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
}
reserve *= ret;
ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
num_maps, reserve);
if (ret < 0)
goto exit;
of_property_for_each_string(np, "nvidia,pins", prop, group) {
if (function) {
ret = add_map_mux(map, reserved_maps, num_maps,
group, function);
ret = pinctrl_utils_add_map_mux(pctldev, map,
reserved_maps, num_maps, group,
function);
if (ret < 0)
goto exit;
}
if (num_configs) {
ret = add_map_configs(dev, map, reserved_maps,
num_maps, group, configs,
num_configs);
ret = pinctrl_utils_add_map_configs(pctldev, map,
reserved_maps, num_maps, group,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (ret < 0)
goto exit;
}
@ -305,10 +210,11 @@ static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
*num_maps = 0;
for_each_child_of_node(np_config, np) {
ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
pinctrl_utils_dt_free_map(pctldev, *map,
*num_maps);
return ret;
}
}
@ -324,7 +230,7 @@ static const struct pinctrl_ops tegra_pinctrl_ops = {
.pin_dbg_show = tegra_pinctrl_pin_dbg_show,
#endif
.dt_node_to_map = tegra_pinctrl_dt_node_to_map,
.dt_free_map = tegra_pinctrl_dt_free_map,
.dt_free_map = pinctrl_utils_dt_free_map,
};
static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
@ -530,7 +436,8 @@ static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
}
static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long config)
unsigned pin, unsigned long *configs,
unsigned num_configs)
{
dev_err(pctldev->dev, "pin_config_set op not supported\n");
return -ENOTSUPP;
@ -565,51 +472,57 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
}
static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long config)
unsigned group, unsigned long *configs,
unsigned num_configs)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
enum tegra_pinconf_param param;
u16 arg;
const struct tegra_pingroup *g;
int ret;
int ret, i;
s8 bank, bit, width;
s16 reg;
u32 val, mask;
g = &pmx->soc->groups[group];
ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
&width);
if (ret < 0)
return ret;
for (i = 0; i < num_configs; i++) {
param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
val = pmx_readl(pmx, bank, reg);
ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
&width);
if (ret < 0)
return ret;
/* LOCK can't be cleared */
if (param == TEGRA_PINCONF_PARAM_LOCK) {
if ((val & BIT(bit)) && !arg) {
dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
val = pmx_readl(pmx, bank, reg);
/* LOCK can't be cleared */
if (param == TEGRA_PINCONF_PARAM_LOCK) {
if ((val & BIT(bit)) && !arg) {
dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
return -EINVAL;
}
}
/* Special-case Boolean values; allow any non-zero as true */
if (width == 1)
arg = !!arg;
/* Range-check user-supplied value */
mask = (1 << width) - 1;
if (arg & ~mask) {
dev_err(pctldev->dev,
"config %lx: %x too big for %d bit register\n",
configs[i], arg, width);
return -EINVAL;
}
}
/* Special-case Boolean values; allow any non-zero as true */
if (width == 1)
arg = !!arg;
/* Range-check user-supplied value */
mask = (1 << width) - 1;
if (arg & ~mask) {
dev_err(pctldev->dev,
"config %lx: %x too big for %d bit register\n",
config, arg, width);
return -EINVAL;
}
/* Update register */
val &= ~(mask << bit);
val |= arg << bit;
pmx_writel(pmx, val, bank, reg);
/* Update register */
val &= ~(mask << bit);
val |= arg << bit;
pmx_writel(pmx, val, bank, reg);
} /* for each config */
return 0;
}
@ -737,25 +650,9 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
for (i = 0; i < pmx->nbanks; i++) {
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
if (!res) {
dev_err(&pdev->dev, "Missing MEM resource\n");
return -ENODEV;
}
if (!devm_request_mem_region(&pdev->dev, res->start,
resource_size(res),
dev_name(&pdev->dev))) {
dev_err(&pdev->dev,
"Couldn't request MEM resource %d\n", i);
return -ENODEV;
}
pmx->regs[i] = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!pmx->regs[i]) {
dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
return -ENODEV;
}
pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pmx->regs[i]))
return PTR_ERR(pmx->regs[i]);
}
pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);

157
drivers/pinctrl/pinctrl-tz1090-pdc.c
View File

@ -737,39 +737,46 @@ static int tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev,
}
static int tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long config)
unsigned int pin, unsigned long *configs,
unsigned num_configs)
{
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(config);
unsigned int arg = pinconf_to_config_argument(config);
enum pin_config_param param;
unsigned int arg;
int ret;
u32 reg, width, mask, shift, val, tmp;
unsigned long flags;
int i;
dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n",
__func__, tz1090_pdc_pins[pin].name, config);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
/* Get register information */
ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true,
&reg, &width, &mask, &shift, &val);
if (ret < 0)
return ret;
dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n",
__func__, tz1090_pdc_pins[pin].name, configs[i]);
/* Unpack argument and range check it */
if (arg > 1) {
dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
__func__, arg);
return -EINVAL;
}
/* Get register information */
ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true,
&reg, &width, &mask, &shift, &val);
if (ret < 0)
return ret;
/* Write register field */
__global_lock2(flags);
tmp = pmx_read(pmx, reg);
tmp &= ~mask;
if (arg)
tmp |= val << shift;
pmx_write(pmx, tmp, reg);
__global_unlock2(flags);
/* Unpack argument and range check it */
if (arg > 1) {
dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
__func__, arg);
return -EINVAL;
}
/* Write register field */
__global_lock2(flags);
tmp = pmx_read(pmx, reg);
tmp &= ~mask;
if (arg)
tmp |= val << shift;
pmx_write(pmx, tmp, reg);
__global_unlock2(flags);
} /* for each config */
return 0;
}
@ -860,54 +867,68 @@ static int tz1090_pdc_pinconf_group_get(struct pinctrl_dev *pctldev,
static int tz1090_pdc_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int group,
unsigned long config)
unsigned long *configs,
unsigned num_configs)
{
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group];
enum pin_config_param param = pinconf_to_config_param(config);
enum pin_config_param param;
const unsigned int *pit;
unsigned int i;
int ret, arg;
u32 reg, width, mask, shift, val;
unsigned long flags;
const int *map;
int j;
dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n",
__func__, g->name, config);
for (j = 0; j < num_configs; j++) {
param = pinconf_to_config_param(configs[j]);
/* Get register information */
ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true,
&reg, &width, &mask, &shift, &map);
if (ret < 0) {
/*
* Maybe we're trying to set a per-pin configuration of a group,
* so do the pins one by one. This is mainly as a convenience.
*/
for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) {
ret = tz1090_pdc_pinconf_set(pctldev, *pit, config);
if (ret)
return ret;
}
return 0;
}
dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n",
__func__, g->name, configs[j]);
/* Unpack argument and map it to register value */
arg = pinconf_to_config_argument(config);
for (i = 0; i < BIT(width); ++i) {
if (map[i] == arg || (map[i] == -EINVAL && !arg)) {
/* Write register field */
__global_lock2(flags);
val = pmx_read(pmx, reg);
val &= ~mask;
val |= i << shift;
pmx_write(pmx, val, reg);
__global_unlock2(flags);
/* Get register information */
ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true,
&reg, &width, &mask, &shift,
&map);
if (ret < 0) {
/*
* Maybe we're trying to set a per-pin configuration
* of a group, so do the pins one by one. This is
* mainly as a convenience.
*/
for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) {
ret = tz1090_pdc_pinconf_set(pctldev, *pit,
configs, num_configs);
if (ret)
return ret;
}
return 0;
}
}
dev_dbg(pctldev->dev, "%s: arg %u not supported\n",
__func__, arg);
/* Unpack argument and map it to register value */
arg = pinconf_to_config_argument(configs[j]);
for (i = 0; i < BIT(width); ++i) {
if (map[i] == arg || (map[i] == -EINVAL && !arg)) {
/* Write register field */
__global_lock2(flags);
val = pmx_read(pmx, reg);
val &= ~mask;
val |= i << shift;
pmx_write(pmx, val, reg);
__global_unlock2(flags);
goto next_config;
}
}
dev_dbg(pctldev->dev, "%s: arg %u not supported\n",
__func__, arg);
return 0;
next_config:
;
} /* for each config */
return 0;
}
@ -949,25 +970,9 @@ static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev)
tz1090_pdc_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pdc_pins);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "Missing MEM resource\n");
return -ENODEV;
}
if (!devm_request_mem_region(&pdev->dev, res->start,
resource_size(res),
dev_name(&pdev->dev))) {
dev_err(&pdev->dev,
"Couldn't request MEM resource\n");
return -ENODEV;
}
pmx->regs = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!pmx->regs) {
dev_err(&pdev->dev, "Couldn't ioremap regs\n");
return -ENODEV;
}
pmx->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pmx->regs))
return PTR_ERR(pmx->regs);
pmx->pctl = pinctrl_register(&tz1090_pdc_pinctrl_desc, &pdev->dev, pmx);
if (!pmx->pctl) {

162
drivers/pinctrl/pinctrl-tz1090.c
View File

@ -1762,39 +1762,46 @@ static int tz1090_pinconf_get(struct pinctrl_dev *pctldev,
}
static int tz1090_pinconf_set(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long config)
unsigned int pin, unsigned long *configs,
unsigned num_configs)
{
struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(config);
unsigned int arg = pinconf_to_config_argument(config);
enum pin_config_param param;
unsigned int arg;
int ret;
u32 reg, width, mask, shift, val, tmp;
unsigned long flags;
int i;
dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n",
__func__, tz1090_pins[pin].name, config);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
/* Get register information */
ret = tz1090_pinconf_reg(pctldev, pin, param, true,
&reg, &width, &mask, &shift, &val);
if (ret < 0)
return ret;
dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n",
__func__, tz1090_pins[pin].name, configs[i]);
/* Unpack argument and range check it */
if (arg > 1) {
dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
__func__, arg);
return -EINVAL;
}
/* Get register information */
ret = tz1090_pinconf_reg(pctldev, pin, param, true,
&reg, &width, &mask, &shift, &val);
if (ret < 0)
return ret;
/* Write register field */
__global_lock2(flags);
tmp = pmx_read(pmx, reg);
tmp &= ~mask;
if (arg)
tmp |= val << shift;
pmx_write(pmx, tmp, reg);
__global_unlock2(flags);
/* Unpack argument and range check it */
if (arg > 1) {
dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
__func__, arg);
return -EINVAL;
}
/* Write register field */
__global_lock2(flags);
tmp = pmx_read(pmx, reg);
tmp &= ~mask;
if (arg)
tmp |= val << shift;
pmx_write(pmx, tmp, reg);
__global_unlock2(flags);
} /* for each config */
return 0;
}
@ -1894,68 +1901,81 @@ static int tz1090_pinconf_group_get(struct pinctrl_dev *pctldev,
}
static int tz1090_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long config)
unsigned int group, unsigned long *configs,
unsigned num_configs)
{
struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tz1090_pingroup *g;
enum pin_config_param param = pinconf_to_config_param(config);
enum pin_config_param param;
unsigned int arg, pin, i;
const unsigned int *pit;
int ret;
u32 reg, width, mask, shift, val;
unsigned long flags;
const int *map;
int j;
if (group >= ARRAY_SIZE(tz1090_groups)) {
pin = group - ARRAY_SIZE(tz1090_groups);
return tz1090_pinconf_set(pctldev, pin, config);
return tz1090_pinconf_set(pctldev, pin, configs, num_configs);
}
g = &tz1090_groups[group];
if (g->npins == 1) {
pin = g->pins[0];
ret = tz1090_pinconf_set(pctldev, pin, config);
ret = tz1090_pinconf_set(pctldev, pin, configs, num_configs);
if (ret != -ENOTSUPP)
return ret;
}
dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n",
__func__, g->name, config);
for (j = 0; j < num_configs; j++) {
param = pinconf_to_config_param(configs[j]);
/* Get register information */
ret = tz1090_pinconf_group_reg(pctldev, g, param, true,
&reg, &width, &mask, &shift, &map);
if (ret < 0) {
/*
* Maybe we're trying to set a per-pin configuration of a group,
* so do the pins one by one. This is mainly as a convenience.
*/
for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) {
ret = tz1090_pinconf_set(pctldev, *pit, config);
if (ret)
return ret;
}
return 0;
}
dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n",
__func__, g->name, configs[j]);
/* Unpack argument and map it to register value */
arg = pinconf_to_config_argument(config);
for (i = 0; i < BIT(width); ++i) {
if (map[i] == arg || (map[i] == -EINVAL && !arg)) {
/* Write register field */
__global_lock2(flags);
val = pmx_read(pmx, reg);
val &= ~mask;
val |= i << shift;
pmx_write(pmx, val, reg);
__global_unlock2(flags);
/* Get register information */
ret = tz1090_pinconf_group_reg(pctldev, g, param, true, &reg,
&width, &mask, &shift, &map);
if (ret < 0) {
/*
* Maybe we're trying to set a per-pin configuration
* of a group, so do the pins one by one. This is
* mainly as a convenience.
*/
for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) {
ret = tz1090_pinconf_set(pctldev, *pit, configs,
num_configs);
if (ret)
return ret;
}
return 0;
}
}
dev_dbg(pctldev->dev, "%s: arg %u not supported\n",
__func__, arg);
return -EINVAL;
/* Unpack argument and map it to register value */
arg = pinconf_to_config_argument(configs[j]);
for (i = 0; i < BIT(width); ++i) {
if (map[i] == arg || (map[i] == -EINVAL && !arg)) {
/* Write register field */
__global_lock2(flags);
val = pmx_read(pmx, reg);
val &= ~mask;
val |= i << shift;
pmx_write(pmx, val, reg);
__global_unlock2(flags);
goto next_config;
}
}
dev_dbg(pctldev->dev, "%s: arg %u not supported\n",
__func__, arg);
return -EINVAL;
next_config:
;
} /* for each config */
return 0;
}
static struct pinconf_ops tz1090_pinconf_ops = {
@ -1996,25 +2016,9 @@ static int tz1090_pinctrl_probe(struct platform_device *pdev)
tz1090_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pins);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "Missing MEM resource\n");
return -ENODEV;
}
if (!devm_request_mem_region(&pdev->dev, res->start,
resource_size(res),
dev_name(&pdev->dev))) {
dev_err(&pdev->dev,
"Couldn't request MEM resource\n");
return -ENODEV;
}
pmx->regs = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!pmx->regs) {
dev_err(&pdev->dev, "Couldn't ioremap regs\n");
return -ENODEV;
}
pmx->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pmx->regs))
return PTR_ERR(pmx->regs);
pmx->pctl = pinctrl_register(&tz1090_pinctrl_desc, &pdev->dev, pmx);
if (!pmx->pctl) {

21
drivers/pinctrl/pinctrl-u300.c
View File

@ -1027,21 +1027,23 @@ static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
}
static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long config)
unsigned long *configs, unsigned num_configs)
{
struct pinctrl_gpio_range *range =
pinctrl_find_gpio_range_from_pin(pctldev, pin);
int ret;
int ret, i;
if (!range)
return -EINVAL;
/* Note: none of these configurations take any argument */
ret = u300_gpio_config_set(range->gc,
(pin - range->pin_base + range->base),
pinconf_to_config_param(config));
if (ret)
return ret;
for (i = 0; i < num_configs; i++) {
/* Note: none of these configurations take any argument */
ret = u300_gpio_config_set(range->gc,
(pin - range->pin_base + range->base),
pinconf_to_config_param(configs[i]));
if (ret)
return ret;
} /* for each config */
return 0;
}
@ -1075,9 +1077,6 @@ static int u300_pmx_probe(struct platform_device *pdev)
upmx->dev = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENOENT;
upmx->virtbase = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(upmx->virtbase))
return PTR_ERR(upmx->virtbase);

142
drivers/pinctrl/pinctrl-utils.c Normal file
View File

@ -0,0 +1,142 @@
/*
* Utils functions to implement the pincontrol driver.
*
* Copyright (c) 2013, NVIDIA Corporation.
*
* Author: Laxman Dewangan <ldewangan@nvidia.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
* whether express or implied; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307, USA
*/
#include <linux/device.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/of.h>
#include <linux/slab.h>
#include "core.h"
#include "pinctrl-utils.h"
int pinctrl_utils_reserve_map(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, unsigned reserve)
{
unsigned old_num = *reserved_maps;
unsigned new_num = *num_maps + reserve;
struct pinctrl_map *new_map;
if (old_num >= new_num)
return 0;
new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
if (!new_map) {
dev_err(pctldev->dev, "krealloc(map) failed\n");
return -ENOMEM;
}
memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
*map = new_map;
*reserved_maps = new_num;
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_utils_reserve_map);
int pinctrl_utils_add_map_mux(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, const char *group,
const char *function)
{
if (WARN_ON(*num_maps == *reserved_maps))
return -ENOSPC;
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[*num_maps].data.mux.group = group;
(*map)[*num_maps].data.mux.function = function;
(*num_maps)++;
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_utils_add_map_mux);
int pinctrl_utils_add_map_configs(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, const char *group,
unsigned long *configs, unsigned num_configs,
enum pinctrl_map_type type)
{
unsigned long *dup_configs;
if (WARN_ON(*num_maps == *reserved_maps))
return -ENOSPC;
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
GFP_KERNEL);
if (!dup_configs) {
dev_err(pctldev->dev, "kmemdup(configs) failed\n");
return -ENOMEM;
}
(*map)[*num_maps].type = type;
(*map)[*num_maps].data.configs.group_or_pin = group;
(*map)[*num_maps].data.configs.configs = dup_configs;
(*map)[*num_maps].data.configs.num_configs = num_configs;
(*num_maps)++;
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_utils_add_map_configs);
int pinctrl_utils_add_config(struct pinctrl_dev *pctldev,
unsigned long **configs, unsigned *num_configs,
unsigned long config)
{
unsigned old_num = *num_configs;
unsigned new_num = old_num + 1;
unsigned long *new_configs;
new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
GFP_KERNEL);
if (!new_configs) {
dev_err(pctldev->dev, "krealloc(configs) failed\n");
return -ENOMEM;
}
new_configs[old_num] = config;
*configs = new_configs;
*num_configs = new_num;
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_utils_add_config);
void pinctrl_utils_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
int i;
for (i = 0; i < num_maps; i++) {
switch (map[i].type) {
case PIN_MAP_TYPE_CONFIGS_GROUP:
case PIN_MAP_TYPE_CONFIGS_PIN:
kfree(map[i].data.configs.configs);
break;
default:
break;
}
}
kfree(map);
}
EXPORT_SYMBOL_GPL(pinctrl_utils_dt_free_map);

43
drivers/pinctrl/pinctrl-utils.h Normal file
View File

@ -0,0 +1,43 @@
/*
* Utils functions to implement the pincontrol driver.
*
* Copyright (c) 2013, NVIDIA Corporation.
*
* Author: Laxman Dewangan <ldewangan@nvidia.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
* whether express or implied; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307, USA
*/
#ifndef __PINCTRL_UTILS_H__
#define __PINCTRL_UTILS_H__
int pinctrl_utils_reserve_map(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, unsigned reserve);
int pinctrl_utils_add_map_mux(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, const char *group,
const char *function);
int pinctrl_utils_add_map_configs(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, const char *group,
unsigned long *configs, unsigned num_configs,
enum pinctrl_map_type type);
int pinctrl_utils_add_config(struct pinctrl_dev *pctldev,
unsigned long **configs, unsigned *num_configs,
unsigned long config);
void pinctrl_utils_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps);
#endif /* __PINCTRL_UTILS_H__ */

153
drivers/pinctrl/pinctrl-xway.c
View File

@ -102,6 +102,7 @@ enum xway_mux {
XWAY_MUX_EPHY,
XWAY_MUX_DFE,
XWAY_MUX_SDIO,
XWAY_MUX_GPHY,
XWAY_MUX_NONE = 0xffff,
};
@ -109,12 +110,12 @@ static const struct ltq_mfp_pin xway_mfp[] = {
/* pin f0 f1 f2 f3 */
MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM),
MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE),
MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE),
MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY),
MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI),
MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC),
MFP_XWAY(GPIO5, GPIO, STP, NONE, NONE),
MFP_XWAY(GPIO5, GPIO, STP, NONE, GPHY),
MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
MFP_XWAY(GPIO7, GPIO, CGU, PCI, NONE),
MFP_XWAY(GPIO7, GPIO, CGU, PCI, GPHY),
MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE),
@ -151,10 +152,10 @@ static const struct ltq_mfp_pin xway_mfp[] = {
MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE),
MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
MFP_XWAY(GPIO44, GPIO, NONE, NONE, SIN),
MFP_XWAY(GPIO45, GPIO, NONE, NONE, SIN),
MFP_XWAY(GPIO44, GPIO, NONE, GPHY, SIN),
MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN),
MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN),
MFP_XWAY(GPIO47, GPIO, NONE, NONE, SIN),
MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN),
MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),
@ -208,6 +209,13 @@ static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6};
static const unsigned pins_nmi[] = {GPIO8};
static const unsigned pins_mdio[] = {GPIO42, GPIO43};
static const unsigned pins_gphy0_led0[] = {GPIO5};
static const unsigned pins_gphy0_led1[] = {GPIO7};
static const unsigned pins_gphy0_led2[] = {GPIO2};
static const unsigned pins_gphy1_led0[] = {GPIO44};
static const unsigned pins_gphy1_led1[] = {GPIO45};
static const unsigned pins_gphy1_led2[] = {GPIO47};
static const unsigned pins_ebu_a24[] = {GPIO13};
static const unsigned pins_ebu_clk[] = {GPIO21};
static const unsigned pins_ebu_cs1[] = {GPIO23};
@ -322,6 +330,12 @@ static const struct ltq_pin_group xway_grps[] = {
GRP_MUX("gnt4", PCI, pins_pci_gnt4),
GRP_MUX("req4", PCI, pins_pci_gnt4),
GRP_MUX("mdio", MDIO, pins_mdio),
GRP_MUX("gphy0 led0", GPHY, pins_gphy0_led0),
GRP_MUX("gphy0 led1", GPHY, pins_gphy0_led1),
GRP_MUX("gphy0 lde2", GPHY, pins_gphy0_led2),
GRP_MUX("gphy1 led0", GPHY, pins_gphy1_led0),
GRP_MUX("gphy1 led1", GPHY, pins_gphy1_led1),
GRP_MUX("gphy1 lde2", GPHY, pins_gphy1_led2),
};
static const struct ltq_pin_group ase_grps[] = {
@ -365,6 +379,9 @@ static const char * const xway_nmi_grps[] = {"nmi"};
/* ar9/vr9/gr9 */
static const char * const xrx_mdio_grps[] = {"mdio"};
static const char * const xrx_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
"gphy0 led2", "gphy1 led0",
"gphy1 led1", "gphy1 led2"};
static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24",
"ebu a25", "ebu cs1",
"ebu wait", "ebu clk",
@ -414,6 +431,7 @@ static const struct ltq_pmx_func xrx_funcs[] = {
{"pci", ARRAY_AND_SIZE(xrx_pci_grps)},
{"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)},
{"mdio", ARRAY_AND_SIZE(xrx_mdio_grps)},
{"gphy", ARRAY_AND_SIZE(xrx_gphy_grps)},
};
static const struct ltq_pmx_func ase_funcs[] = {
@ -481,74 +499,101 @@ static int xway_pinconf_get(struct pinctrl_dev *pctldev,
static int xway_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long config)
unsigned long *configs,
unsigned num_configs)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config);
int arg = LTQ_PINCONF_UNPACK_ARG(config);
enum ltq_pinconf_param param;
int arg;
int port = PORT(pin);
u32 reg;
int i;
switch (param) {
case LTQ_PINCONF_PARAM_OPEN_DRAIN:
if (port == PORT3)
reg = GPIO3_OD;
else
reg = GPIO_OD(pin);
if (arg == 0)
gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
else
gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
break;
for (i = 0; i < num_configs; i++) {
param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
case LTQ_PINCONF_PARAM_PULL:
if (port == PORT3)
reg = GPIO3_PUDEN;
else
reg = GPIO_PUDEN(pin);
if (arg == 0) {
gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
switch (param) {
case LTQ_PINCONF_PARAM_OPEN_DRAIN:
if (port == PORT3)
reg = GPIO3_OD;
else
reg = GPIO_OD(pin);
if (arg == 0)
gpio_setbit(info->membase[0],
reg,
PORT_PIN(pin));
else
gpio_clearbit(info->membase[0],
reg,
PORT_PIN(pin));
break;
case LTQ_PINCONF_PARAM_PULL:
if (port == PORT3)
reg = GPIO3_PUDEN;
else
reg = GPIO_PUDEN(pin);
if (arg == 0) {
gpio_clearbit(info->membase[0],
reg,
PORT_PIN(pin));
break;
}
gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
if (port == PORT3)
reg = GPIO3_PUDSEL;
else
reg = GPIO_PUDSEL(pin);
if (arg == 1)
gpio_clearbit(info->membase[0],
reg,
PORT_PIN(pin));
else if (arg == 2)
gpio_setbit(info->membase[0],
reg,
PORT_PIN(pin));
else
dev_err(pctldev->dev,
"Invalid pull value %d\n", arg);
break;
case LTQ_PINCONF_PARAM_OUTPUT:
reg = GPIO_DIR(pin);
if (arg == 0)
gpio_clearbit(info->membase[0],
reg,
PORT_PIN(pin));
else
gpio_setbit(info->membase[0],
reg,
PORT_PIN(pin));
break;
default:
dev_err(pctldev->dev,
"Invalid config param %04x\n", param);
return -ENOTSUPP;
}
gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
} /* for each config */
if (port == PORT3)
reg = GPIO3_PUDSEL;
else
reg = GPIO_PUDSEL(pin);
if (arg == 1)
gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
else if (arg == 2)
gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
else
dev_err(pctldev->dev, "Invalid pull value %d\n", arg);
break;
case LTQ_PINCONF_PARAM_OUTPUT:
reg = GPIO_DIR(pin);
if (arg == 0)
gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
else
gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
break;
default:
dev_err(pctldev->dev, "Invalid config param %04x\n", param);
return -ENOTSUPP;
}
return 0;
}
int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned selector,
unsigned long config)
unsigned long *configs,
unsigned num_configs)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
int i, ret = 0;
for (i = 0; i < info->grps[selector].npins && !ret; i++)
ret = xway_pinconf_set(pctldev,
info->grps[selector].pins[i], config);
info->grps[selector].pins[i],
configs,
num_configs);
return ret;
}

51
drivers/pinctrl/pinmux.c
View File

@ -400,10 +400,14 @@ int pinmux_enable_setting(struct pinctrl_setting const *setting)
ret = pctlops->get_group_pins(pctldev, setting->data.mux.group,
&pins, &num_pins);
if (ret) {
const char *gname;
/* errors only affect debug data, so just warn */
gname = pctlops->get_group_name(pctldev,
setting->data.mux.group);
dev_warn(pctldev->dev,
"could not get pins for group selector %d\n",
setting->data.mux.group);
"could not get pins for group %s\n",
gname);
num_pins = 0;
}
@ -411,9 +415,18 @@ int pinmux_enable_setting(struct pinctrl_setting const *setting)
for (i = 0; i < num_pins; i++) {
ret = pin_request(pctldev, pins[i], setting->dev_name, NULL);
if (ret) {
const char *gname;
const char *pname;
desc = pin_desc_get(pctldev, pins[i]);
pname = desc ? desc->name : "non-existing";
gname = pctlops->get_group_name(pctldev,
setting->data.mux.group);
dev_err(pctldev->dev,
"could not request pin %d on device %s\n",
pins[i], pinctrl_dev_get_name(pctldev));
"could not request pin %d (%s) from group %s "
" on device %s\n",
pins[i], pname, gname,
pinctrl_dev_get_name(pctldev));
goto err_pin_request;
}
}
@ -466,10 +479,14 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
ret = pctlops->get_group_pins(pctldev, setting->data.mux.group,
&pins, &num_pins);
if (ret) {
const char *gname;
/* errors only affect debug data, so just warn */
gname = pctlops->get_group_name(pctldev,
setting->data.mux.group);
dev_warn(pctldev->dev,
"could not get pins for group selector %d\n",
setting->data.mux.group);
"could not get pins for group %s\n",
gname);
num_pins = 0;
}
@ -482,12 +499,24 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
pins[i]);
continue;
}
desc->mux_setting = NULL;
}
if (desc->mux_setting == &(setting->data.mux)) {
desc->mux_setting = NULL;
/* And release the pin */
pin_free(pctldev, pins[i], NULL);
} else {
const char *gname;
const char *pname;
/* And release the pins */
for (i = 0; i < num_pins; i++)
pin_free(pctldev, pins[i], NULL);
pname = desc ? desc->name : "non-existing";
gname = pctlops->get_group_name(pctldev,
setting->data.mux.group);
dev_warn(pctldev->dev,
"not freeing pin %d (%s) as part of "
"deactivating group %s - it is already "
"used for some other setting",
pins[i], pname, gname);
}
}
if (ops->disable)
ops->disable(pctldev, setting->data.mux.func, setting->data.mux.group);

101
drivers/pinctrl/sh-pfc/core.c
View File

@ -82,24 +82,20 @@ int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
unsigned int offset;
unsigned int i;
if (pfc->info->ranges == NULL)
return pin;
for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
const struct pinmux_range *range = &pfc->info->ranges[i];
for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
const struct sh_pfc_pin_range *range = &pfc->ranges[i];
if (pin <= range->end)
return pin >= range->begin
? offset + pin - range->begin : -1;
return pin >= range->start
? offset + pin - range->start : -1;
offset += range->end - range->begin + 1;
offset += range->end - range->start + 1;
}
return -EINVAL;
}
static int sh_pfc_enum_in_range(pinmux_enum_t enum_id,
const struct pinmux_range *r)
static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
{
if (enum_id < r->begin)
return 0;
@ -194,7 +190,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
const struct pinmux_cfg_reg **crp, int *fieldp,
int *valuep)
{
@ -238,10 +234,10 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
return -EINVAL;
}
static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
pinmux_enum_t *enum_idp)
static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
u16 *enum_idp)
{
const pinmux_enum_t *data = pfc->info->gpio_data;
const u16 *data = pfc->info->gpio_data;
int k;
if (pos) {
@ -264,7 +260,7 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
const struct pinmux_cfg_reg *cr = NULL;
pinmux_enum_t enum_id;
u16 enum_id;
const struct pinmux_range *range;
int in_range, pos, field, value;
int ret;
@ -283,14 +279,6 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
range = &pfc->info->input;
break;
case PINMUX_TYPE_INPUT_PULLUP:
range = &pfc->info->input_pu;
break;
case PINMUX_TYPE_INPUT_PULLDOWN:
range = &pfc->info->input_pd;
break;
default:
return -EINVAL;
}
@ -350,6 +338,67 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
return 0;
}
static int sh_pfc_init_ranges(struct sh_pfc *pfc)
{
struct sh_pfc_pin_range *range;
unsigned int nr_ranges;
unsigned int i;
if (pfc->info->pins[0].pin == (u16)-1) {
/* Pin number -1 denotes that the SoC doesn't report pin numbers
* in its pin arrays yet. Consider the pin numbers range as
* continuous and allocate a single range.
*/
pfc->nr_ranges = 1;
pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
GFP_KERNEL);
if (pfc->ranges == NULL)
return -ENOMEM;
pfc->ranges->start = 0;
pfc->ranges->end = pfc->info->nr_pins - 1;
pfc->nr_gpio_pins = pfc->info->nr_pins;
return 0;
}
/* Count, allocate and fill the ranges. The PFC SoC data pins array must
* be sorted by pin numbers, and pins without a GPIO port must come
* last.
*/
for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
nr_ranges++;
}
pfc->nr_ranges = nr_ranges;
pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
GFP_KERNEL);
if (pfc->ranges == NULL)
return -ENOMEM;
range = pfc->ranges;
range->start = pfc->info->pins[0].pin;
for (i = 1; i < pfc->info->nr_pins; ++i) {
if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
continue;
range->end = pfc->info->pins[i-1].pin;
if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
pfc->nr_gpio_pins = range->end + 1;
range++;
range->start = pfc->info->pins[i].pin;
}
range->end = pfc->info->pins[i-1].pin;
if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
pfc->nr_gpio_pins = range->end + 1;
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id sh_pfc_of_table[] = {
#ifdef CONFIG_PINCTRL_PFC_R8A73A4
@ -440,6 +489,10 @@ static int sh_pfc_probe(struct platform_device *pdev)
pinctrl_provide_dummies();
ret = sh_pfc_init_ranges(pfc);
if (ret < 0)
return ret;
/*
* Initialize pinctrl bindings first
*/
@ -486,8 +539,6 @@ static int sh_pfc_remove(struct platform_device *pdev)
if (pfc->info->ops && pfc->info->ops->exit)
pfc->info->ops->exit(pfc);
platform_set_drvdata(pdev, NULL);
return 0;
}

10
drivers/pinctrl/sh-pfc/core.h
View File

@ -25,6 +25,11 @@ struct sh_pfc_window {
struct sh_pfc_chip;
struct sh_pfc_pinctrl;
struct sh_pfc_pin_range {
u16 start;
u16 end;
};
struct sh_pfc {
struct device *dev;
const struct sh_pfc_soc_info *info;
@ -34,7 +39,10 @@ struct sh_pfc {
unsigned int num_windows;
struct sh_pfc_window *window;
unsigned int nr_pins;
struct sh_pfc_pin_range *ranges;
unsigned int nr_ranges;
unsigned int nr_gpio_pins;
struct sh_pfc_chip *gpio;
struct sh_pfc_chip *func;

45
drivers/pinctrl/sh-pfc/gpio.c
View File

@ -48,11 +48,11 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
return gpio_to_pfc_chip(gc)->pfc;
}
static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio,
static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
struct sh_pfc_gpio_data_reg **reg,
unsigned int *bit)
{
int idx = sh_pfc_get_pin_index(chip->pfc, gpio);
int idx = sh_pfc_get_pin_index(chip->pfc, offset);
struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
*reg = &chip->regs[gpio_pin->dreg];
@ -76,11 +76,11 @@ static void gpio_write_data_reg(struct sh_pfc_chip *chip,
sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
}
static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)
static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
{
struct sh_pfc *pfc = chip->pfc;
struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio];
const struct sh_pfc_pin *pin = &pfc->info->pins[gpio];
struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
const struct pinmux_data_reg *dreg;
unsigned int bit;
unsigned int i;
@ -224,8 +224,8 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
struct gpio_chip *gc = &chip->gpio_chip;
int ret;
chip->pins = devm_kzalloc(pfc->dev, pfc->nr_pins * sizeof(*chip->pins),
GFP_KERNEL);
chip->pins = devm_kzalloc(pfc->dev, pfc->info->nr_pins *
sizeof(*chip->pins), GFP_KERNEL);
if (chip->pins == NULL)
return -ENOMEM;
@ -245,7 +245,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
gc->dev = pfc->dev;
gc->owner = THIS_MODULE;
gc->base = 0;
gc->ngpio = pfc->nr_pins;
gc->ngpio = pfc->nr_gpio_pins;
return 0;
}
@ -293,7 +293,7 @@ static int gpio_function_setup(struct sh_pfc_chip *chip)
gc->label = pfc->info->name;
gc->owner = THIS_MODULE;
gc->base = pfc->nr_pins;
gc->base = pfc->nr_gpio_pins;
gc->ngpio = pfc->info->nr_func_gpios;
return 0;
@ -334,10 +334,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
{
const struct pinmux_range *ranges;
struct pinmux_range def_range;
struct sh_pfc_chip *chip;
unsigned int nr_ranges;
unsigned int i;
int ret;
@ -367,24 +364,20 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
pfc->gpio = chip;
/* Register the GPIO to pin mappings. */
if (pfc->info->ranges == NULL) {
def_range.begin = 0;
def_range.end = pfc->info->nr_pins - 1;
ranges = &def_range;
nr_ranges = 1;
} else {
ranges = pfc->info->ranges;
nr_ranges = pfc->info->nr_ranges;
}
/* Register the GPIO to pin mappings. As pins with GPIO ports must come
* first in the ranges, skip the pins without GPIO ports by stopping at
* the first range that contains such a pin.
*/
for (i = 0; i < pfc->nr_ranges; ++i) {
const struct sh_pfc_pin_range *range = &pfc->ranges[i];
for (i = 0; i < nr_ranges; ++i) {
const struct pinmux_range *range = &ranges[i];
if (range->start >= pfc->nr_gpio_pins)
break;
ret = gpiochip_add_pin_range(&chip->gpio_chip,
dev_name(pfc->dev),
range->begin, range->begin,
range->end - range->begin + 1);
range->start, range->start,
range->end - range->start + 1);
if (ret < 0)
return ret;
}

158
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
View File

@ -21,85 +21,84 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <mach/irqs.h>
#include <mach/r8a73a4.h>
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
/* Port0 - Port30 */ \
PORT_10(fn, pfx, sfx), \
PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx), \
PORT_1(fn, pfx##30, sfx), \
PORT_10(0, fn, pfx, sfx), \
PORT_10(10, fn, pfx##1, sfx), \
PORT_10(20, fn, pfx##2, sfx), \
PORT_1(30, fn, pfx##30, sfx), \
/* Port32 - Port40 */ \
PORT_1(fn, pfx##32, sfx), PORT_1(fn, pfx##33, sfx), \
PORT_1(fn, pfx##34, sfx), PORT_1(fn, pfx##35, sfx), \
PORT_1(fn, pfx##36, sfx), PORT_1(fn, pfx##37, sfx), \
PORT_1(fn, pfx##38, sfx), PORT_1(fn, pfx##39, sfx), \
PORT_1(fn, pfx##40, sfx), \
PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \
PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \
PORT_1(36, fn, pfx##36, sfx), PORT_1(37, fn, pfx##37, sfx), \
PORT_1(38, fn, pfx##38, sfx), PORT_1(39, fn, pfx##39, sfx), \
PORT_1(40, fn, pfx##40, sfx), \
/* Port64 - Port85 */ \
PORT_1(fn, pfx##64, sfx), PORT_1(fn, pfx##65, sfx), \
PORT_1(fn, pfx##66, sfx), PORT_1(fn, pfx##67, sfx), \
PORT_1(fn, pfx##68, sfx), PORT_1(fn, pfx##69, sfx), \
PORT_10(fn, pfx##7, sfx), \
PORT_1(fn, pfx##80, sfx), PORT_1(fn, pfx##81, sfx), \
PORT_1(fn, pfx##82, sfx), PORT_1(fn, pfx##83, sfx), \
PORT_1(fn, pfx##84, sfx), PORT_1(fn, pfx##85, sfx), \
PORT_1(64, fn, pfx##64, sfx), PORT_1(65, fn, pfx##65, sfx), \
PORT_1(66, fn, pfx##66, sfx), PORT_1(67, fn, pfx##67, sfx), \
PORT_1(68, fn, pfx##68, sfx), PORT_1(69, fn, pfx##69, sfx), \
PORT_10(70, fn, pfx##7, sfx), \
PORT_1(80, fn, pfx##80, sfx), PORT_1(81, fn, pfx##81, sfx), \
PORT_1(82, fn, pfx##82, sfx), PORT_1(83, fn, pfx##83, sfx), \
PORT_1(84, fn, pfx##84, sfx), PORT_1(85, fn, pfx##85, sfx), \
/* Port96 - Port126 */ \
PORT_1(fn, pfx##96, sfx), PORT_1(fn, pfx##97, sfx), \
PORT_1(fn, pfx##98, sfx), PORT_1(fn, pfx##99, sfx), \
PORT_10(fn, pfx##10, sfx), \
PORT_10(fn, pfx##11, sfx), \
PORT_1(fn, pfx##120, sfx), PORT_1(fn, pfx##121, sfx), \
PORT_1(fn, pfx##122, sfx), PORT_1(fn, pfx##123, sfx), \
PORT_1(fn, pfx##124, sfx), PORT_1(fn, pfx##125, sfx), \
PORT_1(fn, pfx##126, sfx), \
PORT_1(96, fn, pfx##96, sfx), PORT_1(97, fn, pfx##97, sfx), \
PORT_1(98, fn, pfx##98, sfx), PORT_1(99, fn, pfx##99, sfx), \
PORT_10(100, fn, pfx##10, sfx), \
PORT_10(110, fn, pfx##11, sfx), \
PORT_1(120, fn, pfx##120, sfx), PORT_1(121, fn, pfx##121, sfx), \
PORT_1(122, fn, pfx##122, sfx), PORT_1(123, fn, pfx##123, sfx), \
PORT_1(124, fn, pfx##124, sfx), PORT_1(125, fn, pfx##125, sfx), \
PORT_1(126, fn, pfx##126, sfx), \
/* Port128 - Port134 */ \
PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
PORT_1(fn, pfx##130, sfx), PORT_1(fn, pfx##131, sfx), \
PORT_1(fn, pfx##132, sfx), PORT_1(fn, pfx##133, sfx), \
PORT_1(fn, pfx##134, sfx), \
PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
PORT_1(130, fn, pfx##130, sfx), PORT_1(131, fn, pfx##131, sfx), \
PORT_1(132, fn, pfx##132, sfx), PORT_1(133, fn, pfx##133, sfx), \
PORT_1(134, fn, pfx##134, sfx), \
/* Port160 - Port178 */ \
PORT_10(fn, pfx##16, sfx), \
PORT_1(fn, pfx##170, sfx), PORT_1(fn, pfx##171, sfx), \
PORT_1(fn, pfx##172, sfx), PORT_1(fn, pfx##173, sfx), \
PORT_1(fn, pfx##174, sfx), PORT_1(fn, pfx##175, sfx), \
PORT_1(fn, pfx##176, sfx), PORT_1(fn, pfx##177, sfx), \
PORT_1(fn, pfx##178, sfx), \
PORT_10(160, fn, pfx##16, sfx), \
PORT_1(170, fn, pfx##170, sfx), PORT_1(171, fn, pfx##171, sfx), \
PORT_1(172, fn, pfx##172, sfx), PORT_1(173, fn, pfx##173, sfx), \
PORT_1(174, fn, pfx##174, sfx), PORT_1(175, fn, pfx##175, sfx), \
PORT_1(176, fn, pfx##176, sfx), PORT_1(177, fn, pfx##177, sfx), \
PORT_1(178, fn, pfx##178, sfx), \
/* Port192 - Port222 */ \
PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
PORT_10(fn, pfx##20, sfx), \
PORT_10(fn, pfx##21, sfx), \
PORT_1(fn, pfx##220, sfx), PORT_1(fn, pfx##221, sfx), \
PORT_1(fn, pfx##222, sfx), \
PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
PORT_10(200, fn, pfx##20, sfx), \
PORT_10(210, fn, pfx##21, sfx), \
PORT_1(220, fn, pfx##220, sfx), PORT_1(221, fn, pfx##221, sfx), \
PORT_1(222, fn, pfx##222, sfx), \
/* Port224 - Port250 */ \
PORT_1(fn, pfx##224, sfx), PORT_1(fn, pfx##225, sfx), \
PORT_1(fn, pfx##226, sfx), PORT_1(fn, pfx##227, sfx), \
PORT_1(fn, pfx##228, sfx), PORT_1(fn, pfx##229, sfx), \
PORT_10(fn, pfx##23, sfx), \
PORT_10(fn, pfx##24, sfx), \
PORT_1(fn, pfx##250, sfx), \
PORT_1(224, fn, pfx##224, sfx), PORT_1(225, fn, pfx##225, sfx), \
PORT_1(226, fn, pfx##226, sfx), PORT_1(227, fn, pfx##227, sfx), \
PORT_1(228, fn, pfx##228, sfx), PORT_1(229, fn, pfx##229, sfx), \
PORT_10(230, fn, pfx##23, sfx), \
PORT_10(240, fn, pfx##24, sfx), \
PORT_1(250, fn, pfx##250, sfx), \
/* Port256 - Port283 */ \
PORT_1(fn, pfx##256, sfx), PORT_1(fn, pfx##257, sfx), \
PORT_1(fn, pfx##258, sfx), PORT_1(fn, pfx##259, sfx), \
PORT_10(fn, pfx##26, sfx), \
PORT_10(fn, pfx##27, sfx), \
PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
PORT_1(fn, pfx##282, sfx), PORT_1(fn, pfx##283, sfx), \
PORT_1(256, fn, pfx##256, sfx), PORT_1(257, fn, pfx##257, sfx), \
PORT_1(258, fn, pfx##258, sfx), PORT_1(259, fn, pfx##259, sfx), \
PORT_10(260, fn, pfx##26, sfx), \
PORT_10(270, fn, pfx##27, sfx), \
PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
PORT_1(282, fn, pfx##282, sfx), PORT_1(283, fn, pfx##283, sfx), \
/* Port288 - Port308 */ \
PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
PORT_10(fn, pfx##29, sfx), \
PORT_1(fn, pfx##300, sfx), PORT_1(fn, pfx##301, sfx), \
PORT_1(fn, pfx##302, sfx), PORT_1(fn, pfx##303, sfx), \
PORT_1(fn, pfx##304, sfx), PORT_1(fn, pfx##305, sfx), \
PORT_1(fn, pfx##306, sfx), PORT_1(fn, pfx##307, sfx), \
PORT_1(fn, pfx##308, sfx), \
PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
PORT_10(290, fn, pfx##29, sfx), \
PORT_1(300, fn, pfx##300, sfx), PORT_1(301, fn, pfx##301, sfx), \
PORT_1(302, fn, pfx##302, sfx), PORT_1(303, fn, pfx##303, sfx), \
PORT_1(304, fn, pfx##304, sfx), PORT_1(305, fn, pfx##305, sfx), \
PORT_1(306, fn, pfx##306, sfx), PORT_1(307, fn, pfx##307, sfx), \
PORT_1(308, fn, pfx##308, sfx), \
/* Port320 - Port329 */ \
PORT_10(fn, pfx##32, sfx)
PORT_10(320, fn, pfx##32, sfx)
enum {
@ -428,10 +427,7 @@ enum {
PINMUX_MARK_END,
};
#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
PINMUX_DATA_ALL(),
@ -1269,19 +1265,12 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
};
#define R8A73A4_PIN(pin, cfgs) \
{ \
.name = __stringify(PORT##pin), \
.enum_id = PORT##pin##_DATA, \
.configs = cfgs, \
}
#define __O (SH_PFC_PIN_CFG_OUTPUT)
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
#define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD)
#define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O)
#define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
static struct sh_pfc_pin pinmux_pins[] = {
R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
@ -1408,20 +1397,6 @@ static struct sh_pfc_pin pinmux_pins[] = {
R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
};
static const struct pinmux_range pinmux_ranges[] = {
{.begin = 0, .end = 30,},
{.begin = 32, .end = 40,},
{.begin = 64, .end = 85,},
{.begin = 96, .end = 126,},
{.begin = 128, .end = 134,},
{.begin = 160, .end = 178,},
{.begin = 192, .end = 222,},
{.begin = 224, .end = 250,},
{.begin = 256, .end = 283,},
{.begin = 288, .end = 308,},
{.begin = 320, .end = 329,},
};
/* - IRQC ------------------------------------------------------------------- */
#define IRQC_PINS_MUX(pin, irq_mark) \
static const unsigned int irqc_irq##irq_mark##_pins[] = { \
@ -2766,9 +2741,6 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.ranges = pinmux_ranges,
.nr_ranges = ARRAY_SIZE(pinmux_ranges),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,

48
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View File

@ -22,24 +22,16 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <mach/r8a7740.h>
#include <mach/irqs.h>
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
PORT_10(fn, pfx##20, sfx), \
PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
#undef _GPIO_PORT
#define _GPIO_PORT(gpio, sfx) \
[gpio] = { \
.name = __stringify(PORT##gpio), \
.enum_id = PORT##gpio##_DATA, \
}
PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \
PORT_10(200, fn, pfx##20, sfx), \
PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx)
#define IRQC_PIN_MUX(irq, pin) \
static const unsigned int intc_irq##irq##_pins[] = { \
@ -590,11 +582,8 @@ enum {
PINMUX_MARK_END,
};
#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
static const u16 pinmux_data[] = {
PINMUX_DATA_ALL(),
/* Port0 */
PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
@ -1537,13 +1526,6 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
};
#define R8A7740_PIN(pin, cfgs) \
{ \
.name = __stringify(PORT##pin), \
.enum_id = PORT##pin##_DATA, \
.configs = cfgs, \
}
#define __I (SH_PFC_PIN_CFG_INPUT)
#define __O (SH_PFC_PIN_CFG_OUTPUT)
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
@ -1551,15 +1533,15 @@ static const pinmux_enum_t pinmux_data[] = {
#define __PU (SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
#define R8A7740_PIN_I_PD(pin) R8A7740_PIN(pin, __I | __PD)
#define R8A7740_PIN_I_PU(pin) R8A7740_PIN(pin, __I | __PU)
#define R8A7740_PIN_I_PU_PD(pin) R8A7740_PIN(pin, __I | __PUD)
#define R8A7740_PIN_IO(pin) R8A7740_PIN(pin, __IO)
#define R8A7740_PIN_IO_PD(pin) R8A7740_PIN(pin, __IO | __PD)
#define R8A7740_PIN_IO_PU(pin) R8A7740_PIN(pin, __IO | __PU)
#define R8A7740_PIN_IO_PU_PD(pin) R8A7740_PIN(pin, __IO | __PUD)
#define R8A7740_PIN_O(pin) R8A7740_PIN(pin, __O)
#define R8A7740_PIN_O_PU_PD(pin) R8A7740_PIN(pin, __O | __PUD)
#define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
#define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
#define R8A7740_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
#define R8A7740_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
#define R8A7740_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
#define R8A7740_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
#define R8A7740_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
#define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
static struct sh_pfc_pin pinmux_pins[] = {
/* Table 56-1 (I/O and Pull U/D) */

55
drivers/pinctrl/sh-pfc/pfc-r8a7778.c
View File

@ -23,26 +23,6 @@
#include <linux/kernel.h>
#include "sh_pfc.h"
#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
#define PORT_GP_32(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
#define PORT_GP_27(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
@ -66,26 +46,6 @@
PORT_GP_32(3, fn, sfx), \
PORT_GP_27(4, fn, sfx)
#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
#define _GP_GPIO(bank, pin, _name, sfx) \
[RCAR_GP_PIN(bank, pin)] = { \
.name = __stringify(_name), \
.enum_id = _name##_DATA, \
}
#define _GP_DATA(bank, pin, name, sfx) \
PINMUX_DATA(name##_DATA, name##_FN)
#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
#define PINMUX_IPSR_NOGP(ispr, fn) PINMUX_DATA(fn##_MARK, FN_##fn)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
#define PINMUX_IPSR_MSEL(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
#define PINMUX_IPSR_NOGM(ispr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
enum {
PINMUX_RESERVED = 0,
@ -579,7 +539,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(PENC0_MARK, FN_PENC0),
@ -1294,16 +1254,21 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C),
};
static struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
/* Pin numbers for pins without a corresponding GPIO port number are computed
* from the row and column numbers with a 1000 offset to avoid collisions with
* GPIO port numbers.
*/
#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1)
static struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
/* Pins not associated with a GPIO port */
SH_PFC_PIN_NAMED(3, 20, C20),
SH_PFC_PIN_NAMED(20, 1, T1),
SH_PFC_PIN_NAMED(25, 2, Y2),
};
/* - macro */
#define SH_PFC_PINS(name, args...) \
static const unsigned int name ##_pins[] = { args }

168
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
View File

@ -24,51 +24,13 @@
#include "sh_pfc.h"
#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
#define PORT_GP_32(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
#define PORT_GP_32_9(bank, fn, sfx) \
#define PORT_GP_9(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx)
#define PORT_GP_32_REV(bank, fn, sfx) \
PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
@ -76,26 +38,7 @@
PORT_GP_32(3, fn, sfx), \
PORT_GP_32(4, fn, sfx), \
PORT_GP_32(5, fn, sfx), \
PORT_GP_32_9(6, fn, sfx)
#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
#define _GP_GPIO(bank, pin, _name, sfx) \
[RCAR_GP_PIN(bank, pin)] = { \
.name = __stringify(_name), \
.enum_id = _name##_DATA, \
}
#define _GP_DATA(bank, pin, name, sfx) \
PINMUX_DATA(name##_DATA, name##_FN)
#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
FN_##ipsr, FN_##fn)
PORT_GP_9(6, fn, sfx)
enum {
PINMUX_RESERVED = 0,
@ -664,7 +607,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(AVS1_MARK, FN_AVS1),
@ -1731,6 +1674,79 @@ static const unsigned int hspi2_b_pins[] = {
static const unsigned int hspi2_b_mux[] = {
HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
};
/* - I2C1 ------------------------------------------------------------------ */
static const unsigned int i2c1_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
};
static const unsigned int i2c1_mux[] = {
SCL1_MARK, SDA1_MARK,
};
static const unsigned int i2c1_b_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
};
static const unsigned int i2c1_b_mux[] = {
SCL1_B_MARK, SDA1_B_MARK,
};
static const unsigned int i2c1_c_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
};
static const unsigned int i2c1_c_mux[] = {
SCL1_C_MARK, SDA1_C_MARK,
};
static const unsigned int i2c1_d_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
};
static const unsigned int i2c1_d_mux[] = {
SCL1_D_MARK, SDA1_D_MARK,
};
/* - I2C2 ------------------------------------------------------------------ */
static const unsigned int i2c2_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26),
};
static const unsigned int i2c2_mux[] = {
SCL2_MARK, SDA2_MARK,
};
static const unsigned int i2c2_b_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
};
static const unsigned int i2c2_b_mux[] = {
SCL2_B_MARK, SDA2_B_MARK,
};
static const unsigned int i2c2_c_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30),
};
static const unsigned int i2c2_c_mux[] = {
SCL2_C_MARK, SDA2_C_MARK,
};
static const unsigned int i2c2_d_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
};
static const unsigned int i2c2_d_mux[] = {
SCL2_D_MARK, SDA2_D_MARK,
};
/* - I2C3 ------------------------------------------------------------------ */
static const unsigned int i2c3_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30),
};
static const unsigned int i2c3_mux[] = {
SCL3_MARK, SDA3_MARK,
};
static const unsigned int i2c3_b_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30),
};
static const unsigned int i2c3_b_mux[] = {
SCL3_B_MARK, SDA3_B_MARK,
};
/* - INTC ------------------------------------------------------------------- */
static const unsigned int intc_irq0_pins[] = {
/* IRQ */
@ -2600,6 +2616,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(hspi1_d),
SH_PFC_PIN_GROUP(hspi2),
SH_PFC_PIN_GROUP(hspi2_b),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c1_c),
SH_PFC_PIN_GROUP(i2c1_d),
SH_PFC_PIN_GROUP(i2c2),
SH_PFC_PIN_GROUP(i2c2_b),
SH_PFC_PIN_GROUP(i2c2_c),
SH_PFC_PIN_GROUP(i2c2_d),
SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(i2c3_b),
SH_PFC_PIN_GROUP(intc_irq0),
SH_PFC_PIN_GROUP(intc_irq0_b),
SH_PFC_PIN_GROUP(intc_irq1),
@ -2760,6 +2786,25 @@ static const char * const hspi2_groups[] = {
"hspi2_b",
};
static const char * const i2c1_groups[] = {
"i2c1",
"i2c1_b",
"i2c1_c",
"i2c1_d",
};
static const char * const i2c2_groups[] = {
"i2c2",
"i2c2_b",
"i2c2_c",
"i2c2_d",
};
static const char * const i2c3_groups[] = {
"i2c3",
"i2c3_b",
};
static const char * const intc_groups[] = {
"intc_irq0",
"intc_irq0_b",
@ -2943,6 +2988,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(hspi0),
SH_PFC_FUNCTION(hspi1),
SH_PFC_FUNCTION(hspi2),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(intc),
SH_PFC_FUNCTION(lbsc),
SH_PFC_FUNCTION(mmc0),

1750
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
View File

File diff suppressed because it is too large Load Diff

202
drivers/pinctrl/sh-pfc/pfc-sh7203.c
View File

@ -272,8 +272,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* PA */
PINMUX_DATA(PA7_DATA, PA7_IN),
PINMUX_DATA(PA6_DATA, PA6_IN),
@ -704,117 +703,116 @@ static const pinmux_enum_t pinmux_data[] = {
};
static struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
PINMUX_GPIO(GPIO_PA5, PA5_DATA),
PINMUX_GPIO(GPIO_PA4, PA4_DATA),
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
PINMUX_GPIO(PA7),
PINMUX_GPIO(PA6),
PINMUX_GPIO(PA5),
PINMUX_GPIO(PA4),
PINMUX_GPIO(PA3),
PINMUX_GPIO(PA2),
PINMUX_GPIO(PA1),
PINMUX_GPIO(PA0),
/* PB */
PINMUX_GPIO(GPIO_PB12, PB12_DATA),
PINMUX_GPIO(GPIO_PB11, PB11_DATA),
PINMUX_GPIO(GPIO_PB10, PB10_DATA),
PINMUX_GPIO(GPIO_PB9, PB9_DATA),
PINMUX_GPIO(GPIO_PB8, PB8_DATA),
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
PINMUX_GPIO(GPIO_PB0, PB0_DATA),
PINMUX_GPIO(PB12),
PINMUX_GPIO(PB11),
PINMUX_GPIO(PB10),
PINMUX_GPIO(PB9),
PINMUX_GPIO(PB8),
PINMUX_GPIO(PB7),
PINMUX_GPIO(PB6),
PINMUX_GPIO(PB5),
PINMUX_GPIO(PB4),
PINMUX_GPIO(PB3),
PINMUX_GPIO(PB2),
PINMUX_GPIO(PB1),
PINMUX_GPIO(PB0),
/* PC */
PINMUX_GPIO(GPIO_PC14, PC14_DATA),
PINMUX_GPIO(GPIO_PC13, PC13_DATA),
PINMUX_GPIO(GPIO_PC12, PC12_DATA),
PINMUX_GPIO(GPIO_PC11, PC11_DATA),
PINMUX_GPIO(GPIO_PC10, PC10_DATA),
PINMUX_GPIO(GPIO_PC9, PC9_DATA),
PINMUX_GPIO(GPIO_PC8, PC8_DATA),
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
PINMUX_GPIO(PC14),
PINMUX_GPIO(PC13),
PINMUX_GPIO(PC12),
PINMUX_GPIO(PC11),
PINMUX_GPIO(PC10),
PINMUX_GPIO(PC9),
PINMUX_GPIO(PC8),
PINMUX_GPIO(PC7),
PINMUX_GPIO(PC6),
PINMUX_GPIO(PC5),
PINMUX_GPIO(PC4),
PINMUX_GPIO(PC3),
PINMUX_GPIO(PC2),
PINMUX_GPIO(PC1),
PINMUX_GPIO(PC0),
/* PD */
PINMUX_GPIO(GPIO_PD15, PD15_DATA),
PINMUX_GPIO(GPIO_PD14, PD14_DATA),
PINMUX_GPIO(GPIO_PD13, PD13_DATA),
PINMUX_GPIO(GPIO_PD12, PD12_DATA),
PINMUX_GPIO(GPIO_PD11, PD11_DATA),
PINMUX_GPIO(GPIO_PD10, PD10_DATA),
PINMUX_GPIO(GPIO_PD9, PD9_DATA),
PINMUX_GPIO(GPIO_PD8, PD8_DATA),
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
PINMUX_GPIO(PD15),
PINMUX_GPIO(PD14),
PINMUX_GPIO(PD13),
PINMUX_GPIO(PD12),
PINMUX_GPIO(PD11),
PINMUX_GPIO(PD10),
PINMUX_GPIO(PD9),
PINMUX_GPIO(PD8),
PINMUX_GPIO(PD7),
PINMUX_GPIO(PD6),
PINMUX_GPIO(PD5),
PINMUX_GPIO(PD4),
PINMUX_GPIO(PD3),
PINMUX_GPIO(PD2),
PINMUX_GPIO(PD1),
PINMUX_GPIO(PD0),
/* PE */
PINMUX_GPIO(GPIO_PE15, PE15_DATA),
PINMUX_GPIO(GPIO_PE14, PE14_DATA),
PINMUX_GPIO(GPIO_PE13, PE13_DATA),
PINMUX_GPIO(GPIO_PE12, PE12_DATA),
PINMUX_GPIO(GPIO_PE11, PE11_DATA),
PINMUX_GPIO(GPIO_PE10, PE10_DATA),
PINMUX_GPIO(GPIO_PE9, PE9_DATA),
PINMUX_GPIO(GPIO_PE8, PE8_DATA),
PINMUX_GPIO(GPIO_PE7, PE7_DATA),
PINMUX_GPIO(GPIO_PE6, PE6_DATA),
PINMUX_GPIO(GPIO_PE5, PE5_DATA),
PINMUX_GPIO(GPIO_PE4, PE4_DATA),
PINMUX_GPIO(GPIO_PE3, PE3_DATA),
PINMUX_GPIO(GPIO_PE2, PE2_DATA),
PINMUX_GPIO(GPIO_PE1, PE1_DATA),
PINMUX_GPIO(GPIO_PE0, PE0_DATA),
PINMUX_GPIO(PE15),
PINMUX_GPIO(PE14),
PINMUX_GPIO(PE13),
PINMUX_GPIO(PE12),
PINMUX_GPIO(PE11),
PINMUX_GPIO(PE10),
PINMUX_GPIO(PE9),
PINMUX_GPIO(PE8),
PINMUX_GPIO(PE7),
PINMUX_GPIO(PE6),
PINMUX_GPIO(PE5),
PINMUX_GPIO(PE4),
PINMUX_GPIO(PE3),
PINMUX_GPIO(PE2),
PINMUX_GPIO(PE1),
PINMUX_GPIO(PE0),
/* PF */
PINMUX_GPIO(GPIO_PF30, PF30_DATA),
PINMUX_GPIO(GPIO_PF29, PF29_DATA),
PINMUX_GPIO(GPIO_PF28, PF28_DATA),
PINMUX_GPIO(GPIO_PF27, PF27_DATA),
PINMUX_GPIO(GPIO_PF26, PF26_DATA),
PINMUX_GPIO(GPIO_PF25, PF25_DATA),
PINMUX_GPIO(GPIO_PF24, PF24_DATA),
PINMUX_GPIO(GPIO_PF23, PF23_DATA),
PINMUX_GPIO(GPIO_PF22, PF22_DATA),
PINMUX_GPIO(GPIO_PF21, PF21_DATA),
PINMUX_GPIO(GPIO_PF20, PF20_DATA),
PINMUX_GPIO(GPIO_PF19, PF19_DATA),
PINMUX_GPIO(GPIO_PF18, PF18_DATA),
PINMUX_GPIO(GPIO_PF17, PF17_DATA),
PINMUX_GPIO(GPIO_PF16, PF16_DATA),
PINMUX_GPIO(GPIO_PF15, PF15_DATA),
PINMUX_GPIO(GPIO_PF14, PF14_DATA),
PINMUX_GPIO(GPIO_PF13, PF13_DATA),
PINMUX_GPIO(GPIO_PF12, PF12_DATA),
PINMUX_GPIO(GPIO_PF11, PF11_DATA),
PINMUX_GPIO(GPIO_PF10, PF10_DATA),
PINMUX_GPIO(GPIO_PF9, PF9_DATA),
PINMUX_GPIO(GPIO_PF8, PF8_DATA),
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
PINMUX_GPIO(PF30),
PINMUX_GPIO(PF29),
PINMUX_GPIO(PF28),
PINMUX_GPIO(PF27),
PINMUX_GPIO(PF26),
PINMUX_GPIO(PF25),
PINMUX_GPIO(PF24),
PINMUX_GPIO(PF23),
PINMUX_GPIO(PF22),
PINMUX_GPIO(PF21),
PINMUX_GPIO(PF20),
PINMUX_GPIO(PF19),
PINMUX_GPIO(PF18),
PINMUX_GPIO(PF17),
PINMUX_GPIO(PF16),
PINMUX_GPIO(PF15),
PINMUX_GPIO(PF14),
PINMUX_GPIO(PF13),
PINMUX_GPIO(PF12),
PINMUX_GPIO(PF11),
PINMUX_GPIO(PF10),
PINMUX_GPIO(PF9),
PINMUX_GPIO(PF8),
PINMUX_GPIO(PF7),
PINMUX_GPIO(PF6),
PINMUX_GPIO(PF5),
PINMUX_GPIO(PF4),
PINMUX_GPIO(PF3),
PINMUX_GPIO(PF2),
PINMUX_GPIO(PF1),
PINMUX_GPIO(PF0),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)

246
drivers/pinctrl/sh-pfc/pfc-sh7264.c
View File

@ -604,8 +604,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* Port A */
PINMUX_DATA(PA3_DATA, PA3_IN),
PINMUX_DATA(PA2_DATA, PA2_IN),
@ -1073,149 +1072,148 @@ static const pinmux_enum_t pinmux_data[] = {
};
static struct sh_pfc_pin pinmux_pins[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
PINMUX_GPIO(PA3),
PINMUX_GPIO(PA2),
PINMUX_GPIO(PA1),
PINMUX_GPIO(PA0),
/* Port B */
PINMUX_GPIO(GPIO_PB22, PB22_DATA),
PINMUX_GPIO(GPIO_PB21, PB21_DATA),
PINMUX_GPIO(GPIO_PB20, PB20_DATA),
PINMUX_GPIO(GPIO_PB19, PB19_DATA),
PINMUX_GPIO(GPIO_PB18, PB18_DATA),
PINMUX_GPIO(GPIO_PB17, PB17_DATA),
PINMUX_GPIO(GPIO_PB16, PB16_DATA),
PINMUX_GPIO(GPIO_PB15, PB15_DATA),
PINMUX_GPIO(GPIO_PB14, PB14_DATA),
PINMUX_GPIO(GPIO_PB13, PB13_DATA),
PINMUX_GPIO(GPIO_PB12, PB12_DATA),
PINMUX_GPIO(GPIO_PB11, PB11_DATA),
PINMUX_GPIO(GPIO_PB10, PB10_DATA),
PINMUX_GPIO(GPIO_PB9, PB9_DATA),
PINMUX_GPIO(GPIO_PB8, PB8_DATA),
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
PINMUX_GPIO(PB22),
PINMUX_GPIO(PB21),
PINMUX_GPIO(PB20),
PINMUX_GPIO(PB19),
PINMUX_GPIO(PB18),
PINMUX_GPIO(PB17),
PINMUX_GPIO(PB16),
PINMUX_GPIO(PB15),
PINMUX_GPIO(PB14),
PINMUX_GPIO(PB13),
PINMUX_GPIO(PB12),
PINMUX_GPIO(PB11),
PINMUX_GPIO(PB10),
PINMUX_GPIO(PB9),
PINMUX_GPIO(PB8),
PINMUX_GPIO(PB7),
PINMUX_GPIO(PB6),
PINMUX_GPIO(PB5),
PINMUX_GPIO(PB4),
PINMUX_GPIO(PB3),
PINMUX_GPIO(PB2),
PINMUX_GPIO(PB1),
/* Port C */
PINMUX_GPIO(GPIO_PC10, PC10_DATA),
PINMUX_GPIO(GPIO_PC9, PC9_DATA),
PINMUX_GPIO(GPIO_PC8, PC8_DATA),
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
PINMUX_GPIO(PC10),
PINMUX_GPIO(PC9),
PINMUX_GPIO(PC8),
PINMUX_GPIO(PC7),
PINMUX_GPIO(PC6),
PINMUX_GPIO(PC5),
PINMUX_GPIO(PC4),
PINMUX_GPIO(PC3),
PINMUX_GPIO(PC2),
PINMUX_GPIO(PC1),
PINMUX_GPIO(PC0),
/* Port D */
PINMUX_GPIO(GPIO_PD15, PD15_DATA),
PINMUX_GPIO(GPIO_PD14, PD14_DATA),
PINMUX_GPIO(GPIO_PD13, PD13_DATA),
PINMUX_GPIO(GPIO_PD12, PD12_DATA),
PINMUX_GPIO(GPIO_PD11, PD11_DATA),
PINMUX_GPIO(GPIO_PD10, PD10_DATA),
PINMUX_GPIO(GPIO_PD9, PD9_DATA),
PINMUX_GPIO(GPIO_PD8, PD8_DATA),
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
PINMUX_GPIO(PD15),
PINMUX_GPIO(PD14),
PINMUX_GPIO(PD13),
PINMUX_GPIO(PD12),
PINMUX_GPIO(PD11),
PINMUX_GPIO(PD10),
PINMUX_GPIO(PD9),
PINMUX_GPIO(PD8),
PINMUX_GPIO(PD7),
PINMUX_GPIO(PD6),
PINMUX_GPIO(PD5),
PINMUX_GPIO(PD4),
PINMUX_GPIO(PD3),
PINMUX_GPIO(PD2),
PINMUX_GPIO(PD1),
PINMUX_GPIO(PD0),
/* Port E */
PINMUX_GPIO(GPIO_PE5, PE5_DATA),
PINMUX_GPIO(GPIO_PE4, PE4_DATA),
PINMUX_GPIO(GPIO_PE3, PE3_DATA),
PINMUX_GPIO(GPIO_PE2, PE2_DATA),
PINMUX_GPIO(GPIO_PE1, PE1_DATA),
PINMUX_GPIO(GPIO_PE0, PE0_DATA),
PINMUX_GPIO(PE5),
PINMUX_GPIO(PE4),
PINMUX_GPIO(PE3),
PINMUX_GPIO(PE2),
PINMUX_GPIO(PE1),
PINMUX_GPIO(PE0),
/* Port F */
PINMUX_GPIO(GPIO_PF12, PF12_DATA),
PINMUX_GPIO(GPIO_PF11, PF11_DATA),
PINMUX_GPIO(GPIO_PF10, PF10_DATA),
PINMUX_GPIO(GPIO_PF9, PF9_DATA),
PINMUX_GPIO(GPIO_PF8, PF8_DATA),
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
PINMUX_GPIO(PF12),
PINMUX_GPIO(PF11),
PINMUX_GPIO(PF10),
PINMUX_GPIO(PF9),
PINMUX_GPIO(PF8),
PINMUX_GPIO(PF7),
PINMUX_GPIO(PF6),
PINMUX_GPIO(PF5),
PINMUX_GPIO(PF4),
PINMUX_GPIO(PF3),
PINMUX_GPIO(PF2),
PINMUX_GPIO(PF1),
PINMUX_GPIO(PF0),
/* Port G */
PINMUX_GPIO(GPIO_PG24, PG24_DATA),
PINMUX_GPIO(GPIO_PG23, PG23_DATA),
PINMUX_GPIO(GPIO_PG22, PG22_DATA),
PINMUX_GPIO(GPIO_PG21, PG21_DATA),
PINMUX_GPIO(GPIO_PG20, PG20_DATA),
PINMUX_GPIO(GPIO_PG19, PG19_DATA),
PINMUX_GPIO(GPIO_PG18, PG18_DATA),
PINMUX_GPIO(GPIO_PG17, PG17_DATA),
PINMUX_GPIO(GPIO_PG16, PG16_DATA),
PINMUX_GPIO(GPIO_PG15, PG15_DATA),
PINMUX_GPIO(GPIO_PG14, PG14_DATA),
PINMUX_GPIO(GPIO_PG13, PG13_DATA),
PINMUX_GPIO(GPIO_PG12, PG12_DATA),
PINMUX_GPIO(GPIO_PG11, PG11_DATA),
PINMUX_GPIO(GPIO_PG10, PG10_DATA),
PINMUX_GPIO(GPIO_PG9, PG9_DATA),
PINMUX_GPIO(GPIO_PG8, PG8_DATA),
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
PINMUX_GPIO(GPIO_PG4, PG4_DATA),
PINMUX_GPIO(GPIO_PG3, PG3_DATA),
PINMUX_GPIO(GPIO_PG2, PG2_DATA),
PINMUX_GPIO(GPIO_PG1, PG1_DATA),
PINMUX_GPIO(GPIO_PG0, PG0_DATA),
PINMUX_GPIO(PG24),
PINMUX_GPIO(PG23),
PINMUX_GPIO(PG22),
PINMUX_GPIO(PG21),
PINMUX_GPIO(PG20),
PINMUX_GPIO(PG19),
PINMUX_GPIO(PG18),
PINMUX_GPIO(PG17),
PINMUX_GPIO(PG16),
PINMUX_GPIO(PG15),
PINMUX_GPIO(PG14),
PINMUX_GPIO(PG13),
PINMUX_GPIO(PG12),
PINMUX_GPIO(PG11),
PINMUX_GPIO(PG10),
PINMUX_GPIO(PG9),
PINMUX_GPIO(PG8),
PINMUX_GPIO(PG7),
PINMUX_GPIO(PG6),
PINMUX_GPIO(PG5),
PINMUX_GPIO(PG4),
PINMUX_GPIO(PG3),
PINMUX_GPIO(PG2),
PINMUX_GPIO(PG1),
PINMUX_GPIO(PG0),
/* Port H - Port H does not have a Data Register */
/* Port I - not on device */
/* Port J */
PINMUX_GPIO(GPIO_PJ11, PJ11_DATA),
PINMUX_GPIO(GPIO_PJ10, PJ10_DATA),
PINMUX_GPIO(GPIO_PJ9, PJ9_DATA),
PINMUX_GPIO(GPIO_PJ8, PJ8_DATA),
PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
PINMUX_GPIO(PJ11),
PINMUX_GPIO(PJ10),
PINMUX_GPIO(PJ9),
PINMUX_GPIO(PJ8),
PINMUX_GPIO(PJ7),
PINMUX_GPIO(PJ6),
PINMUX_GPIO(PJ5),
PINMUX_GPIO(PJ4),
PINMUX_GPIO(PJ3),
PINMUX_GPIO(PJ2),
PINMUX_GPIO(PJ1),
PINMUX_GPIO(PJ0),
/* Port K */
PINMUX_GPIO(GPIO_PK11, PK11_DATA),
PINMUX_GPIO(GPIO_PK10, PK10_DATA),
PINMUX_GPIO(GPIO_PK9, PK9_DATA),
PINMUX_GPIO(GPIO_PK8, PK8_DATA),
PINMUX_GPIO(GPIO_PK7, PK7_DATA),
PINMUX_GPIO(GPIO_PK6, PK6_DATA),
PINMUX_GPIO(GPIO_PK5, PK5_DATA),
PINMUX_GPIO(GPIO_PK4, PK4_DATA),
PINMUX_GPIO(GPIO_PK3, PK3_DATA),
PINMUX_GPIO(GPIO_PK2, PK2_DATA),
PINMUX_GPIO(GPIO_PK1, PK1_DATA),
PINMUX_GPIO(GPIO_PK0, PK0_DATA),
PINMUX_GPIO(PK11),
PINMUX_GPIO(PK10),
PINMUX_GPIO(PK9),
PINMUX_GPIO(PK8),
PINMUX_GPIO(PK7),
PINMUX_GPIO(PK6),
PINMUX_GPIO(PK5),
PINMUX_GPIO(PK4),
PINMUX_GPIO(PK3),
PINMUX_GPIO(PK2),
PINMUX_GPIO(PK1),
PINMUX_GPIO(PK0),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)

285
drivers/pinctrl/sh-pfc/pfc-sh7269.c
View File

@ -781,8 +781,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* Port A */
PINMUX_DATA(PA1_DATA, PA1_IN),
PINMUX_DATA(PA0_DATA, PA0_IN),
@ -1454,165 +1453,165 @@ static const pinmux_enum_t pinmux_data[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
PINMUX_GPIO(PA1),
PINMUX_GPIO(PA0),
/* Port B */
PINMUX_GPIO(GPIO_PB22, PB22_DATA),
PINMUX_GPIO(GPIO_PB21, PB21_DATA),
PINMUX_GPIO(GPIO_PB20, PB20_DATA),
PINMUX_GPIO(GPIO_PB19, PB19_DATA),
PINMUX_GPIO(GPIO_PB18, PB18_DATA),
PINMUX_GPIO(GPIO_PB17, PB17_DATA),
PINMUX_GPIO(GPIO_PB16, PB16_DATA),
PINMUX_GPIO(GPIO_PB15, PB15_DATA),
PINMUX_GPIO(GPIO_PB14, PB14_DATA),
PINMUX_GPIO(GPIO_PB13, PB13_DATA),
PINMUX_GPIO(GPIO_PB12, PB12_DATA),
PINMUX_GPIO(GPIO_PB11, PB11_DATA),
PINMUX_GPIO(GPIO_PB10, PB10_DATA),
PINMUX_GPIO(GPIO_PB9, PB9_DATA),
PINMUX_GPIO(GPIO_PB8, PB8_DATA),
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
PINMUX_GPIO(PB22),
PINMUX_GPIO(PB21),
PINMUX_GPIO(PB20),
PINMUX_GPIO(PB19),
PINMUX_GPIO(PB18),
PINMUX_GPIO(PB17),
PINMUX_GPIO(PB16),
PINMUX_GPIO(PB15),
PINMUX_GPIO(PB14),
PINMUX_GPIO(PB13),
PINMUX_GPIO(PB12),
PINMUX_GPIO(PB11),
PINMUX_GPIO(PB10),
PINMUX_GPIO(PB9),
PINMUX_GPIO(PB8),
PINMUX_GPIO(PB7),
PINMUX_GPIO(PB6),
PINMUX_GPIO(PB5),
PINMUX_GPIO(PB4),
PINMUX_GPIO(PB3),
PINMUX_GPIO(PB2),
PINMUX_GPIO(PB1),
/* Port C */
PINMUX_GPIO(GPIO_PC8, PC8_DATA),
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
PINMUX_GPIO(PC8),
PINMUX_GPIO(PC7),
PINMUX_GPIO(PC6),
PINMUX_GPIO(PC5),
PINMUX_GPIO(PC4),
PINMUX_GPIO(PC3),
PINMUX_GPIO(PC2),
PINMUX_GPIO(PC1),
PINMUX_GPIO(PC0),
/* Port D */
PINMUX_GPIO(GPIO_PD15, PD15_DATA),
PINMUX_GPIO(GPIO_PD14, PD14_DATA),
PINMUX_GPIO(GPIO_PD13, PD13_DATA),
PINMUX_GPIO(GPIO_PD12, PD12_DATA),
PINMUX_GPIO(GPIO_PD11, PD11_DATA),
PINMUX_GPIO(GPIO_PD10, PD10_DATA),
PINMUX_GPIO(GPIO_PD9, PD9_DATA),
PINMUX_GPIO(GPIO_PD8, PD8_DATA),
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
PINMUX_GPIO(PD15),
PINMUX_GPIO(PD14),
PINMUX_GPIO(PD13),
PINMUX_GPIO(PD12),
PINMUX_GPIO(PD11),
PINMUX_GPIO(PD10),
PINMUX_GPIO(PD9),
PINMUX_GPIO(PD8),
PINMUX_GPIO(PD7),
PINMUX_GPIO(PD6),
PINMUX_GPIO(PD5),
PINMUX_GPIO(PD4),
PINMUX_GPIO(PD3),
PINMUX_GPIO(PD2),
PINMUX_GPIO(PD1),
PINMUX_GPIO(PD0),
/* Port E */
PINMUX_GPIO(GPIO_PE7, PE7_DATA),
PINMUX_GPIO(GPIO_PE6, PE6_DATA),
PINMUX_GPIO(GPIO_PE5, PE5_DATA),
PINMUX_GPIO(GPIO_PE4, PE4_DATA),
PINMUX_GPIO(GPIO_PE3, PE3_DATA),
PINMUX_GPIO(GPIO_PE2, PE2_DATA),
PINMUX_GPIO(GPIO_PE1, PE1_DATA),
PINMUX_GPIO(GPIO_PE0, PE0_DATA),
PINMUX_GPIO(PE7),
PINMUX_GPIO(PE6),
PINMUX_GPIO(PE5),
PINMUX_GPIO(PE4),
PINMUX_GPIO(PE3),
PINMUX_GPIO(PE2),
PINMUX_GPIO(PE1),
PINMUX_GPIO(PE0),
/* Port F */
PINMUX_GPIO(GPIO_PF23, PF23_DATA),
PINMUX_GPIO(GPIO_PF22, PF22_DATA),
PINMUX_GPIO(GPIO_PF21, PF21_DATA),
PINMUX_GPIO(GPIO_PF20, PF20_DATA),
PINMUX_GPIO(GPIO_PF19, PF19_DATA),
PINMUX_GPIO(GPIO_PF18, PF18_DATA),
PINMUX_GPIO(GPIO_PF17, PF17_DATA),
PINMUX_GPIO(GPIO_PF16, PF16_DATA),
PINMUX_GPIO(GPIO_PF15, PF15_DATA),
PINMUX_GPIO(GPIO_PF14, PF14_DATA),
PINMUX_GPIO(GPIO_PF13, PF13_DATA),
PINMUX_GPIO(GPIO_PF12, PF12_DATA),
PINMUX_GPIO(GPIO_PF11, PF11_DATA),
PINMUX_GPIO(GPIO_PF10, PF10_DATA),
PINMUX_GPIO(GPIO_PF9, PF9_DATA),
PINMUX_GPIO(GPIO_PF8, PF8_DATA),
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
PINMUX_GPIO(PF23),
PINMUX_GPIO(PF22),
PINMUX_GPIO(PF21),
PINMUX_GPIO(PF20),
PINMUX_GPIO(PF19),
PINMUX_GPIO(PF18),
PINMUX_GPIO(PF17),
PINMUX_GPIO(PF16),
PINMUX_GPIO(PF15),
PINMUX_GPIO(PF14),
PINMUX_GPIO(PF13),
PINMUX_GPIO(PF12),
PINMUX_GPIO(PF11),
PINMUX_GPIO(PF10),
PINMUX_GPIO(PF9),
PINMUX_GPIO(PF8),
PINMUX_GPIO(PF7),
PINMUX_GPIO(PF6),
PINMUX_GPIO(PF5),
PINMUX_GPIO(PF4),
PINMUX_GPIO(PF3),
PINMUX_GPIO(PF2),
PINMUX_GPIO(PF1),
PINMUX_GPIO(PF0),
/* Port G */
PINMUX_GPIO(GPIO_PG27, PG27_DATA),
PINMUX_GPIO(GPIO_PG26, PG26_DATA),
PINMUX_GPIO(GPIO_PG25, PG25_DATA),
PINMUX_GPIO(GPIO_PG24, PG24_DATA),
PINMUX_GPIO(GPIO_PG23, PG23_DATA),
PINMUX_GPIO(GPIO_PG22, PG22_DATA),
PINMUX_GPIO(GPIO_PG21, PG21_DATA),
PINMUX_GPIO(GPIO_PG20, PG20_DATA),
PINMUX_GPIO(GPIO_PG19, PG19_DATA),
PINMUX_GPIO(GPIO_PG18, PG18_DATA),
PINMUX_GPIO(GPIO_PG17, PG17_DATA),
PINMUX_GPIO(GPIO_PG16, PG16_DATA),
PINMUX_GPIO(GPIO_PG15, PG15_DATA),
PINMUX_GPIO(GPIO_PG14, PG14_DATA),
PINMUX_GPIO(GPIO_PG13, PG13_DATA),
PINMUX_GPIO(GPIO_PG12, PG12_DATA),
PINMUX_GPIO(GPIO_PG11, PG11_DATA),
PINMUX_GPIO(GPIO_PG10, PG10_DATA),
PINMUX_GPIO(GPIO_PG9, PG9_DATA),
PINMUX_GPIO(GPIO_PG8, PG8_DATA),
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
PINMUX_GPIO(GPIO_PG4, PG4_DATA),
PINMUX_GPIO(GPIO_PG3, PG3_DATA),
PINMUX_GPIO(GPIO_PG2, PG2_DATA),
PINMUX_GPIO(GPIO_PG1, PG1_DATA),
PINMUX_GPIO(GPIO_PG0, PG0_DATA),
PINMUX_GPIO(PG27),
PINMUX_GPIO(PG26),
PINMUX_GPIO(PG25),
PINMUX_GPIO(PG24),
PINMUX_GPIO(PG23),
PINMUX_GPIO(PG22),
PINMUX_GPIO(PG21),
PINMUX_GPIO(PG20),
PINMUX_GPIO(PG19),
PINMUX_GPIO(PG18),
PINMUX_GPIO(PG17),
PINMUX_GPIO(PG16),
PINMUX_GPIO(PG15),
PINMUX_GPIO(PG14),
PINMUX_GPIO(PG13),
PINMUX_GPIO(PG12),
PINMUX_GPIO(PG11),
PINMUX_GPIO(PG10),
PINMUX_GPIO(PG9),
PINMUX_GPIO(PG8),
PINMUX_GPIO(PG7),
PINMUX_GPIO(PG6),
PINMUX_GPIO(PG5),
PINMUX_GPIO(PG4),
PINMUX_GPIO(PG3),
PINMUX_GPIO(PG2),
PINMUX_GPIO(PG1),
PINMUX_GPIO(PG0),
/* Port H - Port H does not have a Data Register */
/* Port I - not on device */
/* Port J */
PINMUX_GPIO(GPIO_PJ31, PJ31_DATA),
PINMUX_GPIO(GPIO_PJ30, PJ30_DATA),
PINMUX_GPIO(GPIO_PJ29, PJ29_DATA),
PINMUX_GPIO(GPIO_PJ28, PJ28_DATA),
PINMUX_GPIO(GPIO_PJ27, PJ27_DATA),
PINMUX_GPIO(GPIO_PJ26, PJ26_DATA),
PINMUX_GPIO(GPIO_PJ25, PJ25_DATA),
PINMUX_GPIO(GPIO_PJ24, PJ24_DATA),
PINMUX_GPIO(GPIO_PJ23, PJ23_DATA),
PINMUX_GPIO(GPIO_PJ22, PJ22_DATA),
PINMUX_GPIO(GPIO_PJ21, PJ21_DATA),
PINMUX_GPIO(GPIO_PJ20, PJ20_DATA),
PINMUX_GPIO(GPIO_PJ19, PJ19_DATA),
PINMUX_GPIO(GPIO_PJ18, PJ18_DATA),
PINMUX_GPIO(GPIO_PJ17, PJ17_DATA),
PINMUX_GPIO(GPIO_PJ16, PJ16_DATA),
PINMUX_GPIO(GPIO_PJ15, PJ15_DATA),
PINMUX_GPIO(GPIO_PJ14, PJ14_DATA),
PINMUX_GPIO(GPIO_PJ13, PJ13_DATA),
PINMUX_GPIO(GPIO_PJ12, PJ12_DATA),
PINMUX_GPIO(GPIO_PJ11, PJ11_DATA),
PINMUX_GPIO(GPIO_PJ10, PJ10_DATA),
PINMUX_GPIO(GPIO_PJ9, PJ9_DATA),
PINMUX_GPIO(GPIO_PJ8, PJ8_DATA),
PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
PINMUX_GPIO(PJ31),
PINMUX_GPIO(PJ30),
PINMUX_GPIO(PJ29),
PINMUX_GPIO(PJ28),
PINMUX_GPIO(PJ27),
PINMUX_GPIO(PJ26),
PINMUX_GPIO(PJ25),
PINMUX_GPIO(PJ24),
PINMUX_GPIO(PJ23),
PINMUX_GPIO(PJ22),
PINMUX_GPIO(PJ21),
PINMUX_GPIO(PJ20),
PINMUX_GPIO(PJ19),
PINMUX_GPIO(PJ18),
PINMUX_GPIO(PJ17),
PINMUX_GPIO(PJ16),
PINMUX_GPIO(PJ15),
PINMUX_GPIO(PJ14),
PINMUX_GPIO(PJ13),
PINMUX_GPIO(PJ12),
PINMUX_GPIO(PJ11),
PINMUX_GPIO(PJ10),
PINMUX_GPIO(PJ9),
PINMUX_GPIO(PJ8),
PINMUX_GPIO(PJ7),
PINMUX_GPIO(PJ6),
PINMUX_GPIO(PJ5),
PINMUX_GPIO(PJ4),
PINMUX_GPIO(PJ3),
PINMUX_GPIO(PJ2),
PINMUX_GPIO(PJ1),
PINMUX_GPIO(PJ0),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)

57
drivers/pinctrl/sh-pfc/pfc-sh7372.c
View File

@ -23,27 +23,18 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <mach/irqs.h>
#include <mach/sh7372.h>
#include <linux/sh_intc.h>
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), PORT_10(fn, pfx##11, sfx), \
PORT_10(fn, pfx##12, sfx), PORT_10(fn, pfx##13, sfx), \
PORT_10(fn, pfx##14, sfx), PORT_10(fn, pfx##15, sfx), \
PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \
PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx)
#undef _GPIO_PORT
#define _GPIO_PORT(gpio, sfx) \
[gpio] = { \
.name = __stringify(PORT##gpio), \
.enum_id = PORT##gpio##_DATA, \
}
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \
PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \
PORT_10(140, fn, pfx##14, sfx), PORT_10(150, fn, pfx##15, sfx), \
PORT_10(160, fn, pfx##16, sfx), PORT_10(170, fn, pfx##17, sfx), \
PORT_10(180, fn, pfx##18, sfx), PORT_1(190, fn, pfx##190, sfx)
#define IRQC_PIN_MUX(irq, pin) \
static const unsigned int intc_irq##irq##_pins[] = { \
@ -391,11 +382,8 @@ enum {
PINMUX_MARK_END,
};
#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
static const u16 pinmux_data[] = {
PINMUX_DATA_ALL(),
/* IRQ */
PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0),
@ -839,13 +827,6 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
};
#define SH7372_PIN(pin, cfgs) \
{ \
.name = __stringify(PORT##pin), \
.enum_id = PORT##pin##_DATA, \
.configs = cfgs, \
}
#define __I (SH_PFC_PIN_CFG_INPUT)
#define __O (SH_PFC_PIN_CFG_OUTPUT)
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
@ -853,15 +834,15 @@ static const pinmux_enum_t pinmux_data[] = {
#define __PU (SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
#define SH7372_PIN_I_PD(pin) SH7372_PIN(pin, __I | __PD)
#define SH7372_PIN_I_PU(pin) SH7372_PIN(pin, __I | __PU)
#define SH7372_PIN_I_PU_PD(pin) SH7372_PIN(pin, __I | __PUD)
#define SH7372_PIN_IO(pin) SH7372_PIN(pin, __IO)
#define SH7372_PIN_IO_PD(pin) SH7372_PIN(pin, __IO | __PD)
#define SH7372_PIN_IO_PU(pin) SH7372_PIN(pin, __IO | __PU)
#define SH7372_PIN_IO_PU_PD(pin) SH7372_PIN(pin, __IO | __PUD)
#define SH7372_PIN_O(pin) SH7372_PIN(pin, __O)
#define SH7372_PIN_O_PU_PD(pin) SH7372_PIN(pin, __O | __PUD)
#define SH7372_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
#define SH7372_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
#define SH7372_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
#define SH7372_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
#define SH7372_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
#define SH7372_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
#define SH7372_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define SH7372_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
#define SH7372_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
static struct sh_pfc_pin pinmux_pins[] = {
/* Table 57-1 (I/O and Pull U/D) */

172
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
View File

@ -31,32 +31,32 @@
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), \
PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
PORT_1(fn, pfx##118, sfx), \
PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
PORT_10(fn, pfx##15, sfx), \
PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
PORT_1(fn, pfx##164, sfx), \
PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \
PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
PORT_1(fn, pfx##282, sfx), \
PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
PORT_10(100, fn, pfx##10, sfx), \
PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
PORT_1(118, fn, pfx##118, sfx), \
PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
PORT_10(150, fn, pfx##15, sfx), \
PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \
PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \
PORT_1(164, fn, pfx##164, sfx), \
PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \
PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \
PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \
PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \
PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
PORT_1(282, fn, pfx##282, sfx), \
PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
enum {
PINMUX_RESERVED = 0,
@ -466,12 +466,9 @@ enum {
PINMUX_MARK_END,
};
#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
PINMUX_DATA_GP_ALL(),
PINMUX_DATA_ALL(),
/* Table 25-1 (Function 0-7) */
PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
@ -1160,13 +1157,6 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
};
#define SH73A0_PIN(pin, cfgs) \
{ \
.name = __stringify(PORT##pin), \
.enum_id = PORT##pin##_DATA, \
.configs = cfgs, \
}
#define __I (SH_PFC_PIN_CFG_INPUT)
#define __O (SH_PFC_PIN_CFG_OUTPUT)
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
@ -1174,14 +1164,20 @@ static const pinmux_enum_t pinmux_data[] = {
#define __PU (SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD)
#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU)
#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD)
#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO)
#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD)
#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU)
#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD)
#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O)
#define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
#define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
#define SH73A0_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
#define SH73A0_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
#define SH73A0_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
#define SH73A0_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
#define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
/* Pin numbers for pins without a corresponding GPIO port number are computed
* from the row and column numbers with a 1000 offset to avoid collisions with
* GPIO port numbers.
*/
#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
static struct sh_pfc_pin pinmux_pins[] = {
/* Table 25-1 (I/O and Pull U/D) */
@ -1454,21 +1450,11 @@ static struct sh_pfc_pin pinmux_pins[] = {
SH73A0_PIN_O(307),
SH73A0_PIN_I_PU(308),
SH73A0_PIN_O(309),
};
static const struct pinmux_range pinmux_ranges[] = {
{.begin = 0, .end = 118,},
{.begin = 128, .end = 164,},
{.begin = 192, .end = 282,},
{.begin = 288, .end = 309,},
/* Pins not associated with a GPIO port */
SH_PFC_PIN_NAMED(6, 26, F26),
};
/* Pin numbers for pins without a corresponding GPIO port number are computed
* from the row and column numbers with a 1000 offset to avoid collisions with
* GPIO port numbers.
*/
#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
/* - BSC -------------------------------------------------------------------- */
static const unsigned int bsc_data_0_7_pins[] = {
/* D[0:7] */
@ -3674,43 +3660,39 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
/* External IRQ pins mapped at IRQPIN_BASE */
#define EXT_IRQ16L(n) irq_pin(n)
#define EXT_IRQ16H(n) irq_pin(n)
static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(EXT_IRQ16H(19), 9),
PINMUX_IRQ(EXT_IRQ16L(1), 10),
PINMUX_IRQ(EXT_IRQ16L(0), 11),
PINMUX_IRQ(EXT_IRQ16H(18), 13),
PINMUX_IRQ(EXT_IRQ16H(20), 14),
PINMUX_IRQ(EXT_IRQ16H(21), 15),
PINMUX_IRQ(EXT_IRQ16H(31), 26),
PINMUX_IRQ(EXT_IRQ16H(30), 27),
PINMUX_IRQ(EXT_IRQ16H(29), 28),
PINMUX_IRQ(EXT_IRQ16H(22), 40),
PINMUX_IRQ(EXT_IRQ16H(23), 53),
PINMUX_IRQ(EXT_IRQ16L(10), 54),
PINMUX_IRQ(EXT_IRQ16L(9), 56),
PINMUX_IRQ(EXT_IRQ16H(26), 115),
PINMUX_IRQ(EXT_IRQ16H(27), 116),
PINMUX_IRQ(EXT_IRQ16H(28), 117),
PINMUX_IRQ(EXT_IRQ16H(24), 118),
PINMUX_IRQ(EXT_IRQ16L(6), 147),
PINMUX_IRQ(EXT_IRQ16L(2), 149),
PINMUX_IRQ(EXT_IRQ16L(7), 150),
PINMUX_IRQ(EXT_IRQ16L(12), 156),
PINMUX_IRQ(EXT_IRQ16L(4), 159),
PINMUX_IRQ(EXT_IRQ16H(25), 164),
PINMUX_IRQ(EXT_IRQ16L(8), 223),
PINMUX_IRQ(EXT_IRQ16L(3), 224),
PINMUX_IRQ(EXT_IRQ16L(5), 227),
PINMUX_IRQ(EXT_IRQ16H(17), 234),
PINMUX_IRQ(EXT_IRQ16L(11), 238),
PINMUX_IRQ(EXT_IRQ16L(13), 239),
PINMUX_IRQ(EXT_IRQ16H(16), 249),
PINMUX_IRQ(EXT_IRQ16L(14), 251),
PINMUX_IRQ(EXT_IRQ16L(9), 308),
PINMUX_IRQ(irq_pin(19), 9),
PINMUX_IRQ(irq_pin(1), 10),
PINMUX_IRQ(irq_pin(0), 11),
PINMUX_IRQ(irq_pin(18), 13),
PINMUX_IRQ(irq_pin(20), 14),
PINMUX_IRQ(irq_pin(21), 15),
PINMUX_IRQ(irq_pin(31), 26),
PINMUX_IRQ(irq_pin(30), 27),
PINMUX_IRQ(irq_pin(29), 28),
PINMUX_IRQ(irq_pin(22), 40),
PINMUX_IRQ(irq_pin(23), 53),
PINMUX_IRQ(irq_pin(10), 54),
PINMUX_IRQ(irq_pin(9), 56),
PINMUX_IRQ(irq_pin(26), 115),
PINMUX_IRQ(irq_pin(27), 116),
PINMUX_IRQ(irq_pin(28), 117),
PINMUX_IRQ(irq_pin(24), 118),
PINMUX_IRQ(irq_pin(6), 147),
PINMUX_IRQ(irq_pin(2), 149),
PINMUX_IRQ(irq_pin(7), 150),
PINMUX_IRQ(irq_pin(12), 156),
PINMUX_IRQ(irq_pin(4), 159),
PINMUX_IRQ(irq_pin(25), 164),
PINMUX_IRQ(irq_pin(8), 223),
PINMUX_IRQ(irq_pin(3), 224),
PINMUX_IRQ(irq_pin(5), 227),
PINMUX_IRQ(irq_pin(17), 234),
PINMUX_IRQ(irq_pin(11), 238),
PINMUX_IRQ(irq_pin(13), 239),
PINMUX_IRQ(irq_pin(16), 249),
PINMUX_IRQ(irq_pin(14), 251),
PINMUX_IRQ(irq_pin(9), 308),
};
/* -----------------------------------------------------------------------------
@ -3905,8 +3887,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.ranges = pinmux_ranges,
.nr_ranges = ARRAY_SIZE(pinmux_ranges),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,

701
drivers/pinctrl/sh-pfc/pfc-sh7720.c
View File

@ -81,36 +81,6 @@ enum {
PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU,
PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU,
PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU,
PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU,
PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
PTE4_IN_PU, PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
PTF0_IN_PU,
PTG6_IN_PU, PTG5_IN_PU, PTG4_IN_PU,
PTG3_IN_PU, PTG2_IN_PU, PTG1_IN_PU, PTG0_IN_PU,
PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU,
PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, PTL3_IN_PU,
PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU,
PTP4_IN_PU, PTP3_IN_PU, PTP2_IN_PU, PTP1_IN_PU, PTP0_IN_PU,
PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU,
PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU,
PTS4_IN_PU, PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU,
PTT4_IN_PU, PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
PTU4_IN_PU, PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
PTV4_IN_PU, PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU,
PINMUX_INPUT_PULLUP_END,
PINMUX_OUTPUT_BEGIN,
PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
@ -262,55 +232,55 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* PTA GPIO */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU),
PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU),
PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU),
PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU),
PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU),
PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU),
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT),
PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT),
PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT),
PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT),
PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT),
/* PTB GPIO */
PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU),
PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU),
PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU),
PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU),
PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU),
PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU),
PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU),
PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU),
PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
/* PTC GPIO */
PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU),
PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU),
PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU),
PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU),
PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU),
PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU),
PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU),
PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU),
PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT),
PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT),
PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT),
PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT),
PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
/* PTD GPIO */
PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU),
PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU),
PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU),
PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU),
PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU),
PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU),
PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU),
PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU),
PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT),
PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT),
PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT),
PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT),
PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT),
PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT),
PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT),
PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
/* PTE GPIO */
PINMUX_DATA(PTE6_DATA, PTE6_IN),
PINMUX_DATA(PTE5_DATA, PTE5_IN),
PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU),
PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU),
PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU),
PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU),
PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU),
PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT),
PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT),
PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT),
/* PTF GPIO */
PINMUX_DATA(PTF6_DATA, PTF6_IN),
@ -319,102 +289,102 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(PTF3_DATA, PTF3_IN),
PINMUX_DATA(PTF2_DATA, PTF2_IN),
PINMUX_DATA(PTF1_DATA, PTF1_IN),
PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU),
PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT),
/* PTG GPIO */
PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT, PTG6_IN_PU),
PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT, PTG5_IN_PU),
PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT, PTG4_IN_PU),
PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT, PTG3_IN_PU),
PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT, PTG2_IN_PU),
PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT, PTG1_IN_PU),
PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT, PTG0_IN_PU),
PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT),
PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT),
PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT),
PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT),
PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT),
PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT),
PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT),
/* PTH GPIO */
PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU),
PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU),
PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU),
PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU),
PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU),
PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU),
PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU),
PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT),
PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT),
PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT),
PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT),
PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT),
PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT),
PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT),
/* PTJ GPIO */
PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT, PTJ6_IN_PU),
PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT, PTJ5_IN_PU),
PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT, PTJ4_IN_PU),
PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU),
PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU),
PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU),
PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU),
PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT),
PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT),
PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT),
PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT),
PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT),
PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT),
PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT),
/* PTK GPIO */
PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU),
PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU),
PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU),
PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU),
PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT),
PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT),
PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT),
PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
/* PTL GPIO */
PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU),
PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU),
PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU),
PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU),
PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU),
PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT),
PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT),
/* PTM GPIO */
PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU),
PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU),
PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU),
PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU),
PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU),
PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU),
PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU),
PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU),
PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT),
PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT),
PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT),
PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT),
PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT),
PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT),
PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT),
PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
/* PTP GPIO */
PINMUX_DATA(PTP4_DATA, PTP4_IN, PTP4_OUT, PTP4_IN_PU),
PINMUX_DATA(PTP3_DATA, PTP3_IN, PTP3_OUT, PTP3_IN_PU),
PINMUX_DATA(PTP2_DATA, PTP2_IN, PTP2_OUT, PTP2_IN_PU),
PINMUX_DATA(PTP1_DATA, PTP1_IN, PTP1_OUT, PTP1_IN_PU),
PINMUX_DATA(PTP0_DATA, PTP0_IN, PTP0_OUT, PTP0_IN_PU),
PINMUX_DATA(PTP4_DATA, PTP4_IN, PTP4_OUT),
PINMUX_DATA(PTP3_DATA, PTP3_IN, PTP3_OUT),
PINMUX_DATA(PTP2_DATA, PTP2_IN, PTP2_OUT),
PINMUX_DATA(PTP1_DATA, PTP1_IN, PTP1_OUT),
PINMUX_DATA(PTP0_DATA, PTP0_IN, PTP0_OUT),
/* PTR GPIO */
PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU),
PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU),
PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU),
PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU),
PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT, PTR3_IN_PU),
PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT, PTR2_IN_PU),
PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU),
PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU),
PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT),
PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT),
PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT),
PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT),
PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
/* PTS GPIO */
PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU),
PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU),
PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU),
PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU),
PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU),
PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT),
PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT),
PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT),
PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT),
PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
/* PTT GPIO */
PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU),
PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU),
PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU),
PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU),
PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU),
PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT),
PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT),
PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT),
/* PTU GPIO */
PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU),
PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU),
PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU),
PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU),
PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU),
PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT),
PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT),
PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT),
PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT),
PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT),
/* PTV GPIO */
PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU),
PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU),
PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU),
PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU),
PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU),
PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT),
PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT),
PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT),
PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT),
PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT),
/* PTA FN */
PINMUX_DATA(D23_MARK, PTA7_FN),
@ -608,157 +578,157 @@ static const pinmux_enum_t pinmux_data[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
PINMUX_GPIO(PTA7),
PINMUX_GPIO(PTA6),
PINMUX_GPIO(PTA5),
PINMUX_GPIO(PTA4),
PINMUX_GPIO(PTA3),
PINMUX_GPIO(PTA2),
PINMUX_GPIO(PTA1),
PINMUX_GPIO(PTA0),
/* PTB */
PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
PINMUX_GPIO(PTB7),
PINMUX_GPIO(PTB6),
PINMUX_GPIO(PTB5),
PINMUX_GPIO(PTB4),
PINMUX_GPIO(PTB3),
PINMUX_GPIO(PTB2),
PINMUX_GPIO(PTB1),
PINMUX_GPIO(PTB0),
/* PTC */
PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
PINMUX_GPIO(PTC7),
PINMUX_GPIO(PTC6),
PINMUX_GPIO(PTC5),
PINMUX_GPIO(PTC4),
PINMUX_GPIO(PTC3),
PINMUX_GPIO(PTC2),
PINMUX_GPIO(PTC1),
PINMUX_GPIO(PTC0),
/* PTD */
PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
PINMUX_GPIO(PTD7),
PINMUX_GPIO(PTD6),
PINMUX_GPIO(PTD5),
PINMUX_GPIO(PTD4),
PINMUX_GPIO(PTD3),
PINMUX_GPIO(PTD2),
PINMUX_GPIO(PTD1),
PINMUX_GPIO(PTD0),
/* PTE */
PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
PINMUX_GPIO(PTE6),
PINMUX_GPIO(PTE5),
PINMUX_GPIO(PTE4),
PINMUX_GPIO(PTE3),
PINMUX_GPIO(PTE2),
PINMUX_GPIO(PTE1),
PINMUX_GPIO(PTE0),
/* PTF */
PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
PINMUX_GPIO(PTF6),
PINMUX_GPIO(PTF5),
PINMUX_GPIO(PTF4),
PINMUX_GPIO(PTF3),
PINMUX_GPIO(PTF2),
PINMUX_GPIO(PTF1),
PINMUX_GPIO(PTF0),
/* PTG */
PINMUX_GPIO(GPIO_PTG6, PTG6_DATA),
PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
PINMUX_GPIO(PTG6),
PINMUX_GPIO(PTG5),
PINMUX_GPIO(PTG4),
PINMUX_GPIO(PTG3),
PINMUX_GPIO(PTG2),
PINMUX_GPIO(PTG1),
PINMUX_GPIO(PTG0),
/* PTH */
PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
PINMUX_GPIO(PTH6),
PINMUX_GPIO(PTH5),
PINMUX_GPIO(PTH4),
PINMUX_GPIO(PTH3),
PINMUX_GPIO(PTH2),
PINMUX_GPIO(PTH1),
PINMUX_GPIO(PTH0),
/* PTJ */
PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA),
PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
PINMUX_GPIO(PTJ6),
PINMUX_GPIO(PTJ5),
PINMUX_GPIO(PTJ4),
PINMUX_GPIO(PTJ3),
PINMUX_GPIO(PTJ2),
PINMUX_GPIO(PTJ1),
PINMUX_GPIO(PTJ0),
/* PTK */
PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
PINMUX_GPIO(PTK3),
PINMUX_GPIO(PTK2),
PINMUX_GPIO(PTK1),
PINMUX_GPIO(PTK0),
/* PTL */
PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
PINMUX_GPIO(PTL7),
PINMUX_GPIO(PTL6),
PINMUX_GPIO(PTL5),
PINMUX_GPIO(PTL4),
PINMUX_GPIO(PTL3),
/* PTM */
PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
PINMUX_GPIO(PTM7),
PINMUX_GPIO(PTM6),
PINMUX_GPIO(PTM5),
PINMUX_GPIO(PTM4),
PINMUX_GPIO(PTM3),
PINMUX_GPIO(PTM2),
PINMUX_GPIO(PTM1),
PINMUX_GPIO(PTM0),
/* PTP */
PINMUX_GPIO(GPIO_PTP4, PTP4_DATA),
PINMUX_GPIO(GPIO_PTP3, PTP3_DATA),
PINMUX_GPIO(GPIO_PTP2, PTP2_DATA),
PINMUX_GPIO(GPIO_PTP1, PTP1_DATA),
PINMUX_GPIO(GPIO_PTP0, PTP0_DATA),
PINMUX_GPIO(PTP4),
PINMUX_GPIO(PTP3),
PINMUX_GPIO(PTP2),
PINMUX_GPIO(PTP1),
PINMUX_GPIO(PTP0),
/* PTR */
PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
PINMUX_GPIO(PTR7),
PINMUX_GPIO(PTR6),
PINMUX_GPIO(PTR5),
PINMUX_GPIO(PTR4),
PINMUX_GPIO(PTR3),
PINMUX_GPIO(PTR2),
PINMUX_GPIO(PTR1),
PINMUX_GPIO(PTR0),
/* PTS */
PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
PINMUX_GPIO(PTS4),
PINMUX_GPIO(PTS3),
PINMUX_GPIO(PTS2),
PINMUX_GPIO(PTS1),
PINMUX_GPIO(PTS0),
/* PTT */
PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
PINMUX_GPIO(PTT4),
PINMUX_GPIO(PTT3),
PINMUX_GPIO(PTT2),
PINMUX_GPIO(PTT1),
PINMUX_GPIO(PTT0),
/* PTU */
PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
PINMUX_GPIO(PTU4),
PINMUX_GPIO(PTU3),
PINMUX_GPIO(PTU2),
PINMUX_GPIO(PTU1),
PINMUX_GPIO(PTU0),
/* PTV */
PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
PINMUX_GPIO(PTV4),
PINMUX_GPIO(PTV3),
PINMUX_GPIO(PTV2),
PINMUX_GPIO(PTV1),
PINMUX_GPIO(PTV0),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
@ -959,54 +929,54 @@ static const struct pinmux_func pinmux_func_gpios[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN,
PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN,
PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN,
PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN,
PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN,
PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN }
PTA7_FN, PTA7_OUT, 0, PTA7_IN,
PTA6_FN, PTA6_OUT, 0, PTA6_IN,
PTA5_FN, PTA5_OUT, 0, PTA5_IN,
PTA4_FN, PTA4_OUT, 0, PTA4_IN,
PTA3_FN, PTA3_OUT, 0, PTA3_IN,
PTA2_FN, PTA2_OUT, 0, PTA2_IN,
PTA1_FN, PTA1_OUT, 0, PTA1_IN,
PTA0_FN, PTA0_OUT, 0, PTA0_IN }
},
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN,
PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN,
PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN,
PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN,
PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN,
PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN,
PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN,
PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN }
PTB7_FN, PTB7_OUT, 0, PTB7_IN,
PTB6_FN, PTB6_OUT, 0, PTB6_IN,
PTB5_FN, PTB5_OUT, 0, PTB5_IN,
PTB4_FN, PTB4_OUT, 0, PTB4_IN,
PTB3_FN, PTB3_OUT, 0, PTB3_IN,
PTB2_FN, PTB2_OUT, 0, PTB2_IN,
PTB1_FN, PTB1_OUT, 0, PTB1_IN,
PTB0_FN, PTB0_OUT, 0, PTB0_IN }
},
{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN,
PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN,
PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN,
PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN,
PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN,
PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN,
PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN,
PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN }
PTC7_FN, PTC7_OUT, 0, PTC7_IN,
PTC6_FN, PTC6_OUT, 0, PTC6_IN,
PTC5_FN, PTC5_OUT, 0, PTC5_IN,
PTC4_FN, PTC4_OUT, 0, PTC4_IN,
PTC3_FN, PTC3_OUT, 0, PTC3_IN,
PTC2_FN, PTC2_OUT, 0, PTC2_IN,
PTC1_FN, PTC1_OUT, 0, PTC1_IN,
PTC0_FN, PTC0_OUT, 0, PTC0_IN }
},
{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN,
PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN,
PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN,
PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN,
PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN,
PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN,
PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN,
PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN }
PTD7_FN, PTD7_OUT, 0, PTD7_IN,
PTD6_FN, PTD6_OUT, 0, PTD6_IN,
PTD5_FN, PTD5_OUT, 0, PTD5_IN,
PTD4_FN, PTD4_OUT, 0, PTD4_IN,
PTD3_FN, PTD3_OUT, 0, PTD3_IN,
PTD2_FN, PTD2_OUT, 0, PTD2_IN,
PTD1_FN, PTD1_OUT, 0, PTD1_IN,
PTD0_FN, PTD0_OUT, 0, PTD0_IN }
},
{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
0, 0, 0, 0,
PTE6_FN, 0, 0, PTE6_IN,
PTE5_FN, 0, 0, PTE5_IN,
PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN,
PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN,
PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN,
PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN,
PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN }
PTE4_FN, PTE4_OUT, 0, PTE4_IN,
PTE3_FN, PTE3_OUT, 0, PTE3_IN,
PTE2_FN, PTE2_OUT, 0, PTE2_IN,
PTE1_FN, PTE1_OUT, 0, PTE1_IN,
PTE0_FN, PTE0_OUT, 0, PTE0_IN }
},
{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
0, 0, 0, 0,
@ -1020,123 +990,123 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
0, 0, 0, 0,
PTG6_FN, PTG6_OUT, PTG6_IN_PU, PTG6_IN,
PTG5_FN, PTG5_OUT, PTG5_IN_PU, PTG5_IN,
PTG4_FN, PTG4_OUT, PTG4_IN_PU, PTG4_IN,
PTG3_FN, PTG3_OUT, PTG3_IN_PU, PTG3_IN,
PTG2_FN, PTG2_OUT, PTG2_IN_PU, PTG2_IN,
PTG1_FN, PTG1_OUT, PTG1_IN_PU, PTG1_IN,
PTG0_FN, PTG0_OUT, PTG0_IN_PU, PTG0_IN }
PTG6_FN, PTG6_OUT, 0, PTG6_IN,
PTG5_FN, PTG5_OUT, 0, PTG5_IN,
PTG4_FN, PTG4_OUT, 0, PTG4_IN,
PTG3_FN, PTG3_OUT, 0, PTG3_IN,
PTG2_FN, PTG2_OUT, 0, PTG2_IN,
PTG1_FN, PTG1_OUT, 0, PTG1_IN,
PTG0_FN, PTG0_OUT, 0, PTG0_IN }
},
{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
0, 0, 0, 0,
PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN,
PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN,
PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN,
PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN,
PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN,
PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN,
PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN }
PTH6_FN, PTH6_OUT, 0, PTH6_IN,
PTH5_FN, PTH5_OUT, 0, PTH5_IN,
PTH4_FN, PTH4_OUT, 0, PTH4_IN,
PTH3_FN, PTH3_OUT, 0, PTH3_IN,
PTH2_FN, PTH2_OUT, 0, PTH2_IN,
PTH1_FN, PTH1_OUT, 0, PTH1_IN,
PTH0_FN, PTH0_OUT, 0, PTH0_IN }
},
{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
0, 0, 0, 0,
PTJ6_FN, PTJ6_OUT, PTJ6_IN_PU, PTJ6_IN,
PTJ5_FN, PTJ5_OUT, PTJ5_IN_PU, PTJ5_IN,
PTJ4_FN, PTJ4_OUT, PTJ4_IN_PU, PTJ4_IN,
PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN,
PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN,
PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN,
PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN }
PTJ6_FN, PTJ6_OUT, 0, PTJ6_IN,
PTJ5_FN, PTJ5_OUT, 0, PTJ5_IN,
PTJ4_FN, PTJ4_OUT, 0, PTJ4_IN,
PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN }
},
{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN,
PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN,
PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN,
PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN }
PTK3_FN, PTK3_OUT, 0, PTK3_IN,
PTK2_FN, PTK2_OUT, 0, PTK2_IN,
PTK1_FN, PTK1_OUT, 0, PTK1_IN,
PTK0_FN, PTK0_OUT, 0, PTK0_IN }
},
{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN,
PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN,
PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN,
PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN,
PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN,
PTL7_FN, PTL7_OUT, 0, PTL7_IN,
PTL6_FN, PTL6_OUT, 0, PTL6_IN,
PTL5_FN, PTL5_OUT, 0, PTL5_IN,
PTL4_FN, PTL4_OUT, 0, PTL4_IN,
PTL3_FN, PTL3_OUT, 0, PTL3_IN,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN,
PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN,
PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN,
PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN,
PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN,
PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN,
PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN,
PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN }
PTM7_FN, PTM7_OUT, 0, PTM7_IN,
PTM6_FN, PTM6_OUT, 0, PTM6_IN,
PTM5_FN, PTM5_OUT, 0, PTM5_IN,
PTM4_FN, PTM4_OUT, 0, PTM4_IN,
PTM3_FN, PTM3_OUT, 0, PTM3_IN,
PTM2_FN, PTM2_OUT, 0, PTM2_IN,
PTM1_FN, PTM1_OUT, 0, PTM1_IN,
PTM0_FN, PTM0_OUT, 0, PTM0_IN }
},
{ PINMUX_CFG_REG("PPCR", 0xa4050118, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
PTP4_FN, PTP4_OUT, PTP4_IN_PU, PTP4_IN,
PTP3_FN, PTP3_OUT, PTP3_IN_PU, PTP3_IN,
PTP2_FN, PTP2_OUT, PTP2_IN_PU, PTP2_IN,
PTP1_FN, PTP1_OUT, PTP1_IN_PU, PTP1_IN,
PTP0_FN, PTP0_OUT, PTP0_IN_PU, PTP0_IN }
PTP4_FN, PTP4_OUT, 0, PTP4_IN,
PTP3_FN, PTP3_OUT, 0, PTP3_IN,
PTP2_FN, PTP2_OUT, 0, PTP2_IN,
PTP1_FN, PTP1_OUT, 0, PTP1_IN,
PTP0_FN, PTP0_OUT, 0, PTP0_IN }
},
{ PINMUX_CFG_REG("PRCR", 0xa405011a, 16, 2) {
PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN,
PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN,
PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN,
PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN,
PTR3_FN, PTR3_OUT, PTR3_IN_PU, PTR3_IN,
PTR2_FN, PTR2_OUT, PTR2_IN_PU, PTR2_IN,
PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN,
PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN }
PTR7_FN, PTR7_OUT, 0, PTR7_IN,
PTR6_FN, PTR6_OUT, 0, PTR6_IN,
PTR5_FN, PTR5_OUT, 0, PTR5_IN,
PTR4_FN, PTR4_OUT, 0, PTR4_IN,
PTR3_FN, PTR3_OUT, 0, PTR3_IN,
PTR2_FN, PTR2_OUT, 0, PTR2_IN,
PTR1_FN, PTR1_OUT, 0, PTR1_IN,
PTR0_FN, PTR0_OUT, 0, PTR0_IN }
},
{ PINMUX_CFG_REG("PSCR", 0xa405011c, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN,
PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN,
PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN,
PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN,
PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN }
PTS4_FN, PTS4_OUT, 0, PTS4_IN,
PTS3_FN, PTS3_OUT, 0, PTS3_IN,
PTS2_FN, PTS2_OUT, 0, PTS2_IN,
PTS1_FN, PTS1_OUT, 0, PTS1_IN,
PTS0_FN, PTS0_OUT, 0, PTS0_IN }
},
{ PINMUX_CFG_REG("PTCR", 0xa405011e, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN,
PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN,
PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN,
PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN,
PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN }
PTT4_FN, PTT4_OUT, 0, PTT4_IN,
PTT3_FN, PTT3_OUT, 0, PTT3_IN,
PTT2_FN, PTT2_OUT, 0, PTT2_IN,
PTT1_FN, PTT1_OUT, 0, PTT1_IN,
PTT0_FN, PTT0_OUT, 0, PTT0_IN }
},
{ PINMUX_CFG_REG("PUCR", 0xa4050120, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN,
PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN,
PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN,
PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN,
PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN }
PTU4_FN, PTU4_OUT, 0, PTU4_IN,
PTU3_FN, PTU3_OUT, 0, PTU3_IN,
PTU2_FN, PTU2_OUT, 0, PTU2_IN,
PTU1_FN, PTU1_OUT, 0, PTU1_IN,
PTU0_FN, PTU0_OUT, 0, PTU0_IN }
},
{ PINMUX_CFG_REG("PVCR", 0xa4050122, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN,
PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN,
PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN,
PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN,
PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN }
PTV4_FN, PTV4_OUT, 0, PTV4_IN,
PTV3_FN, PTV3_OUT, 0, PTV3_IN,
PTV2_FN, PTV2_OUT, 0, PTV2_IN,
PTV1_FN, PTV1_OUT, 0, PTV1_IN,
PTV0_FN, PTV0_OUT, 0, PTV0_IN }
},
{}
};
@ -1220,7 +1190,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
const struct sh_pfc_soc_info sh7720_pinmux_info = {
.name = "sh7720_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

747
drivers/pinctrl/sh-pfc/pfc-sh7722.c
View File

@ -77,39 +77,6 @@ enum {
PTZ5_IN, PTZ4_IN, PTZ3_IN, PTZ2_IN, PTZ1_IN,
PINMUX_INPUT_END,
PINMUX_INPUT_PULLDOWN_BEGIN,
PTA7_IN_PD, PTA6_IN_PD, PTA5_IN_PD, PTA4_IN_PD,
PTA3_IN_PD, PTA2_IN_PD, PTA1_IN_PD, PTA0_IN_PD,
PTE7_IN_PD, PTE6_IN_PD, PTE5_IN_PD, PTE4_IN_PD, PTE1_IN_PD, PTE0_IN_PD,
PTF6_IN_PD, PTF5_IN_PD, PTF4_IN_PD, PTF3_IN_PD, PTF2_IN_PD, PTF1_IN_PD,
PTH6_IN_PD, PTH5_IN_PD, PTH1_IN_PD, PTH0_IN_PD,
PTK6_IN_PD, PTK5_IN_PD, PTK4_IN_PD, PTK3_IN_PD, PTK2_IN_PD, PTK0_IN_PD,
PTL7_IN_PD, PTL6_IN_PD, PTL5_IN_PD, PTL4_IN_PD,
PTL3_IN_PD, PTL2_IN_PD, PTL1_IN_PD, PTL0_IN_PD,
PTM7_IN_PD, PTM6_IN_PD, PTM5_IN_PD, PTM4_IN_PD,
PTM3_IN_PD, PTM2_IN_PD, PTM1_IN_PD, PTM0_IN_PD,
PTQ5_IN_PD, PTQ4_IN_PD, PTQ3_IN_PD, PTQ2_IN_PD,
PTS4_IN_PD, PTS2_IN_PD, PTS1_IN_PD,
PTT4_IN_PD, PTT3_IN_PD, PTT2_IN_PD, PTT1_IN_PD,
PTU4_IN_PD, PTU3_IN_PD, PTU2_IN_PD, PTU1_IN_PD, PTU0_IN_PD,
PTV4_IN_PD, PTV3_IN_PD, PTV2_IN_PD, PTV1_IN_PD, PTV0_IN_PD,
PTW6_IN_PD, PTW4_IN_PD, PTW3_IN_PD, PTW2_IN_PD, PTW1_IN_PD, PTW0_IN_PD,
PTX6_IN_PD, PTX5_IN_PD, PTX4_IN_PD,
PTX3_IN_PD, PTX2_IN_PD, PTX1_IN_PD, PTX0_IN_PD,
PINMUX_INPUT_PULLDOWN_END,
PINMUX_INPUT_PULLUP_BEGIN,
PTC7_IN_PU, PTC5_IN_PU,
PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU,
PTJ1_IN_PU, PTJ0_IN_PU,
PTQ0_IN_PU,
PTR2_IN_PU,
PTX6_IN_PU,
PTY5_IN_PU, PTY4_IN_PU, PTY3_IN_PU, PTY2_IN_PU, PTY0_IN_PU,
PTZ5_IN_PU, PTZ4_IN_PU, PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU,
PINMUX_INPUT_PULLUP_END,
PINMUX_OUTPUT_BEGIN,
PTA7_OUT, PTA5_OUT,
PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
@ -296,16 +263,16 @@ enum {
PINMUX_FUNCTION_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* PTA */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD),
PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_IN_PD, PTA5_OUT),
PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_IN_PD),
PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_IN_PD),
PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_IN_PD),
PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_IN_PD),
PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_IN_PD),
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
PINMUX_DATA(PTA6_DATA, PTA6_IN),
PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
PINMUX_DATA(PTA4_DATA, PTA4_IN),
PINMUX_DATA(PTA3_DATA, PTA3_IN),
PINMUX_DATA(PTA2_DATA, PTA2_IN),
PINMUX_DATA(PTA1_DATA, PTA1_IN),
PINMUX_DATA(PTA0_DATA, PTA0_IN),
/* PTB */
PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
@ -318,38 +285,38 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
/* PTC */
PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_IN_PU),
PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_IN_PU),
PINMUX_DATA(PTC7_DATA, PTC7_IN),
PINMUX_DATA(PTC5_DATA, PTC5_IN),
PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
/* PTD */
PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_IN_PU),
PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN, PTD6_IN_PU),
PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN, PTD5_IN_PU),
PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN, PTD4_IN_PU),
PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN, PTD3_IN_PU),
PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN, PTD2_IN_PU),
PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN, PTD1_IN_PU),
PINMUX_DATA(PTD7_DATA, PTD7_IN),
PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN),
PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN),
PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN),
PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN),
PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN),
PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN),
PINMUX_DATA(PTD0_DATA, PTD0_OUT),
/* PTE */
PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN, PTE7_IN_PD),
PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN, PTE6_IN_PD),
PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN, PTE5_IN_PD),
PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN, PTE4_IN_PD),
PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN, PTE1_IN_PD),
PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN, PTE0_IN_PD),
PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN),
PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN),
PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN),
PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN),
PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN),
PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN),
/* PTF */
PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN, PTF6_IN_PD),
PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN, PTF5_IN_PD),
PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN, PTF4_IN_PD),
PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN, PTF3_IN_PD),
PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN, PTF2_IN_PD),
PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_IN_PD),
PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN),
PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN),
PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN),
PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN),
PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN),
PINMUX_DATA(PTF1_DATA, PTF1_IN),
PINMUX_DATA(PTF0_DATA, PTF0_OUT),
/* PTG */
@ -361,49 +328,49 @@ static const pinmux_enum_t pinmux_data[] = {
/* PTH */
PINMUX_DATA(PTH7_DATA, PTH7_OUT),
PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN, PTH6_IN_PD),
PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN, PTH5_IN_PD),
PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN),
PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN),
PINMUX_DATA(PTH4_DATA, PTH4_OUT),
PINMUX_DATA(PTH3_DATA, PTH3_OUT),
PINMUX_DATA(PTH2_DATA, PTH2_OUT),
PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN, PTH1_IN_PD),
PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN, PTH0_IN_PD),
PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN),
PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN),
/* PTJ */
PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
PINMUX_DATA(PTJ6_DATA, PTJ6_OUT),
PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU),
PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU),
PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN),
PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN),
/* PTK */
PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN, PTK6_IN_PD),
PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN, PTK5_IN_PD),
PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN, PTK4_IN_PD),
PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN, PTK3_IN_PD),
PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_IN_PD),
PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN),
PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN),
PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN),
PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN),
PINMUX_DATA(PTK2_DATA, PTK2_IN),
PINMUX_DATA(PTK1_DATA, PTK1_OUT),
PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN, PTK0_IN_PD),
PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN),
/* PTL */
PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN, PTL7_IN_PD),
PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN, PTL6_IN_PD),
PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN, PTL5_IN_PD),
PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN, PTL4_IN_PD),
PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN, PTL3_IN_PD),
PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN, PTL2_IN_PD),
PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN, PTL1_IN_PD),
PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN, PTL0_IN_PD),
PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN),
PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN),
PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN),
PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN),
PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN),
PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN),
PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN),
PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN),
/* PTM */
PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN, PTM7_IN_PD),
PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN, PTM6_IN_PD),
PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN, PTM5_IN_PD),
PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN, PTM4_IN_PD),
PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN, PTM3_IN_PD),
PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN, PTM2_IN_PD),
PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN, PTM1_IN_PD),
PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN, PTM0_IN_PD),
PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN),
PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN),
PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN),
PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN),
PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN),
PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN),
PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN),
PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN),
/* PTN */
PINMUX_DATA(PTN7_DATA, PTN7_OUT, PTN7_IN),
@ -417,80 +384,80 @@ static const pinmux_enum_t pinmux_data[] = {
/* PTQ */
PINMUX_DATA(PTQ6_DATA, PTQ6_OUT),
PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN, PTQ5_IN_PD),
PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN, PTQ4_IN_PD),
PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN, PTQ3_IN_PD),
PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_IN_PD),
PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN),
PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN),
PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN),
PINMUX_DATA(PTQ2_DATA, PTQ2_IN),
PINMUX_DATA(PTQ1_DATA, PTQ1_OUT),
PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN, PTQ0_IN_PU),
PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN),
/* PTR */
PINMUX_DATA(PTR4_DATA, PTR4_OUT),
PINMUX_DATA(PTR3_DATA, PTR3_OUT),
PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU),
PINMUX_DATA(PTR2_DATA, PTR2_IN),
PINMUX_DATA(PTR1_DATA, PTR1_OUT),
PINMUX_DATA(PTR0_DATA, PTR0_OUT),
/* PTS */
PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_IN_PD),
PINMUX_DATA(PTS4_DATA, PTS4_IN),
PINMUX_DATA(PTS3_DATA, PTS3_OUT),
PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN, PTS2_IN_PD),
PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_IN_PD),
PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN),
PINMUX_DATA(PTS1_DATA, PTS1_IN),
PINMUX_DATA(PTS0_DATA, PTS0_OUT),
/* PTT */
PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN, PTT4_IN_PD),
PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN, PTT3_IN_PD),
PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN, PTT2_IN_PD),
PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_IN_PD),
PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN),
PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN),
PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN),
PINMUX_DATA(PTT1_DATA, PTT1_IN),
PINMUX_DATA(PTT0_DATA, PTT0_OUT),
/* PTU */
PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN, PTU4_IN_PD),
PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN, PTU3_IN_PD),
PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN, PTU2_IN_PD),
PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_IN_PD),
PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN, PTU0_IN_PD),
PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN),
PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN),
PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN),
PINMUX_DATA(PTU1_DATA, PTU1_IN),
PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN),
/* PTV */
PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN, PTV4_IN_PD),
PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN, PTV3_IN_PD),
PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN, PTV2_IN_PD),
PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN, PTV1_IN_PD),
PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN, PTV0_IN_PD),
PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN),
PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN),
PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN),
PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN),
PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN),
/* PTW */
PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_IN_PD),
PINMUX_DATA(PTW6_DATA, PTW6_IN),
PINMUX_DATA(PTW5_DATA, PTW5_OUT),
PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN, PTW4_IN_PD),
PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN, PTW3_IN_PD),
PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN, PTW2_IN_PD),
PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN, PTW1_IN_PD),
PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN, PTW0_IN_PD),
PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN),
PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN),
PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN),
PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN),
PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN),
/* PTX */
PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN, PTX6_IN_PD),
PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN, PTX5_IN_PD),
PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN, PTX4_IN_PD),
PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN, PTX3_IN_PD),
PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN, PTX2_IN_PD),
PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN, PTX1_IN_PD),
PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN, PTX0_IN_PD),
PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN),
PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN),
PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN),
PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN),
PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN),
PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN),
PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN),
/* PTY */
PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN, PTY5_IN_PU),
PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN, PTY4_IN_PU),
PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN, PTY3_IN_PU),
PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN, PTY2_IN_PU),
PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN),
PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN),
PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN),
PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN),
PINMUX_DATA(PTY1_DATA, PTY1_OUT),
PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN, PTY0_IN_PU),
PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN),
/* PTZ */
PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_IN_PU),
PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_IN_PU),
PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_IN_PU),
PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_IN_PU),
PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_IN_PU),
PINMUX_DATA(PTZ5_DATA, PTZ5_IN),
PINMUX_DATA(PTZ4_DATA, PTZ4_IN),
PINMUX_DATA(PTZ3_DATA, PTZ3_IN),
PINMUX_DATA(PTZ2_DATA, PTZ2_IN),
PINMUX_DATA(PTZ1_DATA, PTZ1_IN),
/* SCIF0 */
PINMUX_DATA(SCIF0_TXD_MARK, SCIF0_TXD),
@ -789,199 +756,199 @@ static const pinmux_enum_t pinmux_data[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
PINMUX_GPIO(PTA7),
PINMUX_GPIO(PTA6),
PINMUX_GPIO(PTA5),
PINMUX_GPIO(PTA4),
PINMUX_GPIO(PTA3),
PINMUX_GPIO(PTA2),
PINMUX_GPIO(PTA1),
PINMUX_GPIO(PTA0),
/* PTB */
PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
PINMUX_GPIO(PTB7),
PINMUX_GPIO(PTB6),
PINMUX_GPIO(PTB5),
PINMUX_GPIO(PTB4),
PINMUX_GPIO(PTB3),
PINMUX_GPIO(PTB2),
PINMUX_GPIO(PTB1),
PINMUX_GPIO(PTB0),
/* PTC */
PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
PINMUX_GPIO(PTC7),
PINMUX_GPIO(PTC5),
PINMUX_GPIO(PTC4),
PINMUX_GPIO(PTC3),
PINMUX_GPIO(PTC2),
PINMUX_GPIO(PTC0),
/* PTD */
PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
PINMUX_GPIO(PTD7),
PINMUX_GPIO(PTD6),
PINMUX_GPIO(PTD5),
PINMUX_GPIO(PTD4),
PINMUX_GPIO(PTD3),
PINMUX_GPIO(PTD2),
PINMUX_GPIO(PTD1),
PINMUX_GPIO(PTD0),
/* PTE */
PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
PINMUX_GPIO(PTE7),
PINMUX_GPIO(PTE6),
PINMUX_GPIO(PTE5),
PINMUX_GPIO(PTE4),
PINMUX_GPIO(PTE1),
PINMUX_GPIO(PTE0),
/* PTF */
PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
PINMUX_GPIO(PTF6),
PINMUX_GPIO(PTF5),
PINMUX_GPIO(PTF4),
PINMUX_GPIO(PTF3),
PINMUX_GPIO(PTF2),
PINMUX_GPIO(PTF1),
PINMUX_GPIO(PTF0),
/* PTG */
PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
PINMUX_GPIO(PTG4),
PINMUX_GPIO(PTG3),
PINMUX_GPIO(PTG2),
PINMUX_GPIO(PTG1),
PINMUX_GPIO(PTG0),
/* PTH */
PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
PINMUX_GPIO(PTH7),
PINMUX_GPIO(PTH6),
PINMUX_GPIO(PTH5),
PINMUX_GPIO(PTH4),
PINMUX_GPIO(PTH3),
PINMUX_GPIO(PTH2),
PINMUX_GPIO(PTH1),
PINMUX_GPIO(PTH0),
/* PTJ */
PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
PINMUX_GPIO(PTJ7),
PINMUX_GPIO(PTJ6),
PINMUX_GPIO(PTJ5),
PINMUX_GPIO(PTJ1),
PINMUX_GPIO(PTJ0),
/* PTK */
PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
PINMUX_GPIO(PTK6),
PINMUX_GPIO(PTK5),
PINMUX_GPIO(PTK4),
PINMUX_GPIO(PTK3),
PINMUX_GPIO(PTK2),
PINMUX_GPIO(PTK1),
PINMUX_GPIO(PTK0),
/* PTL */
PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
PINMUX_GPIO(PTL7),
PINMUX_GPIO(PTL6),
PINMUX_GPIO(PTL5),
PINMUX_GPIO(PTL4),
PINMUX_GPIO(PTL3),
PINMUX_GPIO(PTL2),
PINMUX_GPIO(PTL1),
PINMUX_GPIO(PTL0),
/* PTM */
PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
PINMUX_GPIO(PTM7),
PINMUX_GPIO(PTM6),
PINMUX_GPIO(PTM5),
PINMUX_GPIO(PTM4),
PINMUX_GPIO(PTM3),
PINMUX_GPIO(PTM2),
PINMUX_GPIO(PTM1),
PINMUX_GPIO(PTM0),
/* PTN */
PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
PINMUX_GPIO(PTN7),
PINMUX_GPIO(PTN6),
PINMUX_GPIO(PTN5),
PINMUX_GPIO(PTN4),
PINMUX_GPIO(PTN3),
PINMUX_GPIO(PTN2),
PINMUX_GPIO(PTN1),
PINMUX_GPIO(PTN0),
/* PTQ */
PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
PINMUX_GPIO(PTQ6),
PINMUX_GPIO(PTQ5),
PINMUX_GPIO(PTQ4),
PINMUX_GPIO(PTQ3),
PINMUX_GPIO(PTQ2),
PINMUX_GPIO(PTQ1),
PINMUX_GPIO(PTQ0),
/* PTR */
PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
PINMUX_GPIO(PTR4),
PINMUX_GPIO(PTR3),
PINMUX_GPIO(PTR2),
PINMUX_GPIO(PTR1),
PINMUX_GPIO(PTR0),
/* PTS */
PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
PINMUX_GPIO(PTS4),
PINMUX_GPIO(PTS3),
PINMUX_GPIO(PTS2),
PINMUX_GPIO(PTS1),
PINMUX_GPIO(PTS0),
/* PTT */
PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
PINMUX_GPIO(PTT4),
PINMUX_GPIO(PTT3),
PINMUX_GPIO(PTT2),
PINMUX_GPIO(PTT1),
PINMUX_GPIO(PTT0),
/* PTU */
PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
PINMUX_GPIO(PTU4),
PINMUX_GPIO(PTU3),
PINMUX_GPIO(PTU2),
PINMUX_GPIO(PTU1),
PINMUX_GPIO(PTU0),
/* PTV */
PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
PINMUX_GPIO(PTV4),
PINMUX_GPIO(PTV3),
PINMUX_GPIO(PTV2),
PINMUX_GPIO(PTV1),
PINMUX_GPIO(PTV0),
/* PTW */
PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
PINMUX_GPIO(PTW6),
PINMUX_GPIO(PTW5),
PINMUX_GPIO(PTW4),
PINMUX_GPIO(PTW3),
PINMUX_GPIO(PTW2),
PINMUX_GPIO(PTW1),
PINMUX_GPIO(PTW0),
/* PTX */
PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
PINMUX_GPIO(PTX6),
PINMUX_GPIO(PTX5),
PINMUX_GPIO(PTX4),
PINMUX_GPIO(PTX3),
PINMUX_GPIO(PTX2),
PINMUX_GPIO(PTX1),
PINMUX_GPIO(PTX0),
/* PTY */
PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
PINMUX_GPIO(PTY5),
PINMUX_GPIO(PTY4),
PINMUX_GPIO(PTY3),
PINMUX_GPIO(PTY2),
PINMUX_GPIO(PTY1),
PINMUX_GPIO(PTY0),
/* PTZ */
PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
PINMUX_GPIO(PTZ5),
PINMUX_GPIO(PTZ4),
PINMUX_GPIO(PTZ3),
PINMUX_GPIO(PTZ2),
PINMUX_GPIO(PTZ1),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
@ -1270,14 +1237,14 @@ static const struct pinmux_func pinmux_func_gpios[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN,
VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN,
VIO_D5_SCIF1_TXD, PTA5_OUT, PTA5_IN_PD, PTA5_IN,
VIO_D4, 0, PTA4_IN_PD, PTA4_IN,
VIO_D3, 0, PTA3_IN_PD, PTA3_IN,
VIO_D2, 0, PTA2_IN_PD, PTA2_IN,
VIO_D1, 0, PTA1_IN_PD, PTA1_IN,
VIO_D0_LCDLCLK, 0, PTA0_IN_PD, PTA0_IN }
VIO_D7_SCIF1_SCK, PTA7_OUT, 0, PTA7_IN,
VIO_D6_SCIF1_RXD, 0, 0, PTA6_IN,
VIO_D5_SCIF1_TXD, PTA5_OUT, 0, PTA5_IN,
VIO_D4, 0, 0, PTA4_IN,
VIO_D3, 0, 0, PTA3_IN,
VIO_D2, 0, 0, PTA2_IN,
VIO_D1, 0, 0, PTA1_IN,
VIO_D0_LCDLCLK, 0, 0, PTA0_IN }
},
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
HPD55, PTB7_OUT, 0, PTB7_IN,
@ -1290,9 +1257,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
HPD48, PTB0_OUT, 0, PTB0_IN }
},
{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
0, 0, PTC7_IN_PU, PTC7_IN,
0, 0, 0, PTC7_IN,
0, 0, 0, 0,
IOIS16, 0, PTC5_IN_PU, PTC5_IN,
IOIS16, 0, 0, PTC5_IN,
HPDQM7, PTC4_OUT, 0, PTC4_IN,
HPDQM6, PTC3_OUT, 0, PTC3_IN,
HPDQM5, PTC2_OUT, 0, PTC2_IN,
@ -1300,33 +1267,33 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
HPDQM4, PTC0_OUT, 0, PTC0_IN }
},
{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
SDHICD, 0, PTD7_IN_PU, PTD7_IN,
SDHIWP, PTD6_OUT, PTD6_IN_PU, PTD6_IN,
SDHID3, PTD5_OUT, PTD5_IN_PU, PTD5_IN,
IRQ2_SDHID2, PTD4_OUT, PTD4_IN_PU, PTD4_IN,
SDHID1, PTD3_OUT, PTD3_IN_PU, PTD3_IN,
SDHID0, PTD2_OUT, PTD2_IN_PU, PTD2_IN,
SDHICMD, PTD1_OUT, PTD1_IN_PU, PTD1_IN,
SDHICD, 0, 0, PTD7_IN,
SDHIWP, PTD6_OUT, 0, PTD6_IN,
SDHID3, PTD5_OUT, 0, PTD5_IN,
IRQ2_SDHID2, PTD4_OUT, 0, PTD4_IN,
SDHID1, PTD3_OUT, 0, PTD3_IN,
SDHID0, PTD2_OUT, 0, PTD2_IN,
SDHICMD, PTD1_OUT, 0, PTD1_IN,
SDHICLK, PTD0_OUT, 0, 0 }
},
{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
A25, PTE7_OUT, PTE7_IN_PD, PTE7_IN,
A24, PTE6_OUT, PTE6_IN_PD, PTE6_IN,
A23, PTE5_OUT, PTE5_IN_PD, PTE5_IN,
A22, PTE4_OUT, PTE4_IN_PD, PTE4_IN,
A25, PTE7_OUT, 0, PTE7_IN,
A24, PTE6_OUT, 0, PTE6_IN,
A23, PTE5_OUT, 0, PTE5_IN,
A22, PTE4_OUT, 0, PTE4_IN,
0, 0, 0, 0,
0, 0, 0, 0,
IRQ5, PTE1_OUT, PTE1_IN_PD, PTE1_IN,
IRQ4_BS, PTE0_OUT, PTE0_IN_PD, PTE0_IN }
IRQ5, PTE1_OUT, 0, PTE1_IN,
IRQ4_BS, PTE0_OUT, 0, PTE0_IN }
},
{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
0, 0, 0, 0,
PTF6, PTF6_OUT, PTF6_IN_PD, PTF6_IN,
SIOSCK_SIUBOBT, PTF5_OUT, PTF5_IN_PD, PTF5_IN,
SIOSTRB1_SIUBOLR, PTF4_OUT, PTF4_IN_PD, PTF4_IN,
SIOSTRB0_SIUBIBT, PTF3_OUT, PTF3_IN_PD, PTF3_IN,
SIOD_SIUBILR, PTF2_OUT, PTF2_IN_PD, PTF2_IN,
SIORXD_SIUBISLD, 0, PTF1_IN_PD, PTF1_IN,
PTF6, PTF6_OUT, 0, PTF6_IN,
SIOSCK_SIUBOBT, PTF5_OUT, 0, PTF5_IN,
SIOSTRB1_SIUBOLR, PTF4_OUT, 0, PTF4_IN,
SIOSTRB0_SIUBIBT, PTF3_OUT, 0, PTF3_IN,
SIOD_SIUBILR, PTF2_OUT, 0, PTF2_IN,
SIORXD_SIUBISLD, 0, 0, PTF1_IN,
SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 }
},
{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
@ -1341,13 +1308,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0,
LCDVSYN2_DACK, PTH6_OUT, PTH6_IN_PD, PTH6_IN,
LCDVSYN, PTH5_OUT, PTH5_IN_PD, PTH5_IN,
LCDVSYN2_DACK, PTH6_OUT, 0, PTH6_IN,
LCDVSYN, PTH5_OUT, 0, PTH5_IN,
LCDDISP_LCDRS, PTH4_OUT, 0, 0,
LCDHSYN_LCDCS, PTH3_OUT, 0, 0,
LCDDON_LCDDON2, PTH2_OUT, 0, 0,
LCDD17_DV_HSYNC, PTH1_OUT, PTH1_IN_PD, PTH1_IN,
LCDD16_DV_VSYNC, PTH0_OUT, PTH0_IN_PD, PTH0_IN }
LCDD17_DV_HSYNC, PTH1_OUT, 0, PTH1_IN,
LCDD16_DV_VSYNC, PTH0_OUT, 0, PTH0_IN }
},
{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
STATUS0, PTJ7_OUT, 0, 0,
@ -1356,38 +1323,38 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
IRQ1, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN,
IRQ0, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN }
IRQ1, PTJ1_OUT, 0, PTJ1_IN,
IRQ0, PTJ0_OUT, 0, PTJ0_IN }
},
{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
0, 0, 0, 0,
SIUAILR_SIOF1_SS2, PTK6_OUT, PTK6_IN_PD, PTK6_IN,
SIUAIBT_SIOF1_SS1, PTK5_OUT, PTK5_IN_PD, PTK5_IN,
SIUAOLR_SIOF1_SYNC, PTK4_OUT, PTK4_IN_PD, PTK4_IN,
SIUAOBT_SIOF1_SCK, PTK3_OUT, PTK3_IN_PD, PTK3_IN,
SIUAISLD_SIOF1_RXD, 0, PTK2_IN_PD, PTK2_IN,
SIUAILR_SIOF1_SS2, PTK6_OUT, 0, PTK6_IN,
SIUAIBT_SIOF1_SS1, PTK5_OUT, 0, PTK5_IN,
SIUAOLR_SIOF1_SYNC, PTK4_OUT, 0, PTK4_IN,
SIUAOBT_SIOF1_SCK, PTK3_OUT, 0, PTK3_IN,
SIUAISLD_SIOF1_RXD, 0, 0, PTK2_IN,
SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0,
PTK0, PTK0_OUT, PTK0_IN_PD, PTK0_IN }
PTK0, PTK0_OUT, 0, PTK0_IN }
},
{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
LCDD15_DV_D15, PTL7_OUT, PTL7_IN_PD, PTL7_IN,
LCDD14_DV_D14, PTL6_OUT, PTL6_IN_PD, PTL6_IN,
LCDD13_DV_D13, PTL5_OUT, PTL5_IN_PD, PTL5_IN,
LCDD12_DV_D12, PTL4_OUT, PTL4_IN_PD, PTL4_IN,
LCDD11_DV_D11, PTL3_OUT, PTL3_IN_PD, PTL3_IN,
LCDD10_DV_D10, PTL2_OUT, PTL2_IN_PD, PTL2_IN,
LCDD9_DV_D9, PTL1_OUT, PTL1_IN_PD, PTL1_IN,
LCDD8_DV_D8, PTL0_OUT, PTL0_IN_PD, PTL0_IN }
LCDD15_DV_D15, PTL7_OUT, 0, PTL7_IN,
LCDD14_DV_D14, PTL6_OUT, 0, PTL6_IN,
LCDD13_DV_D13, PTL5_OUT, 0, PTL5_IN,
LCDD12_DV_D12, PTL4_OUT, 0, PTL4_IN,
LCDD11_DV_D11, PTL3_OUT, 0, PTL3_IN,
LCDD10_DV_D10, PTL2_OUT, 0, PTL2_IN,
LCDD9_DV_D9, PTL1_OUT, 0, PTL1_IN,
LCDD8_DV_D8, PTL0_OUT, 0, PTL0_IN }
},
{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
LCDD7_DV_D7, PTM7_OUT, PTM7_IN_PD, PTM7_IN,
LCDD6_DV_D6, PTM6_OUT, PTM6_IN_PD, PTM6_IN,
LCDD5_DV_D5, PTM5_OUT, PTM5_IN_PD, PTM5_IN,
LCDD4_DV_D4, PTM4_OUT, PTM4_IN_PD, PTM4_IN,
LCDD3_DV_D3, PTM3_OUT, PTM3_IN_PD, PTM3_IN,
LCDD2_DV_D2, PTM2_OUT, PTM2_IN_PD, PTM2_IN,
LCDD1_DV_D1, PTM1_OUT, PTM1_IN_PD, PTM1_IN,
LCDD0_DV_D0, PTM0_OUT, PTM0_IN_PD, PTM0_IN }
LCDD7_DV_D7, PTM7_OUT, 0, PTM7_IN,
LCDD6_DV_D6, PTM6_OUT, 0, PTM6_IN,
LCDD5_DV_D5, PTM5_OUT, 0, PTM5_IN,
LCDD4_DV_D4, PTM4_OUT, 0, PTM4_IN,
LCDD3_DV_D3, PTM3_OUT, 0, PTM3_IN,
LCDD2_DV_D2, PTM2_OUT, 0, PTM2_IN,
LCDD1_DV_D1, PTM1_OUT, 0, PTM1_IN,
LCDD0_DV_D0, PTM0_OUT, 0, PTM0_IN }
},
{ PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
HPD63, PTN7_OUT, 0, PTN7_IN,
@ -1402,12 +1369,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
0, 0, 0, 0,
SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0,
SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, PTQ5_IN_PD, PTQ5_IN,
SIOF0_SYNC_TS_SDEN, PTQ4_OUT, PTQ4_IN_PD, PTQ4_IN,
SIOF0_SCK_TS_SCK, PTQ3_OUT, PTQ3_IN_PD, PTQ3_IN,
PTQ2, 0, PTQ2_IN_PD, PTQ2_IN,
SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, 0, PTQ5_IN,
SIOF0_SYNC_TS_SDEN, PTQ4_OUT, 0, PTQ4_IN,
SIOF0_SCK_TS_SCK, PTQ3_OUT, 0, PTQ3_IN,
PTQ2, 0, 0, PTQ2_IN,
PTQ1, PTQ1_OUT, 0, 0,
PTQ0, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN }
PTQ0, PTQ0_OUT, 0, PTQ0_IN }
},
{ PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
0, 0, 0, 0,
@ -1415,7 +1382,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
LCDRD, PTR4_OUT, 0, 0,
CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0,
WAIT, 0, PTR2_IN_PU, PTR2_IN,
WAIT, 0, 0, PTR2_IN,
LCDDCK_LCDWR, PTR1_OUT, 0, 0,
LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 }
},
@ -1423,80 +1390,80 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
SCIF0_CTS_SIUAISPD, 0, PTS4_IN_PD, PTS4_IN,
SCIF0_CTS_SIUAISPD, 0, 0, PTS4_IN,
SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0,
SCIF0_SCK_TPUTO, PTS2_OUT, PTS2_IN_PD, PTS2_IN,
SCIF0_RXD, 0, PTS1_IN_PD, PTS1_IN,
SCIF0_SCK_TPUTO, PTS2_OUT, 0, PTS2_IN,
SCIF0_RXD, 0, 0, PTS1_IN,
SCIF0_TXD, PTS0_OUT, 0, 0 }
},
{ PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
FOE_VIO_VD2, PTT4_OUT, PTT4_IN_PD, PTT4_IN,
FWE, PTT3_OUT, PTT3_IN_PD, PTT3_IN,
FSC, PTT2_OUT, PTT2_IN_PD, PTT2_IN,
DREQ0, 0, PTT1_IN_PD, PTT1_IN,
FOE_VIO_VD2, PTT4_OUT, 0, PTT4_IN,
FWE, PTT3_OUT, 0, PTT3_IN,
FSC, PTT2_OUT, 0, PTT2_IN,
DREQ0, 0, 0, PTT1_IN,
FCDE, PTT0_OUT, 0, 0 }
},
{ PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
NAF2_VIO_D10, PTU4_OUT, PTU4_IN_PD, PTU4_IN,
NAF1_VIO_D9, PTU3_OUT, PTU3_IN_PD, PTU3_IN,
NAF0_VIO_D8, PTU2_OUT, PTU2_IN_PD, PTU2_IN,
FRB_VIO_CLK2, 0, PTU1_IN_PD, PTU1_IN,
FCE_VIO_HD2, PTU0_OUT, PTU0_IN_PD, PTU0_IN }
NAF2_VIO_D10, PTU4_OUT, 0, PTU4_IN,
NAF1_VIO_D9, PTU3_OUT, 0, PTU3_IN,
NAF0_VIO_D8, PTU2_OUT, 0, PTU2_IN,
FRB_VIO_CLK2, 0, 0, PTU1_IN,
FCE_VIO_HD2, PTU0_OUT, 0, PTU0_IN }
},
{ PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
NAF7_VIO_D15, PTV4_OUT, PTV4_IN_PD, PTV4_IN,
NAF6_VIO_D14, PTV3_OUT, PTV3_IN_PD, PTV3_IN,
NAF5_VIO_D13, PTV2_OUT, PTV2_IN_PD, PTV2_IN,
NAF4_VIO_D12, PTV1_OUT, PTV1_IN_PD, PTV1_IN,
NAF3_VIO_D11, PTV0_OUT, PTV0_IN_PD, PTV0_IN }
NAF7_VIO_D15, PTV4_OUT, 0, PTV4_IN,
NAF6_VIO_D14, PTV3_OUT, 0, PTV3_IN,
NAF5_VIO_D13, PTV2_OUT, 0, PTV2_IN,
NAF4_VIO_D12, PTV1_OUT, 0, PTV1_IN,
NAF3_VIO_D11, PTV0_OUT, 0, PTV0_IN }
},
{ PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
0, 0, 0, 0,
VIO_FLD_SCIF2_CTS, 0, PTW6_IN_PD, PTW6_IN,
VIO_FLD_SCIF2_CTS, 0, 0, PTW6_IN,
VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0,
VIO_STEX_SCIF2_SCK, PTW4_OUT, PTW4_IN_PD, PTW4_IN,
VIO_STEM_SCIF2_TXD, PTW3_OUT, PTW3_IN_PD, PTW3_IN,
VIO_HD_SCIF2_RXD, PTW2_OUT, PTW2_IN_PD, PTW2_IN,
VIO_VD_SCIF1_CTS, PTW1_OUT, PTW1_IN_PD, PTW1_IN,
VIO_CLK_SCIF1_RTS, PTW0_OUT, PTW0_IN_PD, PTW0_IN }
VIO_STEX_SCIF2_SCK, PTW4_OUT, 0, PTW4_IN,
VIO_STEM_SCIF2_TXD, PTW3_OUT, 0, PTW3_IN,
VIO_HD_SCIF2_RXD, PTW2_OUT, 0, PTW2_IN,
VIO_VD_SCIF1_CTS, PTW1_OUT, 0, PTW1_IN,
VIO_CLK_SCIF1_RTS, PTW0_OUT, 0, PTW0_IN }
},
{ PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
0, 0, 0, 0,
CS6A_CE2B, PTX6_OUT, PTX6_IN_PU, PTX6_IN,
LCDD23, PTX5_OUT, PTX5_IN_PD, PTX5_IN,
LCDD22, PTX4_OUT, PTX4_IN_PD, PTX4_IN,
LCDD21, PTX3_OUT, PTX3_IN_PD, PTX3_IN,
LCDD20, PTX2_OUT, PTX2_IN_PD, PTX2_IN,
LCDD19_DV_CLKI, PTX1_OUT, PTX1_IN_PD, PTX1_IN,
LCDD18_DV_CLK, PTX0_OUT, PTX0_IN_PD, PTX0_IN }
CS6A_CE2B, PTX6_OUT, 0, PTX6_IN,
LCDD23, PTX5_OUT, 0, PTX5_IN,
LCDD22, PTX4_OUT, 0, PTX4_IN,
LCDD21, PTX3_OUT, 0, PTX3_IN,
LCDD20, PTX2_OUT, 0, PTX2_IN,
LCDD19_DV_CLKI, PTX1_OUT, 0, PTX1_IN,
LCDD18_DV_CLK, PTX0_OUT, 0, PTX0_IN }
},
{ PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
KEYOUT5_IN5, PTY5_OUT, PTY5_IN_PU, PTY5_IN,
KEYOUT4_IN6, PTY4_OUT, PTY4_IN_PU, PTY4_IN,
KEYOUT3, PTY3_OUT, PTY3_IN_PU, PTY3_IN,
KEYOUT2, PTY2_OUT, PTY2_IN_PU, PTY2_IN,
KEYOUT5_IN5, PTY5_OUT, 0, PTY5_IN,
KEYOUT4_IN6, PTY4_OUT, 0, PTY4_IN,
KEYOUT3, PTY3_OUT, 0, PTY3_IN,
KEYOUT2, PTY2_OUT, 0, PTY2_IN,
KEYOUT1, PTY1_OUT, 0, 0,
KEYOUT0, PTY0_OUT, PTY0_IN_PU, PTY0_IN }
KEYOUT0, PTY0_OUT, 0, PTY0_IN }
},
{ PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
KEYIN4_IRQ7, 0, PTZ5_IN_PU, PTZ5_IN,
KEYIN3, 0, PTZ4_IN_PU, PTZ4_IN,
KEYIN2, 0, PTZ3_IN_PU, PTZ3_IN,
KEYIN1, 0, PTZ2_IN_PU, PTZ2_IN,
KEYIN0_IRQ6, 0, PTZ1_IN_PU, PTZ1_IN,
KEYIN4_IRQ7, 0, 0, PTZ5_IN,
KEYIN3, 0, 0, PTZ4_IN,
KEYIN2, 0, 0, PTZ3_IN,
KEYIN1, 0, 0, PTZ2_IN,
KEYIN0_IRQ6, 0, 0, PTZ1_IN,
0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) {
@ -1763,8 +1730,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
const struct sh_pfc_soc_info sh7722_pinmux_info = {
.name = "sh7722_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

381
drivers/pinctrl/sh-pfc/pfc-sh7723.c
View File

@ -102,12 +102,6 @@ enum {
PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PTA4_IN_PU, PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
PTB2_IN_PU, PTB1_IN_PU,
PTR2_IN_PU,
PINMUX_INPUT_PULLUP_END,
PINMUX_OUTPUT_BEGIN,
PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
@ -350,16 +344,16 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* PTA GPIO */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU),
PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU),
PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU),
PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU),
PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU),
PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT),
PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT),
PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT),
PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT),
PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT),
/* PTB GPIO */
PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
@ -367,8 +361,8 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU),
PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU),
PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
/* PTC GPIO */
@ -487,7 +481,7 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
PINMUX_DATA(PTR3_DATA, PTR3_IN),
PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU),
PINMUX_DATA(PTR2_DATA, PTR2_IN),
PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
@ -925,220 +919,220 @@ static const pinmux_enum_t pinmux_data[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
PINMUX_GPIO(PTA7),
PINMUX_GPIO(PTA6),
PINMUX_GPIO(PTA5),
PINMUX_GPIO(PTA4),
PINMUX_GPIO(PTA3),
PINMUX_GPIO(PTA2),
PINMUX_GPIO(PTA1),
PINMUX_GPIO(PTA0),
/* PTB */
PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
PINMUX_GPIO(PTB7),
PINMUX_GPIO(PTB6),
PINMUX_GPIO(PTB5),
PINMUX_GPIO(PTB4),
PINMUX_GPIO(PTB3),
PINMUX_GPIO(PTB2),
PINMUX_GPIO(PTB1),
PINMUX_GPIO(PTB0),
/* PTC */
PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
PINMUX_GPIO(PTC7),
PINMUX_GPIO(PTC6),
PINMUX_GPIO(PTC5),
PINMUX_GPIO(PTC4),
PINMUX_GPIO(PTC3),
PINMUX_GPIO(PTC2),
PINMUX_GPIO(PTC1),
PINMUX_GPIO(PTC0),
/* PTD */
PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
PINMUX_GPIO(PTD7),
PINMUX_GPIO(PTD6),
PINMUX_GPIO(PTD5),
PINMUX_GPIO(PTD4),
PINMUX_GPIO(PTD3),
PINMUX_GPIO(PTD2),
PINMUX_GPIO(PTD1),
PINMUX_GPIO(PTD0),
/* PTE */
PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
PINMUX_GPIO(PTE5),
PINMUX_GPIO(PTE4),
PINMUX_GPIO(PTE3),
PINMUX_GPIO(PTE2),
PINMUX_GPIO(PTE1),
PINMUX_GPIO(PTE0),
/* PTF */
PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
PINMUX_GPIO(PTF7),
PINMUX_GPIO(PTF6),
PINMUX_GPIO(PTF5),
PINMUX_GPIO(PTF4),
PINMUX_GPIO(PTF3),
PINMUX_GPIO(PTF2),
PINMUX_GPIO(PTF1),
PINMUX_GPIO(PTF0),
/* PTG */
PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
PINMUX_GPIO(PTG5),
PINMUX_GPIO(PTG4),
PINMUX_GPIO(PTG3),
PINMUX_GPIO(PTG2),
PINMUX_GPIO(PTG1),
PINMUX_GPIO(PTG0),
/* PTH */
PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
PINMUX_GPIO(PTH7),
PINMUX_GPIO(PTH6),
PINMUX_GPIO(PTH5),
PINMUX_GPIO(PTH4),
PINMUX_GPIO(PTH3),
PINMUX_GPIO(PTH2),
PINMUX_GPIO(PTH1),
PINMUX_GPIO(PTH0),
/* PTJ */
PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
PINMUX_GPIO(PTJ7),
PINMUX_GPIO(PTJ5),
PINMUX_GPIO(PTJ3),
PINMUX_GPIO(PTJ2),
PINMUX_GPIO(PTJ1),
PINMUX_GPIO(PTJ0),
/* PTK */
PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
PINMUX_GPIO(PTK7),
PINMUX_GPIO(PTK6),
PINMUX_GPIO(PTK5),
PINMUX_GPIO(PTK4),
PINMUX_GPIO(PTK3),
PINMUX_GPIO(PTK2),
PINMUX_GPIO(PTK1),
PINMUX_GPIO(PTK0),
/* PTL */
PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
PINMUX_GPIO(PTL7),
PINMUX_GPIO(PTL6),
PINMUX_GPIO(PTL5),
PINMUX_GPIO(PTL4),
PINMUX_GPIO(PTL3),
PINMUX_GPIO(PTL2),
PINMUX_GPIO(PTL1),
PINMUX_GPIO(PTL0),
/* PTM */
PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
PINMUX_GPIO(PTM7),
PINMUX_GPIO(PTM6),
PINMUX_GPIO(PTM5),
PINMUX_GPIO(PTM4),
PINMUX_GPIO(PTM3),
PINMUX_GPIO(PTM2),
PINMUX_GPIO(PTM1),
PINMUX_GPIO(PTM0),
/* PTN */
PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
PINMUX_GPIO(PTN7),
PINMUX_GPIO(PTN6),
PINMUX_GPIO(PTN5),
PINMUX_GPIO(PTN4),
PINMUX_GPIO(PTN3),
PINMUX_GPIO(PTN2),
PINMUX_GPIO(PTN1),
PINMUX_GPIO(PTN0),
/* PTQ */
PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
PINMUX_GPIO(PTQ3),
PINMUX_GPIO(PTQ2),
PINMUX_GPIO(PTQ1),
PINMUX_GPIO(PTQ0),
/* PTR */
PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
PINMUX_GPIO(PTR7),
PINMUX_GPIO(PTR6),
PINMUX_GPIO(PTR5),
PINMUX_GPIO(PTR4),
PINMUX_GPIO(PTR3),
PINMUX_GPIO(PTR2),
PINMUX_GPIO(PTR1),
PINMUX_GPIO(PTR0),
/* PTS */
PINMUX_GPIO(GPIO_PTS7, PTS7_DATA),
PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
PINMUX_GPIO(PTS7),
PINMUX_GPIO(PTS6),
PINMUX_GPIO(PTS5),
PINMUX_GPIO(PTS4),
PINMUX_GPIO(PTS3),
PINMUX_GPIO(PTS2),
PINMUX_GPIO(PTS1),
PINMUX_GPIO(PTS0),
/* PTT */
PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
PINMUX_GPIO(PTT5),
PINMUX_GPIO(PTT4),
PINMUX_GPIO(PTT3),
PINMUX_GPIO(PTT2),
PINMUX_GPIO(PTT1),
PINMUX_GPIO(PTT0),
/* PTU */
PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
PINMUX_GPIO(PTU5),
PINMUX_GPIO(PTU4),
PINMUX_GPIO(PTU3),
PINMUX_GPIO(PTU2),
PINMUX_GPIO(PTU1),
PINMUX_GPIO(PTU0),
/* PTV */
PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
PINMUX_GPIO(PTV7),
PINMUX_GPIO(PTV6),
PINMUX_GPIO(PTV5),
PINMUX_GPIO(PTV4),
PINMUX_GPIO(PTV3),
PINMUX_GPIO(PTV2),
PINMUX_GPIO(PTV1),
PINMUX_GPIO(PTV0),
/* PTW */
PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
PINMUX_GPIO(PTW7),
PINMUX_GPIO(PTW6),
PINMUX_GPIO(PTW5),
PINMUX_GPIO(PTW4),
PINMUX_GPIO(PTW3),
PINMUX_GPIO(PTW2),
PINMUX_GPIO(PTW1),
PINMUX_GPIO(PTW0),
/* PTX */
PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
PINMUX_GPIO(PTX7),
PINMUX_GPIO(PTX6),
PINMUX_GPIO(PTX5),
PINMUX_GPIO(PTX4),
PINMUX_GPIO(PTX3),
PINMUX_GPIO(PTX2),
PINMUX_GPIO(PTX1),
PINMUX_GPIO(PTX0),
/* PTY */
PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
PINMUX_GPIO(PTY7),
PINMUX_GPIO(PTY6),
PINMUX_GPIO(PTY5),
PINMUX_GPIO(PTY4),
PINMUX_GPIO(PTY3),
PINMUX_GPIO(PTY2),
PINMUX_GPIO(PTY1),
PINMUX_GPIO(PTY0),
/* PTZ */
PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
PINMUX_GPIO(PTZ7),
PINMUX_GPIO(PTZ6),
PINMUX_GPIO(PTZ5),
PINMUX_GPIO(PTZ4),
PINMUX_GPIO(PTZ3),
PINMUX_GPIO(PTZ2),
PINMUX_GPIO(PTZ1),
PINMUX_GPIO(PTZ0),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
@ -1520,11 +1514,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTA7_FN, PTA7_OUT, 0, PTA7_IN,
PTA6_FN, PTA6_OUT, 0, PTA6_IN,
PTA5_FN, PTA5_OUT, 0, PTA5_IN,
PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN,
PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN,
PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN,
PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN,
PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN }
PTA4_FN, PTA4_OUT, 0, PTA4_IN,
PTA3_FN, PTA3_OUT, 0, PTA3_IN,
PTA2_FN, PTA2_OUT, 0, PTA2_IN,
PTA1_FN, PTA1_OUT, 0, PTA1_IN,
PTA0_FN, PTA0_OUT, 0, PTA0_IN }
},
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
PTB7_FN, PTB7_OUT, 0, PTB7_IN,
@ -1532,8 +1526,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTB5_FN, PTB5_OUT, 0, PTB5_IN,
PTB4_FN, PTB4_OUT, 0, PTB4_IN,
PTB3_FN, PTB3_OUT, 0, PTB3_IN,
PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN,
PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN,
PTB2_FN, PTB2_OUT, 0, PTB2_IN,
PTB1_FN, PTB1_OUT, 0, PTB1_IN,
PTB0_FN, PTB0_OUT, 0, PTB0_IN }
},
{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
@ -1662,7 +1656,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTR5_FN, PTR5_OUT, 0, PTR5_IN,
PTR4_FN, PTR4_OUT, 0, PTR4_IN,
PTR3_FN, 0, 0, PTR3_IN,
PTR2_FN, 0, PTR2_IN_PU, PTR2_IN,
PTR2_FN, 0, 0, PTR2_IN,
PTR1_FN, PTR1_OUT, 0, PTR1_IN,
PTR0_FN, PTR0_OUT, 0, PTR0_IN }
},
@ -1888,7 +1882,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
const struct sh_pfc_soc_info sh7723_pinmux_info = {
.name = "sh7723_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

1093
drivers/pinctrl/sh-pfc/pfc-sh7724.c
View File

File diff suppressed because it is too large Load Diff

54
drivers/pinctrl/sh-pfc/pfc-sh7734.c
View File

@ -14,40 +14,30 @@
#include "sh_pfc.h"
#define CPU_32_PORT5(fn, pfx, sfx) \
PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx), \
PORT_1(fn, pfx##10, sfx), PORT_1(fn, pfx##11, sfx)
#define PORT_GP_12(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx)
/* GPSR0 - GPSR5 */
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_32(fn, pfx##_0_, sfx), \
PORT_32(fn, pfx##_1_, sfx), \
PORT_32(fn, pfx##_2_, sfx), \
PORT_32(fn, pfx##_3_, sfx), \
PORT_32(fn, pfx##_4_, sfx), \
CPU_32_PORT5(fn, pfx##_5_, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \
PORT_GP_32(3, fn, sfx), \
PORT_GP_32(4, fn, sfx), \
PORT_GP_12(5, fn, sfx)
#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
GP##pfx##_IN, GP##pfx##_OUT)
#undef _GP_DATA
#define _GP_DATA(bank, pin, name, sfx) \
PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT)
#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
FN_##ipsr, FN_##fn)
#define _GP_INOUTSEL(bank, pin, name, sfx) name##_IN, name##_OUT
#define _GP_INDT(bank, pin, name, sfx) name##_DATA
#define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused)
#define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused)
enum {
PINMUX_RESERVED = 0,
@ -592,7 +582,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT),

709
drivers/pinctrl/sh-pfc/pfc-sh7757.c
View File

@ -132,46 +132,6 @@ enum {
PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU,
PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU,
PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU,
PTG7_IN_PU, PTG6_IN_PU, PTG4_IN_PU,
PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
PTI7_IN_PU, PTI6_IN_PU, PTI4_IN_PU,
PTI3_IN_PU, PTI2_IN_PU, PTI1_IN_PU, PTI0_IN_PU,
PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU,
PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU,
PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU,
PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU,
PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
PTN4_IN_PU,
PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU,
PTO7_IN_PU, PTO6_IN_PU, PTO5_IN_PU, PTO4_IN_PU,
PTO3_IN_PU, PTO2_IN_PU, PTO1_IN_PU, PTO0_IN_PU,
PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU,
PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
PTV3_IN_PU, PTV2_IN_PU,
PTW1_IN_PU, PTW0_IN_PU,
PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU,
PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU,
PINMUX_INPUT_PULLUP_END,
PINMUX_OUTPUT_BEGIN,
PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
@ -526,7 +486,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* PTA GPIO */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
@ -1116,260 +1076,260 @@ static const pinmux_enum_t pinmux_data[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
PINMUX_GPIO(PTA7),
PINMUX_GPIO(PTA6),
PINMUX_GPIO(PTA5),
PINMUX_GPIO(PTA4),
PINMUX_GPIO(PTA3),
PINMUX_GPIO(PTA2),
PINMUX_GPIO(PTA1),
PINMUX_GPIO(PTA0),
/* PTB */
PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
PINMUX_GPIO(PTB7),
PINMUX_GPIO(PTB6),
PINMUX_GPIO(PTB5),
PINMUX_GPIO(PTB4),
PINMUX_GPIO(PTB3),
PINMUX_GPIO(PTB2),
PINMUX_GPIO(PTB1),
PINMUX_GPIO(PTB0),
/* PTC */
PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
PINMUX_GPIO(PTC7),
PINMUX_GPIO(PTC6),
PINMUX_GPIO(PTC5),
PINMUX_GPIO(PTC4),
PINMUX_GPIO(PTC3),
PINMUX_GPIO(PTC2),
PINMUX_GPIO(PTC1),
PINMUX_GPIO(PTC0),
/* PTD */
PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
PINMUX_GPIO(PTD7),
PINMUX_GPIO(PTD6),
PINMUX_GPIO(PTD5),
PINMUX_GPIO(PTD4),
PINMUX_GPIO(PTD3),
PINMUX_GPIO(PTD2),
PINMUX_GPIO(PTD1),
PINMUX_GPIO(PTD0),
/* PTE */
PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
PINMUX_GPIO(PTE7),
PINMUX_GPIO(PTE6),
PINMUX_GPIO(PTE5),
PINMUX_GPIO(PTE4),
PINMUX_GPIO(PTE3),
PINMUX_GPIO(PTE2),
PINMUX_GPIO(PTE1),
PINMUX_GPIO(PTE0),
/* PTF */
PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
PINMUX_GPIO(PTF7),
PINMUX_GPIO(PTF6),
PINMUX_GPIO(PTF5),
PINMUX_GPIO(PTF4),
PINMUX_GPIO(PTF3),
PINMUX_GPIO(PTF2),
PINMUX_GPIO(PTF1),
PINMUX_GPIO(PTF0),
/* PTG */
PINMUX_GPIO(GPIO_PTG7, PTG7_DATA),
PINMUX_GPIO(GPIO_PTG6, PTG6_DATA),
PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
PINMUX_GPIO(PTG7),
PINMUX_GPIO(PTG6),
PINMUX_GPIO(PTG5),
PINMUX_GPIO(PTG4),
PINMUX_GPIO(PTG3),
PINMUX_GPIO(PTG2),
PINMUX_GPIO(PTG1),
PINMUX_GPIO(PTG0),
/* PTH */
PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
PINMUX_GPIO(PTH7),
PINMUX_GPIO(PTH6),
PINMUX_GPIO(PTH5),
PINMUX_GPIO(PTH4),
PINMUX_GPIO(PTH3),
PINMUX_GPIO(PTH2),
PINMUX_GPIO(PTH1),
PINMUX_GPIO(PTH0),
/* PTI */
PINMUX_GPIO(GPIO_PTI7, PTI7_DATA),
PINMUX_GPIO(GPIO_PTI6, PTI6_DATA),
PINMUX_GPIO(GPIO_PTI5, PTI5_DATA),
PINMUX_GPIO(GPIO_PTI4, PTI4_DATA),
PINMUX_GPIO(GPIO_PTI3, PTI3_DATA),
PINMUX_GPIO(GPIO_PTI2, PTI2_DATA),
PINMUX_GPIO(GPIO_PTI1, PTI1_DATA),
PINMUX_GPIO(GPIO_PTI0, PTI0_DATA),
PINMUX_GPIO(PTI7),
PINMUX_GPIO(PTI6),
PINMUX_GPIO(PTI5),
PINMUX_GPIO(PTI4),
PINMUX_GPIO(PTI3),
PINMUX_GPIO(PTI2),
PINMUX_GPIO(PTI1),
PINMUX_GPIO(PTI0),
/* PTJ */
PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA),
PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
PINMUX_GPIO(PTJ6),
PINMUX_GPIO(PTJ5),
PINMUX_GPIO(PTJ4),
PINMUX_GPIO(PTJ3),
PINMUX_GPIO(PTJ2),
PINMUX_GPIO(PTJ1),
PINMUX_GPIO(PTJ0),
/* PTK */
PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
PINMUX_GPIO(PTK7),
PINMUX_GPIO(PTK6),
PINMUX_GPIO(PTK5),
PINMUX_GPIO(PTK4),
PINMUX_GPIO(PTK3),
PINMUX_GPIO(PTK2),
PINMUX_GPIO(PTK1),
PINMUX_GPIO(PTK0),
/* PTL */
PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
PINMUX_GPIO(PTL6),
PINMUX_GPIO(PTL5),
PINMUX_GPIO(PTL4),
PINMUX_GPIO(PTL3),
PINMUX_GPIO(PTL2),
PINMUX_GPIO(PTL1),
PINMUX_GPIO(PTL0),
/* PTM */
PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
PINMUX_GPIO(PTM7),
PINMUX_GPIO(PTM6),
PINMUX_GPIO(PTM5),
PINMUX_GPIO(PTM4),
PINMUX_GPIO(PTM3),
PINMUX_GPIO(PTM2),
PINMUX_GPIO(PTM1),
PINMUX_GPIO(PTM0),
/* PTN */
PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
PINMUX_GPIO(PTN6),
PINMUX_GPIO(PTN5),
PINMUX_GPIO(PTN4),
PINMUX_GPIO(PTN3),
PINMUX_GPIO(PTN2),
PINMUX_GPIO(PTN1),
PINMUX_GPIO(PTN0),
/* PTO */
PINMUX_GPIO(GPIO_PTO7, PTO7_DATA),
PINMUX_GPIO(GPIO_PTO6, PTO6_DATA),
PINMUX_GPIO(GPIO_PTO5, PTO5_DATA),
PINMUX_GPIO(GPIO_PTO4, PTO4_DATA),
PINMUX_GPIO(GPIO_PTO3, PTO3_DATA),
PINMUX_GPIO(GPIO_PTO2, PTO2_DATA),
PINMUX_GPIO(GPIO_PTO1, PTO1_DATA),
PINMUX_GPIO(GPIO_PTO0, PTO0_DATA),
PINMUX_GPIO(PTO7),
PINMUX_GPIO(PTO6),
PINMUX_GPIO(PTO5),
PINMUX_GPIO(PTO4),
PINMUX_GPIO(PTO3),
PINMUX_GPIO(PTO2),
PINMUX_GPIO(PTO1),
PINMUX_GPIO(PTO0),
/* PTP */
PINMUX_GPIO(GPIO_PTP7, PTP7_DATA),
PINMUX_GPIO(GPIO_PTP6, PTP6_DATA),
PINMUX_GPIO(GPIO_PTP5, PTP5_DATA),
PINMUX_GPIO(GPIO_PTP4, PTP4_DATA),
PINMUX_GPIO(GPIO_PTP3, PTP3_DATA),
PINMUX_GPIO(GPIO_PTP2, PTP2_DATA),
PINMUX_GPIO(GPIO_PTP1, PTP1_DATA),
PINMUX_GPIO(GPIO_PTP0, PTP0_DATA),
PINMUX_GPIO(PTP7),
PINMUX_GPIO(PTP6),
PINMUX_GPIO(PTP5),
PINMUX_GPIO(PTP4),
PINMUX_GPIO(PTP3),
PINMUX_GPIO(PTP2),
PINMUX_GPIO(PTP1),
PINMUX_GPIO(PTP0),
/* PTQ */
PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
PINMUX_GPIO(PTQ6),
PINMUX_GPIO(PTQ5),
PINMUX_GPIO(PTQ4),
PINMUX_GPIO(PTQ3),
PINMUX_GPIO(PTQ2),
PINMUX_GPIO(PTQ1),
PINMUX_GPIO(PTQ0),
/* PTR */
PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
PINMUX_GPIO(PTR7),
PINMUX_GPIO(PTR6),
PINMUX_GPIO(PTR5),
PINMUX_GPIO(PTR4),
PINMUX_GPIO(PTR3),
PINMUX_GPIO(PTR2),
PINMUX_GPIO(PTR1),
PINMUX_GPIO(PTR0),
/* PTS */
PINMUX_GPIO(GPIO_PTS7, PTS7_DATA),
PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
PINMUX_GPIO(PTS7),
PINMUX_GPIO(PTS6),
PINMUX_GPIO(PTS5),
PINMUX_GPIO(PTS4),
PINMUX_GPIO(PTS3),
PINMUX_GPIO(PTS2),
PINMUX_GPIO(PTS1),
PINMUX_GPIO(PTS0),
/* PTT */
PINMUX_GPIO(GPIO_PTT7, PTT7_DATA),
PINMUX_GPIO(GPIO_PTT6, PTT6_DATA),
PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
PINMUX_GPIO(PTT7),
PINMUX_GPIO(PTT6),
PINMUX_GPIO(PTT5),
PINMUX_GPIO(PTT4),
PINMUX_GPIO(PTT3),
PINMUX_GPIO(PTT2),
PINMUX_GPIO(PTT1),
PINMUX_GPIO(PTT0),
/* PTU */
PINMUX_GPIO(GPIO_PTU7, PTU7_DATA),
PINMUX_GPIO(GPIO_PTU6, PTU6_DATA),
PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
PINMUX_GPIO(PTU7),
PINMUX_GPIO(PTU6),
PINMUX_GPIO(PTU5),
PINMUX_GPIO(PTU4),
PINMUX_GPIO(PTU3),
PINMUX_GPIO(PTU2),
PINMUX_GPIO(PTU1),
PINMUX_GPIO(PTU0),
/* PTV */
PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
PINMUX_GPIO(PTV7),
PINMUX_GPIO(PTV6),
PINMUX_GPIO(PTV5),
PINMUX_GPIO(PTV4),
PINMUX_GPIO(PTV3),
PINMUX_GPIO(PTV2),
PINMUX_GPIO(PTV1),
PINMUX_GPIO(PTV0),
/* PTW */
PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
PINMUX_GPIO(PTW7),
PINMUX_GPIO(PTW6),
PINMUX_GPIO(PTW5),
PINMUX_GPIO(PTW4),
PINMUX_GPIO(PTW3),
PINMUX_GPIO(PTW2),
PINMUX_GPIO(PTW1),
PINMUX_GPIO(PTW0),
/* PTX */
PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
PINMUX_GPIO(PTX7),
PINMUX_GPIO(PTX6),
PINMUX_GPIO(PTX5),
PINMUX_GPIO(PTX4),
PINMUX_GPIO(PTX3),
PINMUX_GPIO(PTX2),
PINMUX_GPIO(PTX1),
PINMUX_GPIO(PTX0),
/* PTY */
PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
PINMUX_GPIO(PTY7),
PINMUX_GPIO(PTY6),
PINMUX_GPIO(PTY5),
PINMUX_GPIO(PTY4),
PINMUX_GPIO(PTY3),
PINMUX_GPIO(PTY2),
PINMUX_GPIO(PTY1),
PINMUX_GPIO(PTY0),
/* PTZ */
PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
PINMUX_GPIO(PTZ7),
PINMUX_GPIO(PTZ6),
PINMUX_GPIO(PTZ5),
PINMUX_GPIO(PTZ4),
PINMUX_GPIO(PTZ3),
PINMUX_GPIO(PTZ2),
PINMUX_GPIO(PTZ1),
PINMUX_GPIO(PTZ0),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
@ -1728,14 +1688,14 @@ static const struct pinmux_func pinmux_func_gpios[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU,
PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU,
PTA5_FN, PTA5_OUT, PTA5_IN, PTA5_IN_PU,
PTA4_FN, PTA4_OUT, PTA4_IN, PTA4_IN_PU,
PTA3_FN, PTA3_OUT, PTA3_IN, PTA3_IN_PU,
PTA2_FN, PTA2_OUT, PTA2_IN, PTA2_IN_PU,
PTA1_FN, PTA1_OUT, PTA1_IN, PTA1_IN_PU,
PTA0_FN, PTA0_OUT, PTA0_IN, PTA0_IN_PU }
PTA7_FN, PTA7_OUT, PTA7_IN, 0,
PTA6_FN, PTA6_OUT, PTA6_IN, 0,
PTA5_FN, PTA5_OUT, PTA5_IN, 0,
PTA4_FN, PTA4_OUT, PTA4_IN, 0,
PTA3_FN, PTA3_OUT, PTA3_IN, 0,
PTA2_FN, PTA2_OUT, PTA2_IN, 0,
PTA1_FN, PTA1_OUT, PTA1_IN, 0,
PTA0_FN, PTA0_OUT, PTA0_IN, 0 }
},
{ PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) {
PTB7_FN, PTB7_OUT, PTB7_IN, 0,
@ -1758,100 +1718,100 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTC0_FN, PTC0_OUT, PTC0_IN, 0 }
},
{ PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) {
PTD7_FN, PTD7_OUT, PTD7_IN, PTD7_IN_PU,
PTD6_FN, PTD6_OUT, PTD6_IN, PTD6_IN_PU,
PTD5_FN, PTD5_OUT, PTD5_IN, PTD5_IN_PU,
PTD4_FN, PTD4_OUT, PTD4_IN, PTD4_IN_PU,
PTD3_FN, PTD3_OUT, PTD3_IN, PTD3_IN_PU,
PTD2_FN, PTD2_OUT, PTD2_IN, PTD2_IN_PU,
PTD1_FN, PTD1_OUT, PTD1_IN, PTD1_IN_PU,
PTD0_FN, PTD0_OUT, PTD0_IN, PTD0_IN_PU }
PTD7_FN, PTD7_OUT, PTD7_IN, 0,
PTD6_FN, PTD6_OUT, PTD6_IN, 0,
PTD5_FN, PTD5_OUT, PTD5_IN, 0,
PTD4_FN, PTD4_OUT, PTD4_IN, 0,
PTD3_FN, PTD3_OUT, PTD3_IN, 0,
PTD2_FN, PTD2_OUT, PTD2_IN, 0,
PTD1_FN, PTD1_OUT, PTD1_IN, 0,
PTD0_FN, PTD0_OUT, PTD0_IN, 0 }
},
{ PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) {
PTE7_FN, PTE7_OUT, PTE7_IN, PTE7_IN_PU,
PTE6_FN, PTE6_OUT, PTE6_IN, PTE6_IN_PU,
PTE5_FN, PTE5_OUT, PTE5_IN, PTE5_IN_PU,
PTE4_FN, PTE4_OUT, PTE4_IN, PTE4_IN_PU,
PTE3_FN, PTE3_OUT, PTE3_IN, PTE3_IN_PU,
PTE2_FN, PTE2_OUT, PTE2_IN, PTE2_IN_PU,
PTE1_FN, PTE1_OUT, PTE1_IN, PTE1_IN_PU,
PTE0_FN, PTE0_OUT, PTE0_IN, PTE0_IN_PU }
PTE7_FN, PTE7_OUT, PTE7_IN, 0,
PTE6_FN, PTE6_OUT, PTE6_IN, 0,
PTE5_FN, PTE5_OUT, PTE5_IN, 0,
PTE4_FN, PTE4_OUT, PTE4_IN, 0,
PTE3_FN, PTE3_OUT, PTE3_IN, 0,
PTE2_FN, PTE2_OUT, PTE2_IN, 0,
PTE1_FN, PTE1_OUT, PTE1_IN, 0,
PTE0_FN, PTE0_OUT, PTE0_IN, 0 }
},
{ PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) {
PTF7_FN, PTF7_OUT, PTF7_IN, PTF7_IN_PU,
PTF6_FN, PTF6_OUT, PTF6_IN, PTF6_IN_PU,
PTF5_FN, PTF5_OUT, PTF5_IN, PTF5_IN_PU,
PTF4_FN, PTF4_OUT, PTF4_IN, PTF4_IN_PU,
PTF3_FN, PTF3_OUT, PTF3_IN, PTF3_IN_PU,
PTF2_FN, PTF2_OUT, PTF2_IN, PTF2_IN_PU,
PTF1_FN, PTF1_OUT, PTF1_IN, PTF1_IN_PU,
PTF0_FN, PTF0_OUT, PTF0_IN, PTF0_IN_PU }
PTF7_FN, PTF7_OUT, PTF7_IN, 0,
PTF6_FN, PTF6_OUT, PTF6_IN, 0,
PTF5_FN, PTF5_OUT, PTF5_IN, 0,
PTF4_FN, PTF4_OUT, PTF4_IN, 0,
PTF3_FN, PTF3_OUT, PTF3_IN, 0,
PTF2_FN, PTF2_OUT, PTF2_IN, 0,
PTF1_FN, PTF1_OUT, PTF1_IN, 0,
PTF0_FN, PTF0_OUT, PTF0_IN, 0 }
},
{ PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) {
PTG7_FN, PTG7_OUT, PTG7_IN, PTG7_IN_PU ,
PTG6_FN, PTG6_OUT, PTG6_IN, PTG6_IN_PU ,
PTG7_FN, PTG7_OUT, PTG7_IN, 0,
PTG6_FN, PTG6_OUT, PTG6_IN, 0,
PTG5_FN, PTG5_OUT, PTG5_IN, 0,
PTG4_FN, PTG4_OUT, PTG4_IN, PTG4_IN_PU ,
PTG4_FN, PTG4_OUT, PTG4_IN, 0,
PTG3_FN, PTG3_OUT, PTG3_IN, 0,
PTG2_FN, PTG2_OUT, PTG2_IN, 0,
PTG1_FN, PTG1_OUT, PTG1_IN, 0,
PTG0_FN, PTG0_OUT, PTG0_IN, 0 }
},
{ PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) {
PTH7_FN, PTH7_OUT, PTH7_IN, PTH7_IN_PU,
PTH6_FN, PTH6_OUT, PTH6_IN, PTH6_IN_PU,
PTH5_FN, PTH5_OUT, PTH5_IN, PTH5_IN_PU,
PTH4_FN, PTH4_OUT, PTH4_IN, PTH4_IN_PU,
PTH3_FN, PTH3_OUT, PTH3_IN, PTH3_IN_PU,
PTH2_FN, PTH2_OUT, PTH2_IN, PTH2_IN_PU,
PTH1_FN, PTH1_OUT, PTH1_IN, PTH1_IN_PU,
PTH0_FN, PTH0_OUT, PTH0_IN, PTH0_IN_PU }
PTH7_FN, PTH7_OUT, PTH7_IN, 0,
PTH6_FN, PTH6_OUT, PTH6_IN, 0,
PTH5_FN, PTH5_OUT, PTH5_IN, 0,
PTH4_FN, PTH4_OUT, PTH4_IN, 0,
PTH3_FN, PTH3_OUT, PTH3_IN, 0,
PTH2_FN, PTH2_OUT, PTH2_IN, 0,
PTH1_FN, PTH1_OUT, PTH1_IN, 0,
PTH0_FN, PTH0_OUT, PTH0_IN, 0 }
},
{ PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) {
PTI7_FN, PTI7_OUT, PTI7_IN, PTI7_IN_PU,
PTI6_FN, PTI6_OUT, PTI6_IN, PTI6_IN_PU,
PTI7_FN, PTI7_OUT, PTI7_IN, 0,
PTI6_FN, PTI6_OUT, PTI6_IN, 0,
PTI5_FN, PTI5_OUT, PTI5_IN, 0,
PTI4_FN, PTI4_OUT, PTI4_IN, PTI4_IN_PU,
PTI3_FN, PTI3_OUT, PTI3_IN, PTI3_IN_PU,
PTI2_FN, PTI2_OUT, PTI2_IN, PTI2_IN_PU,
PTI1_FN, PTI1_OUT, PTI1_IN, PTI1_IN_PU,
PTI0_FN, PTI0_OUT, PTI0_IN, PTI0_IN_PU }
PTI4_FN, PTI4_OUT, PTI4_IN, 0,
PTI3_FN, PTI3_OUT, PTI3_IN, 0,
PTI2_FN, PTI2_OUT, PTI2_IN, 0,
PTI1_FN, PTI1_OUT, PTI1_IN, 0,
PTI0_FN, PTI0_OUT, PTI0_IN, 0 }
},
{ PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) {
0, 0, 0, 0, /* reserved: always set 1 */
PTJ6_FN, PTJ6_OUT, PTJ6_IN, PTJ6_IN_PU,
PTJ5_FN, PTJ5_OUT, PTJ5_IN, PTJ5_IN_PU,
PTJ4_FN, PTJ4_OUT, PTJ4_IN, PTJ4_IN_PU,
PTJ3_FN, PTJ3_OUT, PTJ3_IN, PTJ3_IN_PU,
PTJ2_FN, PTJ2_OUT, PTJ2_IN, PTJ2_IN_PU,
PTJ1_FN, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU,
PTJ0_FN, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU }
PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0,
PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0,
PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0,
PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0,
PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0,
PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0,
PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 }
},
{ PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) {
PTK7_FN, PTK7_OUT, PTK7_IN, PTK7_IN_PU,
PTK6_FN, PTK6_OUT, PTK6_IN, PTK6_IN_PU,
PTK5_FN, PTK5_OUT, PTK5_IN, PTK5_IN_PU,
PTK4_FN, PTK4_OUT, PTK4_IN, PTK4_IN_PU,
PTK3_FN, PTK3_OUT, PTK3_IN, PTK3_IN_PU,
PTK2_FN, PTK2_OUT, PTK2_IN, PTK2_IN_PU,
PTK1_FN, PTK1_OUT, PTK1_IN, PTK1_IN_PU,
PTK0_FN, PTK0_OUT, PTK0_IN, PTK0_IN_PU }
PTK7_FN, PTK7_OUT, PTK7_IN, 0,
PTK6_FN, PTK6_OUT, PTK6_IN, 0,
PTK5_FN, PTK5_OUT, PTK5_IN, 0,
PTK4_FN, PTK4_OUT, PTK4_IN, 0,
PTK3_FN, PTK3_OUT, PTK3_IN, 0,
PTK2_FN, PTK2_OUT, PTK2_IN, 0,
PTK1_FN, PTK1_OUT, PTK1_IN, 0,
PTK0_FN, PTK0_OUT, PTK0_IN, 0 }
},
{ PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) {
0, 0, 0, 0, /* reserved: always set 1 */
PTL6_FN, PTL6_OUT, PTL6_IN, PTL6_IN_PU,
PTL5_FN, PTL5_OUT, PTL5_IN, PTL5_IN_PU,
PTL4_FN, PTL4_OUT, PTL4_IN, PTL4_IN_PU,
PTL3_FN, PTL3_OUT, PTL3_IN, PTL3_IN_PU,
PTL2_FN, PTL2_OUT, PTL2_IN, PTL2_IN_PU,
PTL1_FN, PTL1_OUT, PTL1_IN, PTL1_IN_PU,
PTL0_FN, PTL0_OUT, PTL0_IN, PTL0_IN_PU }
PTL6_FN, PTL6_OUT, PTL6_IN, 0,
PTL5_FN, PTL5_OUT, PTL5_IN, 0,
PTL4_FN, PTL4_OUT, PTL4_IN, 0,
PTL3_FN, PTL3_OUT, PTL3_IN, 0,
PTL2_FN, PTL2_OUT, PTL2_IN, 0,
PTL1_FN, PTL1_OUT, PTL1_IN, 0,
PTL0_FN, PTL0_OUT, PTL0_IN, 0 }
},
{ PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) {
PTM7_FN, PTM7_OUT, PTM7_IN, PTM7_IN_PU,
PTM6_FN, PTM6_OUT, PTM6_IN, PTM6_IN_PU,
PTM5_FN, PTM5_OUT, PTM5_IN, PTM5_IN_PU,
PTM4_FN, PTM4_OUT, PTM4_IN, PTM4_IN_PU,
PTM7_FN, PTM7_OUT, PTM7_IN, 0,
PTM6_FN, PTM6_OUT, PTM6_IN, 0,
PTM5_FN, PTM5_OUT, PTM5_IN, 0,
PTM4_FN, PTM4_OUT, PTM4_IN, 0,
PTM3_FN, PTM3_OUT, PTM3_IN, 0,
PTM2_FN, PTM2_OUT, PTM2_IN, 0,
PTM1_FN, PTM1_OUT, PTM1_IN, 0,
@ -1861,21 +1821,21 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, /* reserved: always set 1 */
PTN6_FN, PTN6_OUT, PTN6_IN, 0,
PTN5_FN, PTN5_OUT, PTN5_IN, 0,
PTN4_FN, PTN4_OUT, PTN4_IN, PTN4_IN_PU,
PTN3_FN, PTN3_OUT, PTN3_IN, PTN3_IN_PU,
PTN2_FN, PTN2_OUT, PTN2_IN, PTN2_IN_PU,
PTN1_FN, PTN1_OUT, PTN1_IN, PTN1_IN_PU,
PTN0_FN, PTN0_OUT, PTN0_IN, PTN0_IN_PU }
PTN4_FN, PTN4_OUT, PTN4_IN, 0,
PTN3_FN, PTN3_OUT, PTN3_IN, 0,
PTN2_FN, PTN2_OUT, PTN2_IN, 0,
PTN1_FN, PTN1_OUT, PTN1_IN, 0,
PTN0_FN, PTN0_OUT, PTN0_IN, 0 }
},
{ PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) {
PTO7_FN, PTO7_OUT, PTO7_IN, PTO7_IN_PU,
PTO6_FN, PTO6_OUT, PTO6_IN, PTO6_IN_PU,
PTO5_FN, PTO5_OUT, PTO5_IN, PTO5_IN_PU,
PTO4_FN, PTO4_OUT, PTO4_IN, PTO4_IN_PU,
PTO3_FN, PTO3_OUT, PTO3_IN, PTO3_IN_PU,
PTO2_FN, PTO2_OUT, PTO2_IN, PTO2_IN_PU,
PTO1_FN, PTO1_OUT, PTO1_IN, PTO1_IN_PU,
PTO0_FN, PTO0_OUT, PTO0_IN, PTO0_IN_PU }
PTO7_FN, PTO7_OUT, PTO7_IN, 0,
PTO6_FN, PTO6_OUT, PTO6_IN, 0,
PTO5_FN, PTO5_OUT, PTO5_IN, 0,
PTO4_FN, PTO4_OUT, PTO4_IN, 0,
PTO3_FN, PTO3_OUT, PTO3_IN, 0,
PTO2_FN, PTO2_OUT, PTO2_IN, 0,
PTO1_FN, PTO1_OUT, PTO1_IN, 0,
PTO0_FN, PTO0_OUT, PTO0_IN, 0 }
},
#if 0 /* FIXME: Remove it? */
{ PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) {
@ -1920,32 +1880,32 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTS0_FN, PTS0_OUT, PTS0_IN, 0 }
},
{ PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) {
PTT7_FN, PTT7_OUT, PTT7_IN, PTO7_IN_PU,
PTT6_FN, PTT6_OUT, PTT6_IN, PTO6_IN_PU,
PTT5_FN, PTT5_OUT, PTT5_IN, PTO5_IN_PU,
PTT4_FN, PTT4_OUT, PTT4_IN, PTO4_IN_PU,
PTT3_FN, PTT3_OUT, PTT3_IN, PTO3_IN_PU,
PTT2_FN, PTT2_OUT, PTT2_IN, PTO2_IN_PU,
PTT1_FN, PTT1_OUT, PTT1_IN, PTO1_IN_PU,
PTT0_FN, PTT0_OUT, PTT0_IN, PTO0_IN_PU }
PTT7_FN, PTT7_OUT, PTT7_IN, 0,
PTT6_FN, PTT6_OUT, PTT6_IN, 0,
PTT5_FN, PTT5_OUT, PTT5_IN, 0,
PTT4_FN, PTT4_OUT, PTT4_IN, 0,
PTT3_FN, PTT3_OUT, PTT3_IN, 0,
PTT2_FN, PTT2_OUT, PTT2_IN, 0,
PTT1_FN, PTT1_OUT, PTT1_IN, 0,
PTT0_FN, PTT0_OUT, PTT0_IN, 0 }
},
{ PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) {
PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU,
PTU6_FN, PTU6_OUT, PTU6_IN, PTU6_IN_PU,
PTU5_FN, PTU5_OUT, PTU5_IN, PTU5_IN_PU,
PTU4_FN, PTU4_OUT, PTU4_IN, PTU4_IN_PU,
PTU3_FN, PTU3_OUT, PTU3_IN, PTU3_IN_PU,
PTU2_FN, PTU2_OUT, PTU2_IN, PTU2_IN_PU,
PTU1_FN, PTU1_OUT, PTU1_IN, PTU1_IN_PU,
PTU0_FN, PTU0_OUT, PTU0_IN, PTU0_IN_PU }
PTU7_FN, PTU7_OUT, PTU7_IN, 0,
PTU6_FN, PTU6_OUT, PTU6_IN, 0,
PTU5_FN, PTU5_OUT, PTU5_IN, 0,
PTU4_FN, PTU4_OUT, PTU4_IN, 0,
PTU3_FN, PTU3_OUT, PTU3_IN, 0,
PTU2_FN, PTU2_OUT, PTU2_IN, 0,
PTU1_FN, PTU1_OUT, PTU1_IN, 0,
PTU0_FN, PTU0_OUT, PTU0_IN, 0 }
},
{ PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2) {
PTV7_FN, PTV7_OUT, PTV7_IN, PTV7_IN_PU,
PTV6_FN, PTV6_OUT, PTV6_IN, PTV6_IN_PU,
PTV5_FN, PTV5_OUT, PTV5_IN, PTV5_IN_PU,
PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU,
PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU,
PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU,
PTV7_FN, PTV7_OUT, PTV7_IN, 0,
PTV6_FN, PTV6_OUT, PTV6_IN, 0,
PTV5_FN, PTV5_OUT, PTV5_IN, 0,
PTV4_FN, PTV4_OUT, PTV4_IN, 0,
PTV3_FN, PTV3_OUT, PTV3_IN, 0,
PTV2_FN, PTV2_OUT, PTV2_IN, 0,
PTV1_FN, PTV1_OUT, PTV1_IN, 0,
PTV0_FN, PTV0_OUT, PTV0_IN, 0 }
},
@ -1956,28 +1916,28 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTW4_FN, PTW4_OUT, PTW4_IN, 0,
PTW3_FN, PTW3_OUT, PTW3_IN, 0,
PTW2_FN, PTW2_OUT, PTW2_IN, 0,
PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU,
PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU }
PTW1_FN, PTW1_OUT, PTW1_IN, 0,
PTW0_FN, PTW0_OUT, PTW0_IN, 0 }
},
{ PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2) {
PTX7_FN, PTX7_OUT, PTX7_IN, PTX7_IN_PU,
PTX6_FN, PTX6_OUT, PTX6_IN, PTX6_IN_PU,
PTX5_FN, PTX5_OUT, PTX5_IN, PTX5_IN_PU,
PTX4_FN, PTX4_OUT, PTX4_IN, PTX4_IN_PU,
PTX3_FN, PTX3_OUT, PTX3_IN, PTX3_IN_PU,
PTX2_FN, PTX2_OUT, PTX2_IN, PTX2_IN_PU,
PTX1_FN, PTX1_OUT, PTX1_IN, PTX1_IN_PU,
PTX0_FN, PTX0_OUT, PTX0_IN, PTX0_IN_PU }
PTX7_FN, PTX7_OUT, PTX7_IN, 0,
PTX6_FN, PTX6_OUT, PTX6_IN, 0,
PTX5_FN, PTX5_OUT, PTX5_IN, 0,
PTX4_FN, PTX4_OUT, PTX4_IN, 0,
PTX3_FN, PTX3_OUT, PTX3_IN, 0,
PTX2_FN, PTX2_OUT, PTX2_IN, 0,
PTX1_FN, PTX1_OUT, PTX1_IN, 0,
PTX0_FN, PTX0_OUT, PTX0_IN, 0 }
},
{ PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2) {
PTY7_FN, PTY7_OUT, PTY7_IN, PTY7_IN_PU,
PTY6_FN, PTY6_OUT, PTY6_IN, PTY6_IN_PU,
PTY5_FN, PTY5_OUT, PTY5_IN, PTY5_IN_PU,
PTY4_FN, PTY4_OUT, PTY4_IN, PTY4_IN_PU,
PTY3_FN, PTY3_OUT, PTY3_IN, PTY3_IN_PU,
PTY2_FN, PTY2_OUT, PTY2_IN, PTY2_IN_PU,
PTY1_FN, PTY1_OUT, PTY1_IN, PTY1_IN_PU,
PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU }
PTY7_FN, PTY7_OUT, PTY7_IN, 0,
PTY6_FN, PTY6_OUT, PTY6_IN, 0,
PTY5_FN, PTY5_OUT, PTY5_IN, 0,
PTY4_FN, PTY4_OUT, PTY4_IN, 0,
PTY3_FN, PTY3_OUT, PTY3_IN, 0,
PTY2_FN, PTY2_OUT, PTY2_IN, 0,
PTY1_FN, PTY1_OUT, PTY1_IN, 0,
PTY0_FN, PTY0_OUT, PTY0_IN, 0 }
},
{ PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) {
PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0,
@ -2267,7 +2227,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
const struct sh_pfc_soc_info sh7757_pinmux_info = {
.name = "sh7757_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

700
drivers/pinctrl/sh-pfc/pfc-sh7785.c
View File

@ -77,36 +77,6 @@ enum {
PR3_IN, PR2_IN, PR1_IN, PR0_IN,
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
PE5_IN_PU, PE4_IN_PU, PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU,
PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU,
PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU,
PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU, PJ0_IN_PU,
PK7_IN_PU, PK6_IN_PU, PK5_IN_PU, PK4_IN_PU,
PK3_IN_PU, PK2_IN_PU, PK1_IN_PU, PK0_IN_PU,
PL7_IN_PU, PL6_IN_PU, PL5_IN_PU, PL4_IN_PU,
PL3_IN_PU, PL2_IN_PU, PL1_IN_PU, PL0_IN_PU,
PM1_IN_PU, PM0_IN_PU,
PN7_IN_PU, PN6_IN_PU, PN5_IN_PU, PN4_IN_PU,
PN3_IN_PU, PN2_IN_PU, PN1_IN_PU, PN0_IN_PU,
PP5_IN_PU, PP4_IN_PU, PP3_IN_PU, PP2_IN_PU, PP1_IN_PU, PP0_IN_PU,
PQ4_IN_PU, PQ3_IN_PU, PQ2_IN_PU, PQ1_IN_PU, PQ0_IN_PU,
PR3_IN_PU, PR2_IN_PU, PR1_IN_PU, PR0_IN_PU,
PINMUX_INPUT_PULLUP_END,
PINMUX_OUTPUT_BEGIN,
PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
@ -355,150 +325,149 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* PA GPIO */
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT),
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT),
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT),
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT),
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT),
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT),
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT),
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT),
/* PB GPIO */
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT),
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT),
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT),
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT),
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT),
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT),
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT),
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT),
/* PC GPIO */
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT),
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT),
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT),
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT),
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT),
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT),
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT),
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT),
/* PD GPIO */
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT),
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT),
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT),
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT),
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT),
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT),
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT),
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT),
/* PE GPIO */
PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU),
PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU),
PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU),
PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU),
PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU),
PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU),
PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT),
PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT),
PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT),
PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT),
PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT),
PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT),
/* PF GPIO */
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT),
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT),
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT),
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT),
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT),
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT),
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT),
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT),
/* PG GPIO */
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU),
PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU),
PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU),
PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU),
PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU),
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT),
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT),
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT),
PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT),
PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT),
PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT),
PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT),
PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT),
/* PH GPIO */
PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT),
PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT),
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT),
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT),
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT),
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT),
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT),
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT),
/* PJ GPIO */
PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
PINMUX_DATA(PJ0_DATA, PJ0_IN, PJ0_OUT, PJ0_IN_PU),
PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT),
PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT),
PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT),
PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT),
PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT),
PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT),
PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT),
PINMUX_DATA(PJ0_DATA, PJ0_IN, PJ0_OUT),
/* PK GPIO */
PINMUX_DATA(PK7_DATA, PK7_IN, PK7_OUT, PK7_IN_PU),
PINMUX_DATA(PK6_DATA, PK6_IN, PK6_OUT, PK6_IN_PU),
PINMUX_DATA(PK5_DATA, PK5_IN, PK5_OUT, PK5_IN_PU),
PINMUX_DATA(PK4_DATA, PK4_IN, PK4_OUT, PK4_IN_PU),
PINMUX_DATA(PK3_DATA, PK3_IN, PK3_OUT, PK3_IN_PU),
PINMUX_DATA(PK2_DATA, PK2_IN, PK2_OUT, PK2_IN_PU),
PINMUX_DATA(PK1_DATA, PK1_IN, PK1_OUT, PK1_IN_PU),
PINMUX_DATA(PK0_DATA, PK0_IN, PK0_OUT, PK0_IN_PU),
PINMUX_DATA(PK7_DATA, PK7_IN, PK7_OUT),
PINMUX_DATA(PK6_DATA, PK6_IN, PK6_OUT),
PINMUX_DATA(PK5_DATA, PK5_IN, PK5_OUT),
PINMUX_DATA(PK4_DATA, PK4_IN, PK4_OUT),
PINMUX_DATA(PK3_DATA, PK3_IN, PK3_OUT),
PINMUX_DATA(PK2_DATA, PK2_IN, PK2_OUT),
PINMUX_DATA(PK1_DATA, PK1_IN, PK1_OUT),
PINMUX_DATA(PK0_DATA, PK0_IN, PK0_OUT),
/* PL GPIO */
PINMUX_DATA(PL7_DATA, PL7_IN, PL7_OUT, PL7_IN_PU),
PINMUX_DATA(PL6_DATA, PL6_IN, PL6_OUT, PL6_IN_PU),
PINMUX_DATA(PL5_DATA, PL5_IN, PL5_OUT, PL5_IN_PU),
PINMUX_DATA(PL4_DATA, PL4_IN, PL4_OUT, PL4_IN_PU),
PINMUX_DATA(PL3_DATA, PL3_IN, PL3_OUT, PL3_IN_PU),
PINMUX_DATA(PL2_DATA, PL2_IN, PL2_OUT, PL2_IN_PU),
PINMUX_DATA(PL1_DATA, PL1_IN, PL1_OUT, PL1_IN_PU),
PINMUX_DATA(PL0_DATA, PL0_IN, PL0_OUT, PL0_IN_PU),
PINMUX_DATA(PL7_DATA, PL7_IN, PL7_OUT),
PINMUX_DATA(PL6_DATA, PL6_IN, PL6_OUT),
PINMUX_DATA(PL5_DATA, PL5_IN, PL5_OUT),
PINMUX_DATA(PL4_DATA, PL4_IN, PL4_OUT),
PINMUX_DATA(PL3_DATA, PL3_IN, PL3_OUT),
PINMUX_DATA(PL2_DATA, PL2_IN, PL2_OUT),
PINMUX_DATA(PL1_DATA, PL1_IN, PL1_OUT),
PINMUX_DATA(PL0_DATA, PL0_IN, PL0_OUT),
/* PM GPIO */
PINMUX_DATA(PM1_DATA, PM1_IN, PM1_OUT, PM1_IN_PU),
PINMUX_DATA(PM0_DATA, PM0_IN, PM0_OUT, PM0_IN_PU),
PINMUX_DATA(PM1_DATA, PM1_IN, PM1_OUT),
PINMUX_DATA(PM0_DATA, PM0_IN, PM0_OUT),
/* PN GPIO */
PINMUX_DATA(PN7_DATA, PN7_IN, PN7_OUT, PN7_IN_PU),
PINMUX_DATA(PN6_DATA, PN6_IN, PN6_OUT, PN6_IN_PU),
PINMUX_DATA(PN5_DATA, PN5_IN, PN5_OUT, PN5_IN_PU),
PINMUX_DATA(PN4_DATA, PN4_IN, PN4_OUT, PN4_IN_PU),
PINMUX_DATA(PN3_DATA, PN3_IN, PN3_OUT, PN3_IN_PU),
PINMUX_DATA(PN2_DATA, PN2_IN, PN2_OUT, PN2_IN_PU),
PINMUX_DATA(PN1_DATA, PN1_IN, PN1_OUT, PN1_IN_PU),
PINMUX_DATA(PN0_DATA, PN0_IN, PN0_OUT, PN0_IN_PU),
PINMUX_DATA(PN7_DATA, PN7_IN, PN7_OUT),
PINMUX_DATA(PN6_DATA, PN6_IN, PN6_OUT),
PINMUX_DATA(PN5_DATA, PN5_IN, PN5_OUT),
PINMUX_DATA(PN4_DATA, PN4_IN, PN4_OUT),
PINMUX_DATA(PN3_DATA, PN3_IN, PN3_OUT),
PINMUX_DATA(PN2_DATA, PN2_IN, PN2_OUT),
PINMUX_DATA(PN1_DATA, PN1_IN, PN1_OUT),
PINMUX_DATA(PN0_DATA, PN0_IN, PN0_OUT),
/* PP GPIO */
PINMUX_DATA(PP5_DATA, PP5_IN, PP5_OUT, PP5_IN_PU),
PINMUX_DATA(PP4_DATA, PP4_IN, PP4_OUT, PP4_IN_PU),
PINMUX_DATA(PP3_DATA, PP3_IN, PP3_OUT, PP3_IN_PU),
PINMUX_DATA(PP2_DATA, PP2_IN, PP2_OUT, PP2_IN_PU),
PINMUX_DATA(PP1_DATA, PP1_IN, PP1_OUT, PP1_IN_PU),
PINMUX_DATA(PP0_DATA, PP0_IN, PP0_OUT, PP0_IN_PU),
PINMUX_DATA(PP5_DATA, PP5_IN, PP5_OUT),
PINMUX_DATA(PP4_DATA, PP4_IN, PP4_OUT),
PINMUX_DATA(PP3_DATA, PP3_IN, PP3_OUT),
PINMUX_DATA(PP2_DATA, PP2_IN, PP2_OUT),
PINMUX_DATA(PP1_DATA, PP1_IN, PP1_OUT),
PINMUX_DATA(PP0_DATA, PP0_IN, PP0_OUT),
/* PQ GPIO */
PINMUX_DATA(PQ4_DATA, PQ4_IN, PQ4_OUT, PQ4_IN_PU),
PINMUX_DATA(PQ3_DATA, PQ3_IN, PQ3_OUT, PQ3_IN_PU),
PINMUX_DATA(PQ2_DATA, PQ2_IN, PQ2_OUT, PQ2_IN_PU),
PINMUX_DATA(PQ1_DATA, PQ1_IN, PQ1_OUT, PQ1_IN_PU),
PINMUX_DATA(PQ0_DATA, PQ0_IN, PQ0_OUT, PQ0_IN_PU),
PINMUX_DATA(PQ4_DATA, PQ4_IN, PQ4_OUT),
PINMUX_DATA(PQ3_DATA, PQ3_IN, PQ3_OUT),
PINMUX_DATA(PQ2_DATA, PQ2_IN, PQ2_OUT),
PINMUX_DATA(PQ1_DATA, PQ1_IN, PQ1_OUT),
PINMUX_DATA(PQ0_DATA, PQ0_IN, PQ0_OUT),
/* PR GPIO */
PINMUX_DATA(PR3_DATA, PR3_IN, PR3_OUT, PR3_IN_PU),
PINMUX_DATA(PR2_DATA, PR2_IN, PR2_OUT, PR2_IN_PU),
PINMUX_DATA(PR1_DATA, PR1_IN, PR1_OUT, PR1_IN_PU),
PINMUX_DATA(PR0_DATA, PR0_IN, PR0_OUT, PR0_IN_PU),
PINMUX_DATA(PR3_DATA, PR3_IN, PR3_OUT),
PINMUX_DATA(PR2_DATA, PR2_IN, PR2_OUT),
PINMUX_DATA(PR1_DATA, PR1_IN, PR1_OUT),
PINMUX_DATA(PR0_DATA, PR0_IN, PR0_OUT),
/* PA FN */
PINMUX_DATA(D63_AD31_MARK, PA7_FN),
@ -704,147 +673,147 @@ static const pinmux_enum_t pinmux_data[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
PINMUX_GPIO(GPIO_PA5, PA5_DATA),
PINMUX_GPIO(GPIO_PA4, PA4_DATA),
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
PINMUX_GPIO(PA7),
PINMUX_GPIO(PA6),
PINMUX_GPIO(PA5),
PINMUX_GPIO(PA4),
PINMUX_GPIO(PA3),
PINMUX_GPIO(PA2),
PINMUX_GPIO(PA1),
PINMUX_GPIO(PA0),
/* PB */
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
PINMUX_GPIO(GPIO_PB0, PB0_DATA),
PINMUX_GPIO(PB7),
PINMUX_GPIO(PB6),
PINMUX_GPIO(PB5),
PINMUX_GPIO(PB4),
PINMUX_GPIO(PB3),
PINMUX_GPIO(PB2),
PINMUX_GPIO(PB1),
PINMUX_GPIO(PB0),
/* PC */
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
PINMUX_GPIO(PC7),
PINMUX_GPIO(PC6),
PINMUX_GPIO(PC5),
PINMUX_GPIO(PC4),
PINMUX_GPIO(PC3),
PINMUX_GPIO(PC2),
PINMUX_GPIO(PC1),
PINMUX_GPIO(PC0),
/* PD */
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
PINMUX_GPIO(PD7),
PINMUX_GPIO(PD6),
PINMUX_GPIO(PD5),
PINMUX_GPIO(PD4),
PINMUX_GPIO(PD3),
PINMUX_GPIO(PD2),
PINMUX_GPIO(PD1),
PINMUX_GPIO(PD0),
/* PE */
PINMUX_GPIO(GPIO_PE5, PE5_DATA),
PINMUX_GPIO(GPIO_PE4, PE4_DATA),
PINMUX_GPIO(GPIO_PE3, PE3_DATA),
PINMUX_GPIO(GPIO_PE2, PE2_DATA),
PINMUX_GPIO(GPIO_PE1, PE1_DATA),
PINMUX_GPIO(GPIO_PE0, PE0_DATA),
PINMUX_GPIO(PE5),
PINMUX_GPIO(PE4),
PINMUX_GPIO(PE3),
PINMUX_GPIO(PE2),
PINMUX_GPIO(PE1),
PINMUX_GPIO(PE0),
/* PF */
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
PINMUX_GPIO(PF7),
PINMUX_GPIO(PF6),
PINMUX_GPIO(PF5),
PINMUX_GPIO(PF4),
PINMUX_GPIO(PF3),
PINMUX_GPIO(PF2),
PINMUX_GPIO(PF1),
PINMUX_GPIO(PF0),
/* PG */
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
PINMUX_GPIO(GPIO_PG4, PG4_DATA),
PINMUX_GPIO(GPIO_PG3, PG3_DATA),
PINMUX_GPIO(GPIO_PG2, PG2_DATA),
PINMUX_GPIO(GPIO_PG1, PG1_DATA),
PINMUX_GPIO(GPIO_PG0, PG0_DATA),
PINMUX_GPIO(PG7),
PINMUX_GPIO(PG6),
PINMUX_GPIO(PG5),
PINMUX_GPIO(PG4),
PINMUX_GPIO(PG3),
PINMUX_GPIO(PG2),
PINMUX_GPIO(PG1),
PINMUX_GPIO(PG0),
/* PH */
PINMUX_GPIO(GPIO_PH7, PH7_DATA),
PINMUX_GPIO(GPIO_PH6, PH6_DATA),
PINMUX_GPIO(GPIO_PH5, PH5_DATA),
PINMUX_GPIO(GPIO_PH4, PH4_DATA),
PINMUX_GPIO(GPIO_PH3, PH3_DATA),
PINMUX_GPIO(GPIO_PH2, PH2_DATA),
PINMUX_GPIO(GPIO_PH1, PH1_DATA),
PINMUX_GPIO(GPIO_PH0, PH0_DATA),
PINMUX_GPIO(PH7),
PINMUX_GPIO(PH6),
PINMUX_GPIO(PH5),
PINMUX_GPIO(PH4),
PINMUX_GPIO(PH3),
PINMUX_GPIO(PH2),
PINMUX_GPIO(PH1),
PINMUX_GPIO(PH0),
/* PJ */
PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
PINMUX_GPIO(PJ7),
PINMUX_GPIO(PJ6),
PINMUX_GPIO(PJ5),
PINMUX_GPIO(PJ4),
PINMUX_GPIO(PJ3),
PINMUX_GPIO(PJ2),
PINMUX_GPIO(PJ1),
PINMUX_GPIO(PJ0),
/* PK */
PINMUX_GPIO(GPIO_PK7, PK7_DATA),
PINMUX_GPIO(GPIO_PK6, PK6_DATA),
PINMUX_GPIO(GPIO_PK5, PK5_DATA),
PINMUX_GPIO(GPIO_PK4, PK4_DATA),
PINMUX_GPIO(GPIO_PK3, PK3_DATA),
PINMUX_GPIO(GPIO_PK2, PK2_DATA),
PINMUX_GPIO(GPIO_PK1, PK1_DATA),
PINMUX_GPIO(GPIO_PK0, PK0_DATA),
PINMUX_GPIO(PK7),
PINMUX_GPIO(PK6),
PINMUX_GPIO(PK5),
PINMUX_GPIO(PK4),
PINMUX_GPIO(PK3),
PINMUX_GPIO(PK2),
PINMUX_GPIO(PK1),
PINMUX_GPIO(PK0),
/* PL */
PINMUX_GPIO(GPIO_PL7, PL7_DATA),
PINMUX_GPIO(GPIO_PL6, PL6_DATA),
PINMUX_GPIO(GPIO_PL5, PL5_DATA),
PINMUX_GPIO(GPIO_PL4, PL4_DATA),
PINMUX_GPIO(GPIO_PL3, PL3_DATA),
PINMUX_GPIO(GPIO_PL2, PL2_DATA),
PINMUX_GPIO(GPIO_PL1, PL1_DATA),
PINMUX_GPIO(GPIO_PL0, PL0_DATA),
PINMUX_GPIO(PL7),
PINMUX_GPIO(PL6),
PINMUX_GPIO(PL5),
PINMUX_GPIO(PL4),
PINMUX_GPIO(PL3),
PINMUX_GPIO(PL2),
PINMUX_GPIO(PL1),
PINMUX_GPIO(PL0),
/* PM */
PINMUX_GPIO(GPIO_PM1, PM1_DATA),
PINMUX_GPIO(GPIO_PM0, PM0_DATA),
PINMUX_GPIO(PM1),
PINMUX_GPIO(PM0),
/* PN */
PINMUX_GPIO(GPIO_PN7, PN7_DATA),
PINMUX_GPIO(GPIO_PN6, PN6_DATA),
PINMUX_GPIO(GPIO_PN5, PN5_DATA),
PINMUX_GPIO(GPIO_PN4, PN4_DATA),
PINMUX_GPIO(GPIO_PN3, PN3_DATA),
PINMUX_GPIO(GPIO_PN2, PN2_DATA),
PINMUX_GPIO(GPIO_PN1, PN1_DATA),
PINMUX_GPIO(GPIO_PN0, PN0_DATA),
PINMUX_GPIO(PN7),
PINMUX_GPIO(PN6),
PINMUX_GPIO(PN5),
PINMUX_GPIO(PN4),
PINMUX_GPIO(PN3),
PINMUX_GPIO(PN2),
PINMUX_GPIO(PN1),
PINMUX_GPIO(PN0),
/* PP */
PINMUX_GPIO(GPIO_PP5, PP5_DATA),
PINMUX_GPIO(GPIO_PP4, PP4_DATA),
PINMUX_GPIO(GPIO_PP3, PP3_DATA),
PINMUX_GPIO(GPIO_PP2, PP2_DATA),
PINMUX_GPIO(GPIO_PP1, PP1_DATA),
PINMUX_GPIO(GPIO_PP0, PP0_DATA),
PINMUX_GPIO(PP5),
PINMUX_GPIO(PP4),
PINMUX_GPIO(PP3),
PINMUX_GPIO(PP2),
PINMUX_GPIO(PP1),
PINMUX_GPIO(PP0),
/* PQ */
PINMUX_GPIO(GPIO_PQ4, PQ4_DATA),
PINMUX_GPIO(GPIO_PQ3, PQ3_DATA),
PINMUX_GPIO(GPIO_PQ2, PQ2_DATA),
PINMUX_GPIO(GPIO_PQ1, PQ1_DATA),
PINMUX_GPIO(GPIO_PQ0, PQ0_DATA),
PINMUX_GPIO(PQ4),
PINMUX_GPIO(PQ3),
PINMUX_GPIO(PQ2),
PINMUX_GPIO(PQ1),
PINMUX_GPIO(PQ0),
/* PR */
PINMUX_GPIO(GPIO_PR3, PR3_DATA),
PINMUX_GPIO(GPIO_PR2, PR2_DATA),
PINMUX_GPIO(GPIO_PR1, PR1_DATA),
PINMUX_GPIO(GPIO_PR0, PR0_DATA),
PINMUX_GPIO(PR3),
PINMUX_GPIO(PR2),
PINMUX_GPIO(PR1),
PINMUX_GPIO(PR0),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
@ -1020,114 +989,114 @@ static const struct pinmux_func pinmux_func_gpios[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) {
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
PA7_FN, PA7_OUT, PA7_IN, 0,
PA6_FN, PA6_OUT, PA6_IN, 0,
PA5_FN, PA5_OUT, PA5_IN, 0,
PA4_FN, PA4_OUT, PA4_IN, 0,
PA3_FN, PA3_OUT, PA3_IN, 0,
PA2_FN, PA2_OUT, PA2_IN, 0,
PA1_FN, PA1_OUT, PA1_IN, 0,
PA0_FN, PA0_OUT, PA0_IN, 0 }
},
{ PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2) {
PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
PB7_FN, PB7_OUT, PB7_IN, 0,
PB6_FN, PB6_OUT, PB6_IN, 0,
PB5_FN, PB5_OUT, PB5_IN, 0,
PB4_FN, PB4_OUT, PB4_IN, 0,
PB3_FN, PB3_OUT, PB3_IN, 0,
PB2_FN, PB2_OUT, PB2_IN, 0,
PB1_FN, PB1_OUT, PB1_IN, 0,
PB0_FN, PB0_OUT, PB0_IN, 0 }
},
{ PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2) {
PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
PC7_FN, PC7_OUT, PC7_IN, 0,
PC6_FN, PC6_OUT, PC6_IN, 0,
PC5_FN, PC5_OUT, PC5_IN, 0,
PC4_FN, PC4_OUT, PC4_IN, 0,
PC3_FN, PC3_OUT, PC3_IN, 0,
PC2_FN, PC2_OUT, PC2_IN, 0,
PC1_FN, PC1_OUT, PC1_IN, 0,
PC0_FN, PC0_OUT, PC0_IN, 0 }
},
{ PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2) {
PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
PD7_FN, PD7_OUT, PD7_IN, 0,
PD6_FN, PD6_OUT, PD6_IN, 0,
PD5_FN, PD5_OUT, PD5_IN, 0,
PD4_FN, PD4_OUT, PD4_IN, 0,
PD3_FN, PD3_OUT, PD3_IN, 0,
PD2_FN, PD2_OUT, PD2_IN, 0,
PD1_FN, PD1_OUT, PD1_IN, 0,
PD0_FN, PD0_OUT, PD0_IN, 0 }
},
{ PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU,
PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU,
PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU,
PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU,
PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU,
PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU }
PE5_FN, PE5_OUT, PE5_IN, 0,
PE4_FN, PE4_OUT, PE4_IN, 0,
PE3_FN, PE3_OUT, PE3_IN, 0,
PE2_FN, PE2_OUT, PE2_IN, 0,
PE1_FN, PE1_OUT, PE1_IN, 0,
PE0_FN, PE0_OUT, PE0_IN, 0 }
},
{ PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2) {
PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
PF7_FN, PF7_OUT, PF7_IN, 0,
PF6_FN, PF6_OUT, PF6_IN, 0,
PF5_FN, PF5_OUT, PF5_IN, 0,
PF4_FN, PF4_OUT, PF4_IN, 0,
PF3_FN, PF3_OUT, PF3_IN, 0,
PF2_FN, PF2_OUT, PF2_IN, 0,
PF1_FN, PF1_OUT, PF1_IN, 0,
PF0_FN, PF0_OUT, PF0_IN, 0 }
},
{ PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2) {
PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU,
PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU,
PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU,
PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU,
PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU }
PG7_FN, PG7_OUT, PG7_IN, 0,
PG6_FN, PG6_OUT, PG6_IN, 0,
PG5_FN, PG5_OUT, PG5_IN, 0,
PG4_FN, PG4_OUT, PG4_IN, 0,
PG3_FN, PG3_OUT, PG3_IN, 0,
PG2_FN, PG2_OUT, PG2_IN, 0,
PG1_FN, PG1_OUT, PG1_IN, 0,
PG0_FN, PG0_OUT, PG0_IN, 0 }
},
{ PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2) {
PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
PH7_FN, PH7_OUT, PH7_IN, 0,
PH6_FN, PH6_OUT, PH6_IN, 0,
PH5_FN, PH5_OUT, PH5_IN, 0,
PH4_FN, PH4_OUT, PH4_IN, 0,
PH3_FN, PH3_OUT, PH3_IN, 0,
PH2_FN, PH2_OUT, PH2_IN, 0,
PH1_FN, PH1_OUT, PH1_IN, 0,
PH0_FN, PH0_OUT, PH0_IN, 0 }
},
{ PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2) {
PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
PJ0_FN, PJ0_OUT, PJ0_IN, PJ0_IN_PU }
PJ7_FN, PJ7_OUT, PJ7_IN, 0,
PJ6_FN, PJ6_OUT, PJ6_IN, 0,
PJ5_FN, PJ5_OUT, PJ5_IN, 0,
PJ4_FN, PJ4_OUT, PJ4_IN, 0,
PJ3_FN, PJ3_OUT, PJ3_IN, 0,
PJ2_FN, PJ2_OUT, PJ2_IN, 0,
PJ1_FN, PJ1_OUT, PJ1_IN, 0,
PJ0_FN, PJ0_OUT, PJ0_IN, 0 }
},
{ PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2) {
PK7_FN, PK7_OUT, PK7_IN, PK7_IN_PU,
PK6_FN, PK6_OUT, PK6_IN, PK6_IN_PU,
PK5_FN, PK5_OUT, PK5_IN, PK5_IN_PU,
PK4_FN, PK4_OUT, PK4_IN, PK4_IN_PU,
PK3_FN, PK3_OUT, PK3_IN, PK3_IN_PU,
PK2_FN, PK2_OUT, PK2_IN, PK2_IN_PU,
PK1_FN, PK1_OUT, PK1_IN, PK1_IN_PU,
PK0_FN, PK0_OUT, PK0_IN, PK0_IN_PU }
PK7_FN, PK7_OUT, PK7_IN, 0,
PK6_FN, PK6_OUT, PK6_IN, 0,
PK5_FN, PK5_OUT, PK5_IN, 0,
PK4_FN, PK4_OUT, PK4_IN, 0,
PK3_FN, PK3_OUT, PK3_IN, 0,
PK2_FN, PK2_OUT, PK2_IN, 0,
PK1_FN, PK1_OUT, PK1_IN, 0,
PK0_FN, PK0_OUT, PK0_IN, 0 }
},
{ PINMUX_CFG_REG("PLCR", 0xffe70014, 16, 2) {
PL7_FN, PL7_OUT, PL7_IN, PL7_IN_PU,
PL6_FN, PL6_OUT, PL6_IN, PL6_IN_PU,
PL5_FN, PL5_OUT, PL5_IN, PL5_IN_PU,
PL4_FN, PL4_OUT, PL4_IN, PL4_IN_PU,
PL3_FN, PL3_OUT, PL3_IN, PL3_IN_PU,
PL2_FN, PL2_OUT, PL2_IN, PL2_IN_PU,
PL1_FN, PL1_OUT, PL1_IN, PL1_IN_PU,
PL0_FN, PL0_OUT, PL0_IN, PL0_IN_PU }
PL7_FN, PL7_OUT, PL7_IN, 0,
PL6_FN, PL6_OUT, PL6_IN, 0,
PL5_FN, PL5_OUT, PL5_IN, 0,
PL4_FN, PL4_OUT, PL4_IN, 0,
PL3_FN, PL3_OUT, PL3_IN, 0,
PL2_FN, PL2_OUT, PL2_IN, 0,
PL1_FN, PL1_OUT, PL1_IN, 0,
PL0_FN, PL0_OUT, PL0_IN, 0 }
},
{ PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2) {
0, 0, 0, 0,
@ -1136,48 +1105,48 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
PM1_FN, PM1_OUT, PM1_IN, PM1_IN_PU,
PM0_FN, PM0_OUT, PM0_IN, PM0_IN_PU }
PM1_FN, PM1_OUT, PM1_IN, 0,
PM0_FN, PM0_OUT, PM0_IN, 0 }
},
{ PINMUX_CFG_REG("PNCR", 0xffe70018, 16, 2) {
PN7_FN, PN7_OUT, PN7_IN, PN7_IN_PU,
PN6_FN, PN6_OUT, PN6_IN, PN6_IN_PU,
PN5_FN, PN5_OUT, PN5_IN, PN5_IN_PU,
PN4_FN, PN4_OUT, PN4_IN, PN4_IN_PU,
PN3_FN, PN3_OUT, PN3_IN, PN3_IN_PU,
PN2_FN, PN2_OUT, PN2_IN, PN2_IN_PU,
PN1_FN, PN1_OUT, PN1_IN, PN1_IN_PU,
PN0_FN, PN0_OUT, PN0_IN, PN0_IN_PU }
PN7_FN, PN7_OUT, PN7_IN, 0,
PN6_FN, PN6_OUT, PN6_IN, 0,
PN5_FN, PN5_OUT, PN5_IN, 0,
PN4_FN, PN4_OUT, PN4_IN, 0,
PN3_FN, PN3_OUT, PN3_IN, 0,
PN2_FN, PN2_OUT, PN2_IN, 0,
PN1_FN, PN1_OUT, PN1_IN, 0,
PN0_FN, PN0_OUT, PN0_IN, 0 }
},
{ PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
PP5_FN, PP5_OUT, PP5_IN, PP5_IN_PU,
PP4_FN, PP4_OUT, PP4_IN, PP4_IN_PU,
PP3_FN, PP3_OUT, PP3_IN, PP3_IN_PU,
PP2_FN, PP2_OUT, PP2_IN, PP2_IN_PU,
PP1_FN, PP1_OUT, PP1_IN, PP1_IN_PU,
PP0_FN, PP0_OUT, PP0_IN, PP0_IN_PU }
PP5_FN, PP5_OUT, PP5_IN, 0,
PP4_FN, PP4_OUT, PP4_IN, 0,
PP3_FN, PP3_OUT, PP3_IN, 0,
PP2_FN, PP2_OUT, PP2_IN, 0,
PP1_FN, PP1_OUT, PP1_IN, 0,
PP0_FN, PP0_OUT, PP0_IN, 0 }
},
{ PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
PQ4_FN, PQ4_OUT, PQ4_IN, PQ4_IN_PU,
PQ3_FN, PQ3_OUT, PQ3_IN, PQ3_IN_PU,
PQ2_FN, PQ2_OUT, PQ2_IN, PQ2_IN_PU,
PQ1_FN, PQ1_OUT, PQ1_IN, PQ1_IN_PU,
PQ0_FN, PQ0_OUT, PQ0_IN, PQ0_IN_PU }
PQ4_FN, PQ4_OUT, PQ4_IN, 0,
PQ3_FN, PQ3_OUT, PQ3_IN, 0,
PQ2_FN, PQ2_OUT, PQ2_IN, 0,
PQ1_FN, PQ1_OUT, PQ1_IN, 0,
PQ0_FN, PQ0_OUT, PQ0_IN, 0 }
},
{ PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
PR3_FN, PR3_OUT, PR3_IN, PR3_IN_PU,
PR2_FN, PR2_OUT, PR2_IN, PR2_IN_PU,
PR1_FN, PR1_OUT, PR1_IN, PR1_IN_PU,
PR0_FN, PR0_OUT, PR0_IN, PR0_IN_PU }
PR3_FN, PR3_OUT, PR3_IN, 0,
PR2_FN, PR2_OUT, PR2_IN, 0,
PR1_FN, PR1_OUT, PR1_IN, 0,
PR0_FN, PR0_OUT, PR0_IN, 0 }
},
{ PINMUX_CFG_REG("P1MSELR", 0xffe70080, 16, 1) {
P1MSEL15_0, P1MSEL15_1,
@ -1289,7 +1258,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
const struct sh_pfc_soc_info sh7785_pinmux_info = {
.name = "sh7785_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

383
drivers/pinctrl/sh-pfc/pfc-sh7786.c
View File

@ -60,25 +60,6 @@ enum {
PJ3_IN, PJ2_IN, PJ1_IN,
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
PE7_IN_PU, PE6_IN_PU,
PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
PG7_IN_PU, PG6_IN_PU, PG5_IN_PU,
PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU,
PINMUX_INPUT_PULLUP_END,
PINMUX_OUTPUT_BEGIN,
PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
@ -191,85 +172,84 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* PA GPIO */
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT),
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT),
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT),
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT),
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT),
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT),
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT),
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT),
/* PB GPIO */
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT),
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT),
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT),
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT),
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT),
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT),
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT),
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT),
/* PC GPIO */
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT),
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT),
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT),
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT),
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT),
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT),
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT),
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT),
/* PD GPIO */
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT),
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT),
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT),
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT),
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT),
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT),
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT),
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT),
/* PE GPIO */
PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT),
PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT),
/* PF GPIO */
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT),
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT),
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT),
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT),
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT),
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT),
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT),
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT),
/* PG GPIO */
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT),
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT),
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT),
/* PH GPIO */
PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT),
PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT),
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT),
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT),
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT),
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT),
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT),
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT),
/* PJ GPIO */
PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT),
PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT),
PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT),
PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT),
PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT),
PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT),
PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT),
/* PA FN */
PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN),
@ -429,82 +409,82 @@ static const pinmux_enum_t pinmux_data[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
PINMUX_GPIO(GPIO_PA5, PA5_DATA),
PINMUX_GPIO(GPIO_PA4, PA4_DATA),
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
PINMUX_GPIO(PA7),
PINMUX_GPIO(PA6),
PINMUX_GPIO(PA5),
PINMUX_GPIO(PA4),
PINMUX_GPIO(PA3),
PINMUX_GPIO(PA2),
PINMUX_GPIO(PA1),
PINMUX_GPIO(PA0),
/* PB */
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
PINMUX_GPIO(GPIO_PB0, PB0_DATA),
PINMUX_GPIO(PB7),
PINMUX_GPIO(PB6),
PINMUX_GPIO(PB5),
PINMUX_GPIO(PB4),
PINMUX_GPIO(PB3),
PINMUX_GPIO(PB2),
PINMUX_GPIO(PB1),
PINMUX_GPIO(PB0),
/* PC */
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
PINMUX_GPIO(PC7),
PINMUX_GPIO(PC6),
PINMUX_GPIO(PC5),
PINMUX_GPIO(PC4),
PINMUX_GPIO(PC3),
PINMUX_GPIO(PC2),
PINMUX_GPIO(PC1),
PINMUX_GPIO(PC0),
/* PD */
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
PINMUX_GPIO(PD7),
PINMUX_GPIO(PD6),
PINMUX_GPIO(PD5),
PINMUX_GPIO(PD4),
PINMUX_GPIO(PD3),
PINMUX_GPIO(PD2),
PINMUX_GPIO(PD1),
PINMUX_GPIO(PD0),
/* PE */
PINMUX_GPIO(GPIO_PE7, PE7_DATA),
PINMUX_GPIO(GPIO_PE6, PE6_DATA),
PINMUX_GPIO(PE7),
PINMUX_GPIO(PE6),
/* PF */
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
PINMUX_GPIO(PF7),
PINMUX_GPIO(PF6),
PINMUX_GPIO(PF5),
PINMUX_GPIO(PF4),
PINMUX_GPIO(PF3),
PINMUX_GPIO(PF2),
PINMUX_GPIO(PF1),
PINMUX_GPIO(PF0),
/* PG */
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
PINMUX_GPIO(PG7),
PINMUX_GPIO(PG6),
PINMUX_GPIO(PG5),
/* PH */
PINMUX_GPIO(GPIO_PH7, PH7_DATA),
PINMUX_GPIO(GPIO_PH6, PH6_DATA),
PINMUX_GPIO(GPIO_PH5, PH5_DATA),
PINMUX_GPIO(GPIO_PH4, PH4_DATA),
PINMUX_GPIO(GPIO_PH3, PH3_DATA),
PINMUX_GPIO(GPIO_PH2, PH2_DATA),
PINMUX_GPIO(GPIO_PH1, PH1_DATA),
PINMUX_GPIO(GPIO_PH0, PH0_DATA),
PINMUX_GPIO(PH7),
PINMUX_GPIO(PH6),
PINMUX_GPIO(PH5),
PINMUX_GPIO(PH4),
PINMUX_GPIO(PH3),
PINMUX_GPIO(PH2),
PINMUX_GPIO(PH1),
PINMUX_GPIO(PH0),
/* PJ */
PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
PINMUX_GPIO(PJ7),
PINMUX_GPIO(PJ6),
PINMUX_GPIO(PJ5),
PINMUX_GPIO(PJ4),
PINMUX_GPIO(PJ3),
PINMUX_GPIO(PJ2),
PINMUX_GPIO(PJ1),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
@ -651,48 +631,48 @@ static const struct pinmux_func pinmux_func_gpios[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
PA7_FN, PA7_OUT, PA7_IN, 0,
PA6_FN, PA6_OUT, PA6_IN, 0,
PA5_FN, PA5_OUT, PA5_IN, 0,
PA4_FN, PA4_OUT, PA4_IN, 0,
PA3_FN, PA3_OUT, PA3_IN, 0,
PA2_FN, PA2_OUT, PA2_IN, 0,
PA1_FN, PA1_OUT, PA1_IN, 0,
PA0_FN, PA0_OUT, PA0_IN, 0 }
},
{ PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
PB7_FN, PB7_OUT, PB7_IN, 0,
PB6_FN, PB6_OUT, PB6_IN, 0,
PB5_FN, PB5_OUT, PB5_IN, 0,
PB4_FN, PB4_OUT, PB4_IN, 0,
PB3_FN, PB3_OUT, PB3_IN, 0,
PB2_FN, PB2_OUT, PB2_IN, 0,
PB1_FN, PB1_OUT, PB1_IN, 0,
PB0_FN, PB0_OUT, PB0_IN, 0 }
},
{ PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
PC7_FN, PC7_OUT, PC7_IN, 0,
PC6_FN, PC6_OUT, PC6_IN, 0,
PC5_FN, PC5_OUT, PC5_IN, 0,
PC4_FN, PC4_OUT, PC4_IN, 0,
PC3_FN, PC3_OUT, PC3_IN, 0,
PC2_FN, PC2_OUT, PC2_IN, 0,
PC1_FN, PC1_OUT, PC1_IN, 0,
PC0_FN, PC0_OUT, PC0_IN, 0 }
},
{ PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
PD7_FN, PD7_OUT, PD7_IN, 0,
PD6_FN, PD6_OUT, PD6_IN, 0,
PD5_FN, PD5_OUT, PD5_IN, 0,
PD4_FN, PD4_OUT, PD4_IN, 0,
PD3_FN, PD3_OUT, PD3_IN, 0,
PD2_FN, PD2_OUT, PD2_IN, 0,
PD1_FN, PD1_OUT, PD1_IN, 0,
PD0_FN, PD0_OUT, PD0_IN, 0 }
},
{ PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
PE7_FN, PE7_OUT, PE7_IN, 0,
PE6_FN, PE6_OUT, PE6_IN, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -701,19 +681,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, }
},
{ PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
PF7_FN, PF7_OUT, PF7_IN, 0,
PF6_FN, PF6_OUT, PF6_IN, 0,
PF5_FN, PF5_OUT, PF5_IN, 0,
PF4_FN, PF4_OUT, PF4_IN, 0,
PF3_FN, PF3_OUT, PF3_IN, 0,
PF2_FN, PF2_OUT, PF2_IN, 0,
PF1_FN, PF1_OUT, PF1_IN, 0,
PF0_FN, PF0_OUT, PF0_IN, 0 }
},
{ PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
PG7_FN, PG7_OUT, PG7_IN, 0,
PG6_FN, PG6_OUT, PG6_IN, 0,
PG5_FN, PG5_OUT, PG5_IN, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -721,23 +701,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, }
},
{ PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
PH7_FN, PH7_OUT, PH7_IN, 0,
PH6_FN, PH6_OUT, PH6_IN, 0,
PH5_FN, PH5_OUT, PH5_IN, 0,
PH4_FN, PH4_OUT, PH4_IN, 0,
PH3_FN, PH3_OUT, PH3_IN, 0,
PH2_FN, PH2_OUT, PH2_IN, 0,
PH1_FN, PH1_OUT, PH1_IN, 0,
PH0_FN, PH0_OUT, PH0_IN, 0 }
},
{ PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
PJ7_FN, PJ7_OUT, PJ7_IN, 0,
PJ6_FN, PJ6_OUT, PJ6_IN, 0,
PJ5_FN, PJ5_OUT, PJ5_IN, 0,
PJ4_FN, PJ4_OUT, PJ4_IN, 0,
PJ3_FN, PJ3_OUT, PJ3_IN, 0,
PJ2_FN, PJ2_OUT, PJ2_IN, 0,
PJ1_FN, PJ1_OUT, PJ1_IN, 0,
0, 0, 0, 0, }
},
{ PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
@ -822,7 +802,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
const struct sh_pfc_soc_info sh7786_pinmux_info = {
.name = "sh7786_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

423
drivers/pinctrl/sh-pfc/pfc-shx3.c
View File

@ -56,26 +56,6 @@ enum {
PH3_IN, PH2_IN, PH1_IN, PH0_IN,
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
PE7_IN_PU, PE6_IN_PU, PE5_IN_PU, PE4_IN_PU,
PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU,
PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU,
PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU,
PH5_IN_PU, PH4_IN_PU,
PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
PINMUX_INPUT_PULLUP_END,
PINMUX_OUTPUT_BEGIN,
PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
@ -147,85 +127,84 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t shx3_pinmux_data[] = {
static const u16 pinmux_data[] = {
/* PA GPIO */
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT),
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT),
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT),
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT),
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT),
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT),
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT),
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT),
/* PB GPIO */
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT),
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT),
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT),
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT),
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT),
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT),
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT),
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT),
/* PC GPIO */
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT),
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT),
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT),
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT),
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT),
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT),
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT),
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT),
/* PD GPIO */
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT),
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT),
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT),
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT),
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT),
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT),
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT),
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT),
/* PE GPIO */
PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU),
PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU),
PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU),
PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU),
PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU),
PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU),
PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT),
PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT),
PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT),
PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT),
PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT),
PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT),
PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT),
PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT),
/* PF GPIO */
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT),
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT),
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT),
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT),
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT),
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT),
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT),
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT),
/* PG GPIO */
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU),
PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU),
PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU),
PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU),
PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU),
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT),
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT),
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT),
PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT),
PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT),
PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT),
PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT),
PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT),
/* PH GPIO */
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT),
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT),
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT),
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT),
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT),
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT),
/* PA FN */
PINMUX_DATA(D31_MARK, PA7_FN),
@ -306,89 +285,89 @@ static const pinmux_enum_t shx3_pinmux_data[] = {
PINMUX_DATA(IRQOUT_MARK, PH0_FN),
};
static struct sh_pfc_pin shx3_pinmux_pins[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
PINMUX_GPIO(GPIO_PA5, PA5_DATA),
PINMUX_GPIO(GPIO_PA4, PA4_DATA),
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
PINMUX_GPIO(PA7),
PINMUX_GPIO(PA6),
PINMUX_GPIO(PA5),
PINMUX_GPIO(PA4),
PINMUX_GPIO(PA3),
PINMUX_GPIO(PA2),
PINMUX_GPIO(PA1),
PINMUX_GPIO(PA0),
/* PB */
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
PINMUX_GPIO(GPIO_PB0, PB0_DATA),
PINMUX_GPIO(PB7),
PINMUX_GPIO(PB6),
PINMUX_GPIO(PB5),
PINMUX_GPIO(PB4),
PINMUX_GPIO(PB3),
PINMUX_GPIO(PB2),
PINMUX_GPIO(PB1),
PINMUX_GPIO(PB0),
/* PC */
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
PINMUX_GPIO(PC7),
PINMUX_GPIO(PC6),
PINMUX_GPIO(PC5),
PINMUX_GPIO(PC4),
PINMUX_GPIO(PC3),
PINMUX_GPIO(PC2),
PINMUX_GPIO(PC1),
PINMUX_GPIO(PC0),
/* PD */
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
PINMUX_GPIO(PD7),
PINMUX_GPIO(PD6),
PINMUX_GPIO(PD5),
PINMUX_GPIO(PD4),
PINMUX_GPIO(PD3),
PINMUX_GPIO(PD2),
PINMUX_GPIO(PD1),
PINMUX_GPIO(PD0),
/* PE */
PINMUX_GPIO(GPIO_PE7, PE7_DATA),
PINMUX_GPIO(GPIO_PE6, PE6_DATA),
PINMUX_GPIO(GPIO_PE5, PE5_DATA),
PINMUX_GPIO(GPIO_PE4, PE4_DATA),
PINMUX_GPIO(GPIO_PE3, PE3_DATA),
PINMUX_GPIO(GPIO_PE2, PE2_DATA),
PINMUX_GPIO(GPIO_PE1, PE1_DATA),
PINMUX_GPIO(GPIO_PE0, PE0_DATA),
PINMUX_GPIO(PE7),
PINMUX_GPIO(PE6),
PINMUX_GPIO(PE5),
PINMUX_GPIO(PE4),
PINMUX_GPIO(PE3),
PINMUX_GPIO(PE2),
PINMUX_GPIO(PE1),
PINMUX_GPIO(PE0),
/* PF */
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
PINMUX_GPIO(PF7),
PINMUX_GPIO(PF6),
PINMUX_GPIO(PF5),
PINMUX_GPIO(PF4),
PINMUX_GPIO(PF3),
PINMUX_GPIO(PF2),
PINMUX_GPIO(PF1),
PINMUX_GPIO(PF0),
/* PG */
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
PINMUX_GPIO(GPIO_PG4, PG4_DATA),
PINMUX_GPIO(GPIO_PG3, PG3_DATA),
PINMUX_GPIO(GPIO_PG2, PG2_DATA),
PINMUX_GPIO(GPIO_PG1, PG1_DATA),
PINMUX_GPIO(GPIO_PG0, PG0_DATA),
PINMUX_GPIO(PG7),
PINMUX_GPIO(PG6),
PINMUX_GPIO(PG5),
PINMUX_GPIO(PG4),
PINMUX_GPIO(PG3),
PINMUX_GPIO(PG2),
PINMUX_GPIO(PG1),
PINMUX_GPIO(PG0),
/* PH */
PINMUX_GPIO(GPIO_PH5, PH5_DATA),
PINMUX_GPIO(GPIO_PH4, PH4_DATA),
PINMUX_GPIO(GPIO_PH3, PH3_DATA),
PINMUX_GPIO(GPIO_PH2, PH2_DATA),
PINMUX_GPIO(GPIO_PH1, PH1_DATA),
PINMUX_GPIO(GPIO_PH0, PH0_DATA),
PINMUX_GPIO(PH5),
PINMUX_GPIO(PH4),
PINMUX_GPIO(PH3),
PINMUX_GPIO(PH2),
PINMUX_GPIO(PH1),
PINMUX_GPIO(PH0),
};
#define PINMUX_FN_BASE ARRAY_SIZE(shx3_pinmux_pins)
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func shx3_pinmux_func_gpios[] = {
static const struct pinmux_func pinmux_func_gpios[] = {
/* FN */
GPIO_FN(D31),
GPIO_FN(D30),
@ -454,83 +433,83 @@ static const struct pinmux_func shx3_pinmux_func_gpios[] = {
GPIO_FN(IRQOUT),
};
static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU,
PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU, },
PA7_FN, PA7_OUT, PA7_IN, 0,
PA6_FN, PA6_OUT, PA6_IN, 0,
PA5_FN, PA5_OUT, PA5_IN, 0,
PA4_FN, PA4_OUT, PA4_IN, 0,
PA3_FN, PA3_OUT, PA3_IN, 0,
PA2_FN, PA2_OUT, PA2_IN, 0,
PA1_FN, PA1_OUT, PA1_IN, 0,
PA0_FN, PA0_OUT, PA0_IN, 0,
PB7_FN, PB7_OUT, PB7_IN, 0,
PB6_FN, PB6_OUT, PB6_IN, 0,
PB5_FN, PB5_OUT, PB5_IN, 0,
PB4_FN, PB4_OUT, PB4_IN, 0,
PB3_FN, PB3_OUT, PB3_IN, 0,
PB2_FN, PB2_OUT, PB2_IN, 0,
PB1_FN, PB1_OUT, PB1_IN, 0,
PB0_FN, PB0_OUT, PB0_IN, 0, },
},
{ PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) {
PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU,
PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU, },
PC7_FN, PC7_OUT, PC7_IN, 0,
PC6_FN, PC6_OUT, PC6_IN, 0,
PC5_FN, PC5_OUT, PC5_IN, 0,
PC4_FN, PC4_OUT, PC4_IN, 0,
PC3_FN, PC3_OUT, PC3_IN, 0,
PC2_FN, PC2_OUT, PC2_IN, 0,
PC1_FN, PC1_OUT, PC1_IN, 0,
PC0_FN, PC0_OUT, PC0_IN, 0,
PD7_FN, PD7_OUT, PD7_IN, 0,
PD6_FN, PD6_OUT, PD6_IN, 0,
PD5_FN, PD5_OUT, PD5_IN, 0,
PD4_FN, PD4_OUT, PD4_IN, 0,
PD3_FN, PD3_OUT, PD3_IN, 0,
PD2_FN, PD2_OUT, PD2_IN, 0,
PD1_FN, PD1_OUT, PD1_IN, 0,
PD0_FN, PD0_OUT, PD0_IN, 0, },
},
{ PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) {
PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU,
PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU,
PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU,
PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU,
PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU,
PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU,
PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU, },
PE7_FN, PE7_OUT, PE7_IN, 0,
PE6_FN, PE6_OUT, PE6_IN, 0,
PE5_FN, PE5_OUT, PE5_IN, 0,
PE4_FN, PE4_OUT, PE4_IN, 0,
PE3_FN, PE3_OUT, PE3_IN, 0,
PE2_FN, PE2_OUT, PE2_IN, 0,
PE1_FN, PE1_OUT, PE1_IN, 0,
PE0_FN, PE0_OUT, PE0_IN, 0,
PF7_FN, PF7_OUT, PF7_IN, 0,
PF6_FN, PF6_OUT, PF6_IN, 0,
PF5_FN, PF5_OUT, PF5_IN, 0,
PF4_FN, PF4_OUT, PF4_IN, 0,
PF3_FN, PF3_OUT, PF3_IN, 0,
PF2_FN, PF2_OUT, PF2_IN, 0,
PF1_FN, PF1_OUT, PF1_IN, 0,
PF0_FN, PF0_OUT, PF0_IN, 0, },
},
{ PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) {
PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU,
PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU,
PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU,
PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU,
PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU,
PG7_FN, PG7_OUT, PG7_IN, 0,
PG6_FN, PG6_OUT, PG6_IN, 0,
PG5_FN, PG5_OUT, PG5_IN, 0,
PG4_FN, PG4_OUT, PG4_IN, 0,
PG3_FN, PG3_OUT, PG3_IN, 0,
PG2_FN, PG2_OUT, PG2_IN, 0,
PG1_FN, PG1_OUT, PG1_IN, 0,
PG0_FN, PG0_OUT, PG0_IN, 0,
0, 0, 0, 0,
0, 0, 0, 0,
PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU, },
PH5_FN, PH5_OUT, PH5_IN, 0,
PH4_FN, PH4_OUT, PH4_IN, 0,
PH3_FN, PH3_OUT, PH3_IN, 0,
PH2_FN, PH2_OUT, PH2_IN, 0,
PH1_FN, PH1_OUT, PH1_IN, 0,
PH0_FN, PH0_OUT, PH0_IN, 0, },
},
{ },
};
static const struct pinmux_data_reg shx3_pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
0, 0, 0, 0, 0, 0, 0, 0,
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
@ -569,16 +548,14 @@ static const struct pinmux_data_reg shx3_pinmux_data_regs[] = {
const struct sh_pfc_soc_info shx3_pinmux_info = {
.name = "shx3_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = shx3_pinmux_pins,
.nr_pins = ARRAY_SIZE(shx3_pinmux_pins),
.func_gpios = shx3_pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(shx3_pinmux_func_gpios),
.gpio_data = shx3_pinmux_data,
.gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
.cfg_regs = shx3_pinmux_config_regs,
.data_regs = shx3_pinmux_data_regs,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpio_data = pinmux_data,
.gpio_data_size = ARRAY_SIZE(pinmux_data),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
};

91
drivers/pinctrl/sh-pfc/pinctrl.c
View File

@ -529,38 +529,44 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
}
static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
unsigned long config)
unsigned long *configs, unsigned num_configs)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
enum pin_config_param param = pinconf_to_config_param(config);
enum pin_config_param param;
unsigned long flags;
unsigned int i;
if (!sh_pfc_pinconf_validate(pfc, _pin, param))
return -ENOTSUPP;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_DISABLE:
if (!pfc->info->ops || !pfc->info->ops->set_bias)
if (!sh_pfc_pinconf_validate(pfc, _pin, param))
return -ENOTSUPP;
spin_lock_irqsave(&pfc->lock, flags);
pfc->info->ops->set_bias(pfc, _pin, param);
spin_unlock_irqrestore(&pfc->lock, flags);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_DISABLE:
if (!pfc->info->ops || !pfc->info->ops->set_bias)
return -ENOTSUPP;
break;
spin_lock_irqsave(&pfc->lock, flags);
pfc->info->ops->set_bias(pfc, _pin, param);
spin_unlock_irqrestore(&pfc->lock, flags);
default:
return -ENOTSUPP;
}
break;
default:
return -ENOTSUPP;
}
} /* for each config */
return 0;
}
static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
unsigned long config)
unsigned long *configs,
unsigned num_configs)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
const unsigned int *pins;
@ -571,7 +577,7 @@ static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
num_pins = pmx->pfc->info->groups[group].nr_pins;
for (i = 0; i < num_pins; ++i)
sh_pfc_pinconf_set(pctldev, pins[i], config);
sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
return 0;
}
@ -587,22 +593,9 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = {
/* PFC ranges -> pinctrl pin descs */
static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
const struct pinmux_range *ranges;
struct pinmux_range def_range;
unsigned int nr_ranges;
unsigned int nr_pins;
unsigned int i;
if (pfc->info->ranges == NULL) {
def_range.begin = 0;
def_range.end = pfc->info->nr_pins - 1;
ranges = &def_range;
nr_ranges = 1;
} else {
ranges = pfc->info->ranges;
nr_ranges = pfc->info->nr_ranges;
}
/* Allocate and initialize the pins and configs arrays. */
pmx->pins = devm_kzalloc(pfc->dev,
sizeof(*pmx->pins) * pfc->info->nr_pins,
GFP_KERNEL);
@ -615,32 +608,24 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
if (unlikely(!pmx->configs))
return -ENOMEM;
for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
const struct pinmux_range *range = &ranges[i];
unsigned int number;
for (i = 0; i < pfc->info->nr_pins; ++i) {
const struct sh_pfc_pin *info = &pfc->info->pins[i];
struct sh_pfc_pin_config *cfg = &pmx->configs[i];
struct pinctrl_pin_desc *pin = &pmx->pins[i];
for (number = range->begin; number <= range->end;
number++, nr_pins++) {
struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
const struct sh_pfc_pin *info =
&pfc->info->pins[nr_pins];
pin->number = number;
pin->name = info->name;
cfg->type = PINMUX_TYPE_NONE;
}
/* If the pin number is equal to -1 all pins are considered */
pin->number = info->pin != (u16)-1 ? info->pin : i;
pin->name = info->name;
cfg->type = PINMUX_TYPE_NONE;
}
pfc->nr_pins = ranges[nr_ranges-1].end + 1;
return nr_ranges;
return 0;
}
int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
{
struct sh_pfc_pinctrl *pmx;
int nr_ranges;
int ret;
pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
if (unlikely(!pmx))
@ -649,9 +634,9 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
pmx->pfc = pfc;
pfc->pinctrl = pmx;
nr_ranges = sh_pfc_map_pins(pfc, pmx);
if (unlikely(nr_ranges < 0))
return nr_ranges;
ret = sh_pfc_map_pins(pfc, pmx);
if (ret < 0)
return ret;
pmx->pctl_desc.name = DRV_NAME;
pmx->pctl_desc.owner = THIS_MODULE;

243
drivers/pinctrl/sh-pfc/sh_pfc.h
View File

@ -14,30 +14,23 @@
#include <linux/bug.h>
#include <linux/stringify.h>
typedef unsigned short pinmux_enum_t;
#define SH_PFC_MARK_INVALID ((pinmux_enum_t)-1)
enum {
PINMUX_TYPE_NONE,
PINMUX_TYPE_FUNCTION,
PINMUX_TYPE_GPIO,
PINMUX_TYPE_OUTPUT,
PINMUX_TYPE_INPUT,
PINMUX_TYPE_INPUT_PULLUP,
PINMUX_TYPE_INPUT_PULLDOWN,
PINMUX_FLAG_TYPE, /* must be last */
};
#define SH_PFC_PIN_CFG_INPUT (1 << 0)
#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
struct sh_pfc_pin {
const pinmux_enum_t enum_id;
u16 pin;
u16 enum_id;
const char *name;
unsigned int configs;
};
@ -71,46 +64,33 @@ struct sh_pfc_function {
};
struct pinmux_func {
const pinmux_enum_t enum_id;
u16 enum_id;
const char *name;
};
#define PINMUX_GPIO(gpio, data_or_mark) \
[gpio] = { \
.name = __stringify(gpio), \
.enum_id = data_or_mark, \
}
#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
[gpio - (base)] = { \
.name = __stringify(gpio), \
.enum_id = data_or_mark, \
}
#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
struct pinmux_cfg_reg {
unsigned long reg, reg_width, field_width;
const pinmux_enum_t *enum_ids;
const u16 *enum_ids;
const unsigned long *var_field_width;
};
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
.reg = r, .reg_width = r_width, .field_width = f_width, \
.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
.enum_ids = (u16 [(r_width / f_width) * (1 << f_width)])
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
.reg = r, .reg_width = r_width, \
.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
.enum_ids = (pinmux_enum_t [])
.enum_ids = (u16 [])
struct pinmux_data_reg {
unsigned long reg, reg_width;
const pinmux_enum_t *enum_ids;
const u16 *enum_ids;
};
#define PINMUX_DATA_REG(name, r, r_width) \
.reg = r, .reg_width = r_width, \
.enum_ids = (pinmux_enum_t [r_width]) \
.enum_ids = (u16 [r_width]) \
struct pinmux_irq {
int irq;
@ -121,9 +101,9 @@ struct pinmux_irq {
{ .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \
struct pinmux_range {
pinmux_enum_t begin;
pinmux_enum_t end;
pinmux_enum_t force;
u16 begin;
u16 end;
u16 force;
};
struct sh_pfc;
@ -141,15 +121,11 @@ struct sh_pfc_soc_info {
const struct sh_pfc_soc_operations *ops;
struct pinmux_range input;
struct pinmux_range input_pd;
struct pinmux_range input_pu;
struct pinmux_range output;
struct pinmux_range function;
const struct sh_pfc_pin *pins;
unsigned int nr_pins;
const struct pinmux_range *ranges;
unsigned int nr_ranges;
const struct sh_pfc_pin_group *groups;
unsigned int nr_groups;
const struct sh_pfc_function *functions;
@ -161,7 +137,7 @@ struct sh_pfc_soc_info {
const struct pinmux_cfg_reg *cfg_regs;
const struct pinmux_data_reg *data_regs;
const pinmux_enum_t *gpio_data;
const u16 *gpio_data;
unsigned int gpio_data_size;
const struct pinmux_irq *gpio_irq;
@ -170,84 +146,155 @@ struct sh_pfc_soc_info {
unsigned long unlock_reg;
};
enum { GPIO_CFG_REQ, GPIO_CFG_FREE };
/* -----------------------------------------------------------------------------
* Helper macros to create pin and port lists
*/
/* helper macro for port */
#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
/*
* sh_pfc_soc_info gpio_data array macros
*/
#define PORT_10(fn, pfx, sfx) \
PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
#define PORT_10_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
#define PINMUX_IPSR_NOGP(ispr, fn) \
PINMUX_DATA(fn##_MARK, FN_##fn)
#define PINMUX_IPSR_DATA(ipsr, fn) \
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
#define PINMUX_IPSR_NOGM(ispr, fn, ms) \
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \
PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
#define PORT_32(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_1(fn, pfx##31, sfx)
/*
* GP port style (32 ports banks)
*/
#define PORT_32_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
PORT_10_REV(fn, pfx, sfx)
#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
#define PORT_90(fn, pfx, sfx) \
PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \
PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \
PORT_10(fn, pfx##9, sfx)
#define PORT_GP_32(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
#define _PORT_ALL(pfx, sfx) pfx##_##sfx
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
#define PORT_GP_32_REV(bank, fn, sfx) \
PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
/* helper macro for pinmux_enum_t */
#define PORT_DATA_I(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
#define _GP_ALL(bank, pin, name, sfx) name##_##sfx
#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
#define PORT_DATA_I_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PD)
/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
#define _GP_GPIO(bank, _pin, _name, sfx) \
[(bank * 32) + _pin] = { \
.pin = (bank * 32) + _pin, \
.name = __stringify(_name), \
.enum_id = _name##_DATA, \
}
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
#define PORT_DATA_I_PU(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PU)
/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
#define _GP_DATA(bank, pin, name, sfx) PINMUX_DATA(name##_DATA, name##_FN)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
#define PORT_DATA_I_PU_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
/*
* PORT style (linear pin space)
*/
#define PORT_DATA_O(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
#define PORT_DATA_IO(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN)
#define PORT_10(pn, fn, pfx, sfx) \
PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
#define PORT_DATA_IO_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN, PORT##nr##_IN_PD)
#define PORT_90(pn, fn, pfx, sfx) \
PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
PORT_10(pn+90, fn, pfx##9, sfx)
#define PORT_DATA_IO_PU(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN, PORT##nr##_IN_PU)
/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
#define PORT_DATA_IO_PU_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
#define PINMUX_GPIO(_pin) \
[GPIO_##_pin] = { \
.pin = (u16)-1, \
.name = __stringify(name), \
.enum_id = _pin##_DATA, \
}
/* helper macro for top 4 bits in PORTnCR */
/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
#define SH_PFC_PIN_CFG(_pin, cfgs) \
{ \
.pin = _pin, \
.name = __stringify(PORT##_pin), \
.enum_id = PORT##_pin##_DATA, \
.configs = cfgs, \
}
/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
#define SH_PFC_PIN_NAMED(row, col, _name) \
{ \
.pin = PIN_NUMBER(row, col), \
.name = __stringify(PIN_##_name), \
.configs = SH_PFC_PIN_CFG_NO_GPIO, \
}
/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
* PORT_name_OUT, PORT_name_IN marks
*/
#define _PORT_DATA(pn, pfx, sfx) \
PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
PORT##pfx##_OUT, PORT##pfx##_IN)
#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
[gpio - (base)] = { \
.name = __stringify(gpio), \
.enum_id = data_or_mark, \
}
#define GPIO_FN(str) \
PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
/*
* PORTnCR macro
*/
#define _PCRH(in, in_pd, in_pu, out) \
0, (out), (in), 0, \
0, 0, 0, 0, \

4
drivers/pinctrl/sirf/pinctrl-atlas6.c
View File

@ -831,6 +831,7 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
@ -874,6 +875,7 @@ static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
static const char * const lcdromgrp[] = { "lcdromgrp" };
static const char * const uart0grp[] = { "uart0grp" };
static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
static const char * const uart1grp[] = { "uart1grp" };
static const char * const uart2grp[] = { "uart2grp" };
static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
@ -917,6 +919,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp,
uart0_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),

10
drivers/pinctrl/sirf/pinctrl-sirf.c
View File

@ -306,13 +306,13 @@ static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
u32 *flags)
{
if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
return -EINVAL;
return -EINVAL;
if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc)
return -EINVAL;
return -EINVAL;
if (flags)
*flags = gpiospec->args[1];
*flags = gpiospec->args[1];
return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE;
}
@ -440,6 +440,8 @@ static int sirfsoc_pinmux_resume_noirq(struct device *dev)
static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
.suspend_noirq = sirfsoc_pinmux_suspend_noirq,
.resume_noirq = sirfsoc_pinmux_resume_noirq,
.freeze_noirq = sirfsoc_pinmux_suspend_noirq,
.restore_noirq = sirfsoc_pinmux_resume_noirq,
};
#endif
@ -831,7 +833,7 @@ static int sirfsoc_gpio_probe(struct device_node *np)
{
int i, err = 0;
struct sirfsoc_gpio_bank *bank;
void *regs;
void __iomem *regs;
struct platform_device *pdev;
bool is_marco = false;

13
drivers/pinctrl/spear/pinctrl-spear.c
View File

@ -367,21 +367,16 @@ int spear_pinctrl_probe(struct platform_device *pdev,
if (!machdata)
return -ENODEV;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -EINVAL;
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
if (!pmx) {
dev_err(&pdev->dev, "Can't alloc spear_pmx\n");
return -ENOMEM;
}
pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (!pmx->vbase) {
dev_err(&pdev->dev, "Couldn't ioremap at index 0\n");
return -ENODEV;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pmx->vbase = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pmx->vbase))
return PTR_ERR(pmx->vbase);
pmx->dev = &pdev->dev;
pmx->machdata = machdata;

2
drivers/pinctrl/spear/pinctrl-spear310.c
View File

@ -430,4 +430,4 @@ module_exit(spear310_pinctrl_exit);
MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match);
MODULE_DEVICE_TABLE(of, spear310_pinctrl_of_match);

54
drivers/pinctrl/vt8500/pinctrl-wmt.c
View File

@ -424,15 +424,16 @@ static int wmt_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
}
static int wmt_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long config)
unsigned long *configs, unsigned num_configs)
{
struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(config);
u16 arg = pinconf_to_config_argument(config);
enum pin_config_param param;
u16 arg;
u32 bank = WMT_BANK_FROM_PIN(pin);
u32 bit = WMT_BIT_FROM_PIN(pin);
u32 reg_pull_en = data->banks[bank].reg_pull_en;
u32 reg_pull_cfg = data->banks[bank].reg_pull_cfg;
int i;
if ((reg_pull_en == NO_REG) || (reg_pull_cfg == NO_REG)) {
dev_err(data->dev, "bias functions not supported on pin %d\n",
@ -440,28 +441,33 @@ static int wmt_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
return -EINVAL;
}
if ((param == PIN_CONFIG_BIAS_PULL_DOWN) ||
(param == PIN_CONFIG_BIAS_PULL_UP)) {
if (arg == 0)
param = PIN_CONFIG_BIAS_DISABLE;
}
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
wmt_clearbits(data, reg_pull_en, BIT(bit));
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
wmt_clearbits(data, reg_pull_cfg, BIT(bit));
wmt_setbits(data, reg_pull_en, BIT(bit));
break;
case PIN_CONFIG_BIAS_PULL_UP:
wmt_setbits(data, reg_pull_cfg, BIT(bit));
wmt_setbits(data, reg_pull_en, BIT(bit));
break;
default:
dev_err(data->dev, "unknown pinconf param\n");
return -EINVAL;
}
if ((param == PIN_CONFIG_BIAS_PULL_DOWN) ||
(param == PIN_CONFIG_BIAS_PULL_UP)) {
if (arg == 0)
param = PIN_CONFIG_BIAS_DISABLE;
}
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
wmt_clearbits(data, reg_pull_en, BIT(bit));
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
wmt_clearbits(data, reg_pull_cfg, BIT(bit));
wmt_setbits(data, reg_pull_en, BIT(bit));
break;
case PIN_CONFIG_BIAS_PULL_UP:
wmt_setbits(data, reg_pull_cfg, BIT(bit));
wmt_setbits(data, reg_pull_en, BIT(bit));
break;
default:
dev_err(data->dev, "unknown pinconf param\n");
return -EINVAL;
}
} /* for each config */
return 0;
}

35
include/linux/mfd/palmas.h
View File

@ -448,7 +448,7 @@ enum usb_irq_events {
#define PALMAS_DVFS_BASE 0x180
#define PALMAS_PMU_CONTROL_BASE 0x1A0
#define PALMAS_RESOURCE_BASE 0x1D4
#define PALMAS_PU_PD_OD_BASE 0x1F4
#define PALMAS_PU_PD_OD_BASE 0x1F0
#define PALMAS_LED_BASE 0x200
#define PALMAS_INTERRUPT_BASE 0x210
#define PALMAS_USB_OTG_BASE 0x250
@ -1733,16 +1733,20 @@ enum usb_irq_events {
#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0
/* Registers for function PAD_CONTROL */
#define PALMAS_PU_PD_INPUT_CTRL1 0x0
#define PALMAS_PU_PD_INPUT_CTRL2 0x1
#define PALMAS_PU_PD_INPUT_CTRL3 0x2
#define PALMAS_OD_OUTPUT_CTRL 0x4
#define PALMAS_POLARITY_CTRL 0x5
#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6
#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7
#define PALMAS_I2C_SPI 0x8
#define PALMAS_PU_PD_INPUT_CTRL4 0x9
#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA
#define PALMAS_OD_OUTPUT_CTRL2 0x2
#define PALMAS_POLARITY_CTRL2 0x3
#define PALMAS_PU_PD_INPUT_CTRL1 0x4
#define PALMAS_PU_PD_INPUT_CTRL2 0x5
#define PALMAS_PU_PD_INPUT_CTRL3 0x6
#define PALMAS_PU_PD_INPUT_CTRL5 0x7
#define PALMAS_OD_OUTPUT_CTRL 0x8
#define PALMAS_POLARITY_CTRL 0x9
#define PALMAS_PRIMARY_SECONDARY_PAD1 0xA
#define PALMAS_PRIMARY_SECONDARY_PAD2 0xB
#define PALMAS_I2C_SPI 0xC
#define PALMAS_PU_PD_INPUT_CTRL4 0xD
#define PALMAS_PRIMARY_SECONDARY_PAD3 0xE
#define PALMAS_PRIMARY_SECONDARY_PAD4 0xF
/* Bit definitions for PU_PD_INPUT_CTRL1 */
#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
@ -2500,6 +2504,15 @@ enum usb_irq_events {
#define PALMAS_PU_PD_GPIO_CTRL1 0x6
#define PALMAS_PU_PD_GPIO_CTRL2 0x7
#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8
#define PALMAS_GPIO_DATA_IN2 0x9
#define PALMAS_GPIO_DATA_DIR2 0x0A
#define PALMAS_GPIO_DATA_OUT2 0x0B
#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
#define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
#define PALMAS_GPIO_SET_DATA_OUT2 0x0E
#define PALMAS_PU_PD_GPIO_CTRL3 0x0F
#define PALMAS_PU_PD_GPIO_CTRL4 0x10
#define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
/* Bit definitions for GPIO_DATA_IN */
#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80

33
include/linux/pinctrl/pinconf-generic.h
View File

@ -137,6 +137,39 @@ static inline unsigned long pinconf_to_config_packed(enum pin_config_param param
return PIN_CONF_PACKED(param, argument);
}
#ifdef CONFIG_OF
#include <linux/device.h>
#include <linux/pinctrl/machine.h>
struct pinctrl_dev;
struct pinctrl_map;
int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *np, struct pinctrl_map **map,
unsigned *reserved_maps, unsigned *num_maps,
enum pinctrl_map_type type);
int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config, struct pinctrl_map **map,
unsigned *num_maps, enum pinctrl_map_type type);
static inline int pinconf_generic_dt_node_to_map_group(
struct pinctrl_dev *pctldev, struct device_node *np_config,
struct pinctrl_map **map, unsigned *num_maps)
{
return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps,
PIN_MAP_TYPE_CONFIGS_GROUP);
}
static inline int pinconf_generic_dt_node_to_map_pin(
struct pinctrl_dev *pctldev, struct device_node *np_config,
struct pinctrl_map **map, unsigned *num_maps)
{
return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps,
PIN_MAP_TYPE_CONFIGS_PIN);
}
#endif
#endif /* CONFIG_GENERIC_PINCONF */
#endif /* __LINUX_PINCTRL_PINCONF_GENERIC_H */

6
include/linux/pinctrl/pinconf.h
View File

@ -47,13 +47,15 @@ struct pinconf_ops {
unsigned long *config);
int (*pin_config_set) (struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long config);
unsigned long *configs,
unsigned num_configs);
int (*pin_config_group_get) (struct pinctrl_dev *pctldev,
unsigned selector,
unsigned long *config);
int (*pin_config_group_set) (struct pinctrl_dev *pctldev,
unsigned selector,
unsigned long config);
unsigned long *configs,
unsigned num_configs);
int (*pin_config_dbg_parse_modify) (struct pinctrl_dev *pctldev,
const char *arg,
unsigned long *config);

24
include/linux/platform_data/pinctrl-nomadik.h
View File

@ -226,30 +226,6 @@ enum nmk_gpio_slpm {
NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
};
/* Older deprecated pin config API that should go away soon */
extern int nmk_config_pin(pin_cfg_t cfg, bool sleep);
extern int nmk_config_pins(pin_cfg_t *cfgs, int num);
extern int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num);
extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
#ifdef CONFIG_PINCTRL_NOMADIK
extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
#else
static inline int nmk_gpio_set_mode(int gpio, int gpio_mode)
{
return -ENODEV;
}
#endif
extern int nmk_gpio_get_mode(int gpio);
extern void nmk_gpio_wakeups_suspend(void);
extern void nmk_gpio_wakeups_resume(void);
extern void nmk_gpio_clocks_enable(void);
extern void nmk_gpio_clocks_disable(void);
extern void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up);
/*
* Platform data to register a block: only the initial gpio/irq number.
*/