mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 12:43:55 +08:00
drm/nouveau/agp: move all agp stuff into its own source file
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
02a841d434
commit
aa4cc5d274
@ -70,7 +70,7 @@ nouveau-y += nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
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nouveau_display.o nouveau_connector.o nouveau_fbcon.o \
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nouveau_hdmi.o nouveau_dp.o \
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nouveau_pm.o nouveau_volt.o nouveau_perf.o nouveau_temp.o \
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nouveau_mxm.o \
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nouveau_mxm.o nouveau_agp.o \
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nouveau_abi16.o \
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nouveau_bios.o \
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nv04_fence.o nv10_fence.o nv84_fence.o nvc0_fence.o \
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152
drivers/gpu/drm/nouveau/nouveau_agp.c
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152
drivers/gpu/drm/nouveau/nouveau_agp.c
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@ -0,0 +1,152 @@
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#include <linux/module.h>
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_agp.h"
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#if __OS_HAS_AGP
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MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
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static int nouveau_agpmode = -1;
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module_param_named(agpmode, nouveau_agpmode, int, 0400);
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static unsigned long
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get_agp_mode(struct drm_device *dev, unsigned long mode)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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/*
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* FW seems to be broken on nv18, it makes the card lock up
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* randomly.
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*/
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if (dev_priv->chipset == 0x18)
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mode &= ~PCI_AGP_COMMAND_FW;
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/*
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* AGP mode set in the command line.
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*/
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if (nouveau_agpmode > 0) {
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bool agpv3 = mode & 0x8;
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int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
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mode = (mode & ~0x7) | (rate & 0x7);
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}
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return mode;
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}
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static bool
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nouveau_agp_enabled(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (!drm_pci_device_is_agp(dev) || !dev->agp)
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return false;
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switch (dev_priv->gart_info.type) {
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case NOUVEAU_GART_NONE:
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if (!nouveau_agpmode)
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return false;
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break;
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case NOUVEAU_GART_AGP:
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break;
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default:
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return false;
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}
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return true;
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}
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#endif
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void
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nouveau_agp_reset(struct drm_device *dev)
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{
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#if __OS_HAS_AGP
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u32 save[2];
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int ret;
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if (!nouveau_agp_enabled(dev))
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return;
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/* First of all, disable fast writes, otherwise if it's
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* already enabled in the AGP bridge and we disable the card's
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* AGP controller we might be locking ourselves out of it. */
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if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
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dev->agp->mode) & PCI_AGP_COMMAND_FW) {
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struct drm_agp_info info;
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struct drm_agp_mode mode;
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ret = drm_agp_info(dev, &info);
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if (ret)
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return;
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mode.mode = get_agp_mode(dev, info.mode);
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mode.mode &= ~PCI_AGP_COMMAND_FW;
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ret = drm_agp_enable(dev, mode);
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if (ret)
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return;
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}
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/* clear busmaster bit, and disable AGP */
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save[0] = nv_mask(dev, NV04_PBUS_PCI_NV_1, 0x00000004, 0x00000000);
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nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
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/* reset PGRAPH, PFIFO and PTIMER */
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save[1] = nv_mask(dev, 0x000200, 0x00011100, 0x00000000);
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nv_mask(dev, 0x000200, 0x00011100, save[1]);
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/* and restore bustmaster bit (gives effect of resetting AGP) */
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nv_wr32(dev, NV04_PBUS_PCI_NV_1, save[0]);
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#endif
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}
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void
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nouveau_agp_init(struct drm_device *dev)
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{
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#if __OS_HAS_AGP
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct drm_agp_info info;
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struct drm_agp_mode mode;
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int ret;
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if (!nouveau_agp_enabled(dev))
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return;
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ret = drm_agp_acquire(dev);
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if (ret) {
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NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
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return;
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}
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ret = drm_agp_info(dev, &info);
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if (ret) {
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NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
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return;
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}
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/* see agp.h for the AGPSTAT_* modes available */
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mode.mode = get_agp_mode(dev, info.mode);
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ret = drm_agp_enable(dev, mode);
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if (ret) {
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NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
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return;
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}
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dev_priv->gart_info.type = NOUVEAU_GART_AGP;
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dev_priv->gart_info.aper_base = info.aperture_base;
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dev_priv->gart_info.aper_size = info.aperture_size;
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#endif
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}
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void
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nouveau_agp_fini(struct drm_device *dev)
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{
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#if __OS_HAS_AGP
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if (dev->agp && dev->agp->acquired)
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drm_agp_release(dev);
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#endif
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}
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8
drivers/gpu/drm/nouveau/nouveau_agp.h
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8
drivers/gpu/drm/nouveau/nouveau_agp.h
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@ -0,0 +1,8 @@
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#ifndef __NOUVEAU_AGP_H__
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#define __NOUVEAU_AGP_H__
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void nouveau_agp_reset(struct drm_device *);
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void nouveau_agp_init(struct drm_device *);
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void nouveau_agp_fini(struct drm_device *);
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#endif
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@ -29,6 +29,7 @@
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#include "drm.h"
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#include "drm_crtc_helper.h"
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#include "nouveau_drv.h"
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#include "nouveau_agp.h"
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#include "nouveau_abi16.h"
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#include "nouveau_hw.h"
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#include "nouveau_fb.h"
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@ -39,10 +40,6 @@
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#include "drm_pciids.h"
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MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
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int nouveau_agpmode = -1;
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module_param_named(agpmode, nouveau_agpmode, int, 0400);
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MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
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int nouveau_modeset = -1;
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module_param_named(modeset, nouveau_modeset, int, 0400);
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@ -248,6 +245,8 @@ nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
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goto out_abort;
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}
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nouveau_agp_fini(dev);
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NV_INFO(dev, "And we're gone!\n");
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pci_save_state(pdev);
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if (pm_state.event == PM_EVENT_SUSPEND) {
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@ -287,8 +286,7 @@ nouveau_pci_resume(struct pci_dev *pdev)
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pci_set_master(dev->pdev);
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/* Make sure the AGP controller is in a consistent state */
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if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
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nouveau_mem_reset_agp(dev);
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nouveau_agp_reset(dev);
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/* Make the CRTCs accessible */
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engine->display.early_init(dev);
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@ -298,13 +296,7 @@ nouveau_pci_resume(struct pci_dev *pdev)
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if (ret)
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return ret;
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if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
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ret = nouveau_mem_init_agp(dev);
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if (ret) {
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NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
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return ret;
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}
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}
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nouveau_agp_init(dev);
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NV_INFO(dev, "Restoring GPU objects...\n");
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nouveau_gpuobj_resume(dev);
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@ -836,7 +836,6 @@ nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
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/* nouveau_drv.c */
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extern int nouveau_modeset;
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extern int nouveau_agpmode;
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extern int nouveau_duallink;
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extern int nouveau_uscript_lvds;
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extern int nouveau_uscript_tmds;
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@ -884,8 +883,6 @@ extern int nouveau_mem_vram_init(struct drm_device *);
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extern void nouveau_mem_vram_fini(struct drm_device *);
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extern int nouveau_mem_gart_init(struct drm_device *);
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extern void nouveau_mem_gart_fini(struct drm_device *);
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extern int nouveau_mem_init_agp(struct drm_device *);
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extern int nouveau_mem_reset_agp(struct drm_device *);
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extern void nouveau_mem_close(struct drm_device *);
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extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
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extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
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@ -36,6 +36,7 @@
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#include "drm_sarea.h"
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#include "nouveau_drv.h"
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#include "nouveau_agp.h"
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#include "nouveau_pm.h"
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#include <core/mm.h>
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#include <subdev/vm.h>
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@ -172,26 +173,7 @@ void
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nouveau_mem_gart_fini(struct drm_device *dev)
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{
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nouveau_sgdma_takedown(dev);
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if (drm_core_has_AGP(dev) && dev->agp) {
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struct drm_agp_mem *entry, *tempe;
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/* Remove AGP resources, but leave dev->agp
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intact until drv_cleanup is called. */
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list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
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if (entry->bound)
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drm_unbind_agp(entry->memory);
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drm_free_agp(entry->memory, entry->pages);
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kfree(entry);
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}
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INIT_LIST_HEAD(&dev->agp->memory);
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if (dev->agp->acquired)
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drm_agp_release(dev);
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dev->agp->acquired = 0;
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dev->agp->enabled = 0;
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}
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nouveau_agp_fini(dev);
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}
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bool
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@ -203,121 +185,6 @@ nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
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return false;
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}
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#if __OS_HAS_AGP
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static unsigned long
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get_agp_mode(struct drm_device *dev, unsigned long mode)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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/*
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* FW seems to be broken on nv18, it makes the card lock up
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* randomly.
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*/
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if (dev_priv->chipset == 0x18)
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mode &= ~PCI_AGP_COMMAND_FW;
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/*
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* AGP mode set in the command line.
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*/
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if (nouveau_agpmode > 0) {
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bool agpv3 = mode & 0x8;
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int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
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mode = (mode & ~0x7) | (rate & 0x7);
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}
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return mode;
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}
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#endif
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int
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nouveau_mem_reset_agp(struct drm_device *dev)
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{
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#if __OS_HAS_AGP
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uint32_t saved_pci_nv_1, pmc_enable;
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int ret;
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/* First of all, disable fast writes, otherwise if it's
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* already enabled in the AGP bridge and we disable the card's
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* AGP controller we might be locking ourselves out of it. */
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if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
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dev->agp->mode) & PCI_AGP_COMMAND_FW) {
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struct drm_agp_info info;
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struct drm_agp_mode mode;
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ret = drm_agp_info(dev, &info);
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if (ret)
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return ret;
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mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
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ret = drm_agp_enable(dev, mode);
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if (ret)
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return ret;
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}
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saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
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/* clear busmaster bit */
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nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
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/* disable AGP */
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nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
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/* power cycle pgraph, if enabled */
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pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
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if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
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nv_wr32(dev, NV03_PMC_ENABLE,
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pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
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NV_PMC_ENABLE_PGRAPH);
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}
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/* and restore (gives effect of resetting AGP) */
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nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
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#endif
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return 0;
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}
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int
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nouveau_mem_init_agp(struct drm_device *dev)
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{
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#if __OS_HAS_AGP
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct drm_agp_info info;
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struct drm_agp_mode mode;
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int ret;
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if (!dev->agp->acquired) {
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ret = drm_agp_acquire(dev);
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if (ret) {
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NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
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return ret;
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}
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}
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nouveau_mem_reset_agp(dev);
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ret = drm_agp_info(dev, &info);
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if (ret) {
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NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
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return ret;
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}
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/* see agp.h for the AGPSTAT_* modes available */
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mode.mode = get_agp_mode(dev, info.mode);
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ret = drm_agp_enable(dev, mode);
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if (ret) {
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NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
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return ret;
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}
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dev_priv->gart_info.type = NOUVEAU_GART_AGP;
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dev_priv->gart_info.aper_base = info.aperture_base;
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dev_priv->gart_info.aper_size = info.aperture_size;
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#endif
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return 0;
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}
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static const struct vram_types {
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int value;
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const char *name;
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@ -441,15 +308,7 @@ nouveau_mem_gart_init(struct drm_device *dev)
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struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
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int ret;
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dev_priv->gart_info.type = NOUVEAU_GART_NONE;
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#if !defined(__powerpc__) && !defined(__ia64__)
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if (drm_pci_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
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ret = nouveau_mem_init_agp(dev);
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if (ret)
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NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
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}
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#endif
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nouveau_agp_init(dev);
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if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
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ret = nouveau_sgdma_init(dev);
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@ -34,6 +34,7 @@
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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#include "nouveau_agp.h"
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#include "nouveau_fbcon.h"
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#include <core/ramht.h>
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#include <subdev/gpio.h>
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@ -547,6 +548,9 @@ nouveau_card_init(struct drm_device *dev)
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spin_lock_init(&dev_priv->context_switch_lock);
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spin_lock_init(&dev_priv->vm_lock);
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/* Make sure the AGP controller is in a consistent state */
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nouveau_agp_reset(dev);
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/* Make the CRTCs and I2C buses accessible */
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ret = engine->display.early_init(dev);
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if (ret)
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