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Some miscellaneous fixes for OMAP clock code, DRA7xx device data, and
PRCM code (when DSPBridge is used) for v3.16-rc. Basic build, boot, and PM test logs are available here: http://www.pwsan.com/omap/testlogs/prcm-a-v3.16-rc/20140706174258/ -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJTusBYAAoJEMePsQ0LvSpL0JgQAKsVXDTh1yeLzU1NT3Np0zJs rptjUTz3KGdq0ReU5N1Oe0J/cGbz4JFcN/Ug7l2fywKFeqK7QBBzcWL9NBVYKP+v OndbBi7OARd6iYEYsJwgFERe86ZwpE1KpR4Vnyo9uv3sA2AbbXbwvbjC0d/sktnV oCC83X2ahYauPj0/6suHtiZamuTvThCmM3hxMH2TFFoPaQKKV5BHp8dRXNjCZ5jg s/dfCX3dgb9S9HGbgsZBToqTmyMQ09hv0H0m3KAOveJQFgdwBSDgE94chOSdx3Kk DanBawF1LJmkpFwLUcTIbIkdBjGBBat4b2EVgPjyEFqWqWJgEHs56vSLsSwCkbi5 9tIu67aUP7VJCsibWECAOMtli7uYy/liYY/dUZhqrck6TT1tukhHKjjsuWr/9xY+ TU/Rd8PA5ytp92r2AkdN+Ztz6j1HUQQbGPmmIfOHuBB4WilwSF0Zgx+3c6bc9hMf 36J0qLYowaBYY57UN6joLGiPNcR7TgsEunCzsCxuGGby4rpFqy95Ml2aWFRn32bH LUgmAgaSNlk+v4E1iG7jJMHoH2xpKw+2+PNkIVC3WE8saE10qjZvebNUVJXb9bY1 VMuLHHrSc148ou0g+rM4ehF3PEbIBPd4SOxFwVsefPbAnpUSC+hj+SptYGWbLPJJ D+2noXhqssqVlvizxGoj =CanJ -----END PGP SIGNATURE----- Merge tag 'for-v3.16-rc/omap-fixes-b' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.16/fixes Some miscellaneous fixes for OMAP clock code, DRA7xx device data, and PRCM code (when DSPBridge is used) for v3.16-rc. Basic build, boot, and PM test logs are available here: http://www.pwsan.com/omap/testlogs/prcm-a-v3.16-rc/20140706174258/
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commit
aa3b465b5e
@ -76,7 +76,7 @@
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* (assuming that it is counting N upwards), or -2 if the enclosing loop
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* should skip to the next iteration (again assuming N is increasing).
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*/
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static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n)
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static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
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{
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struct dpll_data *dd;
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long fint, fint_min, fint_max;
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@ -26,11 +26,14 @@
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#define OMAP3430_EN_WDT3_SHIFT 12
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#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
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#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
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#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
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#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
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#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
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#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
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#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
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#define OMAP3430_ST_IVA2_SHIFT 0
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#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
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#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
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#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
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#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
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#define OMAP3430_IVA2_CLK_SRC_WIDTH 3
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@ -1268,9 +1268,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
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};
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/* sata */
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static struct omap_hwmod_opt_clk sata_opt_clks[] = {
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{ .role = "ref_clk", .clk = "sata_ref_clk" },
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};
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static struct omap_hwmod dra7xx_sata_hwmod = {
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.name = "sata",
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@ -1278,6 +1275,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
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.clkdm_name = "l3init_clkdm",
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.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
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.main_clk = "func_48m_fclk",
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.mpu_rt_idx = 1,
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
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@ -1285,8 +1283,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = sata_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
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};
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/*
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@ -1731,8 +1727,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
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*
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*/
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static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
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SYSC_HAS_SIDLEMODE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
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MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
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.name = "usb_otg_ss",
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.sysc = &dra7xx_usb_otg_ss_sysc,
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};
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/* usb_otg_ss1 */
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@ -35,6 +35,8 @@
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#define OMAP3430_LOGICSTATEST_MASK (1 << 2)
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#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2)
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#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
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#define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10)
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#define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9)
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#define OMAP3630_GRPSEL_UART4_MASK (1 << 18)
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#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17)
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#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16)
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@ -42,6 +44,10 @@
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#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14)
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#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13)
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#define OMAP3430_GRPSEL_UART3_MASK (1 << 11)
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#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9)
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#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8)
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#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7)
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#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6)
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#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2)
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#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1)
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#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0)
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