mirror of
https://github.com/edk2-porting/linux-next.git
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serial: remove blackfin drivers
The blackfin architecture is getting removed, so both the bfin_uart and bfin_sport_uart can be removed as well. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Aaron Wu <aaron.wu@analog.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
parent
aa4afa2cdd
commit
aa1fbc719e
@ -498,92 +498,6 @@ config SERIAL_SA1100_CONSOLE
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your boot loader (lilo or loadlin) about how to pass options to the
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kernel at boot time.)
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config SERIAL_BFIN
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tristate "Blackfin serial port support"
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depends on BLACKFIN
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select SERIAL_CORE
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select SERIAL_BFIN_UART0 if (BF531 || BF532 || BF533 || BF561)
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help
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Add support for the built-in UARTs on the Blackfin.
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To compile this driver as a module, choose M here: the
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module is named bfin_uart.ko.
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config SERIAL_BFIN_CONSOLE
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bool "Console on Blackfin serial port"
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depends on SERIAL_BFIN=y
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select SERIAL_CORE_CONSOLE
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choice
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prompt "UART Mode"
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depends on SERIAL_BFIN
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default SERIAL_BFIN_DMA
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help
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This driver supports the built-in serial ports of the Blackfin family
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of CPUs
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config SERIAL_BFIN_DMA
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bool "DMA mode"
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depends on !DMA_UNCACHED_NONE && KGDB_SERIAL_CONSOLE=n
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help
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This driver works under DMA mode. If this option is selected, the
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blackfin simple dma driver is also enabled.
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config SERIAL_BFIN_PIO
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bool "PIO mode"
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help
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This driver works under PIO mode.
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endchoice
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config SERIAL_BFIN_UART0
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bool "Enable UART0"
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depends on SERIAL_BFIN
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help
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Enable UART0
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config BFIN_UART0_CTSRTS
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bool "Enable UART0 hardware flow control"
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depends on SERIAL_BFIN_UART0
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help
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Enable hardware flow control in the driver.
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config SERIAL_BFIN_UART1
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bool "Enable UART1"
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depends on SERIAL_BFIN && (!BF531 && !BF532 && !BF533 && !BF561)
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help
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Enable UART1
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config BFIN_UART1_CTSRTS
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bool "Enable UART1 hardware flow control"
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depends on SERIAL_BFIN_UART1
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help
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Enable hardware flow control in the driver.
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config SERIAL_BFIN_UART2
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bool "Enable UART2"
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depends on SERIAL_BFIN && (BF54x || BF538 || BF539)
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help
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Enable UART2
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config BFIN_UART2_CTSRTS
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bool "Enable UART2 hardware flow control"
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depends on SERIAL_BFIN_UART2
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help
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Enable hardware flow control in the driver.
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config SERIAL_BFIN_UART3
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bool "Enable UART3"
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depends on SERIAL_BFIN && (BF54x)
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help
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Enable UART3
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config BFIN_UART3_CTSRTS
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bool "Enable UART3 hardware flow control"
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depends on SERIAL_BFIN_UART3
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help
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Enable hardware flow control in the driver.
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config SERIAL_IMX
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tristate "IMX serial port support"
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depends on HAS_DMA
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@ -1231,69 +1145,6 @@ config SERIAL_SC16IS7XX_SPI
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This is additional support to exsisting driver.
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You must select at least one bus for the driver to be built.
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config SERIAL_BFIN_SPORT
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tristate "Blackfin SPORT emulate UART"
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depends on BLACKFIN
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select SERIAL_CORE
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help
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Enable SPORT emulate UART on Blackfin series.
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To compile this driver as a module, choose M here: the
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module will be called bfin_sport_uart.
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config SERIAL_BFIN_SPORT_CONSOLE
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bool "Console on Blackfin sport emulated uart"
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depends on SERIAL_BFIN_SPORT=y
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select SERIAL_CORE_CONSOLE
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config SERIAL_BFIN_SPORT0_UART
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bool "Enable UART over SPORT0"
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depends on SERIAL_BFIN_SPORT && !(BF542 || BF544)
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help
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Enable UART over SPORT0
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config SERIAL_BFIN_SPORT0_UART_CTSRTS
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bool "Enable UART over SPORT0 hardware flow control"
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depends on SERIAL_BFIN_SPORT0_UART
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help
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Enable hardware flow control in the driver.
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config SERIAL_BFIN_SPORT1_UART
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bool "Enable UART over SPORT1"
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depends on SERIAL_BFIN_SPORT
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help
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Enable UART over SPORT1
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config SERIAL_BFIN_SPORT1_UART_CTSRTS
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bool "Enable UART over SPORT1 hardware flow control"
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depends on SERIAL_BFIN_SPORT1_UART
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help
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Enable hardware flow control in the driver.
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config SERIAL_BFIN_SPORT2_UART
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bool "Enable UART over SPORT2"
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depends on SERIAL_BFIN_SPORT && (BF54x || BF538 || BF539)
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help
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Enable UART over SPORT2
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config SERIAL_BFIN_SPORT2_UART_CTSRTS
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bool "Enable UART over SPORT2 hardware flow control"
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depends on SERIAL_BFIN_SPORT2_UART
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help
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Enable hardware flow control in the driver.
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config SERIAL_BFIN_SPORT3_UART
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bool "Enable UART over SPORT3"
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depends on SERIAL_BFIN_SPORT && (BF54x || BF538 || BF539)
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help
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Enable UART over SPORT3
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config SERIAL_BFIN_SPORT3_UART_CTSRTS
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bool "Enable UART over SPORT3 hardware flow control"
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depends on SERIAL_BFIN_SPORT3_UART
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help
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Enable hardware flow control in the driver.
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config SERIAL_TIMBERDALE
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tristate "Support for timberdale UART"
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select SERIAL_CORE
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@ -29,8 +29,6 @@ obj-$(CONFIG_SERIAL_PXA_NON8250) += pxa.o
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obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o
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obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
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obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o
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obj-$(CONFIG_SERIAL_BFIN) += bfin_uart.o
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obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o
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obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o
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obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
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obj-$(CONFIG_SERIAL_MAX310X) += max310x.o
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@ -1,937 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Blackfin On-Chip Sport Emulated UART Driver
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*
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* Copyright 2006-2009 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*/
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/*
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* This driver and the hardware supported are in term of EE-191 of ADI.
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* http://www.analog.com/static/imported-files/application_notes/EE191.pdf
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* This application note describe how to implement a UART on a Sharc DSP,
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* but this driver is implemented on Blackfin Processor.
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* Transmit Frame Sync is not used by this driver to transfer data out.
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*/
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/* #define DEBUG */
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#define DRV_NAME "bfin-sport-uart"
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#define DEVICE_NAME "ttySS"
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#define pr_fmt(fmt) DRV_NAME ": " fmt
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/gpio.h>
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#include <asm/bfin_sport.h>
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#include <asm/delay.h>
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#include <asm/portmux.h>
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#include "bfin_sport_uart.h"
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struct sport_uart_port {
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struct uart_port port;
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int err_irq;
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unsigned short csize;
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unsigned short rxmask;
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unsigned short txmask1;
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unsigned short txmask2;
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unsigned char stopb;
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/* unsigned char parib; */
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#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
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int cts_pin;
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int rts_pin;
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#endif
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};
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static int sport_uart_tx_chars(struct sport_uart_port *up);
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static void sport_stop_tx(struct uart_port *port);
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static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
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{
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pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
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up->txmask1, up->txmask2);
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/* Place Start and Stop bits */
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__asm__ __volatile__ (
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"%[val] <<= 1;"
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"%[val] = %[val] & %[mask1];"
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"%[val] = %[val] | %[mask2];"
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: [val]"+d"(value)
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: [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
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: "ASTAT"
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);
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pr_debug("%s value:%x\n", __func__, value);
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SPORT_PUT_TX(up, value);
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}
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static inline unsigned char rx_one_byte(struct sport_uart_port *up)
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{
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unsigned int value;
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unsigned char extract;
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u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
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if ((up->csize + up->stopb) > 7)
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value = SPORT_GET_RX32(up);
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else
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value = SPORT_GET_RX(up);
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pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
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up->csize, up->rxmask);
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/* Extract data */
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__asm__ __volatile__ (
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"%[extr] = 0;"
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"%[mask1] = %[rxmask];"
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"%[mask2] = 0x0200(Z);"
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"%[shift] = 0;"
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"LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
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".Lloop_s:"
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"%[tmp] = extract(%[val], %[mask1].L)(Z);"
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"%[tmp] <<= %[shift];"
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"%[extr] = %[extr] | %[tmp];"
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"%[mask1] = %[mask1] - %[mask2];"
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".Lloop_e:"
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"%[shift] += 1;"
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: [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
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[mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
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: [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
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: "ASTAT", "LB0", "LC0", "LT0"
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);
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pr_debug(" extract:%x\n", extract);
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return extract;
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}
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static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
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{
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int tclkdiv, rclkdiv;
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unsigned int sclk = get_sclk();
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/* Set TCR1 and TCR2, TFSR is not enabled for uart */
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SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
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SPORT_PUT_TCR2(up, size + 1);
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pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
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/* Set RCR1 and RCR2 */
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SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
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SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
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pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
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tclkdiv = sclk / (2 * baud_rate) - 1;
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/* The actual uart baud rate of devices vary between +/-2%. The sport
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* RX sample rate should be faster than the double of the worst case,
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* otherwise, wrong data are received. So, set sport RX clock to be
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* 3% faster.
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*/
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rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1;
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SPORT_PUT_TCLKDIV(up, tclkdiv);
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SPORT_PUT_RCLKDIV(up, rclkdiv);
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SSYNC();
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pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
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__func__, sclk, baud_rate, tclkdiv, rclkdiv);
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return 0;
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}
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static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
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{
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struct sport_uart_port *up = dev_id;
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struct tty_port *port = &up->port.state->port;
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unsigned int ch;
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spin_lock(&up->port.lock);
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while (SPORT_GET_STAT(up) & RXNE) {
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ch = rx_one_byte(up);
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up->port.icount.rx++;
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if (!uart_handle_sysrq_char(&up->port, ch))
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tty_insert_flip_char(port, ch, TTY_NORMAL);
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}
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spin_unlock(&up->port.lock);
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/* XXX this won't deadlock with lowlat? */
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tty_flip_buffer_push(port);
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return IRQ_HANDLED;
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}
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static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
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{
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struct sport_uart_port *up = dev_id;
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spin_lock(&up->port.lock);
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sport_uart_tx_chars(up);
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spin_unlock(&up->port.lock);
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return IRQ_HANDLED;
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}
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static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
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{
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struct sport_uart_port *up = dev_id;
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unsigned int stat = SPORT_GET_STAT(up);
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spin_lock(&up->port.lock);
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/* Overflow in RX FIFO */
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if (stat & ROVF) {
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up->port.icount.overrun++;
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tty_insert_flip_char(&up->port.state->port, 0, TTY_OVERRUN);
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SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
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}
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/* These should not happen */
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if (stat & (TOVF | TUVF | RUVF)) {
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pr_err("SPORT Error:%s %s %s\n",
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(stat & TOVF) ? "TX overflow" : "",
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(stat & TUVF) ? "TX underflow" : "",
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(stat & RUVF) ? "RX underflow" : "");
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SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
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SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
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}
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SSYNC();
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spin_unlock(&up->port.lock);
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/* XXX we don't push the overrun bit to TTY? */
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return IRQ_HANDLED;
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}
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#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
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static unsigned int sport_get_mctrl(struct uart_port *port)
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{
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struct sport_uart_port *up = (struct sport_uart_port *)port;
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if (up->cts_pin < 0)
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return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
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/* CTS PIN is negative assertive. */
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if (SPORT_UART_GET_CTS(up))
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return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
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else
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return TIOCM_DSR | TIOCM_CAR;
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}
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static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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struct sport_uart_port *up = (struct sport_uart_port *)port;
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if (up->rts_pin < 0)
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return;
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/* RTS PIN is negative assertive. */
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if (mctrl & TIOCM_RTS)
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SPORT_UART_ENABLE_RTS(up);
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else
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SPORT_UART_DISABLE_RTS(up);
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}
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/*
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* Handle any change of modem status signal.
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*/
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static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
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{
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struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
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unsigned int status;
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status = sport_get_mctrl(&up->port);
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uart_handle_cts_change(&up->port, status & TIOCM_CTS);
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return IRQ_HANDLED;
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}
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#else
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static unsigned int sport_get_mctrl(struct uart_port *port)
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{
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pr_debug("%s enter\n", __func__);
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return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
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}
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static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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pr_debug("%s enter\n", __func__);
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}
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#endif
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/* Reqeust IRQ, Setup clock */
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static int sport_startup(struct uart_port *port)
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{
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struct sport_uart_port *up = (struct sport_uart_port *)port;
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int ret;
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pr_debug("%s enter\n", __func__);
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ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
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"SPORT_UART_RX", up);
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if (ret) {
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dev_err(port->dev, "unable to request SPORT RX interrupt\n");
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return ret;
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}
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|
||||
ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
|
||||
"SPORT_UART_TX", up);
|
||||
if (ret) {
|
||||
dev_err(port->dev, "unable to request SPORT TX interrupt\n");
|
||||
goto fail1;
|
||||
}
|
||||
|
||||
ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
|
||||
"SPORT_UART_STATUS", up);
|
||||
if (ret) {
|
||||
dev_err(port->dev, "unable to request SPORT status interrupt\n");
|
||||
goto fail2;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
|
||||
if (up->cts_pin >= 0) {
|
||||
if (request_irq(gpio_to_irq(up->cts_pin),
|
||||
sport_mctrl_cts_int,
|
||||
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
|
||||
0, "BFIN_SPORT_UART_CTS", up)) {
|
||||
up->cts_pin = -1;
|
||||
dev_info(port->dev, "Unable to attach BlackFin UART over SPORT CTS interrupt. So, disable it.\n");
|
||||
}
|
||||
}
|
||||
if (up->rts_pin >= 0) {
|
||||
if (gpio_request(up->rts_pin, DRV_NAME)) {
|
||||
dev_info(port->dev, "fail to request RTS PIN at GPIO_%d\n", up->rts_pin);
|
||||
up->rts_pin = -1;
|
||||
} else
|
||||
gpio_direction_output(up->rts_pin, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
fail2:
|
||||
free_irq(up->port.irq+1, up);
|
||||
fail1:
|
||||
free_irq(up->port.irq, up);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* sport_uart_tx_chars
|
||||
*
|
||||
* ret 1 means need to enable sport.
|
||||
* ret 0 means do nothing.
|
||||
*/
|
||||
static int sport_uart_tx_chars(struct sport_uart_port *up)
|
||||
{
|
||||
struct circ_buf *xmit = &up->port.state->xmit;
|
||||
|
||||
if (SPORT_GET_STAT(up) & TXF)
|
||||
return 0;
|
||||
|
||||
if (up->port.x_char) {
|
||||
tx_one_byte(up, up->port.x_char);
|
||||
up->port.icount.tx++;
|
||||
up->port.x_char = 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
|
||||
/* The waiting loop to stop SPORT TX from TX interrupt is
|
||||
* too long. This may block SPORT RX interrupts and cause
|
||||
* RX FIFO overflow. So, do stop sport TX only after the last
|
||||
* char in TX FIFO is moved into the shift register.
|
||||
*/
|
||||
if (SPORT_GET_STAT(up) & TXHRE)
|
||||
sport_stop_tx(&up->port);
|
||||
return 0;
|
||||
}
|
||||
|
||||
while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
|
||||
tx_one_byte(up, xmit->buf[xmit->tail]);
|
||||
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
|
||||
up->port.icount.tx++;
|
||||
}
|
||||
|
||||
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
||||
uart_write_wakeup(&up->port);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static unsigned int sport_tx_empty(struct uart_port *port)
|
||||
{
|
||||
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||
unsigned int stat;
|
||||
|
||||
stat = SPORT_GET_STAT(up);
|
||||
pr_debug("%s stat:%04x\n", __func__, stat);
|
||||
if (stat & TXHRE) {
|
||||
return TIOCSER_TEMT;
|
||||
} else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sport_stop_tx(struct uart_port *port)
|
||||
{
|
||||
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||
|
||||
pr_debug("%s enter\n", __func__);
|
||||
|
||||
if (!(SPORT_GET_TCR1(up) & TSPEN))
|
||||
return;
|
||||
|
||||
/* Although the hold register is empty, last byte is still in shift
|
||||
* register and not sent out yet. So, put a dummy data into TX FIFO.
|
||||
* Then, sport tx stops when last byte is shift out and the dummy
|
||||
* data is moved into the shift register.
|
||||
*/
|
||||
SPORT_PUT_TX(up, 0xffff);
|
||||
while (!(SPORT_GET_STAT(up) & TXHRE))
|
||||
cpu_relax();
|
||||
|
||||
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
|
||||
SSYNC();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void sport_start_tx(struct uart_port *port)
|
||||
{
|
||||
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||
|
||||
pr_debug("%s enter\n", __func__);
|
||||
|
||||
/* Write data into SPORT FIFO before enable SPROT to transmit */
|
||||
if (sport_uart_tx_chars(up)) {
|
||||
/* Enable transmit, then an interrupt will generated */
|
||||
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
pr_debug("%s exit\n", __func__);
|
||||
}
|
||||
|
||||
static void sport_stop_rx(struct uart_port *port)
|
||||
{
|
||||
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||
|
||||
pr_debug("%s enter\n", __func__);
|
||||
/* Disable sport to stop rx */
|
||||
SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
static void sport_break_ctl(struct uart_port *port, int break_state)
|
||||
{
|
||||
pr_debug("%s enter\n", __func__);
|
||||
}
|
||||
|
||||
static void sport_shutdown(struct uart_port *port)
|
||||
{
|
||||
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||
|
||||
dev_dbg(port->dev, "%s enter\n", __func__);
|
||||
|
||||
/* Disable sport */
|
||||
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
|
||||
SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
|
||||
SSYNC();
|
||||
|
||||
free_irq(up->port.irq, up);
|
||||
free_irq(up->port.irq+1, up);
|
||||
free_irq(up->err_irq, up);
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
|
||||
if (up->cts_pin >= 0)
|
||||
free_irq(gpio_to_irq(up->cts_pin), up);
|
||||
if (up->rts_pin >= 0)
|
||||
gpio_free(up->rts_pin);
|
||||
#endif
|
||||
}
|
||||
|
||||
static const char *sport_type(struct uart_port *port)
|
||||
{
|
||||
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||
|
||||
pr_debug("%s enter\n", __func__);
|
||||
return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
|
||||
}
|
||||
|
||||
static void sport_release_port(struct uart_port *port)
|
||||
{
|
||||
pr_debug("%s enter\n", __func__);
|
||||
}
|
||||
|
||||
static int sport_request_port(struct uart_port *port)
|
||||
{
|
||||
pr_debug("%s enter\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sport_config_port(struct uart_port *port, int flags)
|
||||
{
|
||||
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||
|
||||
pr_debug("%s enter\n", __func__);
|
||||
up->port.type = PORT_BFIN_SPORT;
|
||||
}
|
||||
|
||||
static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
|
||||
{
|
||||
pr_debug("%s enter\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sport_set_termios(struct uart_port *port,
|
||||
struct ktermios *termios, struct ktermios *old)
|
||||
{
|
||||
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
|
||||
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
|
||||
if (old == NULL && up->cts_pin != -1)
|
||||
termios->c_cflag |= CRTSCTS;
|
||||
else if (up->cts_pin == -1)
|
||||
termios->c_cflag &= ~CRTSCTS;
|
||||
#endif
|
||||
|
||||
switch (termios->c_cflag & CSIZE) {
|
||||
case CS8:
|
||||
up->csize = 8;
|
||||
break;
|
||||
case CS7:
|
||||
up->csize = 7;
|
||||
break;
|
||||
case CS6:
|
||||
up->csize = 6;
|
||||
break;
|
||||
case CS5:
|
||||
up->csize = 5;
|
||||
break;
|
||||
default:
|
||||
pr_warn("requested word length not supported\n");
|
||||
break;
|
||||
}
|
||||
|
||||
if (termios->c_cflag & CSTOPB) {
|
||||
up->stopb = 1;
|
||||
}
|
||||
if (termios->c_cflag & PARENB) {
|
||||
pr_warn("PAREN bit is not supported yet\n");
|
||||
/* up->parib = 1; */
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&up->port.lock, flags);
|
||||
|
||||
port->read_status_mask = 0;
|
||||
|
||||
/*
|
||||
* Characters to ignore
|
||||
*/
|
||||
port->ignore_status_mask = 0;
|
||||
|
||||
/* RX extract mask */
|
||||
up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
|
||||
/* TX masks, 8 bit data and 1 bit stop for example:
|
||||
* mask1 = b#0111111110
|
||||
* mask2 = b#1000000000
|
||||
*/
|
||||
for (i = 0, up->txmask1 = 0; i < up->csize; i++)
|
||||
up->txmask1 |= (1<<i);
|
||||
up->txmask2 = (1<<i);
|
||||
if (up->stopb) {
|
||||
++i;
|
||||
up->txmask2 |= (1<<i);
|
||||
}
|
||||
up->txmask1 <<= 1;
|
||||
up->txmask2 <<= 1;
|
||||
/* uart baud rate */
|
||||
port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
|
||||
|
||||
/* Disable UART */
|
||||
SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
|
||||
SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
|
||||
|
||||
sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
|
||||
|
||||
/* driver TX line high after config, one dummy data is
|
||||
* necessary to stop sport after shift one byte
|
||||
*/
|
||||
SPORT_PUT_TX(up, 0xffff);
|
||||
SPORT_PUT_TX(up, 0xffff);
|
||||
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
|
||||
SSYNC();
|
||||
while (!(SPORT_GET_STAT(up) & TXHRE))
|
||||
cpu_relax();
|
||||
SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
|
||||
SSYNC();
|
||||
|
||||
/* Port speed changed, update the per-port timeout. */
|
||||
uart_update_timeout(port, termios->c_cflag, port->uartclk);
|
||||
|
||||
/* Enable sport rx */
|
||||
SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
|
||||
SSYNC();
|
||||
|
||||
spin_unlock_irqrestore(&up->port.lock, flags);
|
||||
}
|
||||
|
||||
static const struct uart_ops sport_uart_ops = {
|
||||
.tx_empty = sport_tx_empty,
|
||||
.set_mctrl = sport_set_mctrl,
|
||||
.get_mctrl = sport_get_mctrl,
|
||||
.stop_tx = sport_stop_tx,
|
||||
.start_tx = sport_start_tx,
|
||||
.stop_rx = sport_stop_rx,
|
||||
.break_ctl = sport_break_ctl,
|
||||
.startup = sport_startup,
|
||||
.shutdown = sport_shutdown,
|
||||
.set_termios = sport_set_termios,
|
||||
.type = sport_type,
|
||||
.release_port = sport_release_port,
|
||||
.request_port = sport_request_port,
|
||||
.config_port = sport_config_port,
|
||||
.verify_port = sport_verify_port,
|
||||
};
|
||||
|
||||
#define BFIN_SPORT_UART_MAX_PORTS 4
|
||||
|
||||
static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
|
||||
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
|
||||
#define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
|
||||
|
||||
static int __init
|
||||
sport_uart_console_setup(struct console *co, char *options)
|
||||
{
|
||||
struct sport_uart_port *up;
|
||||
int baud = 57600;
|
||||
int bits = 8;
|
||||
int parity = 'n';
|
||||
# ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
|
||||
int flow = 'r';
|
||||
# else
|
||||
int flow = 'n';
|
||||
# endif
|
||||
|
||||
/* Check whether an invalid uart number has been specified */
|
||||
if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
|
||||
return -ENODEV;
|
||||
|
||||
up = bfin_sport_uart_ports[co->index];
|
||||
if (!up)
|
||||
return -ENODEV;
|
||||
|
||||
if (options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
|
||||
return uart_set_options(&up->port, co, baud, parity, bits, flow);
|
||||
}
|
||||
|
||||
static void sport_uart_console_putchar(struct uart_port *port, int ch)
|
||||
{
|
||||
struct sport_uart_port *up = (struct sport_uart_port *)port;
|
||||
|
||||
while (SPORT_GET_STAT(up) & TXF)
|
||||
barrier();
|
||||
|
||||
tx_one_byte(up, ch);
|
||||
}
|
||||
|
||||
/*
|
||||
* Interrupts are disabled on entering
|
||||
*/
|
||||
static void
|
||||
sport_uart_console_write(struct console *co, const char *s, unsigned int count)
|
||||
{
|
||||
struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&up->port.lock, flags);
|
||||
|
||||
if (SPORT_GET_TCR1(up) & TSPEN)
|
||||
uart_console_write(&up->port, s, count, sport_uart_console_putchar);
|
||||
else {
|
||||
/* dummy data to start sport */
|
||||
while (SPORT_GET_STAT(up) & TXF)
|
||||
barrier();
|
||||
SPORT_PUT_TX(up, 0xffff);
|
||||
/* Enable transmit, then an interrupt will generated */
|
||||
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
|
||||
SSYNC();
|
||||
|
||||
uart_console_write(&up->port, s, count, sport_uart_console_putchar);
|
||||
|
||||
/* Although the hold register is empty, last byte is still in shift
|
||||
* register and not sent out yet. So, put a dummy data into TX FIFO.
|
||||
* Then, sport tx stops when last byte is shift out and the dummy
|
||||
* data is moved into the shift register.
|
||||
*/
|
||||
while (SPORT_GET_STAT(up) & TXF)
|
||||
barrier();
|
||||
SPORT_PUT_TX(up, 0xffff);
|
||||
while (!(SPORT_GET_STAT(up) & TXHRE))
|
||||
barrier();
|
||||
|
||||
/* Stop sport tx transfer */
|
||||
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&up->port.lock, flags);
|
||||
}
|
||||
|
||||
static struct uart_driver sport_uart_reg;
|
||||
|
||||
static struct console sport_uart_console = {
|
||||
.name = DEVICE_NAME,
|
||||
.write = sport_uart_console_write,
|
||||
.device = uart_console_device,
|
||||
.setup = sport_uart_console_setup,
|
||||
.flags = CON_PRINTBUFFER,
|
||||
.index = -1,
|
||||
.data = &sport_uart_reg,
|
||||
};
|
||||
|
||||
#define SPORT_UART_CONSOLE (&sport_uart_console)
|
||||
#else
|
||||
#define SPORT_UART_CONSOLE NULL
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
|
||||
|
||||
|
||||
static struct uart_driver sport_uart_reg = {
|
||||
.owner = THIS_MODULE,
|
||||
.driver_name = DRV_NAME,
|
||||
.dev_name = DEVICE_NAME,
|
||||
.major = 204,
|
||||
.minor = 84,
|
||||
.nr = BFIN_SPORT_UART_MAX_PORTS,
|
||||
.cons = SPORT_UART_CONSOLE,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int sport_uart_suspend(struct device *dev)
|
||||
{
|
||||
struct sport_uart_port *sport = dev_get_drvdata(dev);
|
||||
|
||||
dev_dbg(dev, "%s enter\n", __func__);
|
||||
if (sport)
|
||||
uart_suspend_port(&sport_uart_reg, &sport->port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sport_uart_resume(struct device *dev)
|
||||
{
|
||||
struct sport_uart_port *sport = dev_get_drvdata(dev);
|
||||
|
||||
dev_dbg(dev, "%s enter\n", __func__);
|
||||
if (sport)
|
||||
uart_resume_port(&sport_uart_reg, &sport->port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
|
||||
.suspend = sport_uart_suspend,
|
||||
.resume = sport_uart_resume,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int sport_uart_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct sport_uart_port *sport;
|
||||
int ret = 0;
|
||||
|
||||
dev_dbg(&pdev->dev, "%s enter\n", __func__);
|
||||
|
||||
if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
|
||||
dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
if (bfin_sport_uart_ports[pdev->id] == NULL) {
|
||||
bfin_sport_uart_ports[pdev->id] =
|
||||
kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
|
||||
sport = bfin_sport_uart_ports[pdev->id];
|
||||
if (!sport) {
|
||||
dev_err(&pdev->dev,
|
||||
"Fail to malloc sport_uart_port\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = peripheral_request_list(dev_get_platdata(&pdev->dev),
|
||||
DRV_NAME);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
"Fail to request SPORT peripherals\n");
|
||||
goto out_error_free_mem;
|
||||
}
|
||||
|
||||
spin_lock_init(&sport->port.lock);
|
||||
sport->port.fifosize = SPORT_TX_FIFO_SIZE,
|
||||
sport->port.ops = &sport_uart_ops;
|
||||
sport->port.line = pdev->id;
|
||||
sport->port.iotype = UPIO_MEM;
|
||||
sport->port.flags = UPF_BOOT_AUTOCONF;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (res == NULL) {
|
||||
dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
|
||||
ret = -ENOENT;
|
||||
goto out_error_free_peripherals;
|
||||
}
|
||||
|
||||
sport->port.membase = ioremap(res->start, resource_size(res));
|
||||
if (!sport->port.membase) {
|
||||
dev_err(&pdev->dev, "Cannot map sport IO\n");
|
||||
ret = -ENXIO;
|
||||
goto out_error_free_peripherals;
|
||||
}
|
||||
sport->port.mapbase = res->start;
|
||||
|
||||
sport->port.irq = platform_get_irq(pdev, 0);
|
||||
if ((int)sport->port.irq < 0) {
|
||||
dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
|
||||
ret = -ENOENT;
|
||||
goto out_error_unmap;
|
||||
}
|
||||
|
||||
sport->err_irq = platform_get_irq(pdev, 1);
|
||||
if (sport->err_irq < 0) {
|
||||
dev_err(&pdev->dev, "No sport status IRQ specified\n");
|
||||
ret = -ENOENT;
|
||||
goto out_error_unmap;
|
||||
}
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
|
||||
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
|
||||
if (res == NULL)
|
||||
sport->cts_pin = -1;
|
||||
else
|
||||
sport->cts_pin = res->start;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_IO, 1);
|
||||
if (res == NULL)
|
||||
sport->rts_pin = -1;
|
||||
else
|
||||
sport->rts_pin = res->start;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
|
||||
if (!is_early_platform_device(pdev)) {
|
||||
#endif
|
||||
sport = bfin_sport_uart_ports[pdev->id];
|
||||
sport->port.dev = &pdev->dev;
|
||||
dev_set_drvdata(&pdev->dev, sport);
|
||||
ret = uart_add_one_port(&sport_uart_reg, &sport->port);
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
|
||||
}
|
||||
#endif
|
||||
if (!ret)
|
||||
return 0;
|
||||
|
||||
if (sport) {
|
||||
out_error_unmap:
|
||||
iounmap(sport->port.membase);
|
||||
out_error_free_peripherals:
|
||||
peripheral_free_list(dev_get_platdata(&pdev->dev));
|
||||
out_error_free_mem:
|
||||
kfree(sport);
|
||||
bfin_sport_uart_ports[pdev->id] = NULL;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sport_uart_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sport_uart_port *sport = platform_get_drvdata(pdev);
|
||||
|
||||
dev_dbg(&pdev->dev, "%s enter\n", __func__);
|
||||
dev_set_drvdata(&pdev->dev, NULL);
|
||||
|
||||
if (sport) {
|
||||
uart_remove_one_port(&sport_uart_reg, &sport->port);
|
||||
iounmap(sport->port.membase);
|
||||
peripheral_free_list(dev_get_platdata(&pdev->dev));
|
||||
kfree(sport);
|
||||
bfin_sport_uart_ports[pdev->id] = NULL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver sport_uart_driver = {
|
||||
.probe = sport_uart_probe,
|
||||
.remove = sport_uart_remove,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
#ifdef CONFIG_PM
|
||||
.pm = &bfin_sport_uart_dev_pm_ops,
|
||||
#endif
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
|
||||
static struct early_platform_driver early_sport_uart_driver __initdata = {
|
||||
.class_str = CLASS_BFIN_SPORT_CONSOLE,
|
||||
.pdrv = &sport_uart_driver,
|
||||
.requested_id = EARLY_PLATFORM_ID_UNSET,
|
||||
};
|
||||
|
||||
static int __init sport_uart_rs_console_init(void)
|
||||
{
|
||||
early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
|
||||
|
||||
early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
|
||||
BFIN_SPORT_UART_MAX_PORTS, 0);
|
||||
|
||||
register_console(&sport_uart_console);
|
||||
|
||||
return 0;
|
||||
}
|
||||
console_initcall(sport_uart_rs_console_init);
|
||||
#endif
|
||||
|
||||
static int __init sport_uart_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
pr_info("Blackfin uart over sport driver\n");
|
||||
|
||||
ret = uart_register_driver(&sport_uart_reg);
|
||||
if (ret) {
|
||||
pr_err("failed to register %s:%d\n",
|
||||
sport_uart_reg.driver_name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = platform_driver_register(&sport_uart_driver);
|
||||
if (ret) {
|
||||
pr_err("failed to register sport uart driver:%d\n", ret);
|
||||
uart_unregister_driver(&sport_uart_reg);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
module_init(sport_uart_init);
|
||||
|
||||
static void __exit sport_uart_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&sport_uart_driver);
|
||||
uart_unregister_driver(&sport_uart_reg);
|
||||
}
|
||||
module_exit(sport_uart_exit);
|
||||
|
||||
MODULE_AUTHOR("Sonic Zhang, Roy Huang");
|
||||
MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -1,86 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Blackfin On-Chip Sport Emulated UART Driver
|
||||
*
|
||||
* Copyright 2006-2008 Analog Devices Inc.
|
||||
*
|
||||
* Enter bugs at http://blackfin.uclinux.org/
|
||||
*/
|
||||
|
||||
/*
|
||||
* This driver and the hardware supported are in term of EE-191 of ADI.
|
||||
* http://www.analog.com/static/imported-files/application_notes/EE191.pdf
|
||||
* This application note describe how to implement a UART on a Sharc DSP,
|
||||
* but this driver is implemented on Blackfin Processor.
|
||||
* Transmit Frame Sync is not used by this driver to transfer data out.
|
||||
*/
|
||||
|
||||
#ifndef _BFIN_SPORT_UART_H
|
||||
#define _BFIN_SPORT_UART_H
|
||||
|
||||
#define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */
|
||||
#define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */
|
||||
#define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */
|
||||
#define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */
|
||||
#define OFFSET_TX 0x10 /* Transmit Data Register */
|
||||
#define OFFSET_RX 0x18 /* Receive Data Register */
|
||||
#define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */
|
||||
#define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */
|
||||
#define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */
|
||||
#define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */
|
||||
#define OFFSET_STAT 0x30 /* Status Register */
|
||||
|
||||
#define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
|
||||
#define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
|
||||
#define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
|
||||
#define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
|
||||
#define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
|
||||
#define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
|
||||
/*
|
||||
* If another interrupt fires while doing a 32-bit read from RX FIFO,
|
||||
* a fake RX underflow error will be generated. So disable interrupts
|
||||
* to prevent interruption while reading the FIFO.
|
||||
*/
|
||||
#define SPORT_GET_RX32(sport) \
|
||||
({ \
|
||||
unsigned int __ret; \
|
||||
unsigned long flags; \
|
||||
if (ANOMALY_05000473) \
|
||||
local_irq_save(flags); \
|
||||
__ret = bfin_read32((sport)->port.membase + OFFSET_RX); \
|
||||
if (ANOMALY_05000473) \
|
||||
local_irq_restore(flags); \
|
||||
__ret; \
|
||||
})
|
||||
#define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
|
||||
#define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
|
||||
#define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
|
||||
#define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
|
||||
#define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))
|
||||
|
||||
#define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
|
||||
#define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
|
||||
#define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
|
||||
#define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
|
||||
#define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
|
||||
#define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
|
||||
#define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
|
||||
#define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
|
||||
#define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
|
||||
#define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
|
||||
#define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
|
||||
|
||||
#define SPORT_TX_FIFO_SIZE 8
|
||||
|
||||
#define SPORT_UART_GET_CTS(x) gpio_get_value(x->cts_pin)
|
||||
#define SPORT_UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
|
||||
#define SPORT_UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN_SPORT0_UART_CTSRTS) \
|
||||
|| defined(CONFIG_SERIAL_BFIN_SPORT1_UART_CTSRTS) \
|
||||
|| defined(CONFIG_SERIAL_BFIN_SPORT2_UART_CTSRTS) \
|
||||
|| defined(CONFIG_SERIAL_BFIN_SPORT3_UART_CTSRTS)
|
||||
# define CONFIG_SERIAL_BFIN_SPORT_CTSRTS
|
||||
#endif
|
||||
|
||||
#endif /* _BFIN_SPORT_UART_H */
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user