2
0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-25 13:43:55 +08:00

clk: rockchip: fix rk3188 sclk_smc gate data

Fix sclk_smc gate data.
Change variable order, flags come before the register address.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx9999@hotmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Finley Xiao 2018-11-14 15:45:49 +00:00 committed by Heiko Stuebner
parent 8b19faf6fa
commit a9f0c0e563

View File

@ -391,8 +391,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
* Clock-Architecture Diagram 4
*/
GATE(SCLK_SMC, "sclk_smc", "hclk_peri",
RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),
GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
RK2928_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,