Highlights:

-----------
 - Add a dummy L2 cache's write_sec callback as in non secure mode execution,
    we can't get access to L2 cache secure registers
 - Cosmetics change, in case of dump_stack, update the hardware name with a
    more generic for the STi SoCs family
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Merge tag 'sti-soc-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/soc

Merge "STi SoC changes for v4.8" from Patrice Chotard:

- Add a dummy L2 cache's write_sec callback as in non secure mode execution,
   we can't get access to L2 cache secure registers
- Cosmetics change, in case of dump_stack, update the hardware name with a
   more generic for the STi SoCs family

* tag 'sti-soc-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
  ARM: sti: Implement dummy L2 cache's write_sec
  ARM: STi: Update machine _namestr to be more generic.

arch/arm/mach-sti/board-dt.c

@@ -23,7 +23,15 @@ static const char *const stih41x_dt_match[] __initconst = {
 	NULL
 };
 
-DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree")
+static void sti_l2_write_sec(unsigned long val, unsigned reg)
+{
+	/*
+	 * We can't write to secure registers as we are in non-secure
+	 * mode, until we have some SMI service available.
+	 */
+}
+
+DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree")
 	.dt_compat	= stih41x_dt_match,
 	.l2c_aux_val	= L2C_AUX_CTRL_SHARED_OVERRIDE |
 			  L310_AUX_CTRL_DATA_PREFETCH |
@@ -31,4 +39,5 @@ DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree")
 			  L2C_AUX_CTRL_WAY_SIZE(4),
 	.l2c_aux_mask	= 0xc0000fff,
 	.smp		= smp_ops(sti_smp_ops),
+	.l2c_write_sec	= sti_l2_write_sec,
 MACHINE_END